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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id p14-20020a5d48ce000000b0021020517639sm14093823wrs.102.2022.06.20.13.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:16 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 01/49] regmap-irq: Fix a bug in regmap_irq_enable() for type_in_mask chips Date: Mon, 20 Jun 2022 21:05:56 +0100 Message-Id: <20220620200644.1961936-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" When enabling a type_in_mask irq, the type_buf contents must be AND'd with the mask of the IRQ we're enabling to avoid enabling other IRQs by accident, which can happen if several type_in_mask irqs share a mask register. Fixes: bc998a730367 ("regmap: irq: handle HW using separate rising/falling edge interrupts") Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 400c7412a7dc..4f785bc7981c 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -252,6 +252,7 @@ static void regmap_irq_enable(struct irq_data *data) struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); struct regmap *map = d->map; const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); + unsigned int reg = irq_data->reg_offset / map->reg_stride; unsigned int mask, type; type = irq_data->type.type_falling_val | irq_data->type.type_rising_val; @@ -268,14 +269,14 @@ static void regmap_irq_enable(struct irq_data *data) * at the corresponding offset in regmap_irq_set_type(). */ if (d->chip->type_in_mask && type) - mask = d->type_buf[irq_data->reg_offset / map->reg_stride]; + mask = d->type_buf[reg] & irq_data->mask; else mask = irq_data->mask; if (d->chip->clear_on_unmask) d->clear_status = true; - d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask; + d->mask_buf[reg] &= ~mask; } static void regmap_irq_disable(struct irq_data *data) From patchwork Mon Jun 20 20:05:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D7BEC43334 for ; Wed, 22 Jun 2022 15:24:25 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 96BEE1F2E; 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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id n4-20020a05600c4f8400b003971fc23185sm20679416wmq.20.2022.06.20.13.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:17 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 02/49] regmap-irq: Fix offset/index mismatch in read_sub_irq_data() Date: Mon, 20 Jun 2022 21:05:57 +0100 Message-Id: <20220620200644.1961936-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" We need to divide the sub-irq status register offset by register stride to get an index for the status buffer to avoid an out of bounds write when the register stride is greater than 1. Fixes: a2d21848d921 ("regmap: regmap-irq: Add main status register support") Signed-off-by: Aidan MacDonald Reviewed-by: Matti Vaittinen --- drivers/base/regmap/regmap-irq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 4f785bc7981c..a6db605707b0 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -387,6 +387,7 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, subreg = &chip->sub_reg_offsets[b]; for (i = 0; i < subreg->num_regs; i++) { unsigned int offset = subreg->offset[i]; + unsigned int index = offset / map->reg_stride; if (chip->not_fixed_stride) ret = regmap_read(map, @@ -395,7 +396,7 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, else ret = regmap_read(map, chip->status_base + offset, - &data->status_buf[offset]); + &data->status_buf[index]); if (ret) break; From patchwork Mon Jun 20 20:05:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39823C43334 for ; Wed, 22 Jun 2022 15:24:44 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 7DBF41DE3; Wed, 22 Jun 2022 17:23:52 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 7DBF41DE3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911482; bh=QlvVOwoQ6lFmeptQTmb/eEJoyNlDHdD3UTl9WHMxEeQ=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=EvH0x52WD9mWQXeW7/pZWxap2N0Rw+Uo3E3Q+48kLJGNKyaQt9tEUOsWtaumZRbAR aDRlNqJ1nO4qvqykSXNvcvKgd3kvta+swmzj5y2OB+0QiCAqkWtQLL/j5MsI9/kriT SWnezilloXerr4C8cfbp9RA2dXNmHr9kRLR8vO+U= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id C7889F8019B; Wed, 22 Jun 2022 17:23:22 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id B46F4F804DA; Mon, 20 Jun 2022 22:06:27 +0200 (CEST) Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 0FE16F804E5 for ; Mon, 20 Jun 2022 22:06:21 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 0FE16F804E5 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e6An1+k7" Received: by mail-wr1-x430.google.com with SMTP id g4so16059613wrh.11 for ; Mon, 20 Jun 2022 13:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DcQuE9oGehOZto3hA/rTLb2fToN8VqZpboB1wSvVLeU=; b=e6An1+k7URA0wQXNcY2/BdRAilnccZF6A/hAv9jWNU7eSpvfOtHDfFPlFA9Tmj9tdP Q3jbhTK1VDeXWFItQMxcv0vZ7RCc5cmoO02hqrWFt1bNQVvSZ9vWPfkxDdj301roqukK VxcyBZNW8QGynfO8JWI+WWahEFDrUvnJXyIxMEVYx3RByt41ka89CAhjte2WBrFW5mhM TCXItN7+bBmjpnPbHtb5ce5F5Rk9ZgfpC/oo8VuyT8lEVZBE0Oo1B0D7mW2UL08mlg2l JQb9VPre/3jtmwZhYCFcXMZ3dZ9tQ6hqqgn0BUdmCk0DnRF2pxNugG3O1NbKVirJLc3k 3CXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DcQuE9oGehOZto3hA/rTLb2fToN8VqZpboB1wSvVLeU=; b=r0P4QqD3C5LlgqmrUCbej9o6dx0A2UU1nppG77K6pzLaD7HukpFoMLsw6HU22tY6MN 1+/s6yEUuSu47uNBZ+aRSbqmn1bnrMCXmappkJ2J5WOJ57G4Q7qOXUJFbWv1hJgL/YFy 8XCVlABpL15VqTi/AKr1HptHI910EA5Rjl2EyTnGBv55KaxQoeIGGB+oACYofBE+UchF xBYrGJJofiMi+Tm07GoohgitXfyHFsE5VAqeO5hIu61yNBSdtG8VB0BJ+DYnDq2ED0+K rKCbdcUuoWayCuk/fYvfTg6XpVCzqQg0F0v7QR6gSYZZ0HX/wM8jKxG3FyGwoRzqhWFj BtXw== X-Gm-Message-State: AJIora8kXbYwh0lmACUpbKQYzj8KcXH/BR0veeAgNw9tx8TQTrGqhiOK 5hJnFODiS/hIgbqQLVTSVd4= X-Google-Smtp-Source: AGRyM1toV/6s8wRgMxmabtCAeVPKyocBr9a+nW1Hds3EtsXXFabw7Q99ucUCOTs0Oy4tAKumPVl4nQ== X-Received: by 2002:a5d:64c7:0:b0:21b:9661:6aac with SMTP id f7-20020a5d64c7000000b0021b96616aacmr665641wri.496.1655755579596; Mon, 20 Jun 2022 13:06:19 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id c5-20020adffb45000000b0021b91d1ddbfsm2917554wrs.21.2022.06.20.13.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:19 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 03/49] regmap-irq: Remove an unnecessary restriction on type_in_mask Date: Mon, 20 Jun 2022 21:05:58 +0100 Message-Id: <20220620200644.1961936-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Check types_supported instead of checking type_rising/falling_val when using type_in_mask interrupts. This makes the intent clearer and allows a type_in_mask irq to support level or edge triggers, rather than only edge triggers. Update the comment to reflect the new behavior. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index a6db605707b0..59cfd4000e63 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -253,22 +253,19 @@ static void regmap_irq_enable(struct irq_data *data) struct regmap *map = d->map; const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); unsigned int reg = irq_data->reg_offset / map->reg_stride; - unsigned int mask, type; - - type = irq_data->type.type_falling_val | irq_data->type.type_rising_val; + unsigned int mask; /* * The type_in_mask flag means that the underlying hardware uses - * separate mask bits for rising and falling edge interrupts, but - * we want to make them into a single virtual interrupt with - * configurable edge. + * separate mask bits for each interrupt trigger type, but we want + * to have a single logical interrupt with a configurable type. * - * If the interrupt we're enabling defines the falling or rising - * masks then instead of using the regular mask bits for this - * interrupt, use the value previously written to the type buffer - * at the corresponding offset in regmap_irq_set_type(). + * If the interrupt we're enabling defines any supported types + * then instead of using the regular mask bits for this interrupt, + * use the value previously written to the type buffer at the + * corresponding offset in regmap_irq_set_type(). */ - if (d->chip->type_in_mask && type) + if (d->chip->type_in_mask && irq_data->type.types_supported) mask = d->type_buf[reg] & irq_data->mask; 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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id d8-20020adfc088000000b00213ba0cab3asm14319173wrf.44.2022.06.20.13.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:20 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 04/49] regmap-irq: Introduce config registers for irq types Date: Mon, 20 Jun 2022 21:05:59 +0100 Message-Id: <20220620200644.1961936-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Config registers provide a more uniform approach to handling irq type registers. They are essentially an extension of the virtual registers used by the qcom-pm8008 driver. Config registers can be represented as a 2D array: config_base[0] reg0,0 reg0,1 reg0,2 reg0,3 config_base[1] reg1,0 reg1,1 reg1,2 reg1,3 config_base[2] reg2,0 reg2,1 reg2,2 reg2,3 There are 'num_config_bases' base registers, each of which is used to address 'num_config_regs' registers. The addresses are calculated in the same way as for other bases. It is assumed that an irq's type is controlled by one column of registers; that column is identified by the irq's 'type_reg_offset'. The set_type_config() callback is responsible for updating the config register contents. It receives an array of buffers (each represents a row of registers) and the index of the column to update, along with the 'struct regmap_irq' description and requested irq type. Buffered values are written to registers in regmap_irq_sync_unlock(). Note that the entire register contents are overwritten, which is a minor change in behavior from type registers via 'type_base'. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 102 ++++++++++++++++++++++++++++++- include/linux/regmap.h | 12 ++++ 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 59cfd4000e63..be35f2e41b8c 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -39,6 +39,7 @@ struct regmap_irq_chip_data { unsigned int *type_buf; unsigned int *type_buf_def; unsigned int **virt_buf; + unsigned int **config_buf; unsigned int irq_reg_stride; unsigned int type_reg_stride; @@ -231,6 +232,17 @@ static void regmap_irq_sync_unlock(struct irq_data *data) } } + for (i = 0; i < d->chip->num_config_bases; i++) { + for (j = 0; j < d->chip->num_config_regs; j++) { + reg = sub_irq_reg(d, d->chip->config_base[i], j); + ret = regmap_write(map, reg, d->config_buf[i][j]); + if (ret != 0) + dev_err(d->map->dev, + "Failed to write config %x: %d\n", + reg, ret); + } + } + if (d->chip->runtime_pm) pm_runtime_put(map->dev); @@ -298,6 +310,10 @@ static int regmap_irq_set_type(struct irq_data *data, unsigned int type) reg = t->type_reg_offset / map->reg_stride; + if (d->chip->set_type_config) + return d->chip->set_type_config(d->config_buf, type, + irq_data, reg); + if (t->type_reg_mask) d->type_buf[reg] &= ~t->type_reg_mask; else @@ -603,6 +619,62 @@ static const struct irq_domain_ops regmap_domain_ops = { .xlate = irq_domain_xlate_onetwocell, }; +/** + * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. + * + * @buf: Buffer containing configuration register values, this is a 2D array of + * `num_config_bases` rows, each of `num_config_regs` elements. + * @type: The requested IRQ type. + * @irq_data: The IRQ being configured. + * @idx: Index of the irq's config registers within each array `buf[i]` + * + * This is a &struct regmap_irq_chip->set_type_config callback suitable for + * chips with one config register. Register values are updated according to + * the &struct regmap_irq_type data associated with an IRQ. + */ +int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx) +{ + const struct regmap_irq_type *t = &irq_data->type; + + if (t->type_reg_mask) + buf[0][idx] &= ~t->type_reg_mask; + else + buf[0][idx] &= ~(t->type_falling_val | + t->type_rising_val | + t->type_level_low_val | + t->type_level_high_val); + + switch (type) { + case IRQ_TYPE_EDGE_FALLING: + buf[0][idx] |= t->type_falling_val; + break; + + case IRQ_TYPE_EDGE_RISING: + buf[0][idx] |= t->type_rising_val; + break; + + case IRQ_TYPE_EDGE_BOTH: + buf[0][idx] |= (t->type_falling_val | + t->type_rising_val); + break; + + case IRQ_TYPE_LEVEL_HIGH: + buf[0][idx] |= t->type_level_high_val; + break; + + case IRQ_TYPE_LEVEL_LOW: + buf[0][idx] |= t->type_level_low_val; + break; + + default: + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL_GPL(regmap_irq_set_type_config_simple); + /** * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling * @@ -728,6 +800,24 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, } } + if (chip->num_config_bases && chip->num_config_regs) { + /* + * Create config_buf[num_config_bases][num_config_regs] + */ + d->config_buf = kcalloc(chip->num_config_bases, + sizeof(*d->config_buf), GFP_KERNEL); + if (!d->config_buf) + goto err_alloc; + + for (i = 0; i < chip->num_config_regs; i++) { + d->config_buf[i] = kcalloc(chip->num_config_regs, + sizeof(unsigned int), + GFP_KERNEL); + if (!d->config_buf[i]) + goto err_alloc; + } + } + d->irq_chip = regmap_irq_chip; d->irq_chip.name = chip->name; d->irq = irq; @@ -904,6 +994,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, kfree(d->virt_buf[i]); kfree(d->virt_buf); } + if (d->config_buf) { + for (i = 0; i < chip->num_config_bases; i++) + kfree(d->config_buf[i]); + kfree(d->config_buf); + } kfree(d); return ret; } @@ -944,7 +1039,7 @@ EXPORT_SYMBOL_GPL(regmap_add_irq_chip); void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) { unsigned int virq; - int hwirq; + int i, hwirq; if (!d) return; @@ -974,6 +1069,11 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) kfree(d->mask_buf); kfree(d->status_reg_buf); kfree(d->status_buf); + if (d->config_buf) { + for (i = 0; i < d->chip->num_config_bases; i++) + kfree(d->config_buf[i]); + kfree(d->config_buf); + } kfree(d); } EXPORT_SYMBOL_GPL(regmap_del_irq_chip); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 8952fa3d0d59..e48d65756fb4 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1460,6 +1460,7 @@ struct regmap_irq_sub_irq_map { * @wake_base: Base address for wake enables. If zero unsupported. * @type_base: Base address for irq type. If zero unsupported. * @virt_reg_base: Base addresses for extra config regs. + * @config_base: Base address for IRQ type config regs. If null unsupported. * @irq_reg_stride: Stride to use for chips where registers are not contiguous. * @init_ack_masked: Ack all masked interrupts once during initalization. * @mask_invert: Inverted mask register: cleared bits are masked out. @@ -1489,12 +1490,15 @@ struct regmap_irq_sub_irq_map { * If zero unsupported. * @type_reg_stride: Stride to use for chips where type registers are not * contiguous. + * @num_config_bases: Number of config base registers. + * @num_config_regs: Number of config registers for each config base register. * @handle_pre_irq: Driver specific callback to handle interrupt from device * before regmap_irq_handler process the interrupts. * @handle_post_irq: Driver specific callback to handle interrupt from device * after handling the interrupts in regmap_irq_handler(). * @set_type_virt: Driver specific callback to extend regmap_irq_set_type() * and configure virt regs. + * @set_type_config: Callback used for configuring irq types. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. * @@ -1517,6 +1521,7 @@ struct regmap_irq_chip { unsigned int wake_base; unsigned int type_base; unsigned int *virt_reg_base; + const unsigned int *config_base; unsigned int irq_reg_stride; bool mask_writeonly:1; bool init_ack_masked:1; @@ -1539,17 +1544,24 @@ struct regmap_irq_chip { int num_type_reg; int num_virt_regs; + int num_config_bases; + int num_config_regs; unsigned int type_reg_stride; int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); int (*set_type_virt)(unsigned int **buf, unsigned int type, unsigned long hwirq, int reg); + int (*set_type_config)(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx); void *irq_drv_data; }; struct regmap_irq_chip_data; +int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx); + int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, int irq_base, const struct regmap_irq_chip *chip, struct regmap_irq_chip_data **data); From patchwork Mon Jun 20 20:06:00 2022 Content-Type: text/plain; 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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id x13-20020adfdd8d000000b0021b81855c1csm12567311wrl.27.2022.06.20.13.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:22 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 05/49] mfd: qcom-pm8008: Convert irq chip to config regs Date: Mon, 20 Jun 2022 21:06:00 +0100 Message-Id: <20220620200644.1961936-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Use config registers to simplify the driver, putting all of the code for irq type configuration in one place instead of splitting it up arbitrarily between type and virtual registers. Remove the initial register setting in pm8008_init(). The comment indicates this is a hack to work around quirks in regmap-irq, but this is not necessary if using config registers. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 76 +++++++++++---------------------------- 1 file changed, 21 insertions(+), 55 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index c472d7f8103c..da16566f7883 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -73,15 +73,16 @@ static struct regmap_irq_sub_irq_map pm8008_sub_reg_offsets[] = { REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs), }; -static unsigned int pm8008_virt_regs[] = { +static unsigned int pm8008_config_regs[] = { + PM8008_TYPE_BASE, PM8008_POLARITY_HI_BASE, PM8008_POLARITY_LO_BASE, }; enum { + SET_TYPE_INDEX, POLARITY_HI_INDEX, POLARITY_LO_INDEX, - PM8008_NUM_VIRT_REGS, }; static struct regmap_irq pm8008_irqs[] = { @@ -95,32 +96,36 @@ static struct regmap_irq pm8008_irqs[] = { REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)), }; -static int pm8008_set_type_virt(unsigned int **virt_buf, - unsigned int type, unsigned long hwirq, - int reg) +static int pm8008_set_type_config(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx) { switch (type) { case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: - virt_buf[POLARITY_HI_INDEX][reg] &= ~pm8008_irqs[hwirq].mask; - virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask; + buf[POLARITY_HI_INDEX][idx] &= ~irq_data->mask; + buf[POLARITY_LO_INDEX][idx] |= irq_data->mask; break; case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: - virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask; - virt_buf[POLARITY_LO_INDEX][reg] &= ~pm8008_irqs[hwirq].mask; + buf[POLARITY_HI_INDEX][idx] |= irq_data->mask; + buf[POLARITY_LO_INDEX][idx] &= ~irq_data->mask; break; case IRQ_TYPE_EDGE_BOTH: - virt_buf[POLARITY_HI_INDEX][reg] |= pm8008_irqs[hwirq].mask; - virt_buf[POLARITY_LO_INDEX][reg] |= pm8008_irqs[hwirq].mask; + buf[POLARITY_HI_INDEX][idx] |= irq_data->mask; + buf[POLARITY_LO_INDEX][idx] |= irq_data->mask; break; default: return -EINVAL; } + if (type & IRQ_TYPE_EDGE_BOTH) + buf[SET_TYPE_INDEX][idx] |= irq_data->mask; + else + buf[SET_TYPE_INDEX][idx] &= ~irq_data->mask; + return 0; } @@ -128,20 +133,19 @@ static struct regmap_irq_chip pm8008_irq_chip = { .name = "pm8008_irq", .main_status = I2C_INTR_STATUS_BASE, .num_main_regs = 1, - .num_virt_regs = PM8008_NUM_VIRT_REGS, .irqs = pm8008_irqs, .num_irqs = ARRAY_SIZE(pm8008_irqs), .num_regs = PM8008_NUM_PERIPHS, .not_fixed_stride = true, .sub_reg_offsets = pm8008_sub_reg_offsets, - .set_type_virt = pm8008_set_type_virt, .status_base = PM8008_STATUS_BASE, .mask_base = PM8008_MASK_BASE, .unmask_base = PM8008_UNMASK_BASE, - .type_base = PM8008_TYPE_BASE, .ack_base = PM8008_ACK_BASE, - .virt_reg_base = pm8008_virt_regs, - .num_type_reg = PM8008_NUM_PERIPHS, + .config_base = pm8008_config_regs, + .num_config_bases = ARRAY_SIZE(pm8008_config_regs), + .num_config_regs = PM8008_NUM_PERIPHS, + .set_type_config = pm8008_set_type_config, }; static struct regmap_config qcom_mfd_regmap_cfg = { @@ -150,34 +154,6 @@ static struct regmap_config qcom_mfd_regmap_cfg = { .max_register = 0xFFFF, }; -static int pm8008_init(struct pm8008_data *chip) -{ - int rc; - - /* - * Set TEMP_ALARM peripheral's TYPE so that the regmap-irq framework - * reads this as the default value instead of zero, the HW default. - * This is required to enable the writing of TYPE registers in - * regmap_irq_sync_unlock(). - */ - rc = regmap_write(chip->regmap, - (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET), - BIT(0)); - if (rc) - return rc; - - /* Do the same for GPIO1 and GPIO2 peripherals */ - rc = regmap_write(chip->regmap, - (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); - if (rc) - return rc; - - rc = regmap_write(chip->regmap, - (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); - - return rc; -} - static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, int client_irq) { @@ -185,20 +161,10 @@ static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, struct regmap_irq_type *type; struct regmap_irq_chip_data *irq_data; - rc = pm8008_init(chip); - if (rc) { - dev_err(chip->dev, "Init failed: %d\n", rc); - return rc; - } - for (i = 0; i < ARRAY_SIZE(pm8008_irqs); i++) { type = &pm8008_irqs[i].type; - type->type_reg_offset = pm8008_irqs[i].reg_offset; - type->type_rising_val = pm8008_irqs[i].mask; - type->type_falling_val = pm8008_irqs[i].mask; - type->type_level_high_val = 0; - type->type_level_low_val = 0; + type->type_reg_offset = pm8008_irqs[i].reg_offset; if (type->type_reg_offset == PM8008_MISC) type->types_supported = IRQ_TYPE_EDGE_RISING; From patchwork Mon Jun 20 20:06:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D738DC433EF for ; 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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id t22-20020a05600c41d600b0039db7f1a3f5sm15482666wmh.45.2022.06.20.13.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:23 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 06/49] mfd: wcd934x: Convert irq chip to config regs Date: Mon, 20 Jun 2022 21:06:01 +0100 Message-Id: <20220620200644.1961936-7-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Switch the driver to config registers. This will allow the old type register code in regmap-irq to be removed. Signed-off-by: Aidan MacDonald --- drivers/mfd/wcd934x.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/wcd934x.c b/drivers/mfd/wcd934x.c index 68e2fa2fda99..07e884087f2c 100644 --- a/drivers/mfd/wcd934x.c +++ b/drivers/mfd/wcd934x.c @@ -55,17 +55,22 @@ static const struct regmap_irq wcd934x_irqs[] = { WCD934X_REGMAP_IRQ_REG(WCD934X_IRQ_SOUNDWIRE, 2, BIT(4)), }; +static const unsigned int wcd934x_config_regs[] = { + WCD934X_INTR_LEVEL0, +}; + static const struct regmap_irq_chip wcd934x_regmap_irq_chip = { .name = "wcd934x_irq", .status_base = WCD934X_INTR_PIN1_STATUS0, .mask_base = WCD934X_INTR_PIN1_MASK0, .ack_base = WCD934X_INTR_PIN1_CLEAR0, - .type_base = WCD934X_INTR_LEVEL0, - .num_type_reg = 4, - .type_in_mask = false, .num_regs = 4, .irqs = wcd934x_irqs, .num_irqs = ARRAY_SIZE(wcd934x_irqs), + .config_base = wcd934x_config_regs, + .num_config_bases = ARRAY_SIZE(wcd934x_config_regs), + .num_config_regs = 4, + .set_type_config = regmap_irq_set_type_config_simple, }; static bool wcd934x_is_volatile_register(struct device *dev, unsigned int reg) From patchwork Mon Jun 20 20:06:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BD19C43334 for ; Wed, 22 Jun 2022 15:25:53 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id CBAFA1F19; Wed, 22 Jun 2022 17:25:01 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz CBAFA1F19 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911551; bh=npvPMjSZECv5ADKGwrqJNAtSjHJRKaSPFuM0+qR0qPU=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=OUQdsSEEPwinNXLTWdphAKDO6WLWlQUVucryhS7h/mZ/fcX5/mlfmQ8WK2/vcSGxP WAw64mMaXwRXVZDPHMC8da/mNAmXha/GL/c7cb5QrHyQEsv3QsYNBLG1RGOOxoqP0c or0eCu+C0fvbHCI6c3rowM8o4uB/NsjHe99FJlXM= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 08A5DF80553; Wed, 22 Jun 2022 17:23:25 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id B193BF804EB; Mon, 20 Jun 2022 22:06:31 +0200 (CEST) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 8F5DBF804D8 for ; Mon, 20 Jun 2022 22:06:27 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 8F5DBF804D8 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QNECaX95" Received: by mail-wr1-x42a.google.com with SMTP id g27so9431561wrb.10 for ; Mon, 20 Jun 2022 13:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rwq1xrraD4RZAx2kCX1gT4beeMnmuxO1mM9UwNM/j94=; b=QNECaX952+TTlSLlpOVs/6XitpxYvWRdZb+grPlyuTrwlpraID/DEO7pF7pRWsRnhg hjsEeZ5QkVN79568dtxIQ2IXGLbC5nR7sF+MgWAVMh5hkBWMw0P53fMMGZkmjvLcFNNa dhUutUl0wGwONV7Kom3uv28INHcBCYzOkQGuNSDENRNw1sxJZQ0/eMfiA/Qgxb87L4I8 /Ptke0D3H96sRWpppziAeYZU/tnFck/UsfeMN/LXYqm2I78lehUvPTyO3hQ8x4y7ScUk uchno9kgBiWN8XY4/R7yf92muZ6rRsjh0pZSVJsyikq3CxlSVWLF/qU3eR8EP1K+XGbx gjvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rwq1xrraD4RZAx2kCX1gT4beeMnmuxO1mM9UwNM/j94=; b=C7FGvNIRNot2x+5v9zDcBpaT/DVbJdBjBu/aYFvFHKfkxodmSJSsrKVYDTkfoXNPiP pof4EKVg8ja9tHrAIQNmOol6W6HRKO5JNmsnvO3gq6H1HPlnYdxruFgrTwo1OHLbe/Qo YnSFCYDdRTtyQPXYWwFUW1zRhdmam9Xu3s9C0VOgeoY0cycYqwl+/TxSlvy4H3SC3Hh0 QfEdWwI6GIePK/liYITvx4XMg3QmQhgb+XrR9Bri6OjpVlgE6useWbUQ333zgLEVI77E VDNgrfbemfLaFWk4vmQwehkYCvKN1VoAJEuwuRaLqE/QAXtJxabzpjq2UK6rhMdYD17H Ygmg== X-Gm-Message-State: AJIora/qdkLbieHuLtoT7McgO0u2qFnPTKOicq9B2uUx83t1H/6L0Yn7 LBJilNjjt6jcMh0yvfN2vbA= X-Google-Smtp-Source: AGRyM1tP2UDTugiqATrashu5vRyEcZXwb3725FZvBb5Omwk2LFohTTxHAY3xss+vpJU1LZ+f8ik2aw== X-Received: by 2002:adf:ef42:0:b0:21b:8e58:f24b with SMTP id c2-20020adfef42000000b0021b8e58f24bmr7537796wrp.257.1655755585865; Mon, 20 Jun 2022 13:06:25 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id u3-20020adfeb43000000b0021a34023ca3sm13936104wrn.62.2022.06.20.13.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:25 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 07/49] sound: soc: codecs: wcd9335: Convert irq chip to config regs Date: Mon, 20 Jun 2022 21:06:02 +0100 Message-Id: <20220620200644.1961936-8-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Switch the driver to config registers. This will allow the old type register code in regmap-irq to be removed. Signed-off-by: Aidan MacDonald --- sound/soc/codecs/wcd9335.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/wcd9335.c b/sound/soc/codecs/wcd9335.c index 617a36a89dfe..727d4436142a 100644 --- a/sound/soc/codecs/wcd9335.c +++ b/sound/soc/codecs/wcd9335.c @@ -5020,16 +5020,22 @@ static const struct regmap_irq wcd9335_codec_irqs[] = { }, }; +static const unsigned int wcd9335_config_regs[] = { + WCD9335_INTR_LEVEL0, +}; + static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { .name = "wcd9335_pin1_irq", .status_base = WCD9335_INTR_PIN1_STATUS0, .mask_base = WCD9335_INTR_PIN1_MASK0, .ack_base = WCD9335_INTR_PIN1_CLEAR0, - .type_base = WCD9335_INTR_LEVEL0, - .num_type_reg = 4, .num_regs = 4, .irqs = wcd9335_codec_irqs, .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs), + .config_base = wcd9335_config_regs, + .num_config_bases = ARRAY_SIZE(wcd9335_config_regs), + .num_config_regs = 4, + .set_type_config = regmap_irq_set_type_config_simple, }; static int wcd9335_parse_dt(struct wcd9335_codec *wcd) From patchwork Mon Jun 20 20:06:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF454C433EF for ; Wed, 22 Jun 2022 15:26:03 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 2B8DA1EDF; Wed, 22 Jun 2022 17:25:12 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 2B8DA1EDF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911562; bh=okrDuy0DsASAu8239mrCUF8XkolQHRyaQjDe059sY4o=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=OjYO5N8sxDvuXJ6FUKnbMAW2XYVABY2drF9VLrLycndqVd+OOLvPY3xNG1CW09Y/s rTWuUioVhVk6MD84pMideP6kBSEdfWI+cVOXlTVQr7OTlU3Gmx7x5A/solU8Hsj4fU h5XiS8hdOo8b5VwY4Gr7Nqsgufbg6uQnv8rySj20= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 7D9E8F80563; Wed, 22 Jun 2022 17:23:25 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id DF9C9F804D2; Mon, 20 Jun 2022 22:06:31 +0200 (CEST) Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 847E8F800E3 for ; Mon, 20 Jun 2022 22:06:27 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 847E8F800E3 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EJbtvC5h" Received: by mail-wr1-x42f.google.com with SMTP id s1so16072728wra.9 for ; Mon, 20 Jun 2022 13:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EX/yDVwKkfC5joprzjhLTLUj2n8x64TTg4RMNQ20jNw=; b=EJbtvC5hJvHxpndMkFlPD86W4NZOimlOhDeQWXXsnvu8LCn08/ZUypJbCVlZT8Zuhn XmUdbUWQxzrNNs2DmjZS3cX9l4SmZeoOAinDDjt7qIBZ1kZbLnv/kaRvrnevyMBMjeb4 hOXAaAWFkIccOi0rRaIQHvD9FbXJP6JG8+uUM2Yvgiq+4XMa45SLpysk/cPJy2kEz+5M XzYjPDhx4KLybpC23mko2FoWhrLe2DoqaS//+ApXLqEFVX/NLWz82gpyhjFvOFIuBnqD SrjohLlUiNBtgW5OAqfemvUQFWciS+bIq9Btr5bpWiH873KE5azsyZ1i9j1W55ltyC5w XtRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EX/yDVwKkfC5joprzjhLTLUj2n8x64TTg4RMNQ20jNw=; b=sDfXP8hSH7oabFlVwu7F2PsnxthKbRdxwk7OOcoMNtnAjU98/a6EIxne82JQ/O2wYg 0AMc6ohdgwkwqWC0wds2OsToVNnXSxr4zAaoDrrXrIbM0kjS+G6TDDnmRzgf+2liOoqb vIuP/+RvgxM6O/0aGAVbGrDo8N2UUIcaebIySjDyOB4gFyd0PMFUIrYVy4yZdV1SIhAx 7/ea0jhM2iHsfT3LM1B8eYf0nKvBNKLlVEG/C/2YlCIL2M5N9PwFlFMNuW+vXvduVo7w duR5YY46qzu2i9hO85lwT5cAx8YGdqke2qr7IPoYoHIumUi5Arx0a6U1OE8uCj22a8p8 epZA== X-Gm-Message-State: AJIora+cXrEYKJM6QZO0MG2GobURsI4/+xYQ4Xab3S6UciFjnhZ/eBC3 iVVBoqDqQCMPGB4PdcsanI0= X-Google-Smtp-Source: AGRyM1uZmrSpfQCxnF3FN/c4+CKx0AmJvG5Ujc+oe6FV8JjIcjgEvKjL58h/5RQFttDX69HrNrpXpw== X-Received: by 2002:a5d:4d52:0:b0:21b:93b4:6a2a with SMTP id a18-20020a5d4d52000000b0021b93b46a2amr3588083wru.576.1655755587154; Mon, 20 Jun 2022 13:06:27 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id n23-20020a05600c3b9700b0039c5224bfcbsm20984858wms.46.2022.06.20.13.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:26 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 08/49] sound: soc: codecs: wcd938x: Remove spurious type_base from irq chip Date: Mon, 20 Jun 2022 21:06:03 +0100 Message-Id: <20220620200644.1961936-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" This chip does not set num_type_regs or define any supported IRQ types, so regmap-irq can't configure its IRQ types. Including type_base in the chip definition is therefore redundant. Signed-off-by: Aidan MacDonald --- sound/soc/codecs/wcd938x.c | 1 - 1 file changed, 1 deletion(-) diff --git a/sound/soc/codecs/wcd938x.c b/sound/soc/codecs/wcd938x.c index c1b61b997f69..acba253b791e 100644 --- a/sound/soc/codecs/wcd938x.c +++ b/sound/soc/codecs/wcd938x.c @@ -1298,7 +1298,6 @@ static struct regmap_irq_chip wcd938x_regmap_irq_chip = { .num_regs = 3, .status_base = WCD938X_DIGITAL_INTR_STATUS_0, .mask_base = WCD938X_DIGITAL_INTR_MASK_0, - .type_base = WCD938X_DIGITAL_INTR_LEVEL_0, .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0, .use_ack = 1, .runtime_pm = true, From patchwork Mon Jun 20 20:06:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E90FC43334 for ; Wed, 22 Jun 2022 15:26:16 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id BDB331EE8; Wed, 22 Jun 2022 17:25:24 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz BDB331EE8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911574; bh=j8NvU2/YkYyLt/jWrjigSTazKQb0/+Mi3zVI+YV5ckk=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=mHHyvqWUgD4HQX0CGalNjvZo4OQ17eGo0r43AXKP50i2mmeWdsji65Pemf8xeem1T s9JPpyzjbB+MqKeTA/6LJ0gZf+8InFp30AiStdxk2ugbpHVnRwVZeo8244J0Edldth axYrfmALXpIJ7NwVQLFNSWvwKXx1ukl6rprxqK2M= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 0C495F80568; Wed, 22 Jun 2022 17:23:26 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 85EB0F804D2; Mon, 20 Jun 2022 22:06:35 +0200 (CEST) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 9C1F4F804DA for ; Mon, 20 Jun 2022 22:06:30 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 9C1F4F804DA Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VdNEnW4i" Received: by mail-wr1-x42a.google.com with SMTP id e25so12215275wrc.13 for ; Mon, 20 Jun 2022 13:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CygB1KehYAHqhpc4bRUhgcxf+zQL9loE7cQLl/MEP/k=; b=VdNEnW4i4C6kZGpiqp1Jxmc+HT2MVBw6IwavlCehBQXlv5QOH8TPwVeq3H4ho5YMpx H8exp7Pq3R8RMqC3UBwjz4B4XNaNN5lfob6sT6+PndMQfoaU+DTqcC6wBk5rfoCSNQCJ /25J++hcAVbS0URhiPSxzu20PkT4vyStw3QlwmbqipEVuj0SMfiZBMh7ShX9R9n4h95O 9crhgA7QEsaJW7A0sgHALhx1p9ncqoWinxadYQ4mbkrwCqLicK48miZo2piT71YFto5R e92szgit9CnwLu5DANwjGf3x1RqZ4wrj46ixAYyPN9ECBgT4l9bBF3FVNWT0DQBc63Y5 2+BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CygB1KehYAHqhpc4bRUhgcxf+zQL9loE7cQLl/MEP/k=; b=mzkhFZ7gqD+CA6hGd1qoQ6CBryvok5XgZibw7UVxNUmRLbT7EVIHQWjQbLCJbHNUer c+J/uSdfacm/3q9DONGEdMJpzAdyuvPZ1/R3sATpwmMs2un1/p4oRtZI0HxVc12gtiqS IxhmqEIb3d/QUQiZWUYP5V+fPCjhc3RAF6kyKemghEgd3PYSqvJSkFu6e+AYgmjFEP27 +dbtEN41uJpy3RWydRkw4s3N96hYG7t1FZ0CMDFhdJAAHMXSU7Ye8/SoHEry7B6RF0np r8SOr6Ph1LIjnvcYcWngdrDfpUwt16p0vnpzL7JrKnQd6UuNJZF5ABJ5vWwS8YTDlAYB nSuQ== X-Gm-Message-State: AJIora8EyHRMQHutjv4ZKzMtHMCogsL3ccE2YH7+4m8ac1GBSAtOM/d8 5gFakQtcSQcdIjsQ6iuajeE= X-Google-Smtp-Source: AGRyM1v/XOcLvn/YOZvKeR4GgDqyzG8bAWUAUx2H4/vrgHli6exwOFqzUpGDvK4ZhP7QI3IhQMp+Sw== X-Received: by 2002:a05:6000:1567:b0:217:abea:6a67 with SMTP id 7-20020a056000156700b00217abea6a67mr25796898wrz.305.1655755588840; Mon, 20 Jun 2022 13:06:28 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id a13-20020adffb8d000000b0021a3a87fda9sm12865573wrr.47.2022.06.20.13.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:28 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 09/49] mfd: max77650: Remove useless type_invert flag Date: Mon, 20 Jun 2022 21:06:04 +0100 Message-Id: <20220620200644.1961936-10-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The type_invert flag does nothing when type_in_mask is set, so get rid of it. Signed-off-by: Aidan MacDonald --- drivers/mfd/max77650.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mfd/max77650.c b/drivers/mfd/max77650.c index 777485a33bc0..3c07fcdd9d07 100644 --- a/drivers/mfd/max77650.c +++ b/drivers/mfd/max77650.c @@ -138,7 +138,6 @@ static const struct regmap_irq_chip max77650_irq_chip = { .status_base = MAX77650_REG_INT_GLBL, .mask_base = MAX77650_REG_INTM_GLBL, .type_in_mask = true, - .type_invert = true, .init_ack_masked = true, .clear_on_unmask = true, }; From patchwork Mon Jun 20 20:06:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96778C43334 for ; Wed, 22 Jun 2022 15:27:05 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id E06FA1FC9; Wed, 22 Jun 2022 17:26:13 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz E06FA1FC9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911624; bh=IQFbZ81Tkk/TwR3CoDrS75qztXU02oLstDsTVs67B0M=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=ur+DGfez4EsDo+4xEmbgIGRJ65mKe7xIHS/jRnPOTzH7zhkIx2dDcpfAHcUnG+L45 3Uy40wPO/Tz0HeKiDvCa6tFqx1pHJeDqsKWwHWtwZl/hqtynnkqhkKVqG3p0xMWSYW b+tfE8sZhHJB8+mE0KmVJo4kFr3P0ZpDSdEklLQY= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id A1670F8057D; Wed, 22 Jun 2022 17:23:27 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 3473BF804E5; Mon, 20 Jun 2022 22:06:38 +0200 (CEST) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 153C0F804D8 for ; Mon, 20 Jun 2022 22:06:32 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 153C0F804D8 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Z5NU7sru" Received: by mail-wm1-x32c.google.com with SMTP id m125-20020a1ca383000000b0039c63fe5f64so6210561wme.0 for ; Mon, 20 Jun 2022 13:06:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NSMrw3v+dSzormMBlFnVqYO9Ybr8y9x05CczXbq+F0o=; b=Z5NU7srurHjdW0PF4O55elxfUZBgUDk5YPFMpg1RdqsrfEMk7qqDL8ep246OtTDiC4 6ju1VuX4sBfj/74uye9hCH9gCwZwRwcHtZnxI5fARi8+LKkAfdtx6MsYh7Pd2V1TJjz4 mBfORf4k+PothfafLBhj4toSDqA8T3fphY7zdnpKPOEXFqu9HOx5TIDgCjq0SHrD5+CC INWDLlQYTChLHohDgNjGViE1FGyoeWG6e0guIJwG/DdPTqvgerAxAxO0lis9868OmZEE CKl/wzAj2Z91E8tmS3NFKhGL/f5b2L127K+Vv0HRjyl36ABwGlxo+z8eyN1C5YXCAV/1 VXTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NSMrw3v+dSzormMBlFnVqYO9Ybr8y9x05CczXbq+F0o=; b=EHz2uTWqRQLICAsswGWSVEuLRf1d4aqiEVOwiDayw5M4tVrTFPkIOpdrfcwjKtqLFj wLReMMlWXDfRfwgUKAGo/57x1pDjxDJfJRLmNX4haauah4huMh9u77i7d1oTxYExBjY5 Dd7yHbxfV4Fqz2+7DB/0KV9lPpEH6nLLhDTNG0aUl9feXaj5tvYIuDNjmcCXVjUU1cW5 hGGsvFkUUNoFC+EkMpznl36CACbB56Ef94VGkB9EdG8Z5V6tJS6LcP5CBAdfFl1kr6Pv Ieh20BYY48zuzzvNmU6F3i3+Lu1ZHIAbYItHqJWZVm0L1Q8BHm0LWHU4pwm1FBaEQ58z ii7w== X-Gm-Message-State: AJIora86dmR85WqJ3c1VNw1tbMq6J54W5R6Qsit2gWd64dpF9zDWCTB0 mMi0dM2Sm2UV1QF+QWKrGfE= X-Google-Smtp-Source: AGRyM1v4nGqgjAhTskzkWcEAA3t4wJpSGRdFd7rK8rtyVQboY6GtKy9ysgj/zJBTNIGbPGeagfeUtA== X-Received: by 2002:a05:600c:3d18:b0:39c:474c:eb with SMTP id bh24-20020a05600c3d1800b0039c474c00ebmr26181880wmb.87.1655755590681; Mon, 20 Jun 2022 13:06:30 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id u25-20020adfa199000000b002184a3a3641sm14724036wru.100.2022.06.20.13.06.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:30 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 10/49] regmap-irq: Remove virtual registers support Date: Mon, 20 Jun 2022 21:06:05 +0100 Message-Id: <20220620200644.1961936-11-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Virtual registers can be removed, since config registers implement the same functionality. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 42 -------------------------------- include/linux/regmap.h | 9 ------- 2 files changed, 51 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index be35f2e41b8c..5a3e255816fd 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -38,7 +38,6 @@ struct regmap_irq_chip_data { unsigned int *wake_buf; unsigned int *type_buf; unsigned int *type_buf_def; - unsigned int **virt_buf; unsigned int **config_buf; unsigned int irq_reg_stride; @@ -218,20 +217,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) } } - if (d->chip->num_virt_regs) { - for (i = 0; i < d->chip->num_virt_regs; i++) { - for (j = 0; j < d->chip->num_regs; j++) { - reg = sub_irq_reg(d, d->chip->virt_reg_base[i], - j); - ret = regmap_write(map, reg, d->virt_buf[i][j]); - if (ret != 0) - dev_err(d->map->dev, - "Failed to write virt 0x%x: %d\n", - reg, ret); - } - } - } - for (i = 0; i < d->chip->num_config_bases; i++) { for (j = 0; j < d->chip->num_config_regs; j++) { reg = sub_irq_reg(d, d->chip->config_base[i], j); @@ -346,10 +331,6 @@ static int regmap_irq_set_type(struct irq_data *data, unsigned int type) return -EINVAL; } - if (d->chip->set_type_virt) - return d->chip->set_type_virt(d->virt_buf, type, data->hwirq, - reg); - return 0; } @@ -782,24 +763,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, goto err_alloc; } - if (chip->num_virt_regs) { - /* - * Create virt_buf[chip->num_extra_config_regs][chip->num_regs] - */ - d->virt_buf = kcalloc(chip->num_virt_regs, sizeof(*d->virt_buf), - GFP_KERNEL); - if (!d->virt_buf) - goto err_alloc; - - for (i = 0; i < chip->num_virt_regs; i++) { - d->virt_buf[i] = kcalloc(chip->num_regs, - sizeof(unsigned int), - GFP_KERNEL); - if (!d->virt_buf[i]) - goto err_alloc; - } - } - if (chip->num_config_bases && chip->num_config_regs) { /* * Create config_buf[num_config_bases][num_config_regs] @@ -989,11 +952,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, kfree(d->mask_buf); kfree(d->status_buf); kfree(d->status_reg_buf); - if (d->virt_buf) { - for (i = 0; i < chip->num_virt_regs; i++) - kfree(d->virt_buf[i]); - kfree(d->virt_buf); - } if (d->config_buf) { for (i = 0; i < chip->num_config_bases; i++) kfree(d->config_buf[i]); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index e48d65756fb4..bb8c89a83b51 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1459,7 +1459,6 @@ struct regmap_irq_sub_irq_map { * Using zero value is possible with @use_ack bit. * @wake_base: Base address for wake enables. If zero unsupported. * @type_base: Base address for irq type. If zero unsupported. - * @virt_reg_base: Base addresses for extra config regs. * @config_base: Base address for IRQ type config regs. If null unsupported. * @irq_reg_stride: Stride to use for chips where registers are not contiguous. * @init_ack_masked: Ack all masked interrupts once during initalization. @@ -1486,8 +1485,6 @@ struct regmap_irq_sub_irq_map { * assigned based on the index in the array of the interrupt. * @num_irqs: Number of descriptors. * @num_type_reg: Number of type registers. - * @num_virt_regs: Number of non-standard irq configuration registers. - * If zero unsupported. * @type_reg_stride: Stride to use for chips where type registers are not * contiguous. * @num_config_bases: Number of config base registers. @@ -1496,8 +1493,6 @@ struct regmap_irq_sub_irq_map { * before regmap_irq_handler process the interrupts. * @handle_post_irq: Driver specific callback to handle interrupt from device * after handling the interrupts in regmap_irq_handler(). - * @set_type_virt: Driver specific callback to extend regmap_irq_set_type() - * and configure virt regs. * @set_type_config: Callback used for configuring irq types. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. @@ -1520,7 +1515,6 @@ struct regmap_irq_chip { unsigned int ack_base; unsigned int wake_base; unsigned int type_base; - unsigned int *virt_reg_base; const unsigned int *config_base; unsigned int irq_reg_stride; bool mask_writeonly:1; @@ -1543,15 +1537,12 @@ struct regmap_irq_chip { int num_irqs; int num_type_reg; - int num_virt_regs; int num_config_bases; int num_config_regs; unsigned int type_reg_stride; int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); - int (*set_type_virt)(unsigned int **buf, unsigned int type, - unsigned long hwirq, int reg); int (*set_type_config)(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx); void *irq_drv_data; From patchwork Mon Jun 20 20:06:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEE54C43334 for ; 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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id a17-20020a056000101100b00213465d202esm14269010wrx.46.2022.06.20.13.06.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:31 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 11/49] regmap-irq: Remove old type register support, refactor Date: Mon, 20 Jun 2022 21:06:06 +0100 Message-Id: <20220620200644.1961936-12-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Now that all users have been converted to use config registers for setting IRQ types, the old type register handling code can be removed. Also refactor the parts related to type_in_mask. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 102 +++++-------------------------- include/linux/regmap.h | 4 -- 2 files changed, 14 insertions(+), 92 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 5a3e255816fd..85d7fd4e07d7 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -36,8 +36,7 @@ struct regmap_irq_chip_data { unsigned int *mask_buf; unsigned int *mask_buf_def; unsigned int *wake_buf; - unsigned int *type_buf; - unsigned int *type_buf_def; + unsigned int *mask_type_buf; unsigned int **config_buf; unsigned int irq_reg_stride; @@ -199,24 +198,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) } } - /* Don't update the type bits if we're using mask bits for irq type. */ - if (!d->chip->type_in_mask) { - for (i = 0; i < d->chip->num_type_reg; i++) { - if (!d->type_buf_def[i]) - continue; - reg = sub_irq_reg(d, d->chip->type_base, i); - if (d->chip->type_invert) - ret = regmap_irq_update_bits(d, reg, - d->type_buf_def[i], ~d->type_buf[i]); - else - ret = regmap_irq_update_bits(d, reg, - d->type_buf_def[i], d->type_buf[i]); - if (ret != 0) - dev_err(d->map->dev, "Failed to sync type in %x\n", - reg); - } - } - for (i = 0; i < d->chip->num_config_bases; i++) { for (j = 0; j < d->chip->num_config_regs; j++) { reg = sub_irq_reg(d, d->chip->config_base[i], j); @@ -259,11 +240,11 @@ static void regmap_irq_enable(struct irq_data *data) * * If the interrupt we're enabling defines any supported types * then instead of using the regular mask bits for this interrupt, - * use the value previously written to the type buffer at the + * use the value previously written to the mask_type buffer at the * corresponding offset in regmap_irq_set_type(). */ if (d->chip->type_in_mask && irq_data->type.types_supported) - mask = d->type_buf[reg] & irq_data->mask; + mask = d->mask_type_buf[reg] & irq_data->mask; else mask = irq_data->mask; @@ -287,50 +268,21 @@ static int regmap_irq_set_type(struct irq_data *data, unsigned int type) struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); struct regmap *map = d->map; const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); - int reg; const struct regmap_irq_type *t = &irq_data->type; + unsigned int reg; - if ((t->types_supported & type) != type) + if ((irq_data->type.types_supported & type) != type) return 0; reg = t->type_reg_offset / map->reg_stride; + if (d->chip->type_in_mask) + return regmap_irq_set_type_config_simple(&d->mask_type_buf, + type, irq_data, reg); if (d->chip->set_type_config) return d->chip->set_type_config(d->config_buf, type, irq_data, reg); - if (t->type_reg_mask) - d->type_buf[reg] &= ~t->type_reg_mask; - else - d->type_buf[reg] &= ~(t->type_falling_val | - t->type_rising_val | - t->type_level_low_val | - t->type_level_high_val); - switch (type) { - case IRQ_TYPE_EDGE_FALLING: - d->type_buf[reg] |= t->type_falling_val; - break; - - case IRQ_TYPE_EDGE_RISING: - d->type_buf[reg] |= t->type_rising_val; - break; - - case IRQ_TYPE_EDGE_BOTH: - d->type_buf[reg] |= (t->type_falling_val | - t->type_rising_val); - break; - - case IRQ_TYPE_LEVEL_HIGH: - d->type_buf[reg] |= t->type_level_high_val; - break; - - case IRQ_TYPE_LEVEL_LOW: - d->type_buf[reg] |= t->type_level_low_val; - break; - default: - return -EINVAL; - } - return 0; } @@ -682,7 +634,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, struct regmap_irq_chip_data *d; int i; int ret = -ENOMEM; - int num_type_reg; u32 reg; u32 unmask_offset; @@ -750,16 +701,10 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, goto err_alloc; } - num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg; - if (num_type_reg) { - d->type_buf_def = kcalloc(num_type_reg, - sizeof(unsigned int), GFP_KERNEL); - if (!d->type_buf_def) - goto err_alloc; - - d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int), - GFP_KERNEL); - if (!d->type_buf) + if (chip->type_in_mask) { + d->mask_type_buf = kcalloc(chip->num_regs, + sizeof(unsigned int), GFP_KERNEL); + if (!d->mask_type_buf) goto err_alloc; } @@ -899,23 +844,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, } } - if (chip->num_type_reg && !chip->type_in_mask) { - for (i = 0; i < chip->num_type_reg; ++i) { - reg = sub_irq_reg(d, d->chip->type_base, i); - - ret = regmap_read(map, reg, &d->type_buf_def[i]); - - if (d->chip->type_invert) - d->type_buf_def[i] = ~d->type_buf_def[i]; - - if (ret) { - dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n", - reg, ret); - goto err_alloc; - } - } - } - if (irq_base) d->domain = irq_domain_create_legacy(fwnode, chip->num_irqs, irq_base, 0, @@ -945,8 +873,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, err_domain: /* Should really dispose of the domain but... */ err_alloc: - kfree(d->type_buf); - kfree(d->type_buf_def); + kfree(d->mask_type_buf); kfree(d->wake_buf); kfree(d->mask_buf_def); kfree(d->mask_buf); @@ -1020,8 +947,7 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) } irq_domain_remove(d->domain); - kfree(d->type_buf); - kfree(d->type_buf_def); + kfree(d->mask_type_buf); kfree(d->wake_buf); kfree(d->mask_buf_def); kfree(d->mask_buf); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index bb8c89a83b51..879afdc81526 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1458,7 +1458,6 @@ struct regmap_irq_sub_irq_map { * @ack_base: Base ack address. If zero then the chip is clear on read. * Using zero value is possible with @use_ack bit. * @wake_base: Base address for wake enables. If zero unsupported. - * @type_base: Base address for irq type. If zero unsupported. * @config_base: Base address for IRQ type config regs. If null unsupported. * @irq_reg_stride: Stride to use for chips where registers are not contiguous. * @init_ack_masked: Ack all masked interrupts once during initalization. @@ -1484,7 +1483,6 @@ struct regmap_irq_sub_irq_map { * @irqs: Descriptors for individual IRQs. Interrupt numbers are * assigned based on the index in the array of the interrupt. * @num_irqs: Number of descriptors. - * @num_type_reg: Number of type registers. * @type_reg_stride: Stride to use for chips where type registers are not * contiguous. * @num_config_bases: Number of config base registers. @@ -1514,7 +1512,6 @@ struct regmap_irq_chip { unsigned int unmask_base; unsigned int ack_base; unsigned int wake_base; - unsigned int type_base; const unsigned int *config_base; unsigned int irq_reg_stride; bool mask_writeonly:1; @@ -1536,7 +1533,6 @@ struct regmap_irq_chip { const struct regmap_irq *irqs; int num_irqs; - int num_type_reg; int num_config_bases; int num_config_regs; unsigned int type_reg_stride; From patchwork Mon Jun 20 20:06:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBFDFC433EF for ; Wed, 22 Jun 2022 15:26:50 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 2AE361E74; Wed, 22 Jun 2022 17:25:59 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 2AE361E74 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911609; bh=z7ZwsKqeKSWPYOB0EYoi34bX/UVdC4kOWeg+hmpmleo=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=BX+ag81iLq8+Bu+ytDbirIpGs571v7B3uBOt9ri+p0SImXTYJ4oJxALoituLwT7hr 7qTLKaLxnl+swjzpghAaIXJm9z0Sx5sJj21WRW1ImNgsFcTWuY0lkih4Dc4JGkAypJ T6Hw3GYJUl4jk3t3v1wejsnn1apfPhvI3ev0jqLI= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 114DCF8057C; Wed, 22 Jun 2022 17:23:27 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 7803DF804DA; Mon, 20 Jun 2022 22:06:37 +0200 (CEST) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 28EBEF800E3 for ; Mon, 20 Jun 2022 22:06:34 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 28EBEF800E3 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="T/UvuXuo" Received: by mail-wr1-x42a.google.com with SMTP id g27so9431561wrb.10 for ; Mon, 20 Jun 2022 13:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ygggAhOijcuCf3qt1rizt96GNeoo90FsvWvR8LV1nyI=; b=T/UvuXuobHYQjUmOyYbANq63UlOF39LoQ9F0gifyzekhcyCOQUypCEyXG/OKpb2La8 Q6xZerE2gogPQTVjnWE4wmzodDreHkzH5Hob1Yofhw+6nVU3v+x19k/F+1fzWd07Nhyx t3dlqulqzXj03B/a7eof6RPLvdFSbbKgQ0qPPyyfUc0DvtgH5rSWtXFv/QKk3GFNsmgf ba5ere/Jpb7EyG3rOfQF0QhkkW/aBY4cYS4Nq+Vs12xBWeLC+F11zEPyoGk+7XAQtopt 0onYAtqYMepxk8EG5VyJd6DPsfXoBs96h/qfy/t4bsS9pyheZRo3qyXWG31pXvk7VX4q +KwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ygggAhOijcuCf3qt1rizt96GNeoo90FsvWvR8LV1nyI=; b=0jEGs5zulqS1DwgJtBmE+04dJJGihKVDyZ4XG6eivwJadn9Zy/GMashqURYom2Hy4n ZgpAYV0yJdWb2KGtBi+nUX41pTUFoviK3Pecy7g4Q+tjy5Y0hPqpNmNSJFeqDcfs/VF9 WkBHAojsYWqwAHIkfjFaiXdUbTiaid6ds3Ux265NkPUgPRE2pm30SzdwBke1307uqLZJ 0tqjyLCJRBsjGU+yhF3vT1qqQ5oQs89apxzGXEn+6l144ZUMmKiwy7AcmgkAaWsUh4ol KGz1yCx9hatjNGRTbR9J7RYTwqrt8c4B5JfoOqCzFPpts5sjtfjxY3/DjswIQoRINAQg L7Zw== X-Gm-Message-State: AJIora8P1HtBfNGUR2xyocQz0GSt3q6qgOwp0agDtKtJ+zkrIOFBIgUw cKFtHZ07aUBneIorLyOQYos= X-Google-Smtp-Source: AGRyM1solEebsJ8aWFaYBBFyec3sD94nnN3uwK9ZwQuWOqy8ZNWOPbTCC9XYFknZ9HYg3JgppifEhQ== X-Received: by 2002:adf:ef42:0:b0:21b:8e58:f24b with SMTP id c2-20020adfef42000000b0021b8e58f24bmr7538227wrp.257.1655755593841; Mon, 20 Jun 2022 13:06:33 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id a17-20020adffad1000000b0021b8749728dsm8178248wrs.73.2022.06.20.13.06.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:33 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 12/49] regmap-irq: Remove unused type_reg_stride field Date: Mon, 20 Jun 2022 21:06:07 +0100 Message-Id: <20220620200644.1961936-13-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" It appears that no chip ever required a nonzero type_reg_stride and commit 1066cfbdfa3f ("regmap-irq: Extend sub-irq to support non-fixed reg strides") broke support. Just remove the field. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 6 ------ include/linux/regmap.h | 3 --- 2 files changed, 9 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 85d7fd4e07d7..b24818ad36e6 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -40,7 +40,6 @@ struct regmap_irq_chip_data { unsigned int **config_buf; unsigned int irq_reg_stride; - unsigned int type_reg_stride; bool clear_status:1; }; @@ -738,11 +737,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, else d->irq_reg_stride = 1; - if (chip->type_reg_stride) - d->type_reg_stride = chip->type_reg_stride; - else - d->type_reg_stride = 1; - if (!map->use_single_read && map->reg_stride == 1 && d->irq_reg_stride == 1) { d->status_reg_buf = kmalloc_array(chip->num_regs, diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 879afdc81526..1966ad4d0fa5 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1483,8 +1483,6 @@ struct regmap_irq_sub_irq_map { * @irqs: Descriptors for individual IRQs. Interrupt numbers are * assigned based on the index in the array of the interrupt. * @num_irqs: Number of descriptors. - * @type_reg_stride: Stride to use for chips where type registers are not - * contiguous. * @num_config_bases: Number of config base registers. * @num_config_regs: Number of config registers for each config base register. * @handle_pre_irq: Driver specific callback to handle interrupt from device @@ -1535,7 +1533,6 @@ struct regmap_irq_chip { int num_config_bases; int num_config_regs; - unsigned int type_reg_stride; int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); From patchwork Mon Jun 20 20:06:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00CA6C433EF for ; Wed, 22 Jun 2022 15:27:25 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 20F011FB4; Wed, 22 Jun 2022 17:26:34 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 20F011FB4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911644; bh=JM5XVZht+Tn/1kWPdhgXQOf6Y9z/rZYKmQ5arX+rayA=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=uJJQX7YGgYAFXqcKqDnSnRvimZueD5GeiHP0s5BH9K8P6be5OVjnKHFa1ep2BYX2U uL4HIP5OTAOApp7fQkmfjO4Ov4eD87x5IaVrnEnDBer5hmV9AJr0U1TcGr0+K7mm86 vfc+JhIxLsMNuOXOrxPnzQiikN0cHVL0I2mW9olA= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 56460F805A1; Wed, 22 Jun 2022 17:23:28 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id B52D4F804EB; Mon, 20 Jun 2022 22:06:41 +0200 (CEST) Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 045C8F804D8 for ; Mon, 20 Jun 2022 22:06:36 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 045C8F804D8 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iAVKi4f8" Received: by mail-wr1-x429.google.com with SMTP id o16so16088316wra.4 for ; Mon, 20 Jun 2022 13:06:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NpYblgk0QSEipNVW12nK1FeMQGvN8soBnfpEkcmUf1I=; b=iAVKi4f8I7CLeg4ffvFzsvKkDzx2DfoiAbr47iYacvEU+s3bdgepP+twUMbdjqFjZN HP9GhewZ0kBzZGLj0hMJgiO7cc3Vd6E/UF8i8c0andQvvQgzYryRgJ2xWzPE8ISGsHKU 3jAsd30KJ0Vgc2BjN5czd14edV+jCCHuBh/c8p0HdAHMup5HduI34U/Ox+duIKPJ+3ag kMTEimL4vWw+NINiHeamf6NkIE0VHr/u3/NsESG0RHXMSG5UD9ZPmUG7ASDj10MCe43O AkDOSBGlCU7xbJuDGODEpXltkmTY8pHt9UDDKC8kna2c/yvWdCAx6ck4c/uz1z2HYYQ6 wUtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NpYblgk0QSEipNVW12nK1FeMQGvN8soBnfpEkcmUf1I=; b=e1vM3uPjjI2Xe4AynDombqo5L7gCmpVYyOJCve9OtZGIeaQ3mrbv6FaPIn4fmPkGba 1heLbMW3BWSu5bUgTq1619c29ShTPHVlMOXzLqfnxnOYCr744lL6Hb1Cwmdjlc5j3AiK NrALbaLmvDANcxQWpm2tCsqYtfomLDUXV0je+LsicpXEdiwY3eP9L6h3sVbH1tH3Y/jL KSe2aBD00b3/IL8QCjm79ADn1JNDDYBJe1dlf+AuFO1IW1t7keXlm8x3yCFZgstqX2WP hLalBPgizWNH/6KQkO4hpt2tcqoQiBISFM63vGNUA+p93v12mB/rvx8feY0xo1YfEw2S K6kQ== X-Gm-Message-State: AJIora+1b9SZHGp9PL513QjMU9Bbr47Jc5DjG1NT2byKYDizGnFY8qnX HPqpu1A9hBc/UhiHaP1LhEg= X-Google-Smtp-Source: AGRyM1uneR86manlptXeALcQUO9hJesML7Bpy1KKOUEomIro61DKoiDecYWOPz8k3Wd1mtwzsz07yA== X-Received: by 2002:a05:6000:1052:b0:21b:927c:1559 with SMTP id c18-20020a056000105200b0021b927c1559mr4204605wrx.303.1655755595143; Mon, 20 Jun 2022 13:06:35 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id e16-20020adfdbd0000000b0021b91ec8f6esm2936708wrj.67.2022.06.20.13.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:34 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 13/49] regmap-irq: Remove unused type_invert flag Date: Mon, 20 Jun 2022 21:06:08 +0100 Message-Id: <20220620200644.1961936-14-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" No chip has ever required this flag except for the max77650 where it didn't have any effect. Drop it. The code that checked for it has already been removed. Signed-off-by: Aidan MacDonald --- include/linux/regmap.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 1966ad4d0fa5..ee2567a0465c 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1466,7 +1466,6 @@ struct regmap_irq_sub_irq_map { * @ack_invert: Inverted ack register: cleared bits for ack. * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts. * @wake_invert: Inverted wake register: cleared bits are wake enabled. - * @type_invert: Invert the type flags. * @type_in_mask: Use the mask registers for controlling irq type. For * interrupts defining type_rising/falling_mask use mask_base * for edge configuration and never update bits in type_base. @@ -1520,7 +1519,6 @@ struct regmap_irq_chip { bool clear_ack:1; bool wake_invert:1; bool runtime_pm:1; - bool type_invert:1; bool type_in_mask:1; bool clear_on_unmask:1; bool not_fixed_stride:1; From patchwork Mon Jun 20 20:06:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2824C433EF for ; Wed, 22 Jun 2022 15:28:07 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 304591FD6; Wed, 22 Jun 2022 17:27:16 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 304591FD6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911686; bh=4mMKOa/8N28uUEqbmONS7x/kBrogHRvMZdWylXpP0tA=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=YxJ/rdET0aus+ss4JUaNSXA6XfDCFqQneSDKAvZ9tFjIWCIRDxIfAXI/MpdCJsp6T CoY0IGAQ9B0POBi/FVm7sJPkDgiLIi8t2Ivu9RkrRMvc+a2W3GTrpvE1O2P0w67J8O xUMx3DXddmgHHa3UWyO+NKMpAAgT8/z0D35uJCu0= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id F3CC1F805B6; Wed, 22 Jun 2022 17:23:29 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 6DE60F804E5; Mon, 20 Jun 2022 22:06:44 +0200 (CEST) Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id CA91CF804D8 for ; Mon, 20 Jun 2022 22:06:38 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz CA91CF804D8 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="A+HDr9UU" Received: by mail-wm1-x332.google.com with SMTP id x6-20020a1c7c06000000b003972dfca96cso6194028wmc.4 for ; Mon, 20 Jun 2022 13:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+NtcVbwET9acvq+sAYxoy+CjdvzW22WJrtUFi1dmUOo=; b=A+HDr9UU7+WRxYQh+og339fpLCReWCpP3YFgyupAlmxOcZBf7A6aFnN8naHelyc52s wQK8Fy9G6v6mTrGSQG4iRbkz5YauYi4iPPwJMQ1JvKJvozZ8vtLRWwHh4bZf1gWdX2JC dbwqJKti3GJ9HNo1vXGhcyksOzCb4wnGEGjB9WKXRA8144i5ltsXiu2qsbBUMRpGeiKM foGh+rMJtGnYFLs3jAHQB2MuzI/dNK6UnFensNutj1IivbApMFbM7lKCQeTK27rVsLY0 i4E+b9E7gLbrO8WdSQ5sENJyJXaP1cu0PzOoAW96YwnClCEE3EdUU+uTD9Lm7PL5cykC bC6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+NtcVbwET9acvq+sAYxoy+CjdvzW22WJrtUFi1dmUOo=; b=m+jF09Fnh+6uApf0X/0tHmfbaQ7M0xhVUwVIvNIP0c/7jtYE2PvpNLsxW/RT1S+FWB AdS4j7Ib5hetApjGHw5nFIyGaBrO4Br7p8RO0yHffnxHOhTt+Rd3Gc+YZ2F7BPdUmAvr zB0VRqg6hsxRm+XGbMy6LYpG7hEFTVW+Xa8oUFt0sLmGtQlPPtdbzj9fCLHDgv/Uk9CX 7vPjBaPpi7OBM9YMws/8epixrUjTFK2IJqaHd2Gs+b2GARnyleqXqQCQAAxMRJ4oQNtE aFi0XlecAuYDT5cWVVdo1bzCdv2dGr2lxmGJAjPjQEnmy3Q5vaLvoKUfdKgi2xWrYxTE Eq2w== X-Gm-Message-State: AJIora87Aph2DT5NXyzxUWJdEidlE3MLrmeVLfFw+dmLnkVSxnlkjyyJ zHRdAPe824j5hVAzSLzydq8= X-Google-Smtp-Source: AGRyM1uQGdQ7m3OGY9UqaMyRP6uDRepmxOPNYfAd9XL91yLtMli/B6mx4CKZxfd/noc8TeLSorNR9Q== X-Received: by 2002:a05:600c:1547:b0:39c:804c:dc23 with SMTP id f7-20020a05600c154700b0039c804cdc23mr26538403wmg.23.1655755596798; Mon, 20 Jun 2022 13:06:36 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id l15-20020a05600c2ccf00b003974a00697esm20182858wmc.38.2022.06.20.13.06.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:36 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 14/49] regmap-irq: Do not use regmap_irq_update_bits() for wake regs Date: Mon, 20 Jun 2022 21:06:09 +0100 Message-Id: <20220620200644.1961936-15-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" regmap_irq_update_bits() is misnamed and should only be used for updating mask registers, since it checks the mask_writeonly flag. As there are no users of mask_writeonly, it is safe to replace the wake register updates with regmap_update_bits(). Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index b24818ad36e6..dd22d13c54c8 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -157,11 +157,11 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg = sub_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { if (d->chip->wake_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->wake_buf[i]); else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->wake_buf[i]); if (ret != 0) @@ -823,11 +823,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, reg = sub_irq_reg(d, d->chip->wake_base, i); if (chip->wake_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], 0); else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->wake_buf[i]); if (ret != 0) { From patchwork Mon Jun 20 20:06:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B37DC43334 for ; Wed, 22 Jun 2022 15:27:38 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 4F2901F5F; Wed, 22 Jun 2022 17:26:46 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 4F2901F5F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911656; bh=N6oB4qPbpYOk6Do0f3cS+xDSyLYwiCMQhcR835EoURs=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=ts+vR90DmoqZ+Zk2A0sLS+CBT+84+6kLBTtarGmXKPuSgRtWXb2GgdnVbJgyMyhjU jZGsMN1KgFpPsFcHpwJGohV7oXgRPI4SL/mjZffpmlY2TkMC1fswod8M60nff8dteE UeoUkbrbpw3jzwpWUYk/Ti/xHRMCwTt8U1gu5+Vk= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id DE659F805A9; Wed, 22 Jun 2022 17:23:28 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id CC8E7F804E5; Mon, 20 Jun 2022 22:06:42 +0200 (CEST) Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 10073F800CB for ; Mon, 20 Jun 2022 22:06:39 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 10073F800CB Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gfHGkEQo" Received: by mail-wr1-x42c.google.com with SMTP id q9so16079355wrd.8 for ; Mon, 20 Jun 2022 13:06:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eYKul7O4rkuRHadVgAD9GkF5EF0/tHVMEgyPNxDHsC8=; b=gfHGkEQotdDXzonMB5rbM3c8h6BVBrRvbtHhDjj8TB7PUfzKOirNkdHY6GRUcU3QOh pN3K3EMybUVH+S6paaWqW87mojZHxKV/KVv6mbG0MfLyFrJiMUS8aEEqAvLcWCbt6l/P Hzm7Ul+OYaXZyv/zNw15FgCOHKUCC7ntnW4BdzAX7j1i0rwhvAYiIhbdm+UfaPQ12HgW /Ba3wUF9pXtUbhcj50Zvj7lQx6eqKf5c0AarPVaEOvSYvWp73IjYJvOHQOtJ9XQF3QAI uc7N5zEeDGCklg2w1zbzB14CeQdszSSXX0bBBbgpTOXk4/oeMs384ZrqD+jYJS8NiWaQ MGvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eYKul7O4rkuRHadVgAD9GkF5EF0/tHVMEgyPNxDHsC8=; b=e+m0QsFO499N37ukuf9LQLoFX8c3S1KMXZEidJE/cFds1wg2YpqiZu/Ufwl/0aVcm5 18xrm4BedFmWYZmVfVt4ryNLHY5GxqhMhiaMAXz+2JXsFyvLNfJ+LpKOgpzgxlYttFU/ efZoc2o9GHwHvVW00GpNK7f5/yuJjiapHbkbuhaBW1FZqX5kqvoA9K2q4f2xUjBHY9s9 l3JoiOp9x/f9eEAiB6xeLtF/swD7K9adgL2ummom/jdM3nKCXl3FUJJZg2K73OQPIqej mWV6bc+sgGawY2gJvIsdqqdSn3B6pJyyFsX5dHmXsxsfW9jo3d1Xv3bO5mYKPw2MkkbI wujA== X-Gm-Message-State: AJIora+BF9y/aSP1RJX3BJZZidtvEOE/tlAy+p2VBaX/4gifUXfnrLBQ FBwE98klbzu4ppiy0OLURuw= X-Google-Smtp-Source: AGRyM1syc7S1LTS1FFXH6QNulnGOQO1vhdeYnisKeurGdpZwcIyfiJ171d1MMzBPPFFYg3HyKCPoOw== X-Received: by 2002:a5d:410a:0:b0:21b:9549:e151 with SMTP id l10-20020a5d410a000000b0021b9549e151mr2036808wrp.702.1655755598450; Mon, 20 Jun 2022 13:06:38 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id t2-20020a1c4602000000b0039db60fa340sm19508415wma.33.2022.06.20.13.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:37 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 15/49] regmap-irq: Change the behavior of mask_writeonly Date: Mon, 20 Jun 2022 21:06:10 +0100 Message-Id: <20220620200644.1961936-16-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" No drivers currently use mask_writeonly, and in its current form it seems a bit misleading. When set, mask registers will be updated with regmap_write_bits() instead of regmap_update_bits(), but regmap_write_bits() still does a read-modify-write under the hood. It's not a write-only operation. Performing a simple regmap_write() is probably more useful, since it can be used for chips that have separate set & clear registers for controlling mask bits. Such registers are normally volatile and read as 0, so avoiding a register read minimizes bus traffic. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index dd22d13c54c8..4c0d7f7aa544 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -84,7 +84,7 @@ static int regmap_irq_update_bits(struct regmap_irq_chip_data *d, unsigned int val) { if (d->chip->mask_writeonly) - return regmap_write_bits(d->map, reg, mask, val); + return regmap_write(d->map, reg, val & mask); else return regmap_update_bits(d->map, reg, mask, val); } From patchwork Mon Jun 20 20:06:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0420CC433EF for ; Wed, 22 Jun 2022 15:27:50 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 55F8D1FCD; Wed, 22 Jun 2022 17:26:59 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 55F8D1FCD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911669; bh=gMNbHY29UPLkdXChiQNgYIVLZhcUFBbBbZ0ffSudAAA=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=LOAaVTewn0hYFGvrMevi0w4AgWuMOgOHX7caLoG3VhKGnHuqBiXmZy78Np4a/anYs A0zgCYM80V29v5CsG5IAdMEDxqxr2BtZSHbMvC4ZxFjEtmpJFCylNZbXBB9xI/uaZn ubKySDyOClH3baNlP2hvvK+X/ZXs9jEiFVXTeyCc= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 6B1CCF805B2; Wed, 22 Jun 2022 17:23:29 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 54D9CF804E5; Mon, 20 Jun 2022 22:06:43 +0200 (CEST) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 5F9ABF804DA for ; Mon, 20 Jun 2022 22:06:40 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 5F9ABF804DA Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="j2RQqZvh" Received: by mail-wr1-x42a.google.com with SMTP id e25so12215275wrc.13 for ; Mon, 20 Jun 2022 13:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A1yO+P1r84NYRYcFw/ZOtSs0+i9q2Gv8RY8Jy0yOWqY=; b=j2RQqZvh6APhdsK/EoTEu81N6Pul31dRgCB3yZd8hs5x1U3Wtqcpi2IyHAfCICffHg gRE46BYS28U7XDvZvtUKB6Bkt51LTKNLuZl3ptMzn6BQlBgLD2r3jh/R/AjmK32xBhB/ 0LpqqAVt8CRLw8siXXmzBnqgCtafznYB6s/GT5pjpaL3Ybu6ff4EmEAU0UeweWfDlu9D gOHJaQkTCVmjnZ/VC5kfoHwVeu8ak+VVcbBIvos7fbcasrp9o1zr3tS8GqZqPBD0EZVy 6K+rt8doOLqgDBdCB8rSjJnqOboGjisOhkwGg2ROmQbfj+bRGDs7mmQs1WJsKO3Yyqid O2RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A1yO+P1r84NYRYcFw/ZOtSs0+i9q2Gv8RY8Jy0yOWqY=; b=Bo0A3xTJMqI3swdqWZIqdEkI/P63QWbrsp0sGXHu6l111QLxB27wqwiqXHkJBKZBI5 JrL8jeD7gM9Hzs1Np+7sroCojNCliKzORd6KzxHrnz4NBqrCW95zXlop+LXxacT3zZBB LbfO8/nWH/lNTRutcmuc9cieBokxvsoIHVt5shNVhp2byenU5LsItsGDp3niuLqqGy99 ChpmSQGuuRqxv4DZeFrZOjSFAp68oy0GhJvAto3Rli51rL7adHkRo1e2LAhG2Ymr6Jvy RNwQ9nw5J8vg2+XTLun8XS9tX8iHsTm/nxRDF+77uBZ32O7sPB0Kqka3vSh69vSm6fEE QB+Q== X-Gm-Message-State: AJIora+c6FdJfipJMFeXVE2pK7Fup5p7uDk5BIDfTd1XeN/txW7MBbLD m3h4Izdzu5DXadwZbZc8C+Q= X-Google-Smtp-Source: AGRyM1vhjUq4WlL+gX1y0tyZ4A5CURR86xjVYNDJLu6ZP96h77dZI91Uh7rAWnxqjmtwV7H8z5gWhg== X-Received: by 2002:a5d:67c3:0:b0:21b:8cd4:ad60 with SMTP id n3-20020a5d67c3000000b0021b8cd4ad60mr8680011wrw.380.1655755600064; Mon, 20 Jun 2022 13:06:40 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id n1-20020a5d4201000000b0021a36955493sm14274307wrq.74.2022.06.20.13.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:39 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 16/49] regmap-irq: Rename regmap_irq_update_bits() Date: Mon, 20 Jun 2022 21:06:11 +0100 Message-Id: <20220620200644.1961936-17-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" This function should only be used for updating mask bits, since it checks the mask_writeonly flag. To avoid confusion, rename it to regmap_irq_update_mask_bits(). Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 4c0d7f7aa544..875415fc3133 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -79,9 +79,9 @@ static void regmap_irq_lock(struct irq_data *data) mutex_lock(&d->lock); } -static int regmap_irq_update_bits(struct regmap_irq_chip_data *d, - unsigned int reg, unsigned int mask, - unsigned int val) +static int regmap_irq_update_mask_bits(struct regmap_irq_chip_data *d, + unsigned int reg, unsigned int mask, + unsigned int val) { if (d->chip->mask_writeonly) return regmap_write(d->map, reg, val & mask); @@ -129,11 +129,11 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg = sub_irq_reg(d, d->chip->mask_base, i); if (d->chip->mask_invert) { - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); } else if (d->chip->unmask_base) { /* set mask with mask_base register */ - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret < 0) dev_err(d->map->dev, @@ -142,12 +142,12 @@ static void regmap_irq_sync_unlock(struct irq_data *data) unmask_offset = d->chip->unmask_base - d->chip->mask_base; /* clear mask with unmask_base register */ - ret = regmap_irq_update_bits(d, + ret = regmap_irq_update_mask_bits(d, reg + unmask_offset, d->mask_buf_def[i], d->mask_buf[i]); } else { - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], d->mask_buf[i]); } if (ret != 0) @@ -761,17 +761,17 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, reg = sub_irq_reg(d, d->chip->mask_base, i); if (chip->mask_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf[i], ~d->mask_buf[i]); else if (d->chip->unmask_base) { unmask_offset = d->chip->unmask_base - d->chip->mask_base; - ret = regmap_irq_update_bits(d, + ret = regmap_irq_update_mask_bits(d, reg + unmask_offset, d->mask_buf[i], d->mask_buf[i]); } else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf[i], d->mask_buf[i]); if (ret != 0) { dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", From patchwork Mon Jun 20 20:06:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A742EC433EF for ; Wed, 22 Jun 2022 15:28:26 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id E403D1FDE; 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[92.40.169.68]) by smtp.gmail.com with ESMTPSA id v188-20020a1cacc5000000b003973c54bd69sm19423794wme.1.2022.06.20.13.06.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:41 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 17/49] regmap-irq: Add broken_mask_unmask flag Date: Mon, 20 Jun 2022 21:06:12 +0100 Message-Id: <20220620200644.1961936-18-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" This flag is necessary to prepare for fixing the behavior of unmask registers. Existing chips that set mask_base and unmask_base must set broken_mask_unmask=1 to declare that they expect the mask bits will be inverted in both registers, contrary to the usual behavior of mask registers. Signed-off-by: Aidan MacDonald --- include/linux/regmap.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/regmap.h b/include/linux/regmap.h index ee2567a0465c..21a70fd99493 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1523,6 +1523,7 @@ struct regmap_irq_chip { bool clear_on_unmask:1; bool not_fixed_stride:1; bool status_invert:1; + bool broken_mask_unmask:1; int num_regs; From patchwork Mon Jun 20 20:06:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7308AC43334 for ; Wed, 22 Jun 2022 15:28:56 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id B3FE11FF0; Wed, 22 Jun 2022 17:28:04 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz B3FE11FF0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911734; bh=Wq5NQ82Zcz/1kUjbkROMXgpEqf1Ci3lHZ/aKXefzCPw=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Gpc2QnYILB5AfcCFJnZ80kJkfE0hX1NNS/2KabqlRNyT2gCbxidYB7G84JKay3gAN 1oeCl0u8D4lq0YOAVEPsLyEqC+zKXKZBlirZoX55REe/9YaNLUrYE/+ct61vCKaYPa +6CU6W5N3+m2/haFWBeiFzIaCzqGzGPpK4LSnBfw= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id D6E3DF805C6; Wed, 22 Jun 2022 17:23:31 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id AE4FDF804E7; Mon, 20 Jun 2022 22:06:49 +0200 (CEST) Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id A35D0F804D8 for ; Mon, 20 Jun 2022 22:06:44 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz A35D0F804D8 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gdmCZ/lB" Received: by mail-wm1-x330.google.com with SMTP id m39-20020a05600c3b2700b0039c511ebbacso8269579wms.3 for ; Mon, 20 Jun 2022 13:06:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yDbkoyglFzlD/is/5GkDF5bxT9ENs1AtX/zXNAcYF8s=; b=gdmCZ/lBOcInOC7Vpu1bY/iCkTRvuWC70p3sTpyPTGpiGjPvbOfn3qCcOS6TYvfax1 3L11FjZaxXZKn19jySJpcCpWV+xtFrtQQCVooDpT2B76t5Yf89SzliwlOHigso1rDVLk oTKVebpiS712yjcf0kpN9r3uejsVQPOSwQQwOfRTaV3WxoLZf11oL8qGCQ6IIb3JKTvH Gd5oqTmwdqCLXQGfP9Un8n1q4CYFfIWgJvxX8PaS4jqeICZF2WLj79nuYT2SFdtS4Hri hh9xIXG5EB3E4bg9SOAm4e7Z9wjbeiNwP/00cDnzR6iUmi2i9i1qZqeOzh3rmmFV/C0Q vMPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yDbkoyglFzlD/is/5GkDF5bxT9ENs1AtX/zXNAcYF8s=; b=JjprvxEucayTVuYrVQP4oCGQXMXRGWUJnWnNbY2m4XUokx7VOL7TVNZ13unuV7oO/w XcrVfQ4KQ9Mev2Y41jqU64cHGYdCcYV8RSYNQ87jImqjD7c/+9gkKe06eYuOf78y1Kq2 RDEUlJ2SI09+YPa/GXU6CA+TeaS9plvpzQv9Ktt5AaRJOgt7J0MjK2E2fnVJAXJ45R0p xsJ+4sLnw9QCk5m3sRBN5C93PRM/SL3q1abvEJpobHB90Mf8IXDwTfEWsOIvpHgfFzwY zntLxm0MPJC3SCw5gM3vVoQISgCRJ7MMs06OWjGxzgqQsq7ViWiK5k/O2ZSkaVKKqoY+ C9jA== X-Gm-Message-State: AOAM5310ETbe0OvW2KqaIUKMnGAIdJrAsVbIbKF+bg6ZwR4JCd3v7E4O w1+v1d6ZQlnc7Mh59AcbVHo= X-Google-Smtp-Source: ABdhPJynux7C1eoNMlx+vUMO5VOj8q1wBlYfPuBT+ReLmKHLRHcj/n+Q7FNGG42F1xN9EMg0dcGAng== X-Received: by 2002:a05:600c:601f:b0:39c:416c:4069 with SMTP id az31-20020a05600c601f00b0039c416c4069mr36844654wmb.85.1655755603037; Mon, 20 Jun 2022 13:06:43 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id n15-20020a5d4c4f000000b0021b966abc19sm300460wrt.19.2022.06.20.13.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:42 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 18/49] mfd: qcom-pm8008: Add broken_mask_unmask irq chip flag Date: Mon, 20 Jun 2022 21:06:13 +0100 Message-Id: <20220620200644.1961936-19-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The qcom-pm8008 appears to use "1 to enable" convention for enabling interrupts, with separate set and clear registers. It's relying on masks and unmasks being inverted from their intuitive meaning, so it needs the broken_mask_unmask flag. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index da16566f7883..18095e72714e 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -141,6 +141,7 @@ static struct regmap_irq_chip pm8008_irq_chip = { .status_base = PM8008_STATUS_BASE, .mask_base = PM8008_MASK_BASE, .unmask_base = PM8008_UNMASK_BASE, + .broken_mask_unmask = true, .ack_base = PM8008_ACK_BASE, .config_base = pm8008_config_regs, .num_config_bases = ARRAY_SIZE(pm8008_config_regs), From patchwork Mon Jun 20 20:06:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A15B1C43334 for ; Wed, 22 Jun 2022 15:28:39 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id EA6C01FDF; Wed, 22 Jun 2022 17:27:47 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz EA6C01FDF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911718; bh=oJdm5C/8BCNEai6FUvuxoVhFY9oVD4JM7IowAgb8EvE=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=DFg0zZFXPevtc93w7jriWFNaHZrM/Nt/Fv6pwsGdxnZXTBVn72vk9RgNVBBoPbaPB qV320rfYuC6+utA+UPBVEM17j5sE1nkJ+NdnzAYHkYWMLkmdHjWOTohs+Bk6kPm07T Wets5C/rHJ6A+qgPZEpkxzA1Ghgtf05R2ilLTe+o= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 4264FF805C2; Wed, 22 Jun 2022 17:23:31 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 0F1D5F804EB; Mon, 20 Jun 2022 22:06:49 +0200 (CEST) Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 61F0BF800CB for ; Mon, 20 Jun 2022 22:06:46 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 61F0BF800CB Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e+BrKFyU" Received: by mail-wm1-x32e.google.com with SMTP id e5so6390840wma.0 for ; Mon, 20 Jun 2022 13:06:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F4wATPKotQB5JDuhaBZ5Jb5Nh8kCkmxeR4cD85ob0jA=; b=e+BrKFyUAEKrBpsdiTI0hXdQRnQfzScB8duoVAuFg+GJ0Jh4zZD5Q/yH5NsPA1D9fK uaNwGLpdVywtGRLROPl5tTxFT7A8jPHaWbjaPAMdsjcQoj2Fxm0OgNstaADl0insuEPU P50NDcoj6V57762q+5c86res9ZHtgVjfYyuGy0xSGWhhHkfr1HpoVpzrKy1Z/3zFEUFZ 67Fh85T75VnGSm9kPme9xBV7w8ac712S9ul2GLnNaWtQDEdomD1S1aBv1jYpvYeu5a7r MGwYhNujO4gNlNbVwu8A+bWELyeb6pNXvwP3xhw3JTzKit4mY+kzcbb6HrnaUC5RjRIY 8xkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F4wATPKotQB5JDuhaBZ5Jb5Nh8kCkmxeR4cD85ob0jA=; b=hEdL0TfjC84gPTg8mKquJvq/C2VXPObRU4V6P+1AQzY+PKFW+8p4D69wjeG+Fd/ZiU XaqMsJ/G9/B4FRcYnwQpy1GX+Grb0m+luSDbQ63kCOpcHK7/PA3AugGeenSC0Mix/gLU ayEfUGm7ejsUK/hFVPTWcM8I1gTaukmF9QMWxNGCN9m9icH0C6XSwj5JzvfRSm11Dwvz qusLOPpfdJ8SB0jcO21o+qw8+uadG6LV6GeBxD6um3U3Xbnhf0FuFsnhPdQEOSNOzF2n Vv5UDrVewonfdqrajSQrJZrTjXTJC9l4IG8XElbKie4jcfDSaPghggIxFdEFr0WUTbxT 7/1w== X-Gm-Message-State: AJIora/1fJgCCTj/96+pr6Dnl36XxRnKpY2p81pqI7jKXr2t3hwIjEJg EW3eNxZZV4jIROv9B/iFyQw= X-Google-Smtp-Source: AGRyM1viZL39dZzsNTWFK1Nii5H/dfYG1kHfbnLLGc84T/J91auGii4XODLgdHEKlU2wd9OGVZncsg== X-Received: by 2002:a7b:cc8e:0:b0:39c:829d:609b with SMTP id p14-20020a7bcc8e000000b0039c829d609bmr27634897wma.160.1655755604433; Mon, 20 Jun 2022 13:06:44 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id y16-20020a5d6150000000b0021b932de5d6sm2486492wrt.39.2022.06.20.13.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:44 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 19/49] mfd: stpmic1: Add broken_mask_unmask irq chip flag Date: Mon, 20 Jun 2022 21:06:14 +0100 Message-Id: <20220620200644.1961936-20-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The STPMIC1 has a normal "1 to disable" mask register with separate set and clear registers. It's relying on masks and unmasks being inverted from their intuitive meaning, so it needs the broken_mask_unmask flag. Signed-off-by: Aidan MacDonald --- drivers/mfd/stpmic1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c index eb3da558c3fb..2307d1b0269d 100644 --- a/drivers/mfd/stpmic1.c +++ b/drivers/mfd/stpmic1.c @@ -110,6 +110,7 @@ static const struct regmap_irq_chip stpmic1_regmap_irq_chip = { .status_base = INT_PENDING_R1, .mask_base = INT_CLEAR_MASK_R1, .unmask_base = INT_SET_MASK_R1, + .broken_mask_unmask = true, .ack_base = INT_CLEAR_R1, .num_regs = STPMIC1_PMIC_NUM_IRQ_REGS, .irqs = stpmic1_irqs, From patchwork Mon Jun 20 20:06:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E42D9C43334 for ; Wed, 22 Jun 2022 15:29:28 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 3A91E1FF7; Wed, 22 Jun 2022 17:28:37 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 3A91E1FF7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911767; bh=bKR2Ma6Uwh0Hd8xzrlk9x3uRMNl2yTOWCa4uGeCdBS8=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=VL1PERQrQB2MN19sNGhQVjyxnH9AUO/Wq2lN3d9JFOU4KbR8B+Uf31ETOYMNkv8UE lZ17VK2q7lW4ZgHvNJ0WaACs9LSe7jahPN80qJPw29hvzo15t+aJ1XUQjmfTAkuUEL E9E9F7tFeXvXyDmh9+ct8hzLwWYs9dlP1Ejy8Bjw= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 447C3F805D5; Wed, 22 Jun 2022 17:23:33 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 411D5F800E3; Mon, 20 Jun 2022 22:06:51 +0200 (CEST) Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 8B105F804D2 for ; Mon, 20 Jun 2022 22:06:47 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 8B105F804D2 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jmla8ZkA" Received: by mail-wm1-x32e.google.com with SMTP id z17so6380131wmi.1 for ; Mon, 20 Jun 2022 13:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1GpLIZISKqF9zFT4V1VJAxmf6nn2WqheoAcUl14eN+0=; b=jmla8ZkAOgrPskXynLCx05NWcsoEkbzw4ryinc4jYDe2RQIqHhPmV85RQKl7U9EmUI bF6TQ7O+iemjbNinkBjDldrg2yYic5jWOfe5sSL2/VPNdE+cj0lrEbPwTlpJTZs7BttW crq3WUJJa6c/dObTJx9WHn0Fl68Y8gRDUlBvzH70ODYLEG0pgioICXVMDThfVXbcB68W ixmvmMn2GGU7Gnw+8ih+LjNZ3VEsZF5IpRaRfmraY75SBGsUraU0gCZChrsxbjdlp0c3 X2WoHLbmrUSCLmnOMru0muZcahA8wUBHqdqxnvkpgp8UxCePBtXvm2MD7P0hwoO2uvZb BGGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1GpLIZISKqF9zFT4V1VJAxmf6nn2WqheoAcUl14eN+0=; b=TX8RVOEtiNMDih9YVlGCJgqr5npIAdJdFKPEvXECjfbF9o+qwpqBzVht/jjWvwiyUS OVOcjT/CFGPIZKqZDgbHIAWWT1ZUtxnzHGXwTaqkLnKzXImCDPjM7SpZYIlp76OtFX+h GufidGywEenMvGJyTczP9ADRB6BqET5RSR8KCjiP3gUmkMPRYzQeWO3RLjtXMJNK1NWp fS0c+iye5NjTxelERpXuuz40FjwA0XZTLh27oio4/vfTRNNetdmDshkXgGyFXlbAbRGI uTTs1fmNI1q9kTkzywYgcFfmKxZ5HujJ03MLQpckmO+z4cpwZ5f4jSGSsST2LykfAVHb IDUw== X-Gm-Message-State: AOAM530cjdgVsGqdJKgNIFDwAS+NU21/PvtX5BBQrfmclRgezcJcm9pe i0oQuSotPClyP7IkA33vEgM= X-Google-Smtp-Source: ABdhPJx5dO+fQ4bSwFvdlpiB13bqVgu0Tmz5FemzXFKDgDhK5sVpfqzf/x7Jf9ygCYEoM4c832uaSw== X-Received: by 2002:a05:600c:19cb:b0:397:51db:446f with SMTP id u11-20020a05600c19cb00b0039751db446fmr36963462wmq.182.1655755605944; Mon, 20 Jun 2022 13:06:45 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. [92.40.169.68]) by smtp.gmail.com with ESMTPSA id t17-20020adfe111000000b002102cc4d63asm17480550wrz.81.2022.06.20.13.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:45 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 20/49] regmap-irq: Fix inverted handling of unmask registers Date: Mon, 20 Jun 2022 21:06:15 +0100 Message-Id: <20220620200644.1961936-21-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:17 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" To me "unmask" suggests that we write 1s to the register when an interrupt is enabled. This also makes sense because it's the opposite of what the "mask" register does (write 1s to disable an interrupt). But regmap-irq does the opposite: for a disabled interrupt, it writes 1s to "unmask" and 0s to "mask". This is surprising and deviates from the usual way mask registers are handled. Additionally, mask_invert didn't interact with unmask registers properly -- it caused them to be ignored entirely. Fix this by making mask and unmask registers orthogonal, using the following behavior: * Mask registers are written with 1s for disabled interrupts. * Unmask registers are written with 1s for enabled interrupts. This behavior supports both normal or inverted mask registers and separate set/clear registers via different combinations of mask_base/unmask_base. The mask_invert flag is made redundant, since an inverted mask register can be described more directly as an unmask register. To cope with existing drivers that rely on the old "backward" behavior, check for the broken_mask_unmask flag and swap the roles of mask/unmask registers. This is a compatibility measure which can be dropped once the drivers are updated to use the new, more consistent behavior. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 96 +++++++++++++++++--------------- include/linux/regmap.h | 7 ++- 2 files changed, 55 insertions(+), 48 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 875415fc3133..082a2981120c 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -30,6 +30,9 @@ struct regmap_irq_chip_data { int irq; int wake_count; + unsigned int mask_base; + unsigned int unmask_base; + void *status_reg_buf; unsigned int *main_status_buf; unsigned int *status_buf; @@ -95,7 +98,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) struct regmap *map = d->map; int i, j, ret; u32 reg; - u32 unmask_offset; u32 val; if (d->chip->runtime_pm) { @@ -124,35 +126,23 @@ static void regmap_irq_sync_unlock(struct irq_data *data) * suppress pointless writes. */ for (i = 0; i < d->chip->num_regs; i++) { - if (!d->chip->mask_base) - continue; - - reg = sub_irq_reg(d, d->chip->mask_base, i); - if (d->chip->mask_invert) { + if (d->mask_base) { + reg = sub_irq_reg(d, d->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, - d->mask_buf_def[i], ~d->mask_buf[i]); - } else if (d->chip->unmask_base) { - /* set mask with mask_base register */ + d->mask_buf_def[i], d->mask_buf[i]); + if (ret != 0) + dev_err(d->map->dev, "Failed to sync masks in %x\n", + reg); + } + + if (d->unmask_base) { + reg = sub_irq_reg(d, d->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); - if (ret < 0) - dev_err(d->map->dev, - "Failed to sync unmasks in %x\n", + if (ret != 0) + dev_err(d->map->dev, "Failed to sync masks in %x\n", reg); - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; - /* clear mask with unmask_base register */ - ret = regmap_irq_update_mask_bits(d, - reg + unmask_offset, - d->mask_buf_def[i], - d->mask_buf[i]); - } else { - ret = regmap_irq_update_mask_bits(d, reg, - d->mask_buf_def[i], d->mask_buf[i]); } - if (ret != 0) - dev_err(d->map->dev, "Failed to sync masks in %x\n", - reg); reg = sub_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { @@ -634,7 +624,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, int i; int ret = -ENOMEM; u32 reg; - u32 unmask_offset; if (chip->num_regs <= 0) return -EINVAL; @@ -732,6 +721,24 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->chip = chip; d->irq_base = irq_base; + /* + * Swap role of mask_base and unmask_base if mask bits are inverted. + * + * Historically, chips that specify both mask_base and unmask_base + * got inverted mask behavior; this was arguably a bug in regmap-irq + * and there was no way to get the normal, non-inverted behavior. + * Those chips will set the broken_mask_unmask flag. They don't set + * mask_invert so there is no need to worry about interactions with + * that flag. + */ + if (chip->mask_invert || chip->broken_mask_unmask) { + d->mask_base = chip->unmask_base; + d->unmask_base = chip->mask_base; + } else { + d->mask_base = chip->mask_base; + d->unmask_base = chip->unmask_base; + } + if (chip->irq_reg_stride) d->irq_reg_stride = chip->irq_reg_stride; else @@ -755,28 +762,27 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, /* Mask all the interrupts by default */ for (i = 0; i < chip->num_regs; i++) { d->mask_buf[i] = d->mask_buf_def[i]; - if (!chip->mask_base) - continue; - reg = sub_irq_reg(d, d->chip->mask_base, i); - - if (chip->mask_invert) + if (d->mask_base) { + reg = sub_irq_reg(d, d->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, - d->mask_buf[i], ~d->mask_buf[i]); - else if (d->chip->unmask_base) { - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; - ret = regmap_irq_update_mask_bits(d, - reg + unmask_offset, - d->mask_buf[i], - d->mask_buf[i]); - } else + d->mask_buf_def[i], d->mask_buf[i]); + if (ret != 0) { + dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", + reg, ret); + goto err_alloc; + } + } + + if (d->unmask_base) { + reg = sub_irq_reg(d, d->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, - d->mask_buf[i], d->mask_buf[i]); - if (ret != 0) { - dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", - reg, ret); - goto err_alloc; + d->mask_buf_def[i], ~d->mask_buf[i]); + if (ret != 0) { + dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", + reg, ret); + goto err_alloc; + } } if (!chip->init_ack_masked) diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 21a70fd99493..0cf3c4a66946 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1451,10 +1451,11 @@ struct regmap_irq_sub_irq_map { * main_status set. * * @status_base: Base status register address. - * @mask_base: Base mask register address. + * @mask_base: Base mask register address. Mask bits are set to 1 when an + * interrupt is masked, 0 when unmasked. * @mask_writeonly: Base mask register is write only. - * @unmask_base: Base unmask register address. for chips who have - * separate mask and unmask registers + * @unmask_base: Base unmask register address. Unmask bits are set to 1 when + * an interrupt is unmasked and 0 when masked. * @ack_base: Base ack address. If zero then the chip is clear on read. * Using zero value is possible with @use_ack bit. * @wake_base: Base address for wake enables. If zero unsupported. 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Signed-off-by: Aidan MacDonald --- drivers/mfd/tps65090.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/tps65090.c b/drivers/mfd/tps65090.c index bd6235308c6b..e474e1ca253a 100644 --- a/drivers/mfd/tps65090.c +++ b/drivers/mfd/tps65090.c @@ -127,8 +127,7 @@ static struct regmap_irq_chip tps65090_irq_chip = { .num_irqs = ARRAY_SIZE(tps65090_irqs), .num_regs = NUM_INT_REG, .status_base = TPS65090_REG_INTR_STS, - .mask_base = TPS65090_REG_INTR_MASK, - .mask_invert = true, + .unmask_base = TPS65090_REG_INTR_MASK, }; static bool is_volatile_reg(struct device *dev, unsigned int reg) From patchwork Mon Jun 20 20:06:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 978D8C43334 for ; Wed, 22 Jun 2022 15:30:31 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id D97DE2020; Wed, 22 Jun 2022 17:29:39 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz D97DE2020 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911829; bh=dQbuzEPrCnmyUo8+GPhQvJ8bO0NeLYXJv7L8sBLWYXM=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=QAo9ve9lQx7RZLSnaxanWYiCOq3mT8RZhcIU54lWLuPcPA3FetEKmUIXeZQkgSKif 70Jscc3/uLv6g2BDkAczOkkRi2nfpReDz5dWkXpovDZD3nBH5IE7EYs2y6PnvJkFDg DeeVSdEO/5zicrnaMM1ebgp9M3UWbxs/WIKC29lA= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id E8903F805E8; Wed, 22 Jun 2022 17:23:35 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 2695BF804DA; Mon, 20 Jun 2022 22:06:58 +0200 (CEST) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 0EAA4F804D8 for ; Mon, 20 Jun 2022 22:06:50 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 0EAA4F804D8 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="n+dv2OHy" Received: by mail-wr1-x42a.google.com with SMTP id o8so16102621wro.3 for ; Mon, 20 Jun 2022 13:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gBD4FGBJfr7WfKu1UZU1bV8IB7E8/qXlLxTviEK1Akg=; b=n+dv2OHyeLcXNTmM5AoQ5y71hnTNJIpcERPeXRAZGzH3I/VENsQCVHYqLkDxbEjmN/ TTkfawWz7sGx1fEvNmiL1zWs5fqtd8PmEYJ/uuxwTzmlN3TNWDIjfT7h7X2oiiCeJDJo G0D3xiO8ep0dRDPxWfA7mglV2rl0lfdiXs/NgfHf3uClxo2T0zSzKmcugT014uVsbBA4 a8d72hUTWqP7aMSTkN4E6jMQH1AsJpvanWTcr/TzYICesUohxeYCLmlbHF8Or3sDiq5E ReozveZPFU1OGId9YBAanmpEq2oZ6/HDOKmehZPgromaOnVKCB0W7RktevOubR0I+UbT T3Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gBD4FGBJfr7WfKu1UZU1bV8IB7E8/qXlLxTviEK1Akg=; b=rdQrxtMunSQsHI4+68Dh687w3h2d/Z07VWMH5SOzoy0nwDkaTE5z9v5nLu/6pLH7QF TtwSpJzYEoDoiyEOz5Re+9weqLyBw1bo1NECPZ1WhE1UGNjOiV/99+42y2LI6K3bu/ow /9D2Nbb6CZgDkD3REPwJpKhEgvAAHhj3Mfqa5oysbjM3zNSbKwe113UkxTA/aIcDKXhe HiUoM5QmQbi4Nqs4M9yM4HmzwXtQr/8/M1nJ3Xig2cAldUOqqRNb1i0uh3bnHPstRVF9 6jxKLQN6ufgJsmVMPFF+OUU5+33cyedmkz7qYzGYXeSdYk8hVH2ZMi+vkwmlNJ7WPyy1 PAQA== X-Gm-Message-State: AJIora8ptatrOE1sEFTx4x+76NF5mFhHIBScp+8edCCAtEZB/yDvHYZz t4/92NXlN9iI96ZsKXRxbX8= X-Google-Smtp-Source: AGRyM1ueeTVj4W+irPUqcFh4aibJZGRQv0luVUmTWKHSamp2328uXg/JWH281sGfd9zcwAAoGkXCMQ== X-Received: by 2002:adf:ae09:0:b0:20e:e4f0:2133 with SMTP id x9-20020adfae09000000b0020ee4f02133mr24684442wrc.104.1655755608969; Mon, 20 Jun 2022 13:06:48 -0700 (PDT) Received: from localhost (92.40.169.68.threembb.co.uk. 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Signed-off-by: Aidan MacDonald --- drivers/mfd/sun4i-gpadc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/sun4i-gpadc.c b/drivers/mfd/sun4i-gpadc.c index cfe14d9bf6dc..edc180d83a4b 100644 --- a/drivers/mfd/sun4i-gpadc.c +++ b/drivers/mfd/sun4i-gpadc.c @@ -34,9 +34,8 @@ static const struct regmap_irq_chip sun4i_gpadc_regmap_irq_chip = { .name = "sun4i_gpadc_irq_chip", .status_base = SUN4I_GPADC_INT_FIFOS, .ack_base = SUN4I_GPADC_INT_FIFOS, - .mask_base = SUN4I_GPADC_INT_FIFOC, + .unmask_base = SUN4I_GPADC_INT_FIFOC, .init_ack_masked = true, - .mask_invert = true, .irqs = sun4i_gpadc_regmap_irq, .num_irqs = ARRAY_SIZE(sun4i_gpadc_regmap_irq), .num_regs = 1, From patchwork Mon Jun 20 20:06:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E7C6C433EF for ; Wed, 22 Jun 2022 15:30:16 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 86EF9200F; Wed, 22 Jun 2022 17:29:24 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 86EF9200F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911814; bh=ty9T/Yw/+FlBfdOoovses7WGNdhWnvNh/vt5gAcIEt4=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=gPrEgde7w006G2L7Q3faiiwcPocoYhOTW2dvpxh3kWCul89dH0fGpRgq2HKmC4ufG Fb+cmeygDQksIBErunKyXyOSe1Vm6cbtqhJeYCn5NDUIgp6I3dOjXppVSDykLx1qGP /MYQriZ/xufKd1P01icjAuQP2OZKlLlaTdvdleco= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 68E65F805E4; Wed, 22 Jun 2022 17:23:35 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 108F7F804D2; Mon, 20 Jun 2022 22:06:57 +0200 (CEST) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id B18E5F800CB for ; Mon, 20 Jun 2022 22:06:50 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz B18E5F800CB Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nSss6m1i" Received: by mail-wm1-x32c.google.com with SMTP id m125-20020a1ca383000000b0039c63fe5f64so6210561wme.0 for ; Mon, 20 Jun 2022 13:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=83f6yOVGHF33wbJFNUqHVsMRQC83Nm7l3Jffulf5Q20=; b=nSss6m1iZMp9y7Vv5974YLuhhJUZ614v32RzAfng7nP1DgOtE0Apdk3S4hwIYaOcx1 golYgrNSS7bRWfwoAUSA5Og7WysO98jLMv2W9IlYLvHZnPWxMcZHBnXlEYNbFGYXAe4h zkX/QFUpTqAkwk57wIfRoBajgsGcPIRZsVFEZEBTCfHJUtpgAuIwl1tCoiFICvSGYFcM iW1sdZy6IBsByUO4a0aRbsf/NzuzhMMy7unrWxcauagegTS75O7aSHLZgHRYpLH0BAZ+ 4ZZseSMNKYwbZHqZFgQqC8T4HX4zh6g3gg0Rzx4vx6r8K2qxxQIrzGRKLh03m3NFkovC 6bHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=83f6yOVGHF33wbJFNUqHVsMRQC83Nm7l3Jffulf5Q20=; b=3BUm5gSFL71WS6Epzq0Wgs3U4kJbdizjdkmRSbTaOj5F5myawl8t9eH2CWibx9hFMS RgU5+QjPF9cQeLvNQ8CycSv83NpegJI25jS9fZAKdTA5NhHc8QciJSJumcJZxEgTxkeP 8xRPz1CIR/CdVViRMeXwjUTS1JcWKBD5GH+3yIYlzgtJ6UtDmCO+qHjL6Xo8nLefLomv HG8sPi/j5FIyTSoIzmjttE+iv67ypY5+y1I2jMqxdJ1oodqT9wPKa7r3vRZD6QExnim2 LzWTpkFbglzrpZq1wTCR+D6kc4CCYbeYiaiGy2m6N3ToA9dqeelI2WAtNSPSQHE2X7iB g44w== X-Gm-Message-State: AOAM5306grEQBjAenuPAR3Bk5YtLGgNsHixmSkwqdcq5Kj77JwNS161O lv4JUHKi7orQK6+LF+I6fsU= X-Google-Smtp-Source: ABdhPJy5hxDd4tBIdG/h7CHZ7zMWEzJh0oBujvFGRYSxBfUs0KG9/aftZhFj9CMuaUDM6O3W6BLpoA== X-Received: by 2002:a05:600c:1547:b0:39c:7fc6:3082 with SMTP id f7-20020a05600c154700b0039c7fc63082mr36832709wmg.189.1655755610410; Mon, 20 Jun 2022 13:06:50 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id cl10-20020a5d5f0a000000b0021b92171d28sm3418468wrb.54.2022.06.20.13.06.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:50 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 23/49] mfd: sprd-sc27xx-spi: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:18 +0100 Message-Id: <20220620200644.1961936-24-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/sprd-sc27xx-spi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/sprd-sc27xx-spi.c b/drivers/mfd/sprd-sc27xx-spi.c index d05a47c5187f..a4a9b81a952b 100644 --- a/drivers/mfd/sprd-sc27xx-spi.c +++ b/drivers/mfd/sprd-sc27xx-spi.c @@ -181,11 +181,10 @@ static int sprd_pmic_probe(struct spi_device *spi) ddata->irq_chip.name = dev_name(&spi->dev); ddata->irq_chip.status_base = pdata->irq_base + SPRD_PMIC_INT_MASK_STATUS; - ddata->irq_chip.mask_base = pdata->irq_base + SPRD_PMIC_INT_EN; + ddata->irq_chip.unmask_base = pdata->irq_base + SPRD_PMIC_INT_EN; ddata->irq_chip.ack_base = 0; ddata->irq_chip.num_regs = 1; ddata->irq_chip.num_irqs = pdata->num_irqs; - ddata->irq_chip.mask_invert = true; ddata->irqs = devm_kcalloc(&spi->dev, pdata->num_irqs, sizeof(struct regmap_irq), From patchwork Mon Jun 20 20:06:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8AB2AC433EF for ; Wed, 22 Jun 2022 15:29:42 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id C7F131F1E; Wed, 22 Jun 2022 17:28:50 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz C7F131F1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911780; bh=nqza5eL39EyJGclZOlMd2YpPeyNIXN31cw7wq5nyyLU=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=hrjaVDq6o8Q15+p9J/dClM89VVAR+z6bvjfcPGoAtu9YUbAKB7tGXg1reLMT1n0dl J89eJudbFVZXZQFsZx7748hIskvEex0QpWqWG6Ilg6pbm7NXFiHfWrdrqoUJeOlP8b JsKt1uAnopkaqqL66JLq7Ti+h9OmJriE0UOzvsSo= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id E6471F805D9; Wed, 22 Jun 2022 17:23:33 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 1B930F804DA; Mon, 20 Jun 2022 22:06:55 +0200 (CEST) Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 79B4CF804D2 for ; Mon, 20 Jun 2022 22:06:52 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 79B4CF804D2 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fwpJrSBM" Received: by mail-wr1-x42f.google.com with SMTP id s1so16072728wra.9 for ; Mon, 20 Jun 2022 13:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/LPf9h09XUJR/z/RdQdPV0VQS/kTyakjP+1OAofeWXA=; b=fwpJrSBMfmFPeeNXJrlpjWlkFshzFm6Y1DWOVq+h4L71A/9e1R5aHmopQ9JlXAYX77 p/aPMsuwp0jXJ6JA/lErm+8RcPw1nwj/qzcNe82rYLGJJE87iMHlnWgUuO98N/3+uLWl HoFIstzlvMDtCLgfhnOriWLoNwZv6+3clTJtgU5AJImo5hzLcA8Xl5biIy+qCPN0Yl2h sSZ3MIekuF7sfDNA5dosij4OPFFY4DXnc1sarY9jKvYuFBzZIvgCKpyr0XlJB/Ymar7p 76Xyx3zNFdDnkRRyU54ZBIwLy/ubU9zZyaI0NzK9C8RtA20uucTc0zHujNOvDTsjWaG+ UbTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/LPf9h09XUJR/z/RdQdPV0VQS/kTyakjP+1OAofeWXA=; b=XLTbOLtuAipcqytqweZgrPydtbWwc3jxJgBemtah6JG/CRrIGKEOtA+OyI/lTzWxlg YPhfHTDvgIa5QRMWlInXe/J2OdYqvbLn84Utz1gYRKtKrxYSqtjlUWagsm7wnBrk1Vd4 jG4ha8pdpGNXUOfAkyDCgQXG8rBpLxuO4HX020Je2KtAP/zcmRyNDepjWYHv3/siG28i kNAye/ca+MJzZLg7d+HkwJGjnY2n5y9L+Ub6NiM3R2cLIxM6Jmeok4rL9XqqGN6P/oPW oksgiTil9iah6WNBhvXyEsLYh3xKhNPJShr9Wua/DnUzpHFGJGstFdsAr8lSn8yjpGDb YA2w== X-Gm-Message-State: AJIora9eDnFMTqekpUshQ6lzGG3U/p0SwmPEDoVw2bzlt7tpvthu2ctW 2cX1Nx6+xVRrBcDC9BpSZmc= X-Google-Smtp-Source: AGRyM1saqWHhZeAqgNDua/lIIE8QUgq+ce7t9oCt2daRUSekH7GNKx27L1qwZwbxMxNYwR5edglGYw== X-Received: by 2002:a05:6000:156c:b0:218:5691:e72b with SMTP id 12-20020a056000156c00b002185691e72bmr24333023wrz.95.1655755612132; Mon, 20 Jun 2022 13:06:52 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id h17-20020a05600c2cb100b00397393419e3sm20418814wmc.28.2022.06.20.13.06.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:51 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 24/49] mfd: rt5033: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:19 +0100 Message-Id: <20220620200644.1961936-25-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/rt5033.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/rt5033.c b/drivers/mfd/rt5033.c index f1236a9acf30..dc9bf4057a09 100644 --- a/drivers/mfd/rt5033.c +++ b/drivers/mfd/rt5033.c @@ -29,8 +29,7 @@ static const struct regmap_irq rt5033_irqs[] = { static const struct regmap_irq_chip rt5033_irq_chip = { .name = "rt5033", .status_base = RT5033_REG_PMIC_IRQ_STAT, - .mask_base = RT5033_REG_PMIC_IRQ_CTRL, - .mask_invert = true, + .unmask_base = RT5033_REG_PMIC_IRQ_CTRL, .num_regs = 1, .irqs = rt5033_irqs, .num_irqs = ARRAY_SIZE(rt5033_irqs), From patchwork Mon Jun 20 20:06:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C2FCC433EF for ; Wed, 22 Jun 2022 15:29:59 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id B7E0A2009; Wed, 22 Jun 2022 17:29:07 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz B7E0A2009 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911797; bh=JgL4aOwEBx+NyqkasFWMOiuGgm7Pg+Pji9gXyLlefJ8=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=a1XeKvCITYGVlP3rQY2LfgjHwnpnkx9uooJPyPDVHwRMvNCM4WPpS4DvRsLubJ6kb nMLVWdk7iC6mUMzfT+BF72u9WhkJwnX2uTd8EqH7UbgwmnA3Z0AJ9A2/V0QNFB27iQ 0rYWBBYT+3jQbWrmFfSFnb0usuIbS62/7sr/yHfs= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 8A791F805E1; Wed, 22 Jun 2022 17:23:34 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id E956EF804E5; Mon, 20 Jun 2022 22:06:56 +0200 (CEST) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 45995F800E3 for ; Mon, 20 Jun 2022 22:06:54 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 45995F800E3 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="o76wuo0x" Received: by mail-wr1-x42a.google.com with SMTP id e25so12215275wrc.13 for ; Mon, 20 Jun 2022 13:06:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RxzMqxj/eXn7w9NNf93GCQveT2W3i+9cnq4DwR+RJyE=; b=o76wuo0xPC/x3J+fSzV08PvTJNEDSkggAXYsoR9+fouiAFePVvNZxWHKb6V2vQ92OA SE+0Tgogz4/JpWBQo32vpyKXLh2Katf4rLXy/5aiL3oY3i7H+xTu8fBXo9Kmwm+1LdJN n17o06/gfXQXFoYWk4+a7o5AXR1yv4WDcHzYxk5Bo6GjGCsBM4jzZLPAZskoHBAppBrr O0akQIZhIrT1LlNKwQ0GBml8Y9QIufqmcfQWayZorKoyOzzGnKmI65dWbbANUzud/obW h52Jbwhvf8dXR/t08i55bKKmJaWPIdWVSrVoX8K6QhSQSAGB7kcnC01lTkvgx2dqq/2U cwUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RxzMqxj/eXn7w9NNf93GCQveT2W3i+9cnq4DwR+RJyE=; b=Anqjxaw/kpeHZunY+3PhiafQrW8DPfJSBiHKcrzO1dVuEZew297sF0fzmb6/gtAxBw WxHrgIiC+949ZgwHNynw1RkYEo5qGVzPLzyQpq3ElGSkcDmEeoMwMRAlAhBWOpG0wHi1 BkAlSxbHMR8zSuDe8Z6G/7XnV524dvqJCmF5QfDBatQEKpiihBz81aPLmQhPVLIKTKv+ Hg0GnHgdYSjeG4ZC0FNKkzQpSJo4L4cU79gJjNQgs11ztbZPeI1QzRF8uQ+DBy2dWBn1 NvKhCGy+jWmKbHirTz4PRFtf8gqGLUfu8EnW378r6hYtnjgwAcamO29AHPZtB6CliYvg REfg== X-Gm-Message-State: AJIora+h+NZ4nutgc9wIXK3h4EOBSf4QGWr+QgHQMcR6WsYpfWlx7Ona g9/+2X/wLpI33JtMlljY2VUE8N/r5Yg= X-Google-Smtp-Source: AGRyM1uQHejr8zASwoWiI73KhsStma0zb82PJc1yA+xXQ76Hdedooq3WaNWKMgmFn77ar+BE+OUVCQ== X-Received: by 2002:a5d:4592:0:b0:21b:8e50:7fb9 with SMTP id p18-20020a5d4592000000b0021b8e507fb9mr7563688wrq.428.1655755613935; Mon, 20 Jun 2022 13:06:53 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id j13-20020a5d452d000000b0021a3d94c7bdsm11884838wra.28.2022.06.20.13.06.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:53 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 25/49] mfd: rohm-bd71828: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:20 +0100 Message-Id: <20220620200644.1961936-26-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/rohm-bd71828.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c index 714d9fcbf07b..3c5c6c393650 100644 --- a/drivers/mfd/rohm-bd71828.c +++ b/drivers/mfd/rohm-bd71828.c @@ -413,9 +413,8 @@ static struct regmap_irq_chip bd71828_irq_chip = { .irqs = &bd71828_irqs[0], .num_irqs = ARRAY_SIZE(bd71828_irqs), .status_base = BD71828_REG_INT_BUCK, - .mask_base = BD71828_REG_INT_MASK_BUCK, + .unmask_base = BD71828_REG_INT_MASK_BUCK, .ack_base = BD71828_REG_INT_BUCK, - .mask_invert = true, .init_ack_masked = true, .num_regs = 12, .num_main_regs = 1, @@ -430,9 +429,8 @@ static struct regmap_irq_chip bd71815_irq_chip = { .irqs = &bd71815_irqs[0], .num_irqs = ARRAY_SIZE(bd71815_irqs), .status_base = BD71815_REG_INT_STAT_01, - .mask_base = BD71815_REG_INT_EN_01, + .unmask_base = BD71815_REG_INT_EN_01, .ack_base = BD71815_REG_INT_STAT_01, - .mask_invert = true, .init_ack_masked = true, .num_regs = 12, .num_main_regs = 1, From patchwork Mon Jun 20 20:06:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12FD6C433EF for ; Wed, 22 Jun 2022 15:31:02 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 5727B203E; Wed, 22 Jun 2022 17:30:10 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 5727B203E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911860; bh=ZCOzxBLjHX26DoNSlpcgdlSE6xvZicVr3vGGB3CZ7b0=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=anvD+g3f90MIXFYI6rwKzl1Izj81mEipsD1+1frMbkJqdU8BnPrsmf1Sy6AafQGE8 UG69zk1ONAh9M8up5+wPcpeofFFb/E2uJCQ/HEtAQJablr+/7LpUN63IwtmuQJVGh5 XZpR5IcOiRkzJvc+P3CQUIeemkSSwbHNY1d4gnWo= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 33EDEF805F0; Wed, 22 Jun 2022 17:23:37 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 5060CF804E5; Mon, 20 Jun 2022 22:07:03 +0200 (CEST) Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 92A85F800E3 for ; Mon, 20 Jun 2022 22:06:56 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 92A85F800E3 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Hx66dBMo" Received: by mail-wr1-x431.google.com with SMTP id m1so8326299wrb.2 for ; Mon, 20 Jun 2022 13:06:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aFyu5esk/Zb2lNQzmvPRJ9QuwxnaeJqoP/Ih9wxKaVE=; b=Hx66dBMoypw3HFQ6ZlYKo/eR568ezNz8W5y6iElQBkDHOOhjdkd2OOUeXyuM4IJATJ nOWdw0iuhlEmOX8vNXfnAWlMC147l0U4mfE3S2gNMusmdyP2zWZJyHYTvmwCppX/Iskv vwfm6snjUXGKxpT/jRbYfj6RIQgagfupLw7jvBu/UAvy5tQBhPO9eQAGfcl+0IEp9k+M wAT+eo4bwJp8EjwTVNo5vMEs/MgiikrzJ6fDgsNBPx0jramgLds5jhx1zxPNI3c4MG3Q IGQX9FrRR/YfkFCB3wF6UfpCKRFn8rTPevafX0DQ9EPElddTBsBLn3qw+l3BZXYk9GKI 5nXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aFyu5esk/Zb2lNQzmvPRJ9QuwxnaeJqoP/Ih9wxKaVE=; b=oiIekwgoAVi78I/2h7CpAKoLZXRRcvOisMLJm4LfrTh8NKV1DrvUUY1zmhvxty0kSz aLsNjVrMy+ue3pVG2xgYjg9oGcV/qI8Q24YGvhMzaSOT+/6t4iflNcb1YIxJ60+0RFT8 zAzWaqy65PbZoOBlc/qctwUP8RNVHL3FabT5PFVIxPv15B2k99jknhGcIj9DHQFkSeXm 2DzKQc8he//suGARKED0iEJCFRA/QGpgPNA7qBuK/rpEYRQixldsasK/dZaIT0/Vkp8R vcZFOSfiJIJcLiLv+0CX7YYuWuk/+DA1dh98CTe92dbIP6kZ5mnAG9g8VPirHkCB4eLu anPQ== X-Gm-Message-State: AJIora/zozj5K6nI/nJmUH0HKF+Hg+prR7Po44fp6oMLoUyh06K4RSLF Ohj+vsukzrYry5IYvoHxHW0= X-Google-Smtp-Source: AGRyM1tHw8LdpOYQ4ocdkg/wb7xbdY+ptC8YBcgzkEw+K1EEKq9i385MNLM8p7QV0MNlJKBoINhp9g== X-Received: by 2002:a5d:5847:0:b0:218:5319:f4e3 with SMTP id i7-20020a5d5847000000b002185319f4e3mr25586723wrf.500.1655755615568; Mon, 20 Jun 2022 13:06:55 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id w5-20020a7bc105000000b003976fbfbf00sm15528084wmi.30.2022.06.20.13.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:54 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 26/49] mfd: rn5t618: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:21 +0100 Message-Id: <20220620200644.1961936-27-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/rn5t618.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/rn5t618.c b/drivers/mfd/rn5t618.c index 384acb459427..7ed002d090bd 100644 --- a/drivers/mfd/rn5t618.c +++ b/drivers/mfd/rn5t618.c @@ -80,8 +80,7 @@ static const struct regmap_irq_chip rc5t619_irq_chip = { .num_irqs = ARRAY_SIZE(rc5t619_irqs), .num_regs = 1, .status_base = RN5T618_INTMON, - .mask_base = RN5T618_INTEN, - .mask_invert = true, + .unmask_base = RN5T618_INTEN, }; static struct i2c_client *rn5t618_pm_power_off; From patchwork Mon Jun 20 20:06:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE97EC43334 for ; Wed, 22 Jun 2022 15:30:47 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id B0D161F13; Wed, 22 Jun 2022 17:29:55 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz B0D161F13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911845; bh=XdHln75xhqMzmAIajgw37F81FNCUd3sXXKB52owdLIM=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=j8EKfWXMf9S32dpBfwxh9nAy0H9aj09in6TP3wTyetbmRDGIMsXQY0xInxucIl48+ PLOMrIT2YKswHwmu2TuRprMDmWDqw7jImfoP4JWLBXFXnHUIzI0abT6YtNJVZA7+HE HEw019Cj0vMMQ9ZRyqXFh9qgMNTAP4cEq/CxNaf8= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 846EBF805E9; Wed, 22 Jun 2022 17:23:36 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 2C065F804E5; Mon, 20 Jun 2022 22:07:01 +0200 (CEST) Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id A5FACF804D2 for ; Mon, 20 Jun 2022 22:06:58 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz A5FACF804D2 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bpjyLwVi" Received: by mail-wr1-x42f.google.com with SMTP id w17so16065230wrg.7 for ; Mon, 20 Jun 2022 13:06:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dZq4DXS5hfuZufkfinYetDi/sPSwHy1FNwiaqhpssa4=; b=bpjyLwVivcFSW5QVbgosK/o2QuZHms1vCc6tC1sGza+OT1YZWe465cW4jNRW7fx4ks msy9Ia4HJKGcKj1u1StthDIoGNe0jPNNRCwfixCCbhsIu8kl5EdbhBkaAOJGTjzxLAZf Bv9bbx8NKTphmbx8bemLzrtymECuH5WWFEStWDPJlp6dqluOf0EOgjov5G1nTwcbn/99 6V1IcwQ/cUBFnAQ+UHfvGn1YssCCtL98+3EotWIqSk0wFS+MMtuhmD5WuWOcv9MXK3SK oL+O91AqJHe+kT2bNOas/VelkJQaxBD6di93/z4nY9iPMcMc3LCgHQ1sLEmd+cWZ+9Od WH6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dZq4DXS5hfuZufkfinYetDi/sPSwHy1FNwiaqhpssa4=; b=M8+t9dFQV2jwsvlLSuCRC8PdfTAkMTBl4GGdz01Emkx4J97AP+oiv8dBnsUWH9ksXZ nJ1ZClMTe/YSuBEKsg2BRhYfo80Oq1uEE06TYgY4Xe67tnTZnU0bn565l+KWjZr63ob4 FBCjgQML2E3cMdwTsUe0jiuq3TZENhT6MPVxniUXDDveeWYNGaJ/bHnjjSktrn4wI8hY ik8YCNKPiufXBaL63bDgs8tYlsxXm703lHFzT50e+PxyEL6eZ66k6bKtmdr5bfvQ+4Wc j0KkRsLBNl2Nwxr5JqRLfxOgp0MA7f0g3pfN9GJZL0ankv/7EvZK0Mot3DB+fEv3hibu kGJg== X-Gm-Message-State: AJIora8hkB1/7qZ+7mnqKtavmMuu/P/b39yO0aSJ+Cu6BdA149l1cu9D nzm/lWn7Kr6S944Qkg9sQrY= X-Google-Smtp-Source: AGRyM1uUe+TJYcYrAuoAsTQoql0GG3zgxE4cm70M4L11J/HjtjuiCzoxQPxyTkB4HBjRJYR8SssVEQ== X-Received: by 2002:adf:fb06:0:b0:21a:3dc9:f12d with SMTP id c6-20020adffb06000000b0021a3dc9f12dmr19252192wrr.204.1655755617100; Mon, 20 Jun 2022 13:06:57 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id x1-20020adff0c1000000b002103cfd2fbasm14315943wro.65.2022.06.20.13.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:56 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 27/49] mfd: gateworks-gsc: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:22 +0100 Message-Id: <20220620200644.1961936-28-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/gateworks-gsc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/gateworks-gsc.c b/drivers/mfd/gateworks-gsc.c index d87876747b91..28ec167a9861 100644 --- a/drivers/mfd/gateworks-gsc.c +++ b/drivers/mfd/gateworks-gsc.c @@ -189,8 +189,7 @@ static const struct regmap_irq_chip gsc_irq_chip = { .num_irqs = ARRAY_SIZE(gsc_irqs), .num_regs = 1, .status_base = GSC_IRQ_STATUS, - .mask_base = GSC_IRQ_ENABLE, - .mask_invert = true, + .unmask_base = GSC_IRQ_ENABLE, .ack_base = GSC_IRQ_STATUS, .ack_invert = true, }; From patchwork Mon Jun 20 20:06:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB21BC433EF for ; Wed, 22 Jun 2022 15:31:19 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 0C1E71E80; Wed, 22 Jun 2022 17:30:28 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 0C1E71E80 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911878; bh=XW4kyzMVi5YwsnPeL//kAENuSFbFgiljBs7kag1kVQM=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=u6LO8E1ZXRHolPN0kOPcV4pWbqS8xFOFu468rleRnjebfXdLhgM1BatlGf9AWU4qM eV3hVy8W/lSwz6e0qrXQZ6WGJwlWw2xFW/ELHwFGEoxeqVX/avN21gdYvp4SiaaZWL VcMFFusgszap4RYwmNrC9s9VSDZuiufrEuwSZV3A= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id B3F1AF805F1; Wed, 22 Jun 2022 17:23:37 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id B75F7F804E5; Mon, 20 Jun 2022 22:07:04 +0200 (CEST) Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id B764AF800CB for ; Mon, 20 Jun 2022 22:07:00 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz B764AF800CB Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YLV9HVC+" Received: by mail-wr1-x429.google.com with SMTP id v14so16098362wra.5 for ; Mon, 20 Jun 2022 13:07:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DTY/U6s0Ls/Dtw06y3+h8JI8hTjwct+Am+4ddShNVBI=; b=YLV9HVC+AuiPiyFoS3kBS6rWy2Gjdbs/RM2nFfy9wTqwdZFX0UXlXKk5xti7k7/YfQ 2P62pyaX41f81Mx4DSWuyjatSY+/7lA/G8nV48egrVJ2yaymGBYB2GNCkXpSY8BVwdPc UfIABhiWRF+9AghYCFIxPI5Zxc5kChjXJpHLRgpieDaKOWBp5sHc9iq/i8aKzPSn9tFm 4gxgSzdozxH22+jMKs/x0dBZBgERtmU1igIsm48zLXwthMic+vhyTYQctNH5OkVynDcN 7mpW0MeJmLgfC+VbxloiSMxT2IAuB2PsvQjFG1L99Vog+c+Ukv3qRMNVf6Kq/ifo+mKe 7Hdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DTY/U6s0Ls/Dtw06y3+h8JI8hTjwct+Am+4ddShNVBI=; b=7FBnW2+dFT1SmyNyk8g/S9F1z2tesiQ9MiZymq0INWWeka8GCu045S0JKeYfy55FUD LgmPB26HqRrKchM3kGiYzVXxJq/aPR4Dl2mA+/9tLFfhyWe5LYu4c87mAmTOgKP6Z4YQ Cz0aXD7DZiCRa7LFpMjVhoIA5NdwwqviIpRTXfz609TAakgS+PNAXx9jPXiudkZwG9PH oHG1bAsPQa4pSVZKzH79Q8WY7ToDsnIaMp9rdnxEATOaD6hSQWk1+/UCKnKrTwMkh4fc LfmUcAWlfcDbAy9ngakP4MbXhovDH1Q0M6PUrSh2FLroUaRNZAbeeQr18Z13/kE4Ch9k 4EgA== X-Gm-Message-State: AJIora/y5jSinc8c2EnGCloitgUr+B8rUOAflGCHco9oYggYn3ewswID DtKPHzaoqUgTQkpHYbqhVc0= X-Google-Smtp-Source: AGRyM1sDxyahRh5I6JQeiiGBQbk9ax/ShTfPCo/d3S6kQfwtlTUB/zSFPkFow3AhqZQhxwOVIp9FHQ== X-Received: by 2002:a5d:64e9:0:b0:218:3fdb:bfd2 with SMTP id g9-20020a5d64e9000000b002183fdbbfd2mr25588725wri.717.1655755618712; Mon, 20 Jun 2022 13:06:58 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id d9-20020a056000114900b0021b8dd05f45sm4858105wrx.55.2022.06.20.13.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:06:58 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 28/49] mfd: axp20x: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:23 +0100 Message-Id: <20220620200644.1961936-29-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/axp20x.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index 8161a5dc68e8..3be0d0aa8b34 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -506,8 +506,7 @@ static const struct regmap_irq_chip axp152_regmap_irq_chip = { .name = "axp152_irq_chip", .status_base = AXP152_IRQ1_STATE, .ack_base = AXP152_IRQ1_STATE, - .mask_base = AXP152_IRQ1_EN, - .mask_invert = true, + .unmask_base = AXP152_IRQ1_EN, .init_ack_masked = true, .irqs = axp152_regmap_irqs, .num_irqs = ARRAY_SIZE(axp152_regmap_irqs), @@ -518,8 +517,7 @@ static const struct regmap_irq_chip axp20x_regmap_irq_chip = { .name = "axp20x_irq_chip", .status_base = AXP20X_IRQ1_STATE, .ack_base = AXP20X_IRQ1_STATE, - .mask_base = AXP20X_IRQ1_EN, - .mask_invert = true, + .unmask_base = AXP20X_IRQ1_EN, .init_ack_masked = true, .irqs = axp20x_regmap_irqs, .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs), @@ -531,8 +529,7 @@ static const struct regmap_irq_chip axp22x_regmap_irq_chip = { .name = "axp22x_irq_chip", .status_base = AXP20X_IRQ1_STATE, .ack_base = AXP20X_IRQ1_STATE, - .mask_base = AXP20X_IRQ1_EN, - .mask_invert = true, + .unmask_base = AXP20X_IRQ1_EN, .init_ack_masked = true, .irqs = axp22x_regmap_irqs, .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs), @@ -543,8 +540,7 @@ static const struct regmap_irq_chip axp288_regmap_irq_chip = { .name = "axp288_irq_chip", .status_base = AXP20X_IRQ1_STATE, .ack_base = AXP20X_IRQ1_STATE, - .mask_base = AXP20X_IRQ1_EN, - .mask_invert = true, + .unmask_base = AXP20X_IRQ1_EN, .init_ack_masked = true, .irqs = axp288_regmap_irqs, .num_irqs = ARRAY_SIZE(axp288_regmap_irqs), @@ -556,8 +552,7 @@ static const struct regmap_irq_chip axp803_regmap_irq_chip = { .name = "axp803", .status_base = AXP20X_IRQ1_STATE, .ack_base = AXP20X_IRQ1_STATE, - .mask_base = AXP20X_IRQ1_EN, - .mask_invert = true, + .unmask_base = AXP20X_IRQ1_EN, .init_ack_masked = true, .irqs = axp803_regmap_irqs, .num_irqs = ARRAY_SIZE(axp803_regmap_irqs), @@ -568,8 +563,7 @@ static const struct regmap_irq_chip axp806_regmap_irq_chip = { .name = "axp806", .status_base = AXP20X_IRQ1_STATE, .ack_base = AXP20X_IRQ1_STATE, - .mask_base = AXP20X_IRQ1_EN, - .mask_invert = true, + .unmask_base = AXP20X_IRQ1_EN, .init_ack_masked = true, .irqs = axp806_regmap_irqs, .num_irqs = ARRAY_SIZE(axp806_regmap_irqs), @@ -580,8 +574,7 @@ static const struct regmap_irq_chip axp809_regmap_irq_chip = { .name = "axp809", .status_base = AXP20X_IRQ1_STATE, .ack_base = AXP20X_IRQ1_STATE, - .mask_base = AXP20X_IRQ1_EN, - .mask_invert = true, + .unmask_base = AXP20X_IRQ1_EN, .init_ack_masked = true, .irqs = axp809_regmap_irqs, .num_irqs = ARRAY_SIZE(axp809_regmap_irqs), From patchwork Mon Jun 20 20:06:24 2022 Content-Type: text/plain; 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Signed-off-by: Aidan MacDonald --- drivers/mfd/atc260x-core.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/atc260x-core.c b/drivers/mfd/atc260x-core.c index 7148ff5b05b1..7c5de3ae776e 100644 --- a/drivers/mfd/atc260x-core.c +++ b/drivers/mfd/atc260x-core.c @@ -100,8 +100,7 @@ static const struct regmap_irq_chip atc2603c_regmap_irq_chip = { .num_irqs = ARRAY_SIZE(atc2603c_regmap_irqs), .num_regs = 1, .status_base = ATC2603C_INTS_PD, - .mask_base = ATC2603C_INTS_MSK, - .mask_invert = true, + .unmask_base = ATC2603C_INTS_MSK, }; static const struct regmap_irq_chip atc2609a_regmap_irq_chip = { @@ -110,8 +109,7 @@ static const struct regmap_irq_chip atc2609a_regmap_irq_chip = { .num_irqs = ARRAY_SIZE(atc2609a_regmap_irqs), .num_regs = 1, .status_base = ATC2609A_INTS_PD, - .mask_base = ATC2609A_INTS_MSK, - .mask_invert = true, + .unmask_base = ATC2609A_INTS_MSK, }; static const struct resource atc2603c_onkey_resources[] = { From patchwork Mon Jun 20 20:06:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B75D4C43334 for ; Wed, 22 Jun 2022 15:32:21 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 075D12018; Wed, 22 Jun 2022 17:31:30 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 075D12018 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911940; bh=pduRRadCqjm+H5Q0Ot3vxqGM1hN74ck5MfZ2xBpkQAQ=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=f607DuYAEnL9SvYwQAkDlcXyPU4xRYk1ff5lXHkah7XdXRL3YhZ2oaMkvEhNfOAt5 weXwiqEh6lIkxTwsJt+2vA0z1poF68GuUmPQIdIqLRAlJQkXUpHXIK5H8n2BRC0bz7 rqbcRXUBcRrU/cynhW2tWrlodPWR94umknc541ks= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 57817F80606; Wed, 22 Jun 2022 17:23:41 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 7714EF800CB; Mon, 20 Jun 2022 22:07:11 +0200 (CEST) Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 55959F800CB for ; Mon, 20 Jun 2022 22:07:04 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 55959F800CB Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="I9SWwmkb" Received: by mail-wm1-x331.google.com with SMTP id z9so6374441wmf.3 for ; Mon, 20 Jun 2022 13:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oqx3v8Sb2M8GmsYA5Ky+XV9uouybbnIvgB5+4WCQaEA=; b=I9SWwmkbAS0twwPt8IX4E7bPDCP7aUbF2QrdWQqioO/YT8vPWDbo5jafFWHLiMIjc6 1mw/0Uimpyz3cUcNIuL1gNMxnkzOwuSG3edxomlaxXv/3L99G0JTdAg4POHGrEyB2REH 3lIDZKKJ3rfCVWbTQEoaG7JmB0gDKFGBeqb20JXEMuxvSMR5CHUbycRO4F8LKhZqPuhZ YEBHTx15YFCjU5hxF8mncOccOzTdEdvUtBMGeSXsVkIqDI9MxnDbvI8sGUw4c4kcM2YR yU4ZYgDnXaav8BMzDiccmgOUBiOIkEhH4tyXriDpDiHGnyleHXKRGyMCZfOTYeUkSsCw fC3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oqx3v8Sb2M8GmsYA5Ky+XV9uouybbnIvgB5+4WCQaEA=; b=fKJ3EcEV6o0sE60tNXGPOscxL7qM4O3oQjcXW8dk3fPZr0G1e4SojEF9N0ylWmuFtO KQtGG5iGHrvs1gtPXPWWVIvJl7sEA0+lflvmJ6GP29BY+B23ZeVU7OaOpOUQNDqmFvA6 Hu2eFpr8r1JKz/ASmNSstWhSPudme7Cwjh5Oj3y/JoUfI73J/wnI9Ya/z7sKWOPIsbjQ sYsBwbvpVTWDrxml6uf4Ywc6dPv0aM/Q7zMfDnau4ujYedYf81YrBrO/NtS+9omPhPTq tA+9QXSwi4DqKNJLa59ZWeCcdW9sfY83gsvcZUnDPuAW2SvG+PqYPGziH/dUMLkTcDIH d1cw== X-Gm-Message-State: AJIora+9QoChmkfk2QiRpOakxRcywpL7UrcqRFDLkl8gLHO10wmdzOPA kETyGThClqy+/s1/OgSciWw= X-Google-Smtp-Source: AGRyM1swymX/u49DBHMJPPyC7OgnYJ7zcAJGoTucjUXlwJwy4Cy1b+UW+TJYIq67rmm7OR5jau1T3g== X-Received: by 2002:a05:600c:5112:b0:397:53f5:e15b with SMTP id o18-20020a05600c511200b0039753f5e15bmr26726456wms.93.1655755622524; Mon, 20 Jun 2022 13:07:02 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id a17-20020adffad1000000b0021b8749728dsm8178971wrs.73.2022.06.20.13.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:01 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 30/49] mfd: 88pm800: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:25 +0100 Message-Id: <20220620200644.1961936-31-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/mfd/88pm800.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c index eaf9845633b4..6d1192db13c1 100644 --- a/drivers/mfd/88pm800.c +++ b/drivers/mfd/88pm800.c @@ -398,9 +398,8 @@ static struct regmap_irq_chip pm800_irq_chip = { .num_regs = 4, .status_base = PM800_INT_STATUS1, - .mask_base = PM800_INT_ENA_1, + .unmask_base = PM800_INT_ENA_1, .ack_base = PM800_INT_STATUS1, - .mask_invert = 1, }; static int pm800_pages_init(struct pm80x_chip *chip) From patchwork Mon Jun 20 20:06:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4977AC433EF for ; Wed, 22 Jun 2022 15:32:38 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 9014E18FF; Wed, 22 Jun 2022 17:31:46 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 9014E18FF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911956; bh=5U5L11rCWyBgJVVcS+L8bHmJeFeWLj/aqnTHoPwfSCM=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=SqaNTXpTaUzUwb/tmrwQwALqTMDUXlbRmWxObWub5Og+w1q+IyfjKzN5QBeFWsAb+ pk12dM9vRGLPipeeAsGG9EopuXSukYfYO0NPEeyBLWu9QQ0+sbFe/Ou8SDxPhba3+D GmmLtTY+ZiK5luq+VbG8Mtt29wM0KNHl3FRCJx14= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id DF611F80609; Wed, 22 Jun 2022 17:23:41 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 8A3E6F800E3; Mon, 20 Jun 2022 22:07:11 +0200 (CEST) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 6C803F804D8 for ; Mon, 20 Jun 2022 22:07:04 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 6C803F804D8 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qBJcC0Lr" Received: by mail-wm1-x32c.google.com with SMTP id m125-20020a1ca383000000b0039c63fe5f64so6210561wme.0 for ; Mon, 20 Jun 2022 13:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rzfzyKEVoJaKFIv88YU1vTCrVQJBpK7ii1ptmDvGvSE=; b=qBJcC0LrxQSAdxyKj5Dt7HUFUmjMISoYgjBHUUClNbIz3vAp9h4I6Lqto2o/8nRZZx +mUtIMCKQ+xDXPL3Fzv7A9LsfxQhVJy+J3jisVRnKW/heO0ptBVZJfGA10gsSJrLxZO+ MObbJW6hGStsGnZRd48uGh/4qGcgNShaBsFXlaMlKP83cLUJ5mnOfQscQbtReaFC3JVv djWshs0XGTygSwTV7AEfyGWiz4kJ7raOzjYloQWDqDDB2Jm1I+3fzts9p4jEUGs+ylCU BlkyfP5HaSiXqAYXZ7zggOUoAuRHWYspwGWZ2TzWqacHn9MVYPY2Vzt3RKPNhtN644ir H1Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rzfzyKEVoJaKFIv88YU1vTCrVQJBpK7ii1ptmDvGvSE=; b=bqes1IzprhYc3P+DXoHmDKAXiqomikHyio9hYLVrTGo5qPVKICBrqbR6F3uAo4JsHM p87BO29vZbevWUAn+o63JwhXM3E1MLwWpr5g73hkJ09F9bN0ZTZqRQvjxa3KkvHsTMq3 LWXEhbX5qibdHm9/p5X60etpPsmhWH+uzNUCbjAeF3UqVV+PvfCgkCDayGE7gypLlUmA w7NGEXMpDzJs2cy9I6tOGJS32S4iVZ1LM/BsDEn+e4fr/Ye9h7okkmJnmfEznL+j0fzb gzManDV1GolZ0sRfnxxOMVdQPWZcUOGKN9/JwpwPE5nH5S6X30AqhteCAEDrE+MgUMwd RC7Q== X-Gm-Message-State: AOAM532ysNXTM0XRqlGCJr09y4OemHn5LKnws58l1ZLfmloueNZOi1X5 iE0aKlsoKQ0lGDUhEKkYoYo= X-Google-Smtp-Source: ABdhPJyInyenW+OvDrbjpJKIaFUgNOigofr86k1OtUqbh4EqGuM90WNh58WAi7KJRkr+4OM3pXCRPQ== X-Received: by 2002:a1c:4c13:0:b0:39c:5a6b:8540 with SMTP id z19-20020a1c4c13000000b0039c5a6b8540mr36262410wmf.106.1655755624155; Mon, 20 Jun 2022 13:07:04 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b0039c5645c60fsm28045293wms.3.2022.06.20.13.07.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:03 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 31/49] mfd: max14577: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:26 +0100 Message-Id: <20220620200644.1961936-32-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Also drop useless mask_invert flag from the pmic irq chip. Signed-off-by: Aidan MacDonald --- drivers/mfd/max14577.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/max14577.c b/drivers/mfd/max14577.c index 6c487fa14e9c..7a501dcc48f6 100644 --- a/drivers/mfd/max14577.c +++ b/drivers/mfd/max14577.c @@ -209,8 +209,7 @@ static const struct regmap_irq max14577_irqs[] = { static const struct regmap_irq_chip max14577_irq_chip = { .name = "max14577", .status_base = MAX14577_REG_INT1, - .mask_base = MAX14577_REG_INTMASK1, - .mask_invert = true, + .unmask_base = MAX14577_REG_INTMASK1, .num_regs = 3, .irqs = max14577_irqs, .num_irqs = ARRAY_SIZE(max14577_irqs), @@ -239,8 +238,7 @@ static const struct regmap_irq max77836_muic_irqs[] = { static const struct regmap_irq_chip max77836_muic_irq_chip = { .name = "max77836-muic", .status_base = MAX14577_REG_INT1, - .mask_base = MAX14577_REG_INTMASK1, - .mask_invert = true, + .unmask_base = MAX14577_REG_INTMASK1, .num_regs = 3, .irqs = max77836_muic_irqs, .num_irqs = ARRAY_SIZE(max77836_muic_irqs), @@ -255,7 +253,6 @@ static const struct regmap_irq_chip max77836_pmic_irq_chip = { .name = "max77836-pmic", .status_base = MAX77836_PMIC_REG_TOPSYS_INT, .mask_base = MAX77836_PMIC_REG_TOPSYS_INT_MASK, - .mask_invert = false, .num_regs = 1, .irqs = max77836_pmic_irqs, .num_irqs = ARRAY_SIZE(max77836_pmic_irqs), From patchwork Mon Jun 20 20:06:27 2022 Content-Type: text/plain; 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[92.40.169.63]) by smtp.gmail.com with ESMTPSA id z6-20020a5d4d06000000b0021a3dd1c5d5sm11711267wrt.96.2022.06.20.13.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:05 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 32/49] mfd: max77693: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:27 +0100 Message-Id: <20220620200644.1961936-33-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Also drop useless mask_invert flag from other irq chips. Signed-off-by: Aidan MacDonald --- drivers/mfd/max77693.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/mfd/max77693.c b/drivers/mfd/max77693.c index 4e6244e17559..fadea37b97cc 100644 --- a/drivers/mfd/max77693.c +++ b/drivers/mfd/max77693.c @@ -66,7 +66,6 @@ static const struct regmap_irq_chip max77693_led_irq_chip = { .name = "max77693-led", .status_base = MAX77693_LED_REG_FLASH_INT, .mask_base = MAX77693_LED_REG_FLASH_INT_MASK, - .mask_invert = false, .num_regs = 1, .irqs = max77693_led_irqs, .num_irqs = ARRAY_SIZE(max77693_led_irqs), @@ -82,7 +81,6 @@ static const struct regmap_irq_chip max77693_topsys_irq_chip = { .name = "max77693-topsys", .status_base = MAX77693_PMIC_REG_TOPSYS_INT, .mask_base = MAX77693_PMIC_REG_TOPSYS_INT_MASK, - .mask_invert = false, .num_regs = 1, .irqs = max77693_topsys_irqs, .num_irqs = ARRAY_SIZE(max77693_topsys_irqs), @@ -100,7 +98,6 @@ static const struct regmap_irq_chip max77693_charger_irq_chip = { .name = "max77693-charger", .status_base = MAX77693_CHG_REG_CHG_INT, .mask_base = MAX77693_CHG_REG_CHG_INT_MASK, - .mask_invert = false, .num_regs = 1, .irqs = max77693_charger_irqs, .num_irqs = ARRAY_SIZE(max77693_charger_irqs), @@ -136,8 +133,7 @@ static const struct regmap_irq max77693_muic_irqs[] = { static const struct regmap_irq_chip max77693_muic_irq_chip = { .name = "max77693-muic", .status_base = MAX77693_MUIC_REG_INT1, - .mask_base = MAX77693_MUIC_REG_INTMASK1, - .mask_invert = true, + .unmask_base = MAX77693_MUIC_REG_INTMASK1, .num_regs = 3, .irqs = max77693_muic_irqs, .num_irqs = ARRAY_SIZE(max77693_muic_irqs), From patchwork Mon Jun 20 20:06:28 2022 Content-Type: text/plain; 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[92.40.169.63]) by smtp.gmail.com with ESMTPSA id o10-20020a1c4d0a000000b003942a244ee6sm15738587wmh.43.2022.06.20.13.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:07 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 33/49] mfd: rohm-bd718x7: drop useless mask_invert flag on irqchip Date: Mon, 20 Jun 2022 21:06:28 +0100 Message-Id: <20220620200644.1961936-34-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" There's no need to set the flag explicitly to false, since that is the default value from zero initialization. Signed-off-by: Aidan MacDonald Reviewed-by: Matti Vaittinen --- drivers/mfd/rohm-bd718x7.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mfd/rohm-bd718x7.c b/drivers/mfd/rohm-bd718x7.c index bfd81f78beae..ad6c0971a997 100644 --- a/drivers/mfd/rohm-bd718x7.c +++ b/drivers/mfd/rohm-bd718x7.c @@ -70,7 +70,6 @@ static struct regmap_irq_chip bd718xx_irq_chip = { .mask_base = BD718XX_REG_MIRQ, .ack_base = BD718XX_REG_IRQ, .init_ack_masked = true, - .mask_invert = false, }; static const struct regmap_range pmic_status_range = { From patchwork Mon Jun 20 20:06:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6647DC43334 for ; Wed, 22 Jun 2022 15:32:53 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 84F61204F; Wed, 22 Jun 2022 17:32:01 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 84F61204F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911971; bh=bsWHGohdUbfY3nyZypyK44rW2viwGKCYp8ggtV0U/Y8=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=sHRrlCswQ5LgvQkFMumjmfgXDezybQKZ2Mxt68wSp4gySBI0vb2X5Wbx/VlGJWjQX 1SbnrEBHuXn7r2ExREahzmf/XpbT+4/7SFEDWibchJ0fc4IMigsWUf8UKVjy6LR/oC xFDlTG3tfjLpA4seis3/QDOOPyMx66kOpFKVATG8= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 9D6FCF8060D; Wed, 22 Jun 2022 17:23:42 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 2ACC3F804E7; Mon, 20 Jun 2022 22:07:14 +0200 (CEST) Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 30183F804D2 for ; Mon, 20 Jun 2022 22:07:10 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 30183F804D2 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SqSwnGBc" Received: by mail-wm1-x32e.google.com with SMTP id m16-20020a7bca50000000b0039c8a224c95so6195354wml.2 for ; Mon, 20 Jun 2022 13:07:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FJAftx/p0C7OJqXldJ+ksCvuM2Jz1/dLJXnCMlN2VIw=; b=SqSwnGBcriuBOSFplaryTgzwQV9etoBhh79kFYweRlmDdxQeRvrcZhZxeGzYrNQvjK 69NE66snB8AAFxosGQi32hwg8wAh/0UlVrRlylnlYpF3UP2foQigCMMdDJ2hf1VoUcQw IGJhoucIfU9bShmNTRIW7SeERFLMl9SzWwa/gkuyhaNnZGAegN5/b8AD7xgZbr+q96V3 wIZE74xoK0opWS9DO77kd+xhhjv05vYGMC2P4dGUBy6pWp5QiJg6JRI3NjoqvsL5Fuv7 /rYrzhVG+vkyLBPngH5EcdERxjCI3qHqaUK8MI70z8mDb7VK4k5Utxh9mIEOvpvvGk/6 VkjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FJAftx/p0C7OJqXldJ+ksCvuM2Jz1/dLJXnCMlN2VIw=; b=3kvGZjFXZnm6aBo1MEXJvO9PJf45xuMklt5Z762T/fnmCe3YoA5KsQPNDitjWO+xxq qUWXrDHq5zkhP2iZBX0O0IcJv+yEJevnhmSNHoEshxdmm3vHB0PPdqPI7RJehmRkiAks SecOPif2oQxsAYMpre3t4JTKzr3/EcKdmvkmgRd1gntY21c0Zz2Oku0YxkkSKdePcnqJ 6CeR+Gv1E0+rOBa2mTo7V3njiabItTQPszq5sASf3zbtwwDNOByviAAEKNrJdSYknJ7g j1Efir5M6GmpXIV2Pk0DJfYGInRhPFU9wLf3SqGQBqXN4rM3HdGjaelL1A7hB8Wl3+4l mltw== X-Gm-Message-State: AJIora/ukaxfK6OV4uYwC2zZ/fTbLiEkTUwGWqrP+d3OUuI/Q2phVIC3 FaYUMytD/kpGRb0husN6Up4= X-Google-Smtp-Source: AGRyM1uYqQE7GmYoWseO34ZpgDLrPdxmQJYvkYR87njx8ZglDl7MI8oKPbgMJxyF1RluTFoj9tUheA== X-Received: by 2002:a1c:c909:0:b0:3a0:1725:619d with SMTP id f9-20020a1cc909000000b003a01725619dmr5451578wmb.19.1655755629537; Mon, 20 Jun 2022 13:07:09 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id q7-20020adf9dc7000000b0020cdcb0efa2sm7500229wre.34.2022.06.20.13.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:09 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 34/49] mfd: max77843: drop useless mask_invert flag on irqchip Date: Mon, 20 Jun 2022 21:06:29 +0100 Message-Id: <20220620200644.1961936-35-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" There's no need to set the flag explicitly to false, since that is the default value from zero initialization. Signed-off-by: Aidan MacDonald --- drivers/mfd/max77843.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mfd/max77843.c b/drivers/mfd/max77843.c index 209ee24d9ce1..4da58eab1603 100644 --- a/drivers/mfd/max77843.c +++ b/drivers/mfd/max77843.c @@ -59,7 +59,6 @@ static const struct regmap_irq_chip max77843_irq_chip = { .name = "max77843", .status_base = MAX77843_SYS_REG_SYSINTSRC, .mask_base = MAX77843_SYS_REG_SYSINTMASK, - .mask_invert = false, .num_regs = 1, .irqs = max77843_irqs, .num_irqs = ARRAY_SIZE(max77843_irqs), From patchwork Mon Jun 20 20:06:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C3D5C43334 for ; Wed, 22 Jun 2022 15:33:10 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 87EDD1FDD; Wed, 22 Jun 2022 17:32:18 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 87EDD1FDD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655911988; bh=sB6hyCrOr1JiyxvBRqrMiAIcRByL7GK0Ppnds6KEUWE=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=l1uEZ/vQ6SEZx086FkYxFQQVsifLO9lhF+nrmM5+LiKUxxEjIdGiLGGss3jx6Knx2 Agg0+nddsUE2idcag9eL8M1xzxs9SKuRfOo6cElF2yd4ccqDVcgTNNIGl04xKZFEXD 3DpQUPb31ajNVutUg1EpfjOkvNouvhxEb0dl+r4c= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 2C6E1F8060E; Wed, 22 Jun 2022 17:23:43 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 51AB7F804E7; Mon, 20 Jun 2022 22:07:17 +0200 (CEST) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 7B379F800CB for ; Mon, 20 Jun 2022 22:07:11 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 7B379F800CB Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YUDmW8ZJ" Received: by mail-wr1-x42a.google.com with SMTP id o8so16102621wro.3 for ; Mon, 20 Jun 2022 13:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EO+iuOKogLq1gEhCZXsb9WMdWtj7M6TVjC1w+kM7coQ=; b=YUDmW8ZJsJxu9mf+AG0DiMhcJc31kRVZ4ADkdSPk8W6VHXXqo4OhpTn+ltak91umjD t2+KAswtChyR/y4NqqTx+RmQR/8HLN00XtsNQ0e4xwfKxuZBByicexl2a5x5LBn3I0pk x8JO5FxRZt/KDQOCVtNQIKgDYlK/FvLijeVz2EHn2mzjXxfDjOvMwunXb8JB3OkGfefD 6GNtm5l9fhoIdmSS9kdw/3MIBC2aqx27mxgbqN6E4qbJINN1Ul/S8xgw8SLML3o/B/QQ Kk8/5xYVjIsLkrwsviBZMNweB6p+q9qY5xoEECUP5iygiuGIb6cd2pLwlh4Zo+v28+Ho aKgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EO+iuOKogLq1gEhCZXsb9WMdWtj7M6TVjC1w+kM7coQ=; b=4V+bCJ0LFaSl56uj2+oiLmWRQWvMS/3wB0GGybTQU5pR4+zcQ1lxHrwfupMo3DL17u neDHnbjarMZl613pQdhs82xp6+c9h52eyw7zMFeFe+zirYaL8A3LvUxODR03HnaT1r7g VWNhv2DwO371IW1/JDNnFMmozhVikQ+Hjp5N4n8wt/7E7HIqVyV6qBLP0BRsVMainNKC Udew/fN03DfpjAIRQXlW9S3GI5NDiL9A4N/cV+HMHVnpoI7GltuRauRCC07yjsaLzuiR FDmjmKh5NyoGhK7iXqCtf07/Qxh0xcd2AfPKxlah8mvHI6tdOkTL22NgNariAUhG0/O4 I26w== X-Gm-Message-State: AJIora+22EEncFnii2k8hfNPq2SWkhypT5pHMknb5j7pdhhJtcOwIXPH ewTl9YoaMtI4naaiSNF1RSE= X-Google-Smtp-Source: AGRyM1uQnJZI6JTSn/IXnIpbA1+48K9Xd0eSzXtkoL8kKSucoVse7cEUTXPmpKK2qI8vGS5EmgHfHA== X-Received: by 2002:a5d:6a01:0:b0:21a:338c:4862 with SMTP id m1-20020a5d6a01000000b0021a338c4862mr23039009wru.631.1655755631108; Mon, 20 Jun 2022 13:07:11 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id m6-20020a05600c3b0600b00397402ae674sm20063059wms.11.2022.06.20.13.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:10 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 35/49] extcon: max77843: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:30 +0100 Message-Id: <20220620200644.1961936-36-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/extcon/extcon-max77843.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/extcon/extcon-max77843.c b/drivers/extcon/extcon-max77843.c index 8e6e97ec65a8..1bc0426ce3f1 100644 --- a/drivers/extcon/extcon-max77843.c +++ b/drivers/extcon/extcon-max77843.c @@ -189,8 +189,7 @@ static const struct regmap_irq max77843_muic_irq[] = { static const struct regmap_irq_chip max77843_muic_irq_chip = { .name = "max77843-muic", .status_base = MAX77843_MUIC_REG_INT1, - .mask_base = MAX77843_MUIC_REG_INTMASK1, - .mask_invert = true, + .unmask_base = MAX77843_MUIC_REG_INTMASK1, .num_regs = 3, .irqs = max77843_muic_irq, .num_irqs = ARRAY_SIZE(max77843_muic_irq), From patchwork Mon Jun 20 20:06:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C566C433EF for ; Wed, 22 Jun 2022 15:33:24 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id D1C3B2080; Wed, 22 Jun 2022 17:32:32 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz D1C3B2080 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912002; bh=VHYdr7QfZJ2tX5PnSrpqgiTvM/4aEjFRbj0kPGHeAkA=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=LAWE7uW+DfSCixROTqRMXzxF8KpyPDkcrTF9N8/kEw/Vn9J90xbP93ZuJM/uKK/K8 ENy0Y6fT6f4+XhHk24WVMFZstgIrjoXpp5XaAHO/bnlmXgDGtIJtwBnvwaAWHlDd80 QdlB4HMLA8cBkXLAhX7Pi1bwipH01ta9DAhKdUn4= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id CF3B9F80615; Wed, 22 Jun 2022 17:23:43 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 68B11F804E5; Mon, 20 Jun 2022 22:07:17 +0200 (CEST) Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 0D55FF804DA for ; Mon, 20 Jun 2022 22:07:13 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 0D55FF804DA Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="N5XPG9Op" Received: by mail-wr1-x429.google.com with SMTP id o16so16088316wra.4 for ; Mon, 20 Jun 2022 13:07:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y97fwLubKQPhfVzVr/BJ8A0OiHWSUnBqrgJCFHiEuQo=; b=N5XPG9OplADmbLH0pHfxycXOk0ogBS6as/63+9NbBIR+tpKjwFF8jaDqvXytgN7eFN iCIGHlH+jU+vvt27pchv5bzTabl6azkQzKY7vFkafPwH50QQyWfkBzOGOCCVxQXhvncE YaWxNzKfmxeTvJUbcVoUMVUAWlE3JvZZ4lB+5+QyyAHS3e43yyMBrnmUQcQabmJqyNxu yz5S4TVH2O8DPD2Rf80CaJq7lQH+C0gh4FsLbgYgRXSmVebkFxyjrNjhCPP76XpsYQIa zUI7t6/WnGNbz1TtlV3gFxQsN1aO4fpmL8EGt0pWJOiQvv0pEELOjmzyWY2VXTtrFst3 zOhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y97fwLubKQPhfVzVr/BJ8A0OiHWSUnBqrgJCFHiEuQo=; b=Pnms0Hr010XOe/yl97K10bB0mv667gbxh75mINRuJ3gued38ryKCAYBWHBG2lkCK8c AsTysG21EugLteDH+/gXifjco7ttdrs+c0+5JRA+5wOfyZgBE+JTZaPh1zuW3ubq+uoh iT0LzlPacUKLMAsSQDeG4+mOHkoGivcFU4cmSeVdrbptBbRi7b5i76YkKHWfT6kthpcd JWfK3XiRzUteiPaT2zLraa2LlUux6onDHqgXJoJuAQMbkGCqCnZoq9XLgEj4MIWlt1Kw wU55evDqUDIpcnfKKM28sHqSQkw573M4CWvBEDMQQlUXs+NMDB/G30iTQNCIy1SvysVF jTsg== X-Gm-Message-State: AJIora90sSBQpoJq8dcAiKj9CkgReotNN/1Lr+sFsUgEWwXj2YDxKnL5 nkw2jDqI5NBZVX4mqxkrh2U= X-Google-Smtp-Source: AGRyM1snTNRqPq+iZgzXYj3YO4MyMbr+ecuPp+zCi4PLi5xytxdvLNbc3QFI/5y6NXWpWtWF0rRckQ== X-Received: by 2002:a5d:5e92:0:b0:21a:278c:b901 with SMTP id ck18-20020a5d5e92000000b0021a278cb901mr24824370wrb.461.1655755632740; Mon, 20 Jun 2022 13:07:12 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id c5-20020a05600c0a4500b0039c4ba160absm33779394wmq.2.2022.06.20.13.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:12 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 36/49] extcon: sm5502: drop useless mask_invert flag on irqchip Date: Mon, 20 Jun 2022 21:06:31 +0100 Message-Id: <20220620200644.1961936-37-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" There's no need to set the flag explicitly to false, since that is the default value from zero initialization. Signed-off-by: Aidan MacDonald --- drivers/extcon/extcon-sm5502.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/extcon/extcon-sm5502.c b/drivers/extcon/extcon-sm5502.c index f706f5288257..8401e8b27788 100644 --- a/drivers/extcon/extcon-sm5502.c +++ b/drivers/extcon/extcon-sm5502.c @@ -227,7 +227,6 @@ static const struct regmap_irq_chip sm5502_muic_irq_chip = { .name = "sm5502", .status_base = SM5502_REG_INT1, .mask_base = SM5502_REG_INTMASK1, - .mask_invert = false, .num_regs = 2, .irqs = sm5502_irqs, .num_irqs = ARRAY_SIZE(sm5502_irqs), @@ -276,7 +275,6 @@ static const struct regmap_irq_chip sm5504_muic_irq_chip = { .name = "sm5504", .status_base = SM5502_REG_INT1, .mask_base = SM5502_REG_INTMASK1, - .mask_invert = false, .num_regs = 2, .irqs = sm5504_irqs, .num_irqs = ARRAY_SIZE(sm5504_irqs), From patchwork Mon Jun 20 20:06:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A39FDC43334 for ; Wed, 22 Jun 2022 15:34:12 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id DF922209E; Wed, 22 Jun 2022 17:33:20 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz DF922209E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912051; bh=xeYFxgWlLAVDMsEkAA6W1rHTIvjU0RDo7Pn2A8eaPO0=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=bOUuEYI23LIpJAlqlN70zJG3anTWwrnuwWi0yNEWnugEzraOWBH0AamulKVINrDDN 5jzSWpfGQHrbSIwqKScbMx9+jApdwpkTP2BnxIaoPnXvET1GIDH8mgnKPcCxqpOyAE MYx1hifcQaqG4FllqzshkxjdaQGTfI/LBwDgwY6o= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 92A9CF8061F; Wed, 22 Jun 2022 17:23:45 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 8E8E6F804E7; Mon, 20 Jun 2022 22:07:22 +0200 (CEST) Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 1E909F804D2 for ; Mon, 20 Jun 2022 22:07:15 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 1E909F804D2 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="O31tT53s" Received: by mail-wr1-x435.google.com with SMTP id g4so16062228wrh.11 for ; Mon, 20 Jun 2022 13:07:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dbyvlkbY4sJOjh3UQdGyOPNGXQQ/y7Irc+C1CWkw+ak=; b=O31tT53sO/Sz1zUUmz4+b7clogfECSiQb9wF145zFCWeos95kyFGhyMNr0ihPdqpqx bJc50KM0wIrtRqZCqzGADVF4M3k1QjGTHVo1VYjGwT74JLbT3B4kvTSheNe818VtY8DZ HDqJJzSXulU9aA8Q7p64IRscmVk+LyazVQczqtnvFpnAbVUfczXyJXpSX6rv84tpA2ID Fp6mzmh7R3C0ofGj++M07N5Nk1RQvkOi9t24WmMCnaJkp1Xa/s9Jij2cEafhCNNYBn56 seJUbVNIALw9YCjjSnuje4l/jDR/w2Hi2qVNJRlUiL9Bqsun5VReJR/qIIMDhEg6iASO mm4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dbyvlkbY4sJOjh3UQdGyOPNGXQQ/y7Irc+C1CWkw+ak=; b=YmX16GgGEeZf14JO3a3xs8QlW7VaDcQoseJfVxbDFUaz2bIFIKzJs+ENhjQeD7QfQo L5Mt3sy+hQwNyHcYKsTsf5NM8GHhy/qILxSmK0+No6pOYIuIoTSEwGoeJq1Mm9q7+N7w NmxD1/zrb2QVL3aZWtwr+TrqtVWniS7rVV/ik2FLDn793EHV1Jy8jsNNWksr2WWRMkPI fUkjT/vW0Y9ZgcI6ScqPbAMDJMX7pA0+hsaSuZ1lbNSk8bn49vGm0Ngb3HExtnjAk8+5 MNASFD9gTVHkx45fENciJF4pWG+soaEafRdBcCPdSDDUUtevekgdvhMgUYFHBpdfNVSx j+Cg== X-Gm-Message-State: AJIora8QFrlAc1PgTiv1n5Dxx4XpVkbw1JIkJEONrfDT5b9tEPrN0Cj5 cplFRJDpIfpZySKzZr5bFc0= X-Google-Smtp-Source: AGRyM1txLq4Tx5IKJyl2yL+hQwHqEppU3pzgOBeDxgV9FsOmPyXZOlr03TOSB7o38hDoIT4MKowqhA== X-Received: by 2002:a5d:588d:0:b0:218:4d0e:b89 with SMTP id n13-20020a5d588d000000b002184d0e0b89mr24292034wrf.58.1655755634413; Mon, 20 Jun 2022 13:07:14 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id n68-20020a1c2747000000b0039c5a765388sm15705645wmn.28.2022.06.20.13.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:14 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 37/49] extcon: rt8973a: drop useless mask_invert flag on irqchip Date: Mon, 20 Jun 2022 21:06:32 +0100 Message-Id: <20220620200644.1961936-38-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" There's no need to set the flag explicitly to false, since that is the default value from zero initialization. Signed-off-by: Aidan MacDonald --- drivers/extcon/extcon-rt8973a.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/extcon/extcon-rt8973a.c b/drivers/extcon/extcon-rt8973a.c index 40c07f4d656e..02ba770acb27 100644 --- a/drivers/extcon/extcon-rt8973a.c +++ b/drivers/extcon/extcon-rt8973a.c @@ -192,7 +192,6 @@ static const struct regmap_irq_chip rt8973a_muic_irq_chip = { .name = "rt8973a", .status_base = RT8973A_REG_INT1, .mask_base = RT8973A_REG_INTM1, - .mask_invert = false, .num_regs = 2, .irqs = rt8973a_irqs, .num_irqs = ARRAY_SIZE(rt8973a_irqs), From patchwork Mon Jun 20 20:06:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50B86C433EF for ; Wed, 22 Jun 2022 15:33:41 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 865DC1B38; Wed, 22 Jun 2022 17:32:49 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 865DC1B38 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912019; bh=Axzq/NuK+tc7TvHHcMaj/cDHQxJMVCSRD9aOEV2d/wQ=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=ufwG+Ri4B0Mi8ChlH656D+UWx/KquG6axe9/tlCPgRD82bbrPF9XU0E7U1twCE20u a9tTO7WwGwmRMN2hY1nMjjkc2w5JKCwFpScEohc3z0w3HWFjhOawlehZnLuDDSoZAQ PeAIF16euBfAK97Lzkdc+/fB+lYM+NkAIJmWJ2Dk= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 723D5F805F7; Wed, 22 Jun 2022 17:23:44 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 2C950F800E3; Mon, 20 Jun 2022 22:07:20 +0200 (CEST) Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 6E83DF800E3 for ; Mon, 20 Jun 2022 22:07:17 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 6E83DF800E3 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HAVLNiSG" Received: by mail-wm1-x335.google.com with SMTP id x6-20020a1c7c06000000b003972dfca96cso6194801wmc.4 for ; Mon, 20 Jun 2022 13:07:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4twauV1jKrSap9S7bWtY2G6jDd+AwgeAtPmARMXtVJs=; b=HAVLNiSG1Db+lrcRkQRn8OxHpInOCKVObpVGiV2a54L1CQgeoGOooL330nzmb1IrII a3+TudV6Bx14k7cwx4iQj2dXFhyD/5OkarV2X1AcQ8112qn1+A6sYLyb7gP/k60vWcpp QlXmznoiGFzV+kfuaH3NwBCvN7xAfZ6eQWiXmrgD9jVR+QP4E0pwxB386bRkdp7qjh4v RRefsra95ego+spLsfQaC4Onjyy0W/nUDl+zsdYC0d5hRcphjIZcJd2yOdzoQBdmrOLN oGvMMVKLgN9yHbyQ2rgqGCUc73aP/jM/TLKGsXmkumYZuLKeHNvCzWm6gGOK0EhOiQTm KNOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4twauV1jKrSap9S7bWtY2G6jDd+AwgeAtPmARMXtVJs=; b=yDVtRyWfZua3R55AGuki2ZTc7Gr37l7Brc1PKDeQbjxl4ObDFQuZzi4ZXdOpRSCEDp BTHha9XLMDaT5cVDzdVFfoBfg7mXbAl4F2mmv85aoFt7ggNAlCWF2bsh8UoTCZXq1Ot2 0OOK1ZzW7yqi5cGTSdnVrIPDsxqTB0nThuNAZPLs4GwIfQskuWzPhqemEn+Fa5bJ1+EH s8Z/eicvlcOIUtQCiCwVzzafvWHwx5/yQDeJHEzysXxopEK1BQzlbi69ytS8+V1AWWM1 F+VraHZTsBlCQAyaXET+Uka7PXQDMF8VR7J6za2aTGr7F4UawgSNdiDUFKjQQm6oqcwn bpyA== X-Gm-Message-State: AJIora95aZeakksZIVzd8SSZrVjj+mH3gnKkZTLNvSTFkqgzVu2TLT1R 6FAt8F26/BB98i0K6BuFsg4= X-Google-Smtp-Source: AGRyM1vZj7DM/aKfxxiAy6DKWUA3/0+uS2K9N2/ZQZ6xqLKDO+9vKTvK3AWaJgypH2v81OQNNU2jMg== X-Received: by 2002:a05:600c:4787:b0:39c:8576:8f55 with SMTP id k7-20020a05600c478700b0039c85768f55mr25382417wmo.1.1655755635917; Mon, 20 Jun 2022 13:07:15 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id n37-20020a05600c502500b0039c5cecf206sm16544192wmr.4.2022.06.20.13.07.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:15 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 38/49] irqchip: sl28cpld: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:33 +0100 Message-Id: <20220620200644.1961936-39-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald --- drivers/irqchip/irq-sl28cpld.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sl28cpld.c b/drivers/irqchip/irq-sl28cpld.c index fbb354413ffa..f2172240172c 100644 --- a/drivers/irqchip/irq-sl28cpld.c +++ b/drivers/irqchip/irq-sl28cpld.c @@ -65,8 +65,7 @@ static int sl28cpld_intc_probe(struct platform_device *pdev) irqchip->chip.num_irqs = ARRAY_SIZE(sl28cpld_irqs); irqchip->chip.num_regs = 1; irqchip->chip.status_base = base + INTC_IP; - irqchip->chip.mask_base = base + INTC_IE; - irqchip->chip.mask_invert = true; + irqchip->chip.unmask_base = base + INTC_IE; irqchip->chip.ack_base = base + INTC_IP; return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev), From patchwork Mon Jun 20 20:06:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B84F2C433EF for ; Wed, 22 Jun 2022 15:33:55 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 149B62098; Wed, 22 Jun 2022 17:33:04 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 149B62098 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912034; bh=Xk1voGX+liHEb+NZMPIX7T2gTR1FlKHOj3NFh1i2EUI=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=MeHhTQIJFA1t/aO0p6D9G3voFy+v1KGKaX1pjTeIbLO+jXsQPqAqqZr21NiKlCfIS HQBJ0fhShVvwAhg2CcQLNWZCibIc5tlecJA97cQHh1VJkKSsZ42cE5VE9po63QFWiu o38/QYdqS5aN7/RWiPz65HRgz8BRJTy/1XBhAQVI= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 0AA06F8061B; Wed, 22 Jun 2022 17:23:45 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 371D8F804EB; Mon, 20 Jun 2022 22:07:22 +0200 (CEST) Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id DE52FF804D8 for ; Mon, 20 Jun 2022 22:07:17 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz DE52FF804D8 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JYv78xaE" Received: by mail-wr1-x430.google.com with SMTP id c21so16101605wrb.1 for ; Mon, 20 Jun 2022 13:07:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NcUaD1/hetXoR1Hr3zOaIrV5ibqb80WKTQCzVE8bVrc=; b=JYv78xaECQZTaj29SjmNHnhs4gfEEratnCgfJZagJJiK+EVif7vCkcuTP1QF0wfouK JhOxz5Q0vETS+bhO7JLSkwPttvHYnqkEyX3HWyCMGYjjskRlAQvkUsr5XtoBlAJVGwhM Gw+0xCBp9YPW230YKLPHGegCcK1UoKqqxF+q0NM7n1ss/f9b2tA03ELnh9lj8wNVqRiD p3oWRBH9z/0ejlWRohZ3vCWr/VL+wIvmrnrFxL5IVwRiWT8mfm+mPnriC/8/NBkGAEQT cw5lNfhGyRNeY0VAdg2EvhXglVeSK8bk4eq65rFbOML/1pGcXaRo+6lWO3/nbDyuiy/y 5z2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NcUaD1/hetXoR1Hr3zOaIrV5ibqb80WKTQCzVE8bVrc=; b=JllhR564lXgb2+3B+ABw7o/Ha1dlbCjAeaxCsSV1Pe/y8isDypmOxbjzWbeH0mbZGj wO5ENYii0GtbtAR4aTf0G7YgwaE6XlGmDTV+hP+2WfMfxLIKSZ/4a8QPFTwiTK2WnAP3 HUlWUvEcrOrmWEagp5XDM01Zc0hAYWxFbbz+JV6WUQadBMMHnGS7ZXpwMmeUvc7nVtm6 Ghvbrpwi3l+TJZ0AhDPf4KSi8Ul8DfJFxbd+8w9zrA0T673Lrc5/m64Rwj4pj9hJ14l/ u+YDKUZykJSlDeJygJc6tiBGlRqoD+S0QzMgB6pef4XrT3Hwi0bbzdH94MtodHMm93V/ is4Q== X-Gm-Message-State: AJIora97FQsrtAPb8vCanxKQJz7KcIqzTTFZNpI83YDUOikL1QBete3m lSQKCeiMsRlhUndwsluH9+E= X-Google-Smtp-Source: AGRyM1t6EjGq1Ksd7MyVDLpDLClD84TIjP3RmrRekqAiittfXcb8Cp1PUoN9E0quIHfglyDXxzFsVA== X-Received: by 2002:a5d:4601:0:b0:21b:9035:d295 with SMTP id t1-20020a5d4601000000b0021b9035d295mr6103622wrq.63.1655755637616; Mon, 20 Jun 2022 13:07:17 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id m42-20020a05600c3b2a00b003973435c517sm16572141wms.0.2022.06.20.13.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:17 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 39/49] gpio: sl28cpld: replace irqchip mask_invert with unmask_base Date: Mon, 20 Jun 2022 21:06:34 +0100 Message-Id: <20220620200644.1961936-40-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald Reviewed-by: Andy Shevchenko Reviewed-by: Michael Walle --- drivers/gpio/gpio-sl28cpld.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-sl28cpld.c b/drivers/gpio/gpio-sl28cpld.c index 52404736ac86..2195f88c2048 100644 --- a/drivers/gpio/gpio-sl28cpld.c +++ b/drivers/gpio/gpio-sl28cpld.c @@ -70,8 +70,7 @@ static int sl28cpld_gpio_irq_init(struct platform_device *pdev, irq_chip->num_irqs = ARRAY_SIZE(sl28cpld_gpio_irqs); irq_chip->num_regs = 1; irq_chip->status_base = base + GPIO_REG_IP; - irq_chip->mask_base = base + GPIO_REG_IE; - irq_chip->mask_invert = true; + irq_chip->unmask_base = base + GPIO_REG_IE; irq_chip->ack_base = base + GPIO_REG_IP; ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev), From patchwork Mon Jun 20 20:06:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12890999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B23EBC43334 for ; Wed, 22 Jun 2022 15:34:27 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 080222072; Wed, 22 Jun 2022 17:33:36 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 080222072 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912066; bh=C3RLgvOHtC4wW2FaN1spuP4JfxX+4t6GORKGQTVdLCY=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=b1Yd8LuIp87vUwPqmvDp6RuszKWNxuY6t9Y5kSQpOL1w1YLqSHUNOMxaSTerrsNTP pYhVNjRG1+OhWn/2rGLg+nTDqdyu9JPPlTwp/NKD0lhdNfKEyC4skLs3AuMH6tVTOs 9ADnV85L+gq5/P2oqrJTnGZf00tfoQEHwG5v4MU8= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 3D253F80623; Wed, 22 Jun 2022 17:23:46 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 9AD43F804D2; Mon, 20 Jun 2022 22:07:22 +0200 (CEST) Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id B8842F804DA for ; Mon, 20 Jun 2022 22:07:19 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz B8842F804DA Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QjvV+I2L" Received: by mail-wr1-x435.google.com with SMTP id g4so16062228wrh.11 for ; Mon, 20 Jun 2022 13:07:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=drtbL6Ol3nSvJosEWn6BWyNAP++5ZasjbOfmzop3MZQ=; b=QjvV+I2LY/VPVY45eWYJLbt7si9DgUbUdBiK1tnDmgIOAGcJlPEfPEbz0xPv6PFG6C fqwpwN657JaXPxJXBP5AOwcKcjfbM0nFCo3ly+/TCctIcxL8Ez9srZzj3C6ZbVZaRiqz JbpxIf/a/wjakAyd7TsXsc3ArAii392QnIxa2RXb5I35fEt59JdMD+jqhaGkdRCDDnM/ pAKKZGaQWk1j3re/9CnNYt5bHRviVWNWQz6tjo3Kf2EI4KjNuph2+cI7M7xbk0fkDW+c fBjVbekqWUfyD7IfdeqH1QuljKLVCEXC/+72mhEJsa01pPfOg9ygPXXe7cysaPnB7z2q C0NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=drtbL6Ol3nSvJosEWn6BWyNAP++5ZasjbOfmzop3MZQ=; b=rmCgzJ2SgWoN2K34DNXKcqOjy5C7hRKv6fX/iQJgvXuX19jUwNMl+c3RXlBAn2kh2c Nz4DVFo1GXKqTWsAzTeY/0w0fRYgu27khFg0FJVQRjzClhh6iuf2cbsp1EB98VIEqGUr rQwrMIKqd1dzjS6RK9rxPkGLeDt0AcTQrZEBppmlqFuVOHFLIdaphCFjJJfqlU6UrHJx e98E/bT2kjcfUeKUpGysJr2gidLeiQfu00gt8LGdjEYT4mBm/hMmqmEr0sbWS1auN1b8 C0tMEejSrUnqGA2kRp4seBIvb2u3ZL0muCnDcYWcjRe2qAkCQ0CnITeHrBopC5NzC+Kc NjFg== X-Gm-Message-State: AJIora/dNjBo/V3aaa6x/QRTHSb+L9lGJiPPQJZ/LW/7V5qurX4ZeAG7 e+N2VhKGDhOWEEA7gD9yZpk= X-Google-Smtp-Source: AGRyM1upACNZTooDfHG9XrmiWJXxBNAesYYQbcORquUwOuEJ3OJEEk57wgHnkZp1ZcThb45MTPunjw== X-Received: by 2002:a05:6000:1788:b0:219:e28f:dc98 with SMTP id e8-20020a056000178800b00219e28fdc98mr24527156wrg.144.1655755639378; Mon, 20 Jun 2022 13:07:19 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id c130-20020a1c3588000000b0039c798b2dc5sm19765399wma.8.2022.06.20.13.07.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:18 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 40/49] mfd: stpmic1: Fix broken mask/unmask in irq chip Date: Mon, 20 Jun 2022 21:06:35 +0100 Message-Id: <20220620200644.1961936-41-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Swap mask_base and unmask_base, and drop the broken_mask_unmask flag since we're now expecting the registers to have their usual behavior. Signed-off-by: Aidan MacDonald --- drivers/mfd/stpmic1.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c index 2307d1b0269d..11f3d92acbc0 100644 --- a/drivers/mfd/stpmic1.c +++ b/drivers/mfd/stpmic1.c @@ -108,9 +108,8 @@ static const struct regmap_irq stpmic1_irqs[] = { static const struct regmap_irq_chip stpmic1_regmap_irq_chip = { .name = "pmic_irq", .status_base = INT_PENDING_R1, - .mask_base = INT_CLEAR_MASK_R1, - .unmask_base = INT_SET_MASK_R1, - .broken_mask_unmask = true, + .mask_base = INT_SET_MASK_R1, + .unmask_base = INT_CLEAR_MASK_R1, .ack_base = INT_CLEAR_R1, .num_regs = STPMIC1_PMIC_NUM_IRQ_REGS, .irqs = stpmic1_irqs, From patchwork Mon Jun 20 20:06:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C133C433EF for ; Wed, 22 Jun 2022 15:34:44 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 7846920A6; Wed, 22 Jun 2022 17:33:52 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 7846920A6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912082; bh=ZnVGfFx4w4okv/nIK0ywmJeln0DOUFoxvbYe+lWFSJo=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Wg9GD88QXlrcOG2cy4Ca/Lo98Dh49EtT7HbChTb+s9/5P6zVSvQtoIGPqhSch4AIl 5unOS8YbsO0aTeMBCSwautrWOhN/ef/2UCoJOjICbbi3oBcdhTCaKeCKjZ8cUzU3BZ /UbnU/LrLatNl70dDDceR7s28t8LNacdDddYGGDg= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id BDDB7F80624; Wed, 22 Jun 2022 17:23:46 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 6F5A5F800CB; Mon, 20 Jun 2022 22:07:25 +0200 (CEST) Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id B741CF800CB for ; Mon, 20 Jun 2022 22:07:22 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz B741CF800CB Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ebmJPjTe" Received: by mail-wm1-x32e.google.com with SMTP id c130-20020a1c3588000000b0039c6fd897b4so8272060wma.4 for ; Mon, 20 Jun 2022 13:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jlVXT9wSLhbjTPX5ZR3Wmtb87jq29nLk3aAphr92sAg=; b=ebmJPjTeif3YqVHvTJpEhOnpA1LETt7fyC+dYjLX7rLJosvOzs1UQNRtfP7VlocI/M SwIjzmreM6vhiA8WP0nFyAlnvkcR1cph6p9w9CAsCH9xBR/BnJhAC1VOP2xg7dIrjnee +zaNjC6ZldbBdoFD98cx82VUpbinKwzYspMqw+aPPgXpt8M4kAHnWjx5TOKgR6frrIsg bXuvPeqxYG3zzsjOeJPJz1FR22BVk15SC32yeUV3YEF8h3u7ZygHhwDQwSNzGNcaPpgo N13v2bUVREQpLfKZ8qO6chIOpZWPy3oOCIUIt5sPYXlDIPpr/V0HH+XrX7eAvdFaGSwv Ar1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jlVXT9wSLhbjTPX5ZR3Wmtb87jq29nLk3aAphr92sAg=; b=bMWSLUe18N47qbT8Ym3BBiCbSWDUC3xXqMT+b/2wg0x7uVdb2AyEbHOLEXPFpgoW/W Z2MNmrrKno3QpnhYMuYz46QNHpHSKUbtKJLygKnzUZKX/jkfOdjv2I9FJQnMGPmwAsAe GiJRCwfPnwm9EIjZ1PrPMpUnca5EuvWwy9OuayrvrrLs+JiiiTViNoYRNgYzIl/QobqS MYI/4JQo4G6jOm+JWDMAiSGuqXeeL7+CWZa5F3BvCBYcMOggPc/L8gALMdsPr1yaUWYP SGKlvcux8rJbR4diALeFZmRSQc3WCJfvQ0NNuibiWTIJuGbGIuGHZ7MB1ooK8mpm2oHg ILaw== X-Gm-Message-State: AJIora/S8JnlH8gBkxJ2EIR9ZeGii3tWwN29Me/g2U7yul06GKgs/Z4e uiALL2MKtd4fayKv8AKa43U= X-Google-Smtp-Source: AGRyM1sc/mkNVW+Wf51Vzi8+T/JAUXCnQCm+ky6mXOwMd5kGL1382a4p9m8dOR+VJbmTp4xRJYVpMw== X-Received: by 2002:a05:600c:19c9:b0:39c:72fc:9530 with SMTP id u9-20020a05600c19c900b0039c72fc9530mr25836673wmq.88.1655755641072; Mon, 20 Jun 2022 13:07:21 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id b9-20020adfe309000000b0020d0c9c95d3sm14556677wrj.77.2022.06.20.13.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:20 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 41/49] mfd: stpmic1: Enable mask_writeonly flag for irq chip Date: Mon, 20 Jun 2022 21:06:36 +0100 Message-Id: <20220620200644.1961936-42-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The STPMIC1 has separate set and clear registers for controlling its interrupt masks. These are volatile registers; writing a '1' will set or clear the corresponding mask bit, and they read as 0. Marking the registers volatile and using the mask_writeonly flag should reduce bus traffic by avoiding a read-modify-write on the mask set/clear registers. Signed-off-by: Aidan MacDonald --- drivers/mfd/stpmic1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c index 11f3d92acbc0..a99f7b45df57 100644 --- a/drivers/mfd/stpmic1.c +++ b/drivers/mfd/stpmic1.c @@ -42,6 +42,8 @@ static const struct regmap_range stpmic1_volatile_ranges[] = { regmap_reg_range(WCHDG_CR, WCHDG_CR), regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4), regmap_reg_range(INT_SRC_R1, INT_SRC_R4), + regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4), + regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4), }; static const struct regmap_access_table stpmic1_readable_table = { @@ -110,6 +112,7 @@ static const struct regmap_irq_chip stpmic1_regmap_irq_chip = { .status_base = INT_PENDING_R1, .mask_base = INT_SET_MASK_R1, .unmask_base = INT_CLEAR_MASK_R1, + .mask_writeonly = true, .ack_base = INT_CLEAR_R1, .num_regs = STPMIC1_PMIC_NUM_IRQ_REGS, .irqs = stpmic1_irqs, From patchwork Mon Jun 20 20:06:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BD55C43334 for ; Wed, 22 Jun 2022 15:35:15 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 8D95620CD; Wed, 22 Jun 2022 17:34:23 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 8D95620CD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912113; bh=+0yLKRFOKqBW1Upp/o0HCNE6LCYhV91297Rd5m9WDJ8=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Lj2OVpXXJBr5VwaYk/y2B1VOiaEHTPIELnGCkYFJbrL+GeDpLYgnqyDTVl+t89yxv XC9efwD363GM5UEeKTg/Il0D5Vt6k8Spn8NJ5OG1Zz+dr0IgzJ4pfV0xBD/GoBZvCS SmiWjPpzwCJzfoALNcYikpgm9C0NMCj6muyiTMR4= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id D7736F80637; Wed, 22 Jun 2022 17:23:47 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 97C84F804E5; Mon, 20 Jun 2022 22:07:28 +0200 (CEST) Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id E047FF804D2 for ; Mon, 20 Jun 2022 22:07:24 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz E047FF804D2 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TIaLYM+7" Received: by mail-wr1-x430.google.com with SMTP id i10so12335105wrc.0 for ; Mon, 20 Jun 2022 13:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dqZEE7XdviwRWITP3iO6UBVL417kMvPw/5cpdhOCnY0=; b=TIaLYM+7aLuuRlXrQlapwog96FVtU0ooWGOQ047CVxq6/eBhXYieIqxwCcMXfW3g6t f+HGuhXPfSxIelrPnYEN7OU7peoZLJxZnRXDaJcr5fL+fEf69btKbTF4tAUZNYQyHScv iwtpLeRs+BLtCQHpOHV5HTtcb+smm2n5XiEw9va+rWEPvmpRhr9uihWsn8c3AWaKo2tu ixhGNtLy3TSWF+J6E4waInzEuxA2ck3ipVwp4MrV2tbNe0NS3OQkYDrzOC8k9atTsxJT 71CeVTVSDdBpYrNOzHBu5VTgwxnGKG7OS+jOMILWiKTmwhHwDvjmfpRNJ4UZ4pzCshkj 2pww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dqZEE7XdviwRWITP3iO6UBVL417kMvPw/5cpdhOCnY0=; b=pVEO8qcocxfAVSEAS6Gjg1P0+UB7xc9QyQ9n+56Iy2/pn7tr7eDSNBLZRzlSWk4Iuz xMZxeVOEbpBqIhO2cHVJzgWvIWREsnkRw9dqF4p+U7DE3f1F6VlXx/yr2/znXn7gtKP/ CMwvuObln4X3+Qm4KBZRh9/zVB1b/m9qSskV1m+Wz4+Xr/L4CIDxEBSr7hSn/z7hLBMJ 9qsNdY4nIT0x9D94XOY6Gn4pdXsicgffdsFi8K9rXN54yKsWeZ8EMOH3fA7cEdPDAu9O +VjURXZrqSmU7nviCoyIl5F9kpEk9SWYMdcBUs0XNAHddnLSyKmFU0yYRwfCBGaeMpZC wG5Q== X-Gm-Message-State: AJIora9wMfA4gQPuFmYgfz2PYGQELaAeFhpdX37mSd0Dy4taQnBs2l3M zEOMJ6DQIp/hdPEWxxKvbd4= X-Google-Smtp-Source: AGRyM1t7fF9oWyoFMD4Gd1xha3GDwq5quNlzvF+7I8uqpwdkfaVZSf+y3kr/8cPcMtmBqNLfvwIwNg== X-Received: by 2002:a5d:5885:0:b0:218:3d12:e0eb with SMTP id n5-20020a5d5885000000b002183d12e0ebmr24861338wrf.510.1655755642796; Mon, 20 Jun 2022 13:07:22 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id w10-20020a05600c014a00b0039ee51fda45sm12789702wmm.2.2022.06.20.13.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:22 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 42/49] mfd: qcom-pm8008: Fix broken mask/unmask in irq chip Date: Mon, 20 Jun 2022 21:06:37 +0100 Message-Id: <20220620200644.1961936-43-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Swap mask_base and unmask_base, and drop the broken_mask_unmask flag since we're now expecting the registers to have their usual behavior. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index 18095e72714e..7bc6becfe7f4 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -45,8 +45,8 @@ enum { #define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE #define PM8008_STATUS_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET) -#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET) -#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET) +#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET) +#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET) #define PM8008_TYPE_BASE (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET) #define PM8008_ACK_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET) #define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSET) @@ -141,7 +141,6 @@ static struct regmap_irq_chip pm8008_irq_chip = { .status_base = PM8008_STATUS_BASE, .mask_base = PM8008_MASK_BASE, .unmask_base = PM8008_UNMASK_BASE, - .broken_mask_unmask = true, .ack_base = PM8008_ACK_BASE, .config_base = pm8008_config_regs, .num_config_bases = ARRAY_SIZE(pm8008_config_regs), From patchwork Mon Jun 20 20:06:38 2022 Content-Type: text/plain; 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[92.40.169.63]) by smtp.gmail.com with ESMTPSA id o20-20020a1c7514000000b0039c4ec6fdacsm15898561wmc.40.2022.06.20.13.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:23 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 43/49] mfd: qcom-pm8008: Enable mask_writeonly flag for irq chip Date: Mon, 20 Jun 2022 21:06:38 +0100 Message-Id: <20220620200644.1961936-44-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The PM8008 has separate set and clear registers for controlling its interrupt masks. These are likely volatile registers which read as 0, and writing a '1' bit sets or clears the corresponding bit in the mask register. The PM8008's regmap config doesn't enable a cache, so all register access is already volatile. Adding the mask_writeonly flag should reduce bus traffic by avoiding a read-modify-write on the mask set/clear registers. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index 7bc6becfe7f4..c778f2f87a17 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -141,6 +141,7 @@ static struct regmap_irq_chip pm8008_irq_chip = { .status_base = PM8008_STATUS_BASE, .mask_base = PM8008_MASK_BASE, .unmask_base = PM8008_UNMASK_BASE, + .mask_writeonly = true, .ack_base = PM8008_ACK_BASE, .config_base = pm8008_config_regs, .num_config_bases = ARRAY_SIZE(pm8008_config_regs), From patchwork Mon Jun 20 20:06:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4980AC433EF for ; Wed, 22 Jun 2022 15:36:03 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 74E1822E0; Wed, 22 Jun 2022 17:35:11 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 74E1822E0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912161; bh=mngDexp6wCgVRD+P6I+Z+1F8oumIbR2JdIwMty5Rijo=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=aSXYsVnwyBBUgwGxQN7x8q0kch5dXXd6rdzMeeJYYuFnPouuHURzsenx+VOAUUvZz sy7EjQKIpJolAf31ZB/9hY/2gnYwemilBvIDsNzvnLRulw/mNz3LIz5m5YYhLeoKpA ZxhlEoQxB9Us4vDhy31HWpceDqwWn05+N87z2cmA= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id B2345F80641; Wed, 22 Jun 2022 17:23:49 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 0F143F800E3; Mon, 20 Jun 2022 22:07:28 +0200 (CEST) Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 71335F800E3 for ; Mon, 20 Jun 2022 22:07:26 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 71335F800E3 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="R2nM9gpV" Received: by mail-wr1-x42a.google.com with SMTP id o8so16102621wro.3 for ; Mon, 20 Jun 2022 13:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rE0XsHvuQMGHkh+DWN4I0u4Mry72SZTz94U/AwkKe64=; b=R2nM9gpViD7RpxZufBEYDf0sqKPJn+Vqc0jUeZDkwV0e+SnITT7LfK/9yzWVU5IQhu aA8WUpzc6J0Qf7iIoRilFZEWo0nV5HsEN4NblRAipOFGBlQ/fSulqH247JQGB+Vbnmz6 u+j2et5Rf+Emw9sgGoIp8Ua1g6/wgIJuStK0XWLJu64d2gAGwoDQCdtaVYypYAWvkfQX jXux0apgjHCpI8qq2XpRhrhdyFsE0YxHMLP8R6wnnvs9dQt5nl7aqrNMv0hrLaXmrugZ kyh9aob6sQAuWXwqPokSAhhl/C8pUOash7nUyLmMzRyTrdLb7ZhEwWLRjTGZ/E7DshAW tGSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rE0XsHvuQMGHkh+DWN4I0u4Mry72SZTz94U/AwkKe64=; b=ji1dlTSwFHW7T1C7qTWa3ZvkGUku/8U8gZh6WgEig2/orbqXEJJztYjHlwiZtu6bXm HuX13yz40rQUXT9Q8+cUSBip4/a04Dd0wvYre8boLXAIMNegzWAi5dlZNaOl+geUEOmi 57VlwHfSPAC05H/0EbswbrJFmcmocZVkDeasIbymELpX1kDOBgI+aKZMtOv+zBaihh0t CPvihxBzu6iYImvH9TjXKboVmwCtYSRQDDnU5tnLJ1IAnuUsiLfPuOR107TrcpgViWz+ SRC4soonAClliiaBe9zG/EfIqBiWaKhN5khneqSRTKfmLF89ai2dCArjAjM5+GH2/Uqf RlUA== X-Gm-Message-State: AJIora9dmiq3d46omCULLsa1PwjQz3zd+iH7NxbjLx4WFiUp9XjIXiNn CDJwH4bhSiVCmz67eUkAk3c= X-Google-Smtp-Source: AGRyM1utPBE8XYxoB7U0xnTciGPQVtQTgTqRZ99c6POU/yfZ+JPXfl21N1f7SnJeHKblgblpcXVNWQ== X-Received: by 2002:a5d:5481:0:b0:21a:3573:def0 with SMTP id h1-20020a5d5481000000b0021a3573def0mr23413256wrv.28.1655755646148; Mon, 20 Jun 2022 13:07:26 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id p14-20020a5d48ce000000b0021020517639sm14095785wrs.102.2022.06.20.13.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:25 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 44/49] regmap-irq: Remove broken_mask_unmask flag Date: Mon, 20 Jun 2022 21:06:39 +0100 Message-Id: <20220620200644.1961936-45-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Drop broken_mask_unmask flag; no drivers are relying on it anymore. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 9 +-------- include/linux/regmap.h | 1 - 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 082a2981120c..8a718615fd09 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -723,15 +723,8 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, /* * Swap role of mask_base and unmask_base if mask bits are inverted. - * - * Historically, chips that specify both mask_base and unmask_base - * got inverted mask behavior; this was arguably a bug in regmap-irq - * and there was no way to get the normal, non-inverted behavior. - * Those chips will set the broken_mask_unmask flag. They don't set - * mask_invert so there is no need to worry about interactions with - * that flag. */ - if (chip->mask_invert || chip->broken_mask_unmask) { + if (chip->mask_invert) { d->mask_base = chip->unmask_base; d->unmask_base = chip->mask_base; } else { diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 0cf3c4a66946..a3103c88e936 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1524,7 +1524,6 @@ struct regmap_irq_chip { bool clear_on_unmask:1; bool not_fixed_stride:1; bool status_invert:1; - bool broken_mask_unmask:1; int num_regs; From patchwork Mon Jun 20 20:06:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4FE6C433EF for ; Wed, 22 Jun 2022 15:35:31 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id F360E1F6D; Wed, 22 Jun 2022 17:34:39 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz F360E1F6D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912130; bh=FpGKCq2GGtLX13/bAR9ApL0zzxiJlvthiIpB7Iv1RcU=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=STHv0cB/VdUipdai/KOmwlxc+iSOZmfSibWowRyLztJ+SUo8joC80GtbqFoYODOcn oBR0XXeLSftILKbhs2jaqEyGqXOPO6HGikE4SVgMXDNoVJKxyata0rGOsmaz9jbPMF fKL+tpf1L4c2C6gSlxroWHj2XhkajaZqQm8CX3fg= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 7193DF8063B; Wed, 22 Jun 2022 17:23:48 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 5CB9AF804E7; Mon, 20 Jun 2022 22:07:32 +0200 (CEST) Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 5D5DBF804D2 for ; Mon, 20 Jun 2022 22:07:28 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 5D5DBF804D2 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l4GFUZrK" Received: by mail-wr1-x431.google.com with SMTP id m1so8326299wrb.2 for ; Mon, 20 Jun 2022 13:07:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=klzG1EiAdFscBZBcoCzDKMr3GKqX2S6ab3hLTukICYA=; b=l4GFUZrKtyjWTlZn2W6sbNe7RkJpSisjb5nPFCMRsK4VVftYk11OQgyGsUsVQOVVxd WveltYUyuvOFbYFUdYhxpXNuxE4S4YCumzKcvnxPGX4OsA13JEey1GXiYfj+BN3FyuAk YoyM6iFFHOgbk2ykc+NDEEHh/n23+NkaBHDoIRTmULng90YVn+qOGMdpsjX8phANF5/i sk5OxAxVvNJ2GPbb6NqRjZvP8u6Pf1FxTRCjPvzgHPcXQnzfgqR8rhEIYzbMNaK4cAp6 yiv/olpO3Koxh4OhoUfRvU3fEVkmdETxuX090a9/gNWOJYRM4fDVw5XWJYzxI9yxqfA6 IXWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=klzG1EiAdFscBZBcoCzDKMr3GKqX2S6ab3hLTukICYA=; b=h1vQ8BX+ppv7c09DUswXkAB471AZvCDzYTds8A8bASic6/8WA9BYvnOvmpJdh47fH0 Cg8he4hRq2quYoBU5JNzszDpdnoqt4KI+YSGNSu0bLuO2gtHJr0Gfk8XREHAiJkAq7jN FnW1VOrQdQaq7YLAdNw33wea3zbl8sr96FrrL8ttItBJlhJ8mOysNXqEcNsB+QrTQPPD POzevNc3WIRoQZKlqXNOFxD9UybgXX6h4whD3d247dj94fpsi2qVjfwvajJuQ260/EyJ flaURTP4ma65CNUs3VNO1wD1Ihnirh2jccVYLWXZknuuQ6dc7BHi0zODl5chq5uwpprT c4yQ== X-Gm-Message-State: AJIora+CkuN4DcgXuGH81aV32npECv6ZlRZUN0UD3GyzUumrL/aIe2/U JHWD9BKs18sz+IThEI3Nnhk= X-Google-Smtp-Source: AGRyM1tNlpsLQBbADqcDPRR01JRNtswf/HBtBf5oihaYlvZj08PdTVfZrZn0YfVlGpD8PsGFQGId1w== X-Received: by 2002:a5d:5981:0:b0:218:51ae:8808 with SMTP id n1-20020a5d5981000000b0021851ae8808mr24885992wri.244.1655755648056; Mon, 20 Jun 2022 13:07:28 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id d3-20020adffbc3000000b0020e6ce4dabdsm14219147wrs.103.2022.06.20.13.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:27 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 45/49] regmap-irq: Remove mask_invert flag Date: Mon, 20 Jun 2022 21:06:40 +0100 Message-Id: <20220620200644.1961936-46-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" An inverted mask register can be represented more directly as an unmask register. Drop the redundant mask_invert flag. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 30 ++++++++---------------------- include/linux/regmap.h | 2 -- 2 files changed, 8 insertions(+), 24 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 8a718615fd09..0a8edaee064a 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -30,9 +30,6 @@ struct regmap_irq_chip_data { int irq; int wake_count; - unsigned int mask_base; - unsigned int unmask_base; - void *status_reg_buf; unsigned int *main_status_buf; unsigned int *status_buf; @@ -126,8 +123,8 @@ static void regmap_irq_sync_unlock(struct irq_data *data) * suppress pointless writes. */ for (i = 0; i < d->chip->num_regs; i++) { - if (d->mask_base) { - reg = sub_irq_reg(d, d->mask_base, i); + if (d->chip->mask_base) { + reg = sub_irq_reg(d, d->chip->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret != 0) @@ -135,8 +132,8 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg); } - if (d->unmask_base) { - reg = sub_irq_reg(d, d->unmask_base, i); + if (d->chip->unmask_base) { + reg = sub_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret != 0) @@ -721,17 +718,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->chip = chip; d->irq_base = irq_base; - /* - * Swap role of mask_base and unmask_base if mask bits are inverted. - */ - if (chip->mask_invert) { - d->mask_base = chip->unmask_base; - d->unmask_base = chip->mask_base; - } else { - d->mask_base = chip->mask_base; - d->unmask_base = chip->unmask_base; - } - if (chip->irq_reg_stride) d->irq_reg_stride = chip->irq_reg_stride; else @@ -756,8 +742,8 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, for (i = 0; i < chip->num_regs; i++) { d->mask_buf[i] = d->mask_buf_def[i]; - if (d->mask_base) { - reg = sub_irq_reg(d, d->mask_base, i); + if (d->chip->mask_base) { + reg = sub_irq_reg(d, d->chip->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret != 0) { @@ -767,8 +753,8 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, } } - if (d->unmask_base) { - reg = sub_irq_reg(d, d->unmask_base, i); + if (d->chip->unmask_base) { + reg = sub_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret != 0) { diff --git a/include/linux/regmap.h b/include/linux/regmap.h index a3103c88e936..bb625a1edef9 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1462,7 +1462,6 @@ struct regmap_irq_sub_irq_map { * @config_base: Base address for IRQ type config regs. If null unsupported. * @irq_reg_stride: Stride to use for chips where registers are not contiguous. * @init_ack_masked: Ack all masked interrupts once during initalization. - * @mask_invert: Inverted mask register: cleared bits are masked out. * @use_ack: Use @ack register even if it is zero. * @ack_invert: Inverted ack register: cleared bits for ack. * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts. @@ -1514,7 +1513,6 @@ struct regmap_irq_chip { unsigned int irq_reg_stride; bool mask_writeonly:1; bool init_ack_masked:1; - bool mask_invert:1; bool use_ack:1; bool ack_invert:1; bool clear_ack:1; From patchwork Mon Jun 20 20:06:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98700C433EF for ; Wed, 22 Jun 2022 15:35:46 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id D436822DC; Wed, 22 Jun 2022 17:34:54 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz D436822DC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912144; bh=8g+j3a6+bioODTDRzpX8rpodN/x7ZjxXYU21b+igjc0=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=r97mYXcQ2/LJX5ic6O5+Azejn4QIGJ4i7Vszf/vRHUKB1cjwxvt7nFEaF0XfkrUV6 CoHK/8xbbkTWwScYKatr4LIMFVbQ2VsXvbyC1lSU1cAyBrcymYYaWMARGfCW8Kv6yp h3KX7/qJ4EsmPfho8LXq8KjfO5BQbbROgBJTDb84= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 13DC5F80640; Wed, 22 Jun 2022 17:23:49 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 8AD83F804DA; Mon, 20 Jun 2022 22:07:32 +0200 (CEST) Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id D9765F800CB for ; Mon, 20 Jun 2022 22:07:29 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz D9765F800CB Authentication-Results: alsa1.perex.cz; dkim=fail reason="key not found in DNS" (0-bit key) header.d=gmail.com header.i=@gmail.com header.b="U/u1eI8X" Received: by mail-wm1-x32e.google.com with SMTP id m16-20020a7bca50000000b0039c8a224c95so6195354wml.2 for ; Mon, 20 Jun 2022 13:07:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E0jLkqilWpvnbTcSo4wfjkJhQqF1reP5Ib9ezCHoYWc=; b=U/u1eI8XG0RLSewZC9yH0TEBjAQ2QVQeFgi9rzCUa/S/IXH9PHYw0gdakIKNDT90kV hMuwVJCliXAFt+/OKjfOJGf07gA2TRZWRFVa9nvnR7w8MWysPG76mxgNw9ukyrADHZ5N ALr37IiaH9saP7DoyArHAIbUsX5KFRzx8Uw6meqm+M15MdeUmVUAWTmMi15JWu+Wq07m itZyiVgoqQZkvIT6ra3IIfQvQJZJo5C0Y+CD2t4yxMPenkkULdYZFq6Wwj6TJ4CoenZF dRCH3mEbVAzCd1YjOvUgfQGm1TEKpTWU8WSRmJwdw9G0Be/ybY4XqRUVEJ0I0EIJYNRr FSCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E0jLkqilWpvnbTcSo4wfjkJhQqF1reP5Ib9ezCHoYWc=; b=jsNcWDvnbVgL1hP0eSFPfOqrFjNBnnZRiSlq9Xo65n0iowlso8DFZb/lj3y37kyalJ WXK17gh6+TIguRPjpd+G672iP6f6UPPZ0+INT3zfFC8betyuj0wuyRBBubajma/T2L0x N//fxo4RAHCWK65YSUjXIfR1cbhgh4unAvy6B9UVoVXhantF0n0hSV29ix1hw4Ei7NjV TS+ZZdK5l5XmH8Vsc/SGuqeZLrOApt+6wPkBQC619N8he1wvseCGVBgEQK1i80Sw3K85 FZgNZcp6CU9Xrx2Zcg2gn4hLRCzaUWHMD7Cxnj4hbSxLrEU1S+4RoUvrKJZb0sNhyxcr hoLw== X-Gm-Message-State: AJIora/XHHHj9ia5eLnWeG++qhfdAen6MkVxqcIm6Xteb/8ygbMOahkT utmo6873hKoCfQFhCEBjirE= X-Google-Smtp-Source: AGRyM1uhXBLM2mCEhpF1oCgYeIG722Adlji+SZHE2C7bZquQV7GS0wP1KfS6UMHZPFYNwRmyV3niBQ== X-Received: by 2002:a05:600c:1c10:b0:39c:4708:648d with SMTP id j16-20020a05600c1c1000b0039c4708648dmr26590108wms.85.1655755649580; Mon, 20 Jun 2022 13:07:29 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id j11-20020a05600c190b00b0039c5328ad92sm22754411wmq.41.2022.06.20.13.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:29 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 46/49] regmap-irq: Refactor checks for status bulk read support Date: Mon, 20 Jun 2022 21:06:41 +0100 Message-Id: <20220620200644.1961936-47-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" There are several conditions that must be satisfied to support bulk read of status registers. Move the check into a function to avoid duplicating it in two places. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 0a8edaee064a..7b5bd1d45fc0 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -72,6 +72,14 @@ struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, return &data->chip->irqs[irq]; } +static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data) +{ + struct regmap *map = data->map; + + return !map->use_single_read && map->reg_stride == 1 && + data->irq_reg_stride == 1; +} + static void regmap_irq_lock(struct irq_data *data) { struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); @@ -413,8 +421,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } } - } else if (!map->use_single_read && map->reg_stride == 1 && - data->irq_reg_stride == 1) { + } else if (regmap_irq_can_bulk_read_status(data)) { u8 *buf8 = data->status_reg_buf; u16 *buf16 = data->status_reg_buf; @@ -723,8 +730,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, else d->irq_reg_stride = 1; - if (!map->use_single_read && map->reg_stride == 1 && - d->irq_reg_stride == 1) { + if (regmap_irq_can_bulk_read_status(d)) { d->status_reg_buf = kmalloc_array(chip->num_regs, map->format.val_bytes, GFP_KERNEL); From patchwork Mon Jun 20 20:06:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF3BCC43334 for ; Wed, 22 Jun 2022 15:36:17 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 114031DFE; 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[92.40.169.63]) by smtp.gmail.com with ESMTPSA id e1-20020a5d5941000000b0020c5253d907sm14219807wri.83.2022.06.20.13.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:30 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 47/49] regmap-irq: Add get_irq_reg() callback Date: Mon, 20 Jun 2022 21:06:42 +0100 Message-Id: <20220620200644.1961936-48-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Replace the internal sub_irq_reg() function with a public callback that drivers can use when they have more complex register layouts. The default implementation is regmap_irq_get_irq_reg_linear(), used if the chip doesn't provide its own callback. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 122 ++++++++++++++++++++----------- include/linux/regmap.h | 15 +++- 2 files changed, 92 insertions(+), 45 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 7b5bd1d45fc0..acbd6e22b0cd 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -41,30 +41,12 @@ struct regmap_irq_chip_data { unsigned int irq_reg_stride; + unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, + unsigned int base, int index); + bool clear_status:1; }; -static int sub_irq_reg(struct regmap_irq_chip_data *data, - unsigned int base_reg, int i) -{ - const struct regmap_irq_chip *chip = data->chip; - struct regmap *map = data->map; - struct regmap_irq_sub_irq_map *subreg; - unsigned int offset; - int reg = 0; - - if (!chip->sub_reg_offsets || !chip->not_fixed_stride) { - /* Assume linear mapping */ - reg = base_reg + (i * map->reg_stride * data->irq_reg_stride); - } else { - subreg = &chip->sub_reg_offsets[i]; - offset = subreg->offset[0]; - reg = base_reg + offset; - } - - return reg; -} - static inline const struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, int irq) @@ -76,8 +58,14 @@ static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data) { struct regmap *map = data->map; + /* + * While possible that a user-defined get_irq_reg callback might be + * linear enough to support bulk reads, most of the time it won't. + * Therefore only allow them if the default callback is being used. + */ return !map->use_single_read && map->reg_stride == 1 && - data->irq_reg_stride == 1; + data->irq_reg_stride == 1 && + data->get_irq_reg == regmap_irq_get_irq_reg_linear; } static void regmap_irq_lock(struct irq_data *data) @@ -114,7 +102,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) if (d->clear_status) { for (i = 0; i < d->chip->num_regs; i++) { - reg = sub_irq_reg(d, d->chip->status_base, i); + reg = d->get_irq_reg(d, d->chip->status_base, i); ret = regmap_read(map, reg, &val); if (ret) @@ -132,7 +120,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) */ for (i = 0; i < d->chip->num_regs; i++) { if (d->chip->mask_base) { - reg = sub_irq_reg(d, d->chip->mask_base, i); + reg = d->get_irq_reg(d, d->chip->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret != 0) @@ -141,7 +129,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) } if (d->chip->unmask_base) { - reg = sub_irq_reg(d, d->chip->unmask_base, i); + reg = d->get_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret != 0) @@ -149,7 +137,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg); } - reg = sub_irq_reg(d, d->chip->wake_base, i); + reg = d->get_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { if (d->chip->wake_invert) ret = regmap_update_bits(d->map, reg, @@ -173,7 +161,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) * it'll be ignored in irq handler, then may introduce irq storm */ if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { - reg = sub_irq_reg(d, d->chip->ack_base, i); + reg = d->get_irq_reg(d, d->chip->ack_base, i); /* some chips ack by write 0 */ if (d->chip->ack_invert) @@ -194,7 +182,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) for (i = 0; i < d->chip->num_config_bases; i++) { for (j = 0; j < d->chip->num_config_regs; j++) { - reg = sub_irq_reg(d, d->chip->config_base[i], j); + reg = d->get_irq_reg(d, d->chip->config_base[i], j); ret = regmap_write(map, reg, d->config_buf[i][j]); if (ret != 0) dev_err(d->map->dev, @@ -316,14 +304,17 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, const struct regmap_irq_chip *chip = data->chip; struct regmap *map = data->map; struct regmap_irq_sub_irq_map *subreg; + unsigned int reg; int i, ret = 0; if (!chip->sub_reg_offsets) { - /* Assume linear mapping */ - ret = regmap_read(map, chip->status_base + - (b * map->reg_stride * data->irq_reg_stride), - &data->status_buf[b]); + reg = data->get_irq_reg(data, chip->status_base, b); + ret = regmap_read(map, reg, &data->status_buf[b]); } else { + /* + * Note we can't use get_irq_reg() here because the offsets + * in 'subreg' are *not* interchangeable with indices. + */ subreg = &chip->sub_reg_offsets[b]; for (i = 0; i < subreg->num_regs; i++) { unsigned int offset = subreg->offset[i]; @@ -389,10 +380,19 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) * sake of simplicity. and add bulk reads only if needed */ for (i = 0; i < chip->num_main_regs; i++) { - ret = regmap_read(map, chip->main_status + - (i * map->reg_stride - * data->irq_reg_stride), - &data->main_status_buf[i]); + /* + * For not_fixed_stride, don't use get_irq_reg(). + * It would produce an incorrect result. + */ + if (data->chip->not_fixed_stride) + reg = chip->main_status + + (i * map->reg_stride * + data->irq_reg_stride); + else + reg = data->get_irq_reg(data, + chip->main_status, i); + + ret = regmap_read(map, reg, &data->main_status_buf[i]); if (ret) { dev_err(map->dev, "Failed to read IRQ status %d\n", @@ -457,7 +457,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } else { for (i = 0; i < data->chip->num_regs; i++) { - unsigned int reg = sub_irq_reg(data, + unsigned int reg = data->get_irq_reg(data, data->chip->status_base, i); ret = regmap_read(map, reg, &data->status_buf[i]); @@ -485,7 +485,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) data->status_buf[i] &= ~data->mask_buf[i]; if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { - reg = sub_irq_reg(data, data->chip->ack_base, i); + reg = data->get_irq_reg(data, data->chip->ack_base, i); if (chip->ack_invert) ret = regmap_write(map, reg, @@ -545,6 +545,37 @@ static const struct irq_domain_ops regmap_domain_ops = { .xlate = irq_domain_xlate_onetwocell, }; +/** + * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback. + * + * @data: Data for the &struct regmap_irq_chip + * @base: Base register + * @index: Register index + * + * Returns the register address corresponding to the given @base and @index + * by the formula ``base + index * regmap_stride * irq_reg_stride``. + */ +unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data, + unsigned int base, int index) +{ + const struct regmap_irq_chip *chip = data->chip; + struct regmap *map = data->map; + + /* + * NOTE: This is for backward compatibility only and will be removed + * when not_fixed_stride is dropped (it's only used by qcom-pm8008). + */ + if (chip->not_fixed_stride && chip->sub_reg_offsets) { + struct regmap_irq_sub_irq_map *subreg; + + subreg = &chip->sub_reg_offsets[0]; + return base + subreg->offset[0]; + } + + return base + index * (map->reg_stride * chip->irq_reg_stride); +} +EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear); + /** * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. * @@ -730,6 +761,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, else d->irq_reg_stride = 1; + if (chip->get_irq_reg) + d->get_irq_reg = chip->get_irq_reg; + else + d->get_irq_reg = regmap_irq_get_irq_reg_linear; + if (regmap_irq_can_bulk_read_status(d)) { d->status_reg_buf = kmalloc_array(chip->num_regs, map->format.val_bytes, @@ -749,7 +785,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->mask_buf[i] = d->mask_buf_def[i]; if (d->chip->mask_base) { - reg = sub_irq_reg(d, d->chip->mask_base, i); + reg = d->get_irq_reg(d, d->chip->mask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret != 0) { @@ -760,7 +796,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, } if (d->chip->unmask_base) { - reg = sub_irq_reg(d, d->chip->unmask_base, i); + reg = d->get_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_mask_bits(d, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret != 0) { @@ -774,7 +810,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, continue; /* Ack masked but set interrupts */ - reg = sub_irq_reg(d, d->chip->status_base, i); + reg = d->get_irq_reg(d, d->chip->status_base, i); ret = regmap_read(map, reg, &d->status_buf[i]); if (ret != 0) { dev_err(map->dev, "Failed to read IRQ status: %d\n", @@ -786,7 +822,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->status_buf[i] = ~d->status_buf[i]; if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { - reg = sub_irq_reg(d, d->chip->ack_base, i); + reg = d->get_irq_reg(d, d->chip->ack_base, i); if (chip->ack_invert) ret = regmap_write(map, reg, ~(d->status_buf[i] & d->mask_buf[i])); @@ -811,7 +847,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, if (d->wake_buf) { for (i = 0; i < chip->num_regs; i++) { d->wake_buf[i] = d->mask_buf_def[i]; - reg = sub_irq_reg(d, d->chip->wake_base, i); + reg = d->get_irq_reg(d, d->chip->wake_base, i); if (chip->wake_invert) ret = regmap_update_bits(d->map, reg, diff --git a/include/linux/regmap.h b/include/linux/regmap.h index bb625a1edef9..be51af0a2425 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1424,6 +1424,8 @@ struct regmap_irq_sub_irq_map { unsigned int *offset; }; +struct regmap_irq_chip_data; + /** * struct regmap_irq_chip - Description of a generic regmap irq_chip. * @@ -1489,6 +1491,13 @@ struct regmap_irq_sub_irq_map { * @handle_post_irq: Driver specific callback to handle interrupt from device * after handling the interrupts in regmap_irq_handler(). * @set_type_config: Callback used for configuring irq types. + * @get_irq_reg: Callback for mapping (base register, index) pairs to register + * addresses. The base register will be one of @status_base, + * @mask_base, etc., @main_status, or any of @config_base. + * The index will be in the range [0, num_main_regs[ for the + * main status base, [0, num_type_settings[ for any config + * register base, and [0, num_regs[ for any other base. + * If unspecified then regmap_irq_get_irq_reg_linear() is used. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. * @@ -1535,11 +1544,13 @@ struct regmap_irq_chip { int (*handle_post_irq)(void *irq_drv_data); int (*set_type_config)(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx); + unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, + unsigned int base, int index); void *irq_drv_data; }; -struct regmap_irq_chip_data; - +unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data, + unsigned int base, int index); int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx); From patchwork Mon Jun 20 20:06:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09E63C43334 for ; Wed, 22 Jun 2022 15:36:35 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 53E511FB3; Wed, 22 Jun 2022 17:35:43 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 53E511FB3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655912193; bh=/vUTsmLpFI54cIZoWxQv5H61EjMtr9Mdep/1TXV6xzc=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=UlhGJXEgKKtvPv9icCcFhL2FDnk5cJCY5IDIHfSWWEYPfOyeo5hd5fsn5d9Hy+nik IOGmbP3n4d2pElpUMdTeBynzeIRT42dH7gIx0r4Fw2O3sIyogy6yUjUX4ZEn2AeOBQ iasnNep0JPatN3hZqtKaJDqidMjQtu6ox9l9ogHU= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 1A24AF80672; Wed, 22 Jun 2022 17:23:51 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 4966CF804D8; Mon, 20 Jun 2022 22:07:37 +0200 (CEST) Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 86FF2F800CB for ; Mon, 20 Jun 2022 22:07:34 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 86FF2F800CB Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="S/EtAgiY" Received: by mail-wm1-x331.google.com with SMTP id l2-20020a05600c4f0200b0039c55c50482so8297468wmq.0 for ; Mon, 20 Jun 2022 13:07:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gGGGI5LNQd5QfFmuY5vVwQrtUD8WBKwvWjL6Bicr/nE=; b=S/EtAgiYih2o97vzKZ46FuXvAcLZH4aZSRqS9u2yBKGwrnkXOKPCMGGLd7i9ZmxQaG BnBbK63aSq4v1vSjGAPc164mZGaSk3LPHtRt8daUl8xMv0xp20Wh0ybrxjQLqHXLqdDy yhDIj9t6XfrHHFv3whu+IVZQrWETjZ1AesrYnf54NJGg7Cy+3sRgTPv9faAKYSFooPY0 45O48rrjzHJTrXu/6XULoJep5LjaBkkIDGdtmMKtfzD41Z5IcTn0ruAikZetXvnqo0Tl Zdz1vCizcAGpaQKPTcGKQxbHlaaCG3L3c003lP0kS60LBM2I8ti3fkUMC/+0uVt3nR1g Y3+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gGGGI5LNQd5QfFmuY5vVwQrtUD8WBKwvWjL6Bicr/nE=; b=4iV+msPPXYmM69o56yvviysrXWgJUg80INyy/iXAmtw0b8AjEd0/OWschdESWOaDy1 k9XVZaLyNaQs6+Eifdd62Nuy31BJxL5ZREF1qNCGZa6mYvxlgtTNV5YDwY9rLCHeKELZ M1uM87i1uX9iYv6aFbqlw1jFmPaACHyd7N0Lw7THEJFr6gPY2Ql1pVB+SQpY6H7R84KQ 8D/VOA1YECa7PYJxzFv4crVULH5X7iX0VuvrPEnAEwuBBxnaCH8wcwsRc/5YR9GFWj2M 2JuTZAzI6OivnXy4gUXy1Np7/SBL/CeQx/1ULOFzAy6oYEkRoUun5HPf5aDtJjTS2S+Z +oSQ== X-Gm-Message-State: AJIora/Como/DUUIh2g9JURM7RSdWYgtFYwX5DLl4WmYoO9EU3NkOTkP fnEhRWljDji9qAXKcWf5xYc= X-Google-Smtp-Source: AGRyM1t7nmjsnyP7qTIA/w/988Wjv4MiUTlTDpMZzgOJTqyM5/Li8wCJHVRxnaV0tBlHxN/JpqOs4g== X-Received: by 2002:a05:600c:4ec7:b0:39c:84a7:3762 with SMTP id g7-20020a05600c4ec700b0039c84a73762mr25749060wmq.153.1655755653087; Mon, 20 Jun 2022 13:07:33 -0700 (PDT) Received: from localhost (92.40.169.63.threembb.co.uk. [92.40.169.63]) by smtp.gmail.com with ESMTPSA id s7-20020a5d6a87000000b0021b8c99860asm5606007wru.115.2022.06.20.13.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:32 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 48/49] mfd: qcom-pm8008: Use get_irq_reg() for irq chip Date: Mon, 20 Jun 2022 21:06:43 +0100 Message-Id: <20220620200644.1961936-49-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Replace the not_fixed_stride flag with a get_irq_reg() callback, which expresses what we want to do here more directly instead of relying on a convoluted hierarchy of offsets. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 56 +++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 31 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index c778f2f87a17..f6407aa0bcfc 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -44,16 +44,6 @@ enum { #define PM8008_GPIO1_ADDR PM8008_PERIPH_2_BASE #define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE -#define PM8008_STATUS_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET) -#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET) -#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET) -#define PM8008_TYPE_BASE (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET) -#define PM8008_ACK_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET) -#define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSET) -#define PM8008_POLARITY_LO_BASE (PM8008_PERIPH_0_BASE | INT_POL_LOW_OFFSET) - -#define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE) - struct pm8008_data { struct device *dev; struct regmap *regmap; @@ -61,22 +51,10 @@ struct pm8008_data { struct regmap_irq_chip_data *irq_data; }; -static unsigned int p0_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE)}; -static unsigned int p1_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE)}; -static unsigned int p2_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE)}; -static unsigned int p3_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_3_BASE)}; - -static struct regmap_irq_sub_irq_map pm8008_sub_reg_offsets[] = { - REGMAP_IRQ_MAIN_REG_OFFSET(p0_offs), - REGMAP_IRQ_MAIN_REG_OFFSET(p1_offs), - REGMAP_IRQ_MAIN_REG_OFFSET(p2_offs), - REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs), -}; - static unsigned int pm8008_config_regs[] = { - PM8008_TYPE_BASE, - PM8008_POLARITY_HI_BASE, - PM8008_POLARITY_LO_BASE, + INT_SET_TYPE_OFFSET, + INT_POL_HIGH_OFFSET, + INT_POL_LOW_OFFSET, }; enum { @@ -96,6 +74,23 @@ static struct regmap_irq pm8008_irqs[] = { REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)), }; +static const unsigned int pm8008_periph_base[] = { + PM8008_PERIPH_0_BASE, + PM8008_PERIPH_1_BASE, + PM8008_PERIPH_2_BASE, + PM8008_PERIPH_3_BASE, +}; + +static unsigned int pm8008_get_irq_reg(struct regmap_irq_chip_data *data, + unsigned int base, int index) +{ + /* Simple linear addressing for the main status register */ + if (base == I2C_INTR_STATUS_BASE) + return base + index; + + return pm8008_periph_base[index] + base; +} + static int pm8008_set_type_config(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx) { @@ -136,17 +131,16 @@ static struct regmap_irq_chip pm8008_irq_chip = { .irqs = pm8008_irqs, .num_irqs = ARRAY_SIZE(pm8008_irqs), .num_regs = PM8008_NUM_PERIPHS, - .not_fixed_stride = true, - .sub_reg_offsets = pm8008_sub_reg_offsets, - .status_base = PM8008_STATUS_BASE, - .mask_base = PM8008_MASK_BASE, - .unmask_base = PM8008_UNMASK_BASE, + .status_base = INT_LATCHED_STS_OFFSET, + .mask_base = INT_EN_CLR_OFFSET, + .unmask_base = INT_EN_SET_OFFSET, .mask_writeonly = true, - .ack_base = PM8008_ACK_BASE, + .ack_base = INT_LATCHED_CLR_OFFSET, .config_base = pm8008_config_regs, .num_config_bases = ARRAY_SIZE(pm8008_config_regs), .num_config_regs = PM8008_NUM_PERIPHS, .set_type_config = pm8008_set_type_config, + .get_irq_reg = pm8008_get_irq_reg, }; static struct regmap_config qcom_mfd_regmap_cfg = { From patchwork Mon Jun 20 20:06:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12891008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96C9DC433EF for ; Wed, 22 Jun 2022 15:36:49 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id D7527209C; Wed, 22 Jun 2022 17:35:57 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz D7527209C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; 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[92.40.169.63]) by smtp.gmail.com with ESMTPSA id j6-20020adff006000000b0021b892f4b35sm7152390wro.98.2022.06.20.13.07.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 13:07:34 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Subject: [PATCH 49/49] regmap-irq: Remove not_fixed_stride flag Date: Mon, 20 Jun 2022 21:06:44 +0100 Message-Id: <20220620200644.1961936-50-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: alsa-devel@alsa-project.org, bgoswami@codeaurora.org, rafael@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, myungjoo.ham@samsung.com, lee.jones@linaro.org, samuel@sholland.org, maz@kernel.org, brgl@bgdev.pl, mani@kernel.org, krzysztof.kozlowski@linaro.org, jernej.skrabec@gmail.com, cw00.choi@samsung.com, wens@csie.org, agross@kernel.org, orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, b.zolnierkie@samsung.com, linux-arm-msm@vger.kernel.org, tharvey@gateworks.com, linux-actions@lists.infradead.org, linux-gpio@vger.kernel.org, tiwai@suse.com, tglx@linutronix.de, cristian.ciocaltea@gmail.com, linux-arm-kernel@lists.infradead.org, rjones@gateworks.com, gregkh@linuxfoundation.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, michael@walle.cc, zhang.lyra@gmail.com, baolin.wang7@gmail.com, mazziesaccount@gmail.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Clean up all the cruft related to not_fixed_stride. The same thing can be accomplished with a custom get_irq_reg() callback. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 41 +++----------------------------- include/linux/regmap.h | 7 ------ 2 files changed, 3 insertions(+), 45 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index acbd6e22b0cd..0c9dd218614a 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -320,15 +320,8 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, unsigned int offset = subreg->offset[i]; unsigned int index = offset / map->reg_stride; - if (chip->not_fixed_stride) - ret = regmap_read(map, - chip->status_base + offset, - &data->status_buf[b]); - else - ret = regmap_read(map, - chip->status_base + offset, - &data->status_buf[index]); - + ret = regmap_read(map, chip->status_base + offset, + &data->status_buf[index]); if (ret) break; } @@ -380,18 +373,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) * sake of simplicity. and add bulk reads only if needed */ for (i = 0; i < chip->num_main_regs; i++) { - /* - * For not_fixed_stride, don't use get_irq_reg(). - * It would produce an incorrect result. - */ - if (data->chip->not_fixed_stride) - reg = chip->main_status + - (i * map->reg_stride * - data->irq_reg_stride); - else - reg = data->get_irq_reg(data, - chip->main_status, i); - + reg = data->get_irq_reg(data, chip->main_status, i); ret = regmap_read(map, reg, &data->main_status_buf[i]); if (ret) { dev_err(map->dev, @@ -561,17 +543,6 @@ unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data, const struct regmap_irq_chip *chip = data->chip; struct regmap *map = data->map; - /* - * NOTE: This is for backward compatibility only and will be removed - * when not_fixed_stride is dropped (it's only used by qcom-pm8008). - */ - if (chip->not_fixed_stride && chip->sub_reg_offsets) { - struct regmap_irq_sub_irq_map *subreg; - - subreg = &chip->sub_reg_offsets[0]; - return base + subreg->offset[0]; - } - return base + index * (map->reg_stride * chip->irq_reg_stride); } EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear); @@ -674,12 +645,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, return -EINVAL; } - if (chip->not_fixed_stride) { - for (i = 0; i < chip->num_regs; i++) - if (chip->sub_reg_offsets[i].num_regs != 1) - return -EINVAL; - } - if (irq_base) { irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); if (irq_base < 0) { diff --git a/include/linux/regmap.h b/include/linux/regmap.h index be51af0a2425..ecd3682de269 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1446,9 +1446,6 @@ struct regmap_irq_chip_data; * status_base. Should contain num_regs arrays. * Can be provided for chips with more complex mapping than * 1.st bit to 1.st sub-reg, 2.nd bit to 2.nd sub-reg, ... - * When used with not_fixed_stride, each one-element array - * member contains offset calculated as address from each - * peripheral to first peripheral. * @num_main_regs: Number of 'main status' irq registers for chips which have * main_status set. * @@ -1474,9 +1471,6 @@ struct regmap_irq_chip_data; * @clear_on_unmask: For chips with interrupts cleared on read: read the status * registers before unmasking interrupts to clear any bits * set when they were masked. - * @not_fixed_stride: Used when chip peripherals are not laid out with fixed - * stride. Must be used with sub_reg_offsets containing the - * offsets to each peripheral. * @status_invert: Inverted status register: cleared bits are active interrupts. * @runtime_pm: Hold a runtime PM lock on the device when accessing it. * @@ -1529,7 +1523,6 @@ struct regmap_irq_chip { bool runtime_pm:1; bool type_in_mask:1; bool clear_on_unmask:1; - bool not_fixed_stride:1; bool status_invert:1; int num_regs;