From patchwork Wed Jun 22 17:43:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C612CCA481 for ; Wed, 22 Jun 2022 17:54:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9QujE6miWb9/6lvuP/6+UoGPShAlVd6ByWUBqg7sIqk=; b=o8u4CjYV3unmyj AcDl99B7qjWpNtWZw26oLFvNbuiat/EuVtdffotpiKor26Bs1rIjcrBAu8Kjxjn3YRMyNhJuKKjlg HQo1BSlojusjwzgXurA5u/XUota68iPwmMoPezTWNe4ZdT9w0ct2geWTgoe6d0ERiboc2lRx42URM ANCL4TCMmnQZwbgD1ujfLrp4M/q07ibrV0w3Ytnt1/9iIzFJ2E3Vx9FvDv1B3Ufri8SUC1Vd86R05 qPP+bGahma/8emW5yDwNxMYN6L5t37Yf5QNllwrMwl2YDvq4VriazzPUfjuunl2EdT8ausxtXto3F xtKk9oLw+2Kkck4NG0eQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o44XE-00BlUb-Ao; Wed, 22 Jun 2022 17:53:00 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o44X3-00BlS2-2z for linux-arm-kernel@lists.infradead.org; Wed, 22 Jun 2022 17:52:50 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AEE9761CCC; Wed, 22 Jun 2022 17:52:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 19874C341C7; Wed, 22 Jun 2022 17:52:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920368; bh=1iZYkc1hPiqKypGNa6u/smua1y2PeeeLJrraOYdQNQQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SW/lxuVfzJrnygNRxqUc44TTaSGhiNjKqym1g5F/VDZZ7LeFwgL9BDgI+qZIXo4Lq j9a0KRRvNm+cxnsROrEVLoSZZ1Lwnch/GsxGV0vnJjcacyBz4lQJ5vtY/lSsvKrIi+ cBeo9i8pUdQMGl6dDPp7FKjhUQHIsuFreedfp9pfuxItUlj52T0spNHaQcv1uic8vc ovcK9haEtCc267dmGIT9DNqus9dLhjAQIReXpe3T1yGXB3eiNe4hTgegs/iEbfeRES xHFkIZ10RiD2fxfTQzBFxymefJ8EtuPusngZkM5Umbcor5wiCPjIjQmMT0NVl/h+A6 xkFCdT5XtpzFg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 01/27] arm64/cpuinfo: Remove refrences to reserved cache type Date: Wed, 22 Jun 2022 18:43:50 +0100 Message-Id: <20220622174416.1406282-2-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2928; h=from:subject; bh=1iZYkc1hPiqKypGNa6u/smua1y2PeeeLJrraOYdQNQQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1Ta4JiwcLT2rPnakAPjbPyXMjggczAlvJgtnxoh vqdhCCuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU2gAKCRAk1otyXVSH0PbKB/ wPurrm8Fjvqc+9+m1juFMmt2etCeu1Y8F/0cRf3ddQBpH+5/q7gSy4238zf5iyclb0ln59ffzE/AOu sQzPxiRbTEt6x0PmATOCjSRyBwyxLl6PKObwkZRK/1f/nK22nBROymMVm9+0lGQBswkoErd1pVsNy7 rFM1+KOCaGuxkyeEEAP2qKLMboDrKffGHGrrohrJzMoN7ID2LLD5Dkv7Ni0RZ1xgNS5IbpGIOnOV6v W7iJuvKPwCi6NFIeNsFXljCzeToLwUCNWAgQDVvOF/yXPumrxyCC2lydXgLINGEpQhEKD+Be62BpTB Mg9o5HYiyxNIhp0xD092LxYiAq8wBf X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105249_241335_50EF6C46 X-CRM114-Status: GOOD ( 17.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In 155433cb365ee466 ("arm64: cache: Remove support for ASID-tagged VIVT I-caches") we removed all the support fir AIVIVT cache types and renamed all references to the field to say "unknown" since support for AIVIVT caches was removed from the architecture. Some confusion has resulted since the corresponding change to the architecture left the value named as AIVIVT but documented it as reserved in v8, refactor the code so we don't define the constant instead. This will help with automatic generation of this register field since it means we care less about the correspondence with the ARM. No functional change, the value displayed to userspace is unchanged. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cache.h | 1 - arch/arm64/kernel/cpuinfo.c | 27 +++++++++++++++++---------- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 7c2181c72116..0cbe75b9e4e5 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -25,7 +25,6 @@ #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) #define ICACHE_POLICY_VPIPT 0 -#define ICACHE_POLICY_RESERVED 1 #define ICACHE_POLICY_VIPT 2 #define ICACHE_POLICY_PIPT 3 diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 8eff0a34ffd4..7ecf9ffb590b 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -33,12 +33,19 @@ DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); static struct cpuinfo_arm64 boot_cpu_data; -static const char *icache_policy_str[] = { - [ICACHE_POLICY_VPIPT] = "VPIPT", - [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", - [ICACHE_POLICY_VIPT] = "VIPT", - [ICACHE_POLICY_PIPT] = "PIPT", -}; +static inline const char *icache_policy_str(int l1ip) +{ + switch (l1ip) { + case ICACHE_POLICY_VPIPT: + return "VPIPT"; + case ICACHE_POLICY_VIPT: + return "VIPT"; + case ICACHE_POLICY_PIPT: + return "PIPT"; + default: + return "RESERVED/UNKNOWN"; + } +} unsigned long __icache_flags; @@ -342,19 +349,19 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) u32 l1ip = CTR_L1IP(info->reg_ctr); switch (l1ip) { - case ICACHE_POLICY_PIPT: - break; case ICACHE_POLICY_VPIPT: set_bit(ICACHEF_VPIPT, &__icache_flags); break; - case ICACHE_POLICY_RESERVED: case ICACHE_POLICY_VIPT: /* Assume aliasing */ set_bit(ICACHEF_ALIASING, &__icache_flags); break; + case ICACHE_POLICY_PIPT: + default: + break; } - pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); + pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); } static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) From patchwork Wed Jun 22 17:43:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5703DC43334 for ; Wed, 22 Jun 2022 17:54:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mmcTPQN3UlGAH30b1BKxEzrCREVggI32nKJI/WpxcP4=; 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Wed, 22 Jun 2022 17:52:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920370; bh=2ArsSZmKdMsL2Z2QckgwDodtq0Ac8Oi0E83OF81ANUM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K8OCfnUXDLWmOrNy2wbUJ6O0xGBfWNsKFCKW/1d/AnYKV8enEpwZcD4pvmcq7Znxp dy95BE+eIEpBT+n16rMVYTP5CgDvP7bTh8aIPoSclhCdOQxCx5xFB/TirT0S7zZ39F ZUgQ9mOiRe5Pqttz5azaAhCnco9Km5hLarXYKeC1fi9VM916Rq+bOP3oIfccthdtaY LIEQg4JUL6WQFl6MsvOkp5FqpUwT1FxhGFKJwpNewDhJea+z09E1IoZExSXfCzJSYe xcPGG4frKHQpFpVzPj5IMvhfMEc+D+qSUafd6tmSOjQZRFMoGDgH/BQQ4LcZWm7Dxc CVJ34/PHM4zpg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 02/27] arm64/sysreg: Allow leading blanks on comments in sysreg file Date: Wed, 22 Jun 2022 18:43:51 +0100 Message-Id: <20220622174416.1406282-3-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/tools/gen-sysreg.awk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk index 5c55509eb43f..db461921d256 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -88,7 +88,7 @@ END { # skip blank lines and comment lines /^$/ { next } -/^#/ { next } +/^[\t ]*#/ { next } /^SysregFields/ { change_block("SysregFields", "None", "SysregFields") From patchwork Wed Jun 22 17:43:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7006CC43334 for ; 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Wed, 22 Jun 2022 17:53:21 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o44X7-00BlSx-HG for linux-arm-kernel@lists.infradead.org; Wed, 22 Jun 2022 17:52:54 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E6A3A61CC9; Wed, 22 Jun 2022 17:52:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DCAC3C385A5; Wed, 22 Jun 2022 17:52:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920372; bh=KcNDVGah6acFLtY5arEim8rZJff/2fy0mbc1avPAGhg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MEqXu3XZrECB3xWO+OSYUuZflhtwzrPl2GTDYXR2HpYL1b+gLUCO+Fdst5kQyFkdt bl5V5xkGw9RW01PCyFK5wlWDMoFref+yG4MCodGSKIqPDhL9aaGpnuQKnG2k+2id2q rplXnIq6OIqibpsu3uhpPrq8Gnt/E5TurrOJFBFHR5Z8iS1WCDhWeulzj34DKBgFo8 4eNysM5pwgeN/z+nRSLJFKO2jfPpN0ZnFL2o+mH0kf+1kHXeLJuDdrApB1A3FqtHQ5 RQkFTtp45PzYD3+zyLRgygvxp+XKxjqVScDFq832DIoRGGZYNkJjCCh/D6ewEjyqKg vXOvY1htTUeWg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 03/27] arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h Date: Wed, 22 Jun 2022 18:43:52 +0100 Message-Id: <20220622174416.1406282-4-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1663; h=from:subject; bh=KcNDVGah6acFLtY5arEim8rZJff/2fy0mbc1avPAGhg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1TbumBGqmxV9ciYJdW1IkZhGUfdU4c3iQmXres1 WQZi+5SJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU2wAKCRAk1otyXVSH0Mr5CA CA6rx8ey57NuzoOIzf2KfYBw4EOBVYLMjmBWuLHAbtSOJ55u8UdJV8NCEKAJn3xkpDpjIv7UeFEC6w VIYD5wrt0xtBI4bXg/+/qKl30KVY0xYifLQf3CZB9tbwcoF/yKJlTAYAmISUXPMJeFFy33Xkq/77sT c1d48jSgeco6iZXI+bm3YwG7cIcgfKuhXh6Zs5MLvDtHVEPJE4fmjm5iUY7ZLlXWlxVRXjKYBI8/pE yh7NmYVlwMRHni01wCFxihB0VvXTgNlckTtFMMiDedpkRoKpsDjK33oq0miyN/jQni9A13d/V8qg+Z nUrZjJuyA+zZ1pizI7pb0AYp8MEB7p X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105253_650551_93F5ACD1 X-CRM114-Status: GOOD ( 11.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In subsequent patches sysreg.h and gpr-num.h will be included from other headers which can be included from linker scripts (e.g. via cache.h), and contain assember macro directives that don't work in linker scripts (e.g. `.macro` and `.irp`). To avoid needing LINKER_SCRIPT guards in every file which could have a transitive dependency, add those directly to sysreg.h and gpr-num.h. Signed-off-by: Mark Brown --- arch/arm64/include/asm/gpr-num.h | 3 +++ arch/arm64/include/asm/sysreg.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/arch/arm64/include/asm/gpr-num.h b/arch/arm64/include/asm/gpr-num.h index 05da4a7c5788..72c44f63fb41 100644 --- a/arch/arm64/include/asm/gpr-num.h +++ b/arch/arm64/include/asm/gpr-num.h @@ -4,12 +4,15 @@ #ifdef __ASSEMBLY__ +#ifndef LINKER_SCRIPT + .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 .equ .L__gpr_num_x\num, \num .equ .L__gpr_num_w\num, \num .endr .equ .L__gpr_num_xzr, 31 .equ .L__gpr_num_wzr, 31 +#endif /* !LINKER_SCRIPT */ #else /* __ASSEMBLY__ */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 42ff95dba6da..6c7be1a2114b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1219,6 +1219,7 @@ #ifdef __ASSEMBLY__ +#ifndef LINKER_SCRIPT .macro mrs_s, rt, sreg __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt)) .endm @@ -1226,6 +1227,7 @@ .macro msr_s, sreg, rt __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt)) .endm +#endif /* !LINKER_SCRIPT */ #else From patchwork Wed Jun 22 17:43:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 157AEC433EF for ; Wed, 22 Jun 2022 17:54:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ktFzEn9jWvF424dLptmTuq3jPSJn0SzNJLYfA35hH0c=; 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Wed, 22 Jun 2022 17:52:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920374; bh=2/YcaFBMXhItOKk5qQdrya7+piGFgYXucx4zDLzdjZc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PpUvyzRyno0MYCH2dy5zDoTVnVRi4l3AaCE2RonbqB+lABHtWCut1oKN5kBPdjXz/ Xp0leu+494zljRDwIRbs9cFYtkqzID4dFG2sbrVAlyHKL1Wwy+Xvgf0SPPfjwW1F6c zx/ddiA0BCVTjjFAs83lQ4a5NcSZ5jMJlMrrB0BqXRfHUJfN0ML1gFb+fQduti9/NQ QPh0rvJsL8PbRbWFN5qSPRSKzUGQUUGbCrEnxni8uHshTq0FYdSnjkEYCpPw765YV4 TvzvQJR7mVza90MR5o5WhbNji/yxA/CT/a50FHRfx5CYmixRK+sBr3tcVwlVCjQpQe nzPsPqKM0WIUg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 04/27] arm64/sysreg: Add SYS_FIELD_GET() helper Date: Wed, 22 Jun 2022 18:43:53 +0100 Message-Id: <20220622174416.1406282-5-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown Acked-by: Mark Rutland --- arch/arm64/include/asm/sysreg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6c7be1a2114b..0f5771ac5b94 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1326,6 +1326,9 @@ #endif +#define SYS_FIELD_GET(reg, field, val) \ + FIELD_GET(reg##_##field##_MASK, val) + #define SYS_FIELD_PREP(reg, field, val) \ FIELD_PREP(reg##_##field##_MASK, val) From patchwork Wed Jun 22 17:43:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C554AC43334 for ; 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a=openpgp-sha256; l=9501; h=from:subject; bh=hF31K/MuXSvOMtvNLqspnOqB7gMg4U72BLDr+HgVdfA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1Td4zczB/6HP1J6Einpu1w8sUPJgdW3ErH2aV+y 5zVqiNSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU3QAKCRAk1otyXVSH0JlDB/ 4xfihUVfY7wseHRshgJWPTA3mFBb/dzKDEMD+GDzdmaLPkxDVsogXaLnRDkMh7mID8ilFIUj4Cwhpj UIxaBytmosmAtjp3mswllS/yM4nfkqLsYQohgJtQ3uv6hYkfqunSL/4KJIeRyz+TdAsbnY2V3ay8vo Ea4KCVEot6EThucp7GS0J89hRJJNqGuYy76R0VCPM0Ds1jM8acyHXSTzeNTHYhLpr5bqyo2xlltGn5 hpwm8ytW76/i/68vaQxvHdOaP9Air3xG354QwnhZNdJ3OBwu+k8oeX1N7vOIQ+YW3BFdtioEs1fno2 o06mKNerRGIdEvd2NWcOrH1LT4lg18 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105259_646487_FD089166 X-CRM114-Status: GOOD ( 21.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org cache.h contains some defines which are used to represent fields and enumeration values which do not follow the standard naming convention used for when we automatically generate defines for system registers. Update the names of the constants to reflect standardised naming and move them to sysreg.h. There is also a helper CTR_L1IP() which was open coded and has been converted to use SYS_FIELD_GET(). Signed-off-by: Mark Brown --- arch/arm64/include/asm/cache.h | 28 +++++++--------------------- arch/arm64/include/asm/sysreg.h | 15 +++++++++++++++ arch/arm64/kernel/alternative.c | 2 +- arch/arm64/kernel/cpu_errata.c | 2 +- arch/arm64/kernel/cpufeature.c | 20 ++++++++++---------- arch/arm64/kernel/cpuinfo.c | 12 ++++++------ arch/arm64/kernel/traps.c | 6 +++--- 7 files changed, 43 insertions(+), 42 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 0cbe75b9e4e5..3abedf304ec1 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -7,31 +7,17 @@ #include #include - -#define CTR_L1IP_SHIFT 14 -#define CTR_L1IP_MASK 3 -#define CTR_DMINLINE_SHIFT 16 -#define CTR_IMINLINE_SHIFT 0 -#define CTR_IMINLINE_MASK 0xf -#define CTR_ERG_SHIFT 20 -#define CTR_CWG_SHIFT 24 -#define CTR_CWG_MASK 15 -#define CTR_IDC_SHIFT 28 -#define CTR_DIC_SHIFT 29 +#include #define CTR_CACHE_MINLINE_MASK \ - (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT) - -#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) + (0xf << CTR_EL0_DMINLINE_SHIFT | \ + CTR_EL0_IMINLINE_MASK << CTR_EL0_IMINLINE_SHIFT) -#define ICACHE_POLICY_VPIPT 0 -#define ICACHE_POLICY_VIPT 2 -#define ICACHE_POLICY_PIPT 3 +#define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr) #define L1_CACHE_SHIFT (6) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - #define CLIDR_LOUU_SHIFT 27 #define CLIDR_LOC_SHIFT 24 #define CLIDR_LOUIS_SHIFT 21 @@ -85,7 +71,7 @@ static __always_inline int icache_is_vpipt(void) static inline u32 cache_type_cwg(void) { - return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; + return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK; } #define __read_mostly __section(".data..read_mostly") @@ -119,12 +105,12 @@ static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void) { u32 ctr = read_cpuid_cachetype(); - if (!(ctr & BIT(CTR_IDC_SHIFT))) { + if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) { u64 clidr = read_sysreg(clidr_el1); if (CLIDR_LOC(clidr) == 0 || (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0)) - ctr |= BIT(CTR_IDC_SHIFT); + ctr |= BIT(CTR_EL0_IDC_SHIFT); } return ctr; diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 0f5771ac5b94..19c6eabfec7c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1084,6 +1084,21 @@ #define MVFR2_FPMISC_SHIFT 4 #define MVFR2_SIMDMISC_SHIFT 0 +#define CTR_EL0_L1Ip_VPIPT 0 +#define CTR_EL0_L1Ip_VIPT 2 +#define CTR_EL0_L1Ip_PIPT 3 + +#define CTR_EL0_L1Ip_SHIFT 14 +#define CTR_EL0_L1Ip_MASK 3 +#define CTR_EL0_DminLine_SHIFT 16 +#define CTR_EL0_IminLine_SHIFT 0 +#define CTR_EL0_IminLine_MASK 0xf +#define CTR_EL0_ERG_SHIFT 20 +#define CTR_EL0_CWG_SHIFT 24 +#define CTR_EL0_CWG_MASK 15 +#define CTR_EL0_IDC_SHIFT 28 +#define CTR_EL0_DIC_SHIFT 29 + #define DCZID_DZP_SHIFT 4 #define DCZID_BS_SHIFT 0 diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c index 7bbf5104b7b7..9bcaa5eacf16 100644 --- a/arch/arm64/kernel/alternative.c +++ b/arch/arm64/kernel/alternative.c @@ -121,7 +121,7 @@ static void clean_dcache_range_nopatch(u64 start, u64 end) ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0, - CTR_DMINLINE_SHIFT); + CTR_EL0_DminLine_SHIFT); cur = start & ~(d_size - 1); do { /* diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index c05cc3b6162e..a0dd3ea8f585 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -187,7 +187,7 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, int scope) { u32 midr = read_cpuid_id(); - bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); + bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT); const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 8d88433de81d..b7cd50eb6d8a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -396,18 +396,18 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { static const struct arm64_ftr_bits ftr_ctr[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), /* * Linux can handle differing I-cache policies. Userspace JITs will * make use of *minLine. * If we have differing I-cache policies, report it as the weakest - VIPT. */ - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -1480,7 +1480,7 @@ static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, else ctr = read_cpuid_effective_cachetype(); - return ctr & BIT(CTR_IDC_SHIFT); + return ctr & BIT(CTR_EL0_IDC_SHIFT); } static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) @@ -1491,7 +1491,7 @@ static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unu * to the CTR_EL0 on this CPU and emulate it with the real/safe * value. */ - if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) + if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); } @@ -1505,7 +1505,7 @@ static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, else ctr = read_cpuid_cachetype(); - return ctr & BIT(CTR_DIC_SHIFT); + return ctr & BIT(CTR_EL0_DIC_SHIFT); } static bool __maybe_unused diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 7ecf9ffb590b..e44411ff909c 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -36,11 +36,11 @@ static struct cpuinfo_arm64 boot_cpu_data; static inline const char *icache_policy_str(int l1ip) { switch (l1ip) { - case ICACHE_POLICY_VPIPT: + case CTR_EL0_L1Ip_VPIPT: return "VPIPT"; - case ICACHE_POLICY_VIPT: + case CTR_EL0_L1Ip_VIPT: return "VIPT"; - case ICACHE_POLICY_PIPT: + case CTR_EL0_L1Ip_PIPT: return "PIPT"; default: return "RESERVED/UNKNOWN"; @@ -349,14 +349,14 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) u32 l1ip = CTR_L1IP(info->reg_ctr); switch (l1ip) { - case ICACHE_POLICY_VPIPT: + case CTR_EL0_L1Ip_VPIPT: set_bit(ICACHEF_VPIPT, &__icache_flags); break; - case ICACHE_POLICY_VIPT: + case CTR_EL0_L1Ip_VIPT: /* Assume aliasing */ set_bit(ICACHEF_ALIASING, &__icache_flags); break; - case ICACHE_POLICY_PIPT: + case CTR_EL0_L1Ip_PIPT: default: break; } diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 9ac7a81b79be..b7fed33981f7 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -579,11 +579,11 @@ static void ctr_read_handler(unsigned long esr, struct pt_regs *regs) if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { /* Hide DIC so that we can trap the unnecessary maintenance...*/ - val &= ~BIT(CTR_DIC_SHIFT); + val &= ~BIT(CTR_EL0_DIC_SHIFT); /* ... and fake IminLine to reduce the number of traps. */ - val &= ~CTR_IMINLINE_MASK; - val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK; + val &= ~CTR_EL0_IminLine_MASK; + val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK; } pt_regs_write_reg(regs, rt, val); From patchwork Wed Jun 22 17:43:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4973FC43334 for ; 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In preparation for automatic generation of the defines add the _EL0 in. No functional change. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 4 ++-- arch/arm64/kernel/cpufeature.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 19c6eabfec7c..0af7ee9b314d 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1099,8 +1099,8 @@ #define CTR_EL0_IDC_SHIFT 28 #define CTR_EL0_DIC_SHIFT 29 -#define DCZID_DZP_SHIFT 4 -#define DCZID_BS_SHIFT 0 +#define DCZID_EL0_DZP_SHIFT 4 +#define DCZID_EL0_BS_SHIFT 0 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b7cd50eb6d8a..b9c5b11c17c3 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -453,8 +453,8 @@ static const struct arm64_ftr_bits ftr_mvfr2[] = { }; static const struct arm64_ftr_bits ftr_dczid[] = { - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), ARM64_FTR_END, }; From patchwork Wed Jun 22 17:43:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA3A8C433EF for ; Wed, 22 Jun 2022 17:55:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 22 Jun 2022 17:53:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87DAEC3411D; Wed, 22 Jun 2022 17:52:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920379; bh=gg+HwstbBBXxvPKEJ0G5tNAioO0xJMhsln1KH6FrwK0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZId37l/fCX+mKDJmCGAl5V4M7Ntd3NV+SYtSOXnyHL+5UicTIJOov2zyJlFQpB6+5 nr+S4hRR4hV+LiyTTEiBF651VKIG8dDTm6IZyn4mSruCEWWeMByzwOsyWlzxhe339n AaR+iOcS/oFnU3k22KUcHXA5fzxjE7og0mb092DRNuXpXrJGpJSaVXyFmOLbNxmSHp p3Boau1cBLNUXYNYYCB8X/QXSy3DlDuSA+jOuC+21FLcr89u1/wuiXiYHV3VC2ApGf vz1wC42RHIMsHW1Bu0NEOq18/J43IYitgyVzZ+ZKe8uudQ+YG9je8hcuSkgCEE2tCp j8G/0FHM9vsjw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 07/27] arm64/mte: Standardise GMID field name definitions Date: Wed, 22 Jun 2022 18:43:56 +0100 Message-Id: <20220622174416.1406282-8-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1901; h=from:subject; bh=gg+HwstbBBXxvPKEJ0G5tNAioO0xJMhsln1KH6FrwK0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1TfacElfXkbGj9Ma5Fx1ymbEvGQm1PUYfPIpm4t 3LAUk/qJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU3wAKCRAk1otyXVSH0O6hB/ 0ZnSUYW8OrYPHBCllKJDiWqUhq53EMYLUk/6t3jHocAIW3yoDOv0mqIrJYeu596Do7INJHOG0A5g6t 45UgdRNJ0M/a4LtB0CEZ8vXIsJlXyHe1PMMRQ/ugFjhG54I2l48rRu3qVsBbT2yQGxxdXKjMdtS4LR ixBo2i7MwRdhLpxeHtSGeMg6G17zSOXLcec5Ih42onkYwQJtl429JwoBk+FluPhqg5+WtyrwgBl8Mj nKINemVxNVxN4eCyg0W6dne7PtO3fJWvzgSmNRGLxXklWXXAWcs4Inr939hlztXf8w+rRh81PQ9ojt BGJwcFoivm2/AWQ3BAmriaQ8IES6dL X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105302_844399_C7731A7D X-CRM114-Status: GOOD ( 14.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Usually our defines for bitfields in system registers do not include a SYS_ prefix but those for GMID do. In preparation for automatic generation of defines remove that prefix. No functional change. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 4 ++-- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/lib/mte.S | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 0af7ee9b314d..ae86b422ac74 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1136,8 +1136,8 @@ #define SYS_RGSR_EL1_SEED_MASK 0xffffUL /* GMID_EL1 field definitions */ -#define SYS_GMID_EL1_BS_SHIFT 0 -#define SYS_GMID_EL1_BS_SIZE 4 +#define GMID_EL1_BS_SHIFT 0 +#define GMID_EL1_BS_SIZE 4 /* TFSR{,E0}_EL1 bit definitions */ #define SYS_TFSR_EL1_TF0_SHIFT 0 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b9c5b11c17c3..7d838b5f7e20 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -459,7 +459,7 @@ static const struct arm64_ftr_bits ftr_dczid[] = { }; static const struct arm64_ftr_bits ftr_gmid[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), ARM64_FTR_END, }; diff --git a/arch/arm64/lib/mte.S b/arch/arm64/lib/mte.S index eeb9e45bcce8..1b7c93ae7e63 100644 --- a/arch/arm64/lib/mte.S +++ b/arch/arm64/lib/mte.S @@ -18,7 +18,7 @@ */ .macro multitag_transfer_size, reg, tmp mrs_s \reg, SYS_GMID_EL1 - ubfx \reg, \reg, #SYS_GMID_EL1_BS_SHIFT, #SYS_GMID_EL1_BS_SIZE + ubfx \reg, \reg, #GMID_EL1_BS_SHIFT, #GMID_EL1_BS_SIZE mov \tmp, #4 lsl \reg, \tmp, \reg .endm From patchwork Wed Jun 22 17:43:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3499DC43334 for ; Wed, 22 Jun 2022 17:56:32 +0000 (UTC) DKIM-Signature: v=1; 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Wed, 22 Jun 2022 17:53:04 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 558DD61CC2; Wed, 22 Jun 2022 17:53:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BEFDC341C7; Wed, 22 Jun 2022 17:53:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920381; bh=HtZpgKRRfVW79abpleb9KdtlOr7sZiu4LfKX5toMvz0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AftuI6ToiaKxd1TG+PtVTfWgmy9kRryTRH6nbtoDNehWXFkA5jZzKNHIg+EfuU0IP zfIoFlAm/OymmUfQeuv6AjmO/Qb5VBy9TAIXDeek4f4CrgSSjk42nQgh1XQqW8qbHf D3GX5KPKCIUpLWInDUHoPobnMZ9pU0HgeVc88FItUHbsFhhWM1LhXu4r7DpCr0B/i+ QBjkMOBzY26I6Tuy7/HjcNhXa0xUpvoXkI04wTYrfZ3SAznK28VbW6Spt+P7FA+4PM bmu+QGbtdh4Jlc6vRFiO0rZidTDbm/imXc0MY028IJZgxok0LRw/oEHpSXjVEZJl6w rTrNQTTTbtHEA== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 08/27] arm64/sysreg: Align pointer auth enumeration defines with architecture Date: Wed, 22 Jun 2022 18:43:57 +0100 Message-Id: <20220622174416.1406282-9-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6271; h=from:subject; bh=HtZpgKRRfVW79abpleb9KdtlOr7sZiu4LfKX5toMvz0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1TfV2L08HpOGMCuKP8nt05iJVbkkqBoKhqvCsnx CL9V4FmJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU3wAKCRAk1otyXVSH0EVdB/ 9007WbJaDVDLVI2lposrd6IGgBy0Eg27MOg7gP2MaXKuT+afLJ5OGML+eLEQt/ONUqsITGAaCSUd3s RLsvMLGCIT0vKfzKVk7TnxXlgQCIcu0LYaghFIeQyobFadjMiXE/TSat4l4BQwjeO9Hprp1m1GcEVV r63qPa5K5jUqa36xozsJtvtTpGLT9nFIFpCp+9Qz7SznCQ0+AFq6UPu6ZbWg5u7vk5vVlBYNFi/L+k TaiEWhiipo/NfQn6aR6K4IGzBAEfuh+4P4s2jXVei2Z+YfM9djQ+ar00fTgLzWGEjNM1eAORRuKs+C eVnadMM26AIuHhMcLVEK9WDisWsOoA X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105302_990239_E6EDDDE8 X-CRM114-Status: GOOD ( 13.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The defines used for the pointer authentication feature enumerations do not follow the naming convention we've decided to use where we name things after the architecture feature that introduced. Prepare for generating the defines for the ISA ID registers by updating to use the feature names. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 34 ++++++++++++++++----------------- arch/arm64/kernel/cpufeature.c | 24 +++++++++++------------ 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ae86b422ac74..9a7e7b61d3ea 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -721,21 +721,21 @@ #define ID_AA64ISAR1_DPB_SHIFT 0 #define ID_AA64ISAR1_APA_NI 0x0 -#define ID_AA64ISAR1_APA_ARCHITECTED 0x1 +#define ID_AA64ISAR1_APA_PAuth 0x1 #define ID_AA64ISAR1_APA_ARCH_EPAC 0x2 -#define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3 -#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4 -#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5 +#define ID_AA64ISAR1_APA_Pauth2 0x3 +#define ID_AA64ISAR1_APA_FPAC 0x4 +#define ID_AA64ISAR1_APA_FPACCOMBINE 0x5 #define ID_AA64ISAR1_API_NI 0x0 -#define ID_AA64ISAR1_API_IMP_DEF 0x1 -#define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2 -#define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3 -#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4 -#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5 +#define ID_AA64ISAR1_API_PAuth 0x1 +#define ID_AA64ISAR1_API_EPAC 0x2 +#define ID_AA64ISAR1_API_PAuth2 0x3 +#define ID_AA64ISAR1_API_FPAC 0x4 +#define ID_AA64ISAR1_API_FPACCOMBINE 0x5 #define ID_AA64ISAR1_GPA_NI 0x0 -#define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 +#define ID_AA64ISAR1_GPA_IMP 0x1 #define ID_AA64ISAR1_GPI_NI 0x0 -#define ID_AA64ISAR1_GPI_IMP_DEF 0x1 +#define ID_AA64ISAR1_GPI_IMP 0x1 /* id_aa64isar2 */ #define ID_AA64ISAR2_CLEARBHB_SHIFT 28 @@ -755,14 +755,14 @@ #define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 #define ID_AA64ISAR2_APA3_NI 0x0 -#define ID_AA64ISAR2_APA3_ARCHITECTED 0x1 -#define ID_AA64ISAR2_APA3_ARCH_EPAC 0x2 -#define ID_AA64ISAR2_APA3_ARCH_EPAC2 0x3 -#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC 0x4 -#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB 0x5 +#define ID_AA64ISAR2_APA3_PAuth 0x1 +#define ID_AA64ISAR2_APA3_EPAC 0x2 +#define ID_AA64ISAR2_APA3_PAuth2 0x3 +#define ID_AA64ISAR2_APA3_FPAC 0x4 +#define ID_AA64ISAR2_APA3_FPACCOMBINE 0x5 #define ID_AA64ISAR2_GPA3_NI 0x0 -#define ID_AA64ISAR2_GPA3_ARCHITECTED 0x1 +#define ID_AA64ISAR2_GPA3_IMP 0x1 /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 7d838b5f7e20..838b3dcd8473 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2317,7 +2317,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_APA_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, + .min_field_value = ID_AA64ISAR1_APA_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2328,7 +2328,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR2_APA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED, + .min_field_value = ID_AA64ISAR2_APA3_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2339,7 +2339,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_API_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_API_IMP_DEF, + .min_field_value = ID_AA64ISAR1_API_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2355,7 +2355,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_GPA_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, + .min_field_value = ID_AA64ISAR1_GPA_IMP, .matches = has_cpuid_feature, }, { @@ -2366,7 +2366,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR2_GPA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED, + .min_field_value = ID_AA64ISAR2_GPA3_IMP, .matches = has_cpuid_feature, }, { @@ -2377,7 +2377,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_GPI_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, + .min_field_value = ID_AA64ISAR1_GPI_IMP, .matches = has_cpuid_feature, }, { @@ -2562,15 +2562,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 4, FTR_UNSIGNED, - ID_AA64ISAR1_APA_ARCHITECTED) + ID_AA64ISAR1_APA_PAuth) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED) + 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) + 4, FTR_UNSIGNED, ID_AA64ISAR1_API_PAuth) }, {}, }; @@ -2578,15 +2578,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) + 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_IMP) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED) + 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) + 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP) }, {}, }; From patchwork Wed Jun 22 17:43:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6AA87C433EF for ; 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In preparation for generation of defines for ID_AA64ISAR2_EL1 rename to use the architecture's naming. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/include/asm/sysreg.h | 2 +- arch/arm64/kernel/cpufeature.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 14a8f3d93add..6472f2badc97 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope) isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); return cpuid_feature_extract_unsigned_field(isar2, - ID_AA64ISAR2_CLEARBHB_SHIFT); + ID_AA64ISAR2_BC_SHIFT); } const struct cpumask *system_32bit_el0_cpumask(void); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9a7e7b61d3ea..478af541410d 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -738,7 +738,7 @@ #define ID_AA64ISAR1_GPI_IMP 0x1 /* id_aa64isar2 */ -#define ID_AA64ISAR2_CLEARBHB_SHIFT 28 +#define ID_AA64ISAR2_BC_SHIFT 28 #define ID_AA64ISAR2_APA3_SHIFT 12 #define ID_AA64ISAR2_GPA3_SHIFT 8 #define ID_AA64ISAR2_RPRES_SHIFT 4 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 838b3dcd8473..0f9c9d8b21a2 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -231,7 +231,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_BC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), From patchwork Wed Jun 22 17:43:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB4BFC43334 for ; Wed, 22 Jun 2022 17:57:39 +0000 (UTC) DKIM-Signature: v=1; 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Wed, 22 Jun 2022 17:53:09 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 9C0E1B82078; Wed, 22 Jun 2022 17:53:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C5D7C3411D; Wed, 22 Jun 2022 17:53:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920385; bh=RtFamDuyvgAC3wZ8+GYzzW3JOCYwRksSkxeAA/ag+FE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=caVfbd75JD6Kmv+6CotLgZXESZcuFyFJlOY4aFh8ftfoKoCN+xWzbbebCCSgUlS7R uuKqf2aV1fh9MIpO/h8A7FNfAdczbICf2HQSOwYCvz+H/2l8aKOQbAgpsW+JVRvGse Jc6jhtTxSEDhXUUgl24EPKgtPvco2zdMtWFu+1Dh7+gmaGlDyy9pOTXr76COGg8O0q jnhynWLTrELMXOtYbYTCBgXVtoYkufgU8WiSB/dIQk7Xe7r84xOn8n1IAoRCHsTWPw HHI54CF0KWzqaUd0R6YV9uEM4kwTasf8jEEXq45KeB0BOzx/Km6PcJ582ZIgh94kqz jrP9m8NEKf6gw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 10/27] arm64/sysreg: Standardise naming for WFxT defines Date: Wed, 22 Jun 2022 18:43:59 +0100 Message-Id: <20220622174416.1406282-11-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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In preparation for automatic generation of defines update these to be more standard. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 6 +++--- arch/arm64/kernel/cpufeature.c | 8 ++++---- arch/arm64/kvm/sys_regs.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 478af541410d..6cd0f3c87267 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -742,7 +742,7 @@ #define ID_AA64ISAR2_APA3_SHIFT 12 #define ID_AA64ISAR2_GPA3_SHIFT 8 #define ID_AA64ISAR2_RPRES_SHIFT 4 -#define ID_AA64ISAR2_WFXT_SHIFT 0 +#define ID_AA64ISAR2_WFxT_SHIFT 0 #define ID_AA64ISAR2_RPRES_8BIT 0x0 #define ID_AA64ISAR2_RPRES_12BIT 0x1 @@ -751,8 +751,8 @@ * reserved, but has not yet been removed from the ARM ARM * as of ARM DDI 0487G.b. */ -#define ID_AA64ISAR2_WFXT_NI 0x0 -#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 +#define ID_AA64ISAR2_WFxT_NI 0x0 +#define ID_AA64ISAR2_WFxT_IMP 0x2 #define ID_AA64ISAR2_APA3_NI 0x0 #define ID_AA64ISAR2_APA3_PAuth 0x1 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0f9c9d8b21a2..83f8e9d360ce 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -237,7 +237,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFXT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFxT_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2516,10 +2516,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_WFXT_SHIFT, + .field_pos = ID_AA64ISAR2_WFxT_SHIFT, .field_width = 4, .matches = has_cpuid_feature, - .min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED, + .min_field_value = ID_AA64ISAR2_WFxT_IMP, }, {}, }; @@ -2654,7 +2654,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), - HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFXT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFXT_SUPPORTED, CAP_HWCAP, KERNEL_HWCAP_WFXT), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), #ifdef CONFIG_ARM64_SME HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c06c0477fab5..f12c6d457677 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1146,7 +1146,7 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); if (!cpus_have_final_cap(ARM64_HAS_WFXT)) - val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFXT); + val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFxT); break; case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ From patchwork Wed Jun 22 17:44:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F078C43334 for ; Wed, 22 Jun 2022 17:57:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 22 Jun 2022 17:53:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D6D4BC341C7; Wed, 22 Jun 2022 17:53:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920387; bh=t2CMfxxc9TMkKKVxsyOOFft/8KRgyBVMx9jpcP66F9o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DLFDttlf2rl9+FBWW6Hey3mds9tUI0HNER6YTkS5WggdBn5adYArRzfZbcgGIDG5L 8cWZDCx2ILMDlAMjTV+sJxV0FIx1+QzwsJgUMGJVZ4vs45YfIqbhZMyFXayAIaYJ2V ChTxQO4gu7Jzh9Uz3j/KFXFRLLQgLfDo19BT0uabnIIye4CqyTYpalZb3ldgd8Muvi LRN/xoTFqAYjDihWQBhVA6F/PRfXACxTOTUs9CAXGiQxSyPsF/D/yGhAStwI0QNkhN t9N1K+FquBJmIxnpWK3E7eqT25WvS0DBNmfN6fPL2SkAcCgP/Z9OHimT+rU65HXVAC 2KLf3rlPbE0zQ== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 11/27] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Date: Wed, 22 Jun 2022 18:44:00 +0100 Message-Id: <20220622174416.1406282-12-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7266; h=from:subject; bh=t2CMfxxc9TMkKKVxsyOOFft/8KRgyBVMx9jpcP66F9o=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1TiIqTy2RwKdguL+pzHJMiUN9BwXsmk9sxAIE+f WOwhspeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU4gAKCRAk1otyXVSH0LF6B/ 4o8Oj+2EHwEg+KTn3W1HAzUALZQJ0vd9khj/9yK9ss3EiBagXDgsQYntdx5TZWJWn8O6RRiBGo+FIM Mf1XkbKQb7T/DtHYJ0Bh+dQYS+BrVEFKWHZo5TgESjMECxHPMjc+NiF/+vvMhss7YEDwlRh0rhfB3T tpq+pBx+CUJerQhUiXRyW7P8/VEf5q17nhGZDMmTwkCq8hDHdKtVaR6UncMACbF6pWf9q4PTa2Db1m LuWMmSTa/Za9xncu7KpzqdxXoEvAVHFFNtLjh2goFwrd5nXoc2DSJ4RWKmlRft2dH2iV1RuZlvGTzT 5gUF1vi0uWThxa/hRBwcNIomK3Ft1J X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105310_383978_01066540 X-CRM114-Status: GOOD ( 14.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We have a series of defines for enumeration values we test for in the fields in ID_AA64SMFR0_EL1 which do not follow our usual convention of including the EL1 in the name and having _IMP at the end of the basic "feature present" define. In preparation for automatic register generation bring the defines into sync with convention, no functional change. Signed-off-by: Mark Brown --- arch/arm64/include/asm/el2_setup.h | 2 +- arch/arm64/include/asm/sysreg.h | 30 ++++++++++++++-------------- arch/arm64/kernel/cpufeature.c | 32 +++++++++++++++--------------- 3 files changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 34ceff08cac4..bfd0ad64b598 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -161,7 +161,7 @@ mov x1, #0 // SMCR controls mrs_s x2, SYS_ID_AA64SMFR0_EL1 - ubfx x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM? + ubfx x2, x2, #ID_AA64SMFR0_EL1_FA64_SHIFT, #1 // Full FP in SM? cbz x2, .Lskip_sme_fa64_\@ orr x1, x1, SMCR_ELx_FA64_MASK diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6cd0f3c87267..763f0f90dca8 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -834,21 +834,21 @@ #define ID_AA64ZFR0_SVEVER_SVE2 0x1 /* id_aa64smfr0 */ -#define ID_AA64SMFR0_FA64_SHIFT 63 -#define ID_AA64SMFR0_I16I64_SHIFT 52 -#define ID_AA64SMFR0_F64F64_SHIFT 48 -#define ID_AA64SMFR0_I8I32_SHIFT 36 -#define ID_AA64SMFR0_F16F32_SHIFT 35 -#define ID_AA64SMFR0_B16F32_SHIFT 34 -#define ID_AA64SMFR0_F32F32_SHIFT 32 - -#define ID_AA64SMFR0_FA64 0x1 -#define ID_AA64SMFR0_I16I64 0xf -#define ID_AA64SMFR0_F64F64 0x1 -#define ID_AA64SMFR0_I8I32 0xf -#define ID_AA64SMFR0_F16F32 0x1 -#define ID_AA64SMFR0_B16F32 0x1 -#define ID_AA64SMFR0_F32F32 0x1 +#define ID_AA64SMFR0_EL1_FA64_SHIFT 63 +#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52 +#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48 +#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36 +#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35 +#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34 +#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32 + +#define ID_AA64SMFR0_EL1_FA64_IMP 0x1 +#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf +#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1 +#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf +#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1 +#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1 +#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1 /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 83f8e9d360ce..a6c224539ce4 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -298,19 +298,19 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_FA64_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I16I64_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F64F64_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I8I32_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F16F32_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_B16F32_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F32F32_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), ARM64_FTR_END, }; @@ -2503,9 +2503,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .capability = ARM64_SME_FA64, .sys_reg = SYS_ID_AA64SMFR0_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64SMFR0_FA64_SHIFT, + .field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT, .field_width = 1, - .min_field_value = ID_AA64SMFR0_FA64, + .min_field_value = ID_AA64SMFR0_EL1_FA64_IMP, .matches = has_cpuid_feature, .cpu_enable = fa64_kernel_enable, }, @@ -2657,13 +2657,13 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), #ifdef CONFIG_ARM64_SME HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I16I64, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F64F64, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I8I32, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F16F32, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_B16F32, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F32F32, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), #endif /* CONFIG_ARM64_SME */ {}, }; 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Wed, 22 Jun 2022 17:53:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AE72AC341C5; Wed, 22 Jun 2022 17:53:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920389; bh=L8a+x5mk08F1uRGymRDdE5U15GtKzn2RdzPMzWDT3Y0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lSHLE87vy9XFb/e/5hQwRwuOJdY6w14sSrSpvmpM78wmF3cQc3HxLKxqg77cc7WUe dIHfFyACWF9+wAOZQzjT11KM7HVC+Y/DNq9nIg4Qa/Y81PiO5CAU4T8E4lbd1UoaPV TukDvFIRkNScp+6pjjBkwIKFANiYS+FTnGNvvP4HhQVomY5rvP9yWS51c8UdImtvtk T0HoahAu68oa5gH3+t7u7btd3ceOJPyr8ZI/6YqNjXeUfnp/BFjGmQ8X5ENAMNg+AQ 8LxnkLI34pe8VxTtt8JaTeyhtz8vo3dsndtK2YVgxD6zUwVlq/DPgLLpk/nGvcSO9m +0Pq1eTRzB+9Q== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 12/27] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Date: Wed, 22 Jun 2022 18:44:01 +0100 Message-Id: <20220622174416.1406282-13-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7866; h=from:subject; bh=L8a+x5mk08F1uRGymRDdE5U15GtKzn2RdzPMzWDT3Y0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1Ti5Nl7aZ3DeounFmHUC6qE/eab5nPDw2gJEB8F SC05fviJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU4gAKCRAk1otyXVSH0F+NB/ 4ktBw7XCDF8MIJAeZGHHYw/gu+NSxSmyHOkUbXtO8wacE3AEKkl+UxgMFX7WjTV0L/HgjZVYrF9wTr HyugTAYISu/oq2FuVQ3HU+iQwJPtQoPt8Yo3tVh/FdEepPFocMi854TXDUOWOS/sAh7aI9cZ/dFDYR AL2OybfzuJnLnJeMCKLqaHmCeZsscnoYf04c+L/F7v3vQZjfqHwNPhUjUkrDkHLep3R29ZerzoXvzD lxt/kAoyKGDXrl5KZlXlzg48WAiUa/pAOiBGgUCCkor1pCODGgdT2fI5FgH5DEJZu9YcEr+o4Yh3Zm TaRwF0pt56REpQ2u8Ae88zMow2/dL5 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105312_018132_C8B5DACF X-CRM114-Status: GOOD ( 12.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The various defines for bitfields in ID_AA64ZFR0_EL1 do not follow our conventions for register field names, they omit the _EL1, they don't use specific defines for enumeration values and they don't follow the naming in the architecture in some cases. In preparation for automatic generation bring them into line with convention. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 40 ++++++++++++++++----------------- arch/arm64/kernel/cpufeature.c | 38 +++++++++++++++---------------- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 763f0f90dca8..899e1e52b2b2 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -812,26 +812,26 @@ #define ID_AA64PFR1_MTE_ASYMM 0x3 /* id_aa64zfr0 */ -#define ID_AA64ZFR0_F64MM_SHIFT 56 -#define ID_AA64ZFR0_F32MM_SHIFT 52 -#define ID_AA64ZFR0_I8MM_SHIFT 44 -#define ID_AA64ZFR0_SM4_SHIFT 40 -#define ID_AA64ZFR0_SHA3_SHIFT 32 -#define ID_AA64ZFR0_BF16_SHIFT 20 -#define ID_AA64ZFR0_BITPERM_SHIFT 16 -#define ID_AA64ZFR0_AES_SHIFT 4 -#define ID_AA64ZFR0_SVEVER_SHIFT 0 - -#define ID_AA64ZFR0_F64MM 0x1 -#define ID_AA64ZFR0_F32MM 0x1 -#define ID_AA64ZFR0_I8MM 0x1 -#define ID_AA64ZFR0_BF16 0x1 -#define ID_AA64ZFR0_SM4 0x1 -#define ID_AA64ZFR0_SHA3 0x1 -#define ID_AA64ZFR0_BITPERM 0x1 -#define ID_AA64ZFR0_AES 0x1 -#define ID_AA64ZFR0_AES_PMULL 0x2 -#define ID_AA64ZFR0_SVEVER_SVE2 0x1 +#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56 +#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52 +#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44 +#define ID_AA64ZFR0_EL1_SM4_SHIFT 40 +#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32 +#define ID_AA64ZFR0_EL1_BF16_SHIFT 20 +#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16 +#define ID_AA64ZFR0_EL1_AES_SHIFT 4 +#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0 + +#define ID_AA64ZFR0_EL1_F64MM_IMP 0x1 +#define ID_AA64ZFR0_EL1_F32MM_IMP 0x1 +#define ID_AA64ZFR0_EL1_I8MM_IMP 0x1 +#define ID_AA64ZFR0_EL1_BF16_IMP 0x1 +#define ID_AA64ZFR0_EL1_SM4_IMP 0x1 +#define ID_AA64ZFR0_EL1_SHA3_IMP 0x1 +#define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1 +#define ID_AA64ZFR0_EL1_AES_IMP 0x1 +#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 +#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 /* id_aa64smfr0 */ #define ID_AA64SMFR0_EL1_FA64_SHIFT 63 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index a6c224539ce4..08288ad17307 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -276,23 +276,23 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2628,16 +2628,16 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), #endif HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), #ifdef CONFIG_ARM64_BTI From patchwork Wed Jun 22 17:44:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E68DC43334 for ; Wed, 22 Jun 2022 17:58:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=z/cz/fRNgeWsVgBXLTdWBIBPW4jfL0XvMW9f1XKzTHY=; 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Wed, 22 Jun 2022 17:53:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920391; bh=yzXQzVwjHcc0Du+7vCoUTSCuWL9mTbEVweAh9VCRzP4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wc576jTi0ljODdDe8uf9+2cfv9LXswM5t9Mpyyj6KKMMPYbvQ+3X/wwWYuXMKVkaq a6vWsxpVRs/hM9bNLKhpMAmbhU3R8yCQnulK3Y+F1Gu8N5g1J30gceo/mpZi1DI+lB vnAyFWSS1KFC8yYcqXoH/rQkg80ewBWd3LQGmElnXLLj/1m490ZXiRXWZdnY/LNuwr ktpGAMacW9HMPWqLqGPDVFz9rwGZuMWJ8XXFTMhaf80ZqLPij5BOgZqOWrxTT3tx1M /bnkVtwqTbdZm5T18ZENd6N08Ykq5NOVHFOjdprhFOAu9mRTb0QPDO8mWxCV9yncYV FbvBlRim3Y79w== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 13/27] arm64/sysreg: Remove defines for RPRES enumeration Date: Wed, 22 Jun 2022 18:44:02 +0100 Message-Id: <20220622174416.1406282-14-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Since these defines are never used just remove them. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 899e1e52b2b2..d3112117b7e6 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -744,8 +744,6 @@ #define ID_AA64ISAR2_RPRES_SHIFT 4 #define ID_AA64ISAR2_WFxT_SHIFT 0 -#define ID_AA64ISAR2_RPRES_8BIT 0x0 -#define ID_AA64ISAR2_RPRES_12BIT 0x1 /* * Value 0x1 has been removed from the architecture, and is * reserved, but has not yet been removed from the ARM ARM From patchwork Wed Jun 22 17:44:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C696AC43334 for ; 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a=openpgp-sha256; l=19245; h=from:subject; bh=NJ5cnVVjTwpwXkMhx5zQJvMKgxBohAxGF6wW6TIx9Xk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1TkT8qeAqbvBF5r2O/s0Bo0PZh9gxDixS6pTJ+i GhsaCFSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU5AAKCRAk1otyXVSH0F6/B/ 9+ds+8NV4JMYiYO0JAnvjMOlGJ2SbXrHleuPhSwyXcAvUx44kzq7FICu1uchKfgI6wxoI0CDT+tcwB tYtJO29tMi01jdtasGEM7hjYagIQGgfasoFyR0+NAoS4MK+usR8B53FJJImEcdpSdOxhEg6vWbvEA0 tNvExDcmhYHrGBawF0+UFDmXAmRm4FcpIpM7HsA/aauxZyre8rZff6lPw29PTBOv0DBwdE0LxeOLS/ hmwSxBLgtR9SyqRwjaGKkO3uDHg0tMZTUbS7FcYzwniG/Qzf6yDLfywQp2sb3Y/WWjzczEuKcTw1U9 sVT/5mkCeDiN+sau2uyzuFH4XBCk+1 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105314_283734_7D6500D5 X-CRM114-Status: GOOD ( 16.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Normally we include the full register name in the defines for fields within registers but this has not been followed for ID registers. In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR1_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/asm_pointer_auth.h | 2 +- arch/arm64/include/asm/sysreg.h | 62 ++++++------- arch/arm64/kernel/cpufeature.c | 90 +++++++++---------- arch/arm64/kernel/idreg-override.c | 8 +- .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 28 +++--- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 8 +- arch/arm64/kvm/sys_regs.c | 8 +- 7 files changed, 103 insertions(+), 103 deletions(-) diff --git a/arch/arm64/include/asm/asm_pointer_auth.h b/arch/arm64/include/asm/asm_pointer_auth.h index ead62f7dd269..3b192e04a5dd 100644 --- a/arch/arm64/include/asm/asm_pointer_auth.h +++ b/arch/arm64/include/asm/asm_pointer_auth.h @@ -59,7 +59,7 @@ alternative_else_nop_endif .macro __ptrauth_keys_init_cpu tsk, tmp1, tmp2, tmp3 mrs \tmp1, id_aa64isar1_el1 - ubfx \tmp1, \tmp1, #ID_AA64ISAR1_APA_SHIFT, #8 + ubfx \tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8 mrs_s \tmp2, SYS_ID_AA64ISAR2_EL1 ubfx \tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4 orr \tmp1, \tmp1, \tmp2 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d3112117b7e6..ba9053bc33c2 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -705,37 +705,37 @@ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) /* id_aa64isar1 */ -#define ID_AA64ISAR1_I8MM_SHIFT 52 -#define ID_AA64ISAR1_DGH_SHIFT 48 -#define ID_AA64ISAR1_BF16_SHIFT 44 -#define ID_AA64ISAR1_SPECRES_SHIFT 40 -#define ID_AA64ISAR1_SB_SHIFT 36 -#define ID_AA64ISAR1_FRINTTS_SHIFT 32 -#define ID_AA64ISAR1_GPI_SHIFT 28 -#define ID_AA64ISAR1_GPA_SHIFT 24 -#define ID_AA64ISAR1_LRCPC_SHIFT 20 -#define ID_AA64ISAR1_FCMA_SHIFT 16 -#define ID_AA64ISAR1_JSCVT_SHIFT 12 -#define ID_AA64ISAR1_API_SHIFT 8 -#define ID_AA64ISAR1_APA_SHIFT 4 -#define ID_AA64ISAR1_DPB_SHIFT 0 - -#define ID_AA64ISAR1_APA_NI 0x0 -#define ID_AA64ISAR1_APA_PAuth 0x1 -#define ID_AA64ISAR1_APA_ARCH_EPAC 0x2 -#define ID_AA64ISAR1_APA_Pauth2 0x3 -#define ID_AA64ISAR1_APA_FPAC 0x4 -#define ID_AA64ISAR1_APA_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_API_NI 0x0 -#define ID_AA64ISAR1_API_PAuth 0x1 -#define ID_AA64ISAR1_API_EPAC 0x2 -#define ID_AA64ISAR1_API_PAuth2 0x3 -#define ID_AA64ISAR1_API_FPAC 0x4 -#define ID_AA64ISAR1_API_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_GPA_NI 0x0 -#define ID_AA64ISAR1_GPA_IMP 0x1 -#define ID_AA64ISAR1_GPI_NI 0x0 -#define ID_AA64ISAR1_GPI_IMP 0x1 +#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52 +#define ID_AA64ISAR1_EL1_DGH_SHIFT 48 +#define ID_AA64ISAR1_EL1_BF16_SHIFT 44 +#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 +#define ID_AA64ISAR1_EL1_SB_SHIFT 36 +#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 +#define ID_AA64ISAR1_EL1_GPI_SHIFT 28 +#define ID_AA64ISAR1_EL1_GPA_SHIFT 24 +#define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20 +#define ID_AA64ISAR1_EL1_FCMA_SHIFT 16 +#define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12 +#define ID_AA64ISAR1_EL1_API_SHIFT 8 +#define ID_AA64ISAR1_EL1_APA_SHIFT 5 +#define ID_AA64ISAR1_EL1_DPB_SHIFT 0 + +#define ID_AA64ISAR1_EL1_APA_NI 0x0 +#define ID_AA64ISAR1_EL1_APA_PAuth 0x1 +#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC 0x2 +#define ID_AA64ISAR1_EL1_APA_Pauth2 0x3 +#define ID_AA64ISAR1_EL1_APA_FPAC 0x4 +#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE 0x5 +#define ID_AA64ISAR1_EL1_API_NI 0x0 +#define ID_AA64ISAR1_EL1_API_PAuth 0x1 +#define ID_AA64ISAR1_EL1_API_EPAC 0x2 +#define ID_AA64ISAR1_EL1_API_PAuth2 0x3 +#define ID_AA64ISAR1_EL1_API_FPAC 0x4 +#define ID_AA64ISAR1_EL1_API_FPACCOMBINE 0x5 +#define ID_AA64ISAR1_EL1_GPA_NI 0x0 +#define ID_AA64ISAR1_EL1_GPA_IMP 0x1 +#define ID_AA64ISAR1_EL1_GPI_NI 0x0 +#define ID_AA64ISAR1_EL1_GPI_IMP 0x1 /* id_aa64isar2 */ #define ID_AA64ISAR2_BC_SHIFT 28 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 08288ad17307..0d4f0120c516 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -209,24 +209,24 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2132,7 +2132,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR1_EL1, - .field_pos = ID_AA64ISAR1_DPB_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, .field_width = 4, .min_field_value = 1, }, @@ -2143,7 +2143,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_DPB_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, .field_width = 4, .min_field_value = 2, }, @@ -2303,7 +2303,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR1_EL1, - .field_pos = ID_AA64ISAR1_SB_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_SB_SHIFT, .field_width = 4, .sign = FTR_UNSIGNED, .min_field_value = 1, @@ -2315,9 +2315,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_APA_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_APA_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_APA_PAuth, + .min_field_value = ID_AA64ISAR1_EL1_APA_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2337,9 +2337,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_API_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_API_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_API_PAuth, + .min_field_value = ID_AA64ISAR1_EL1_API_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2353,9 +2353,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_GPA_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_GPA_IMP, + .min_field_value = ID_AA64ISAR1_EL1_GPA_IMP, .matches = has_cpuid_feature, }, { @@ -2375,9 +2375,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_GPI_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_GPI_IMP, + .min_field_value = ID_AA64ISAR1_EL1_GPI_IMP, .matches = has_cpuid_feature, }, { @@ -2478,7 +2478,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT, .field_width = 4, .matches = has_cpuid_feature, .min_field_value = 1, @@ -2560,33 +2560,33 @@ static const struct arm64_cpu_capabilities arm64_features[] = { #ifdef CONFIG_ARM64_PTR_AUTH static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT, 4, FTR_UNSIGNED, - ID_AA64ISAR1_APA_PAuth) + ID_AA64ISAR1_EL1_APA_PAuth) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_API_PAuth) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth) }, {}, }; static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_IMP) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP) }, {}, }; @@ -2614,17 +2614,17 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index 8a2ceb591686..652c19b13588 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -63,10 +63,10 @@ static const struct ftr_set_desc isar1 __initconst = { .name = "id_aa64isar1", .override = &id_aa64isar1_override, .fields = { - { "gpi", ID_AA64ISAR1_GPI_SHIFT }, - { "gpa", ID_AA64ISAR1_GPA_SHIFT }, - { "api", ID_AA64ISAR1_API_SHIFT }, - { "apa", ID_AA64ISAR1_APA_SHIFT }, + { "gpi", ID_AA64ISAR1_EL1_GPI_SHIFT }, + { "gpa", ID_AA64ISAR1_EL1_GPA_SHIFT }, + { "api", ID_AA64ISAR1_EL1_API_SHIFT }, + { "apa", ID_AA64ISAR1_EL1_APA_SHIFT }, {} }, }; diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index fd55014b3497..46cf9dec21ba 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -176,20 +176,20 @@ ) #define PVM_ID_AA64ISAR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR1_DPB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_JSCVT) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_FCMA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_LRCPC) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_FRINTTS) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_SB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_SPECRES) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_BF16) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_DGH) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_I8MM) \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \ ) #define PVM_ID_AA64ISAR2_ALLOW (\ diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 35a4331ba5f3..5b77bc1cca0c 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -173,10 +173,10 @@ static u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR1_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI)); + allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); return id_aa64isar1_el1_sys_val & allow_mask; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f12c6d457677..ccd973dc346a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1136,10 +1136,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, break; case SYS_ID_AA64ISAR1_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI)); + val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 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Wed, 22 Jun 2022 17:53:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B455C3411D; Wed, 22 Jun 2022 17:53:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920394; bh=M/C0f7QFe7fvshqOippHw0Unx9VEAZ/cIw3cWYYe6/4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I9Ernh9CH6AXFiS3tmC1dYrfKX2AbRUQmuydCpKHB9nT96WemZAdbpZ3EnCw9/0Wz fvX5aAwXVpFP/JuCnZA2ZCP22GFPGSKFtPg69FlEyZtn5VfMhIWAbnwISJFBvws9UM AQ0L6HlL4qbMk+9qbbxBSe2T5TU2wdvJIY5NsZpAo08wQqJZYshNzWXntyBvx6jWw/ Nu7PWyWyXVsd2PIML1syloBt6l1T5ReK6S1dmyJh//vuabqrnMzkBw3ms9cIRKQ5Q8 ylws+/bbeyH4/rrvEKV9PyK2a3QtBZvuYssyHgtEl5DCFb+MjpNmslXm7yOMMsT/XU Cqkzz+bUWVahQ== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 15/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names Date: Wed, 22 Jun 2022 18:44:04 +0100 Message-Id: <20220622174416.1406282-16-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR2_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/asm_pointer_auth.h | 2 +- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/include/asm/sysreg.h | 34 +++++++++---------- arch/arm64/kernel/cpufeature.c | 34 +++++++++---------- arch/arm64/kernel/idreg-override.c | 4 +-- .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 4 +-- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 4 +-- arch/arm64/kvm/sys_regs.c | 6 ++-- 8 files changed, 45 insertions(+), 45 deletions(-) diff --git a/arch/arm64/include/asm/asm_pointer_auth.h b/arch/arm64/include/asm/asm_pointer_auth.h index 3b192e04a5dd..13ecc79854ee 100644 --- a/arch/arm64/include/asm/asm_pointer_auth.h +++ b/arch/arm64/include/asm/asm_pointer_auth.h @@ -61,7 +61,7 @@ alternative_else_nop_endif mrs \tmp1, id_aa64isar1_el1 ubfx \tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8 mrs_s \tmp2, SYS_ID_AA64ISAR2_EL1 - ubfx \tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4 + ubfx \tmp2, \tmp2, #ID_AA64ISAR2_EL1_APA3_SHIFT, #4 orr \tmp1, \tmp1, \tmp2 cbz \tmp1, .Lno_addr_auth\@ mov_q \tmp1, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \ diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 6472f2badc97..fe59035bdc22 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope) isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); return cpuid_feature_extract_unsigned_field(isar2, - ID_AA64ISAR2_BC_SHIFT); + ID_AA64ISAR2_EL1_BC_SHIFT); } const struct cpumask *system_32bit_el0_cpumask(void); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ba9053bc33c2..7f083a2ed7dc 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -738,29 +738,29 @@ #define ID_AA64ISAR1_EL1_GPI_IMP 0x1 /* id_aa64isar2 */ -#define ID_AA64ISAR2_BC_SHIFT 28 -#define ID_AA64ISAR2_APA3_SHIFT 12 -#define ID_AA64ISAR2_GPA3_SHIFT 8 -#define ID_AA64ISAR2_RPRES_SHIFT 4 -#define ID_AA64ISAR2_WFxT_SHIFT 0 +#define ID_AA64ISAR2_EL1_BC_SHIFT 28 +#define ID_AA64ISAR2_EL1_APA3_SHIFT 12 +#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 +#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 +#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 /* * Value 0x1 has been removed from the architecture, and is * reserved, but has not yet been removed from the ARM ARM * as of ARM DDI 0487G.b. */ -#define ID_AA64ISAR2_WFxT_NI 0x0 -#define ID_AA64ISAR2_WFxT_IMP 0x2 - -#define ID_AA64ISAR2_APA3_NI 0x0 -#define ID_AA64ISAR2_APA3_PAuth 0x1 -#define ID_AA64ISAR2_APA3_EPAC 0x2 -#define ID_AA64ISAR2_APA3_PAuth2 0x3 -#define ID_AA64ISAR2_APA3_FPAC 0x4 -#define ID_AA64ISAR2_APA3_FPACCOMBINE 0x5 - -#define ID_AA64ISAR2_GPA3_NI 0x0 -#define ID_AA64ISAR2_GPA3_IMP 0x1 +#define ID_AA64ISAR2_EL1_WFxT_NI 0x0 +#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2 + +#define ID_AA64ISAR2_EL1_APA3_NI 0x0 +#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1 +#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2 +#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3 +#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4 +#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5 + +#define ID_AA64ISAR2_EL1_GPA3_NI 0x0 +#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1 /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0d4f0120c516..be20100a7d4c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -231,13 +231,13 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_BC_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFxT_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2326,9 +2326,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_APA3_SHIFT, + .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_APA3_PAuth, + .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2364,9 +2364,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_GPA3_SHIFT, + .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_GPA3_IMP, + .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP, .matches = has_cpuid_feature, }, { @@ -2516,10 +2516,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_WFxT_SHIFT, + .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT, .field_width = 4, .matches = has_cpuid_feature, - .min_field_value = ID_AA64ISAR2_WFxT_IMP, + .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP, }, {}, }; @@ -2565,8 +2565,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { ID_AA64ISAR1_EL1_APA_PAuth) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, @@ -2581,8 +2581,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, @@ -2653,8 +2653,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #endif /* CONFIG_ARM64_MTE */ HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), - HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), - HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), #ifdef CONFIG_ARM64_SME HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index 652c19b13588..720a847f7dfe 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -75,8 +75,8 @@ static const struct ftr_set_desc isar2 __initconst = { .name = "id_aa64isar2", .override = &id_aa64isar2_override, .fields = { - { "gpa3", ID_AA64ISAR2_GPA3_SHIFT }, - { "apa3", ID_AA64ISAR2_APA3_SHIFT }, + { "gpa3", ID_AA64ISAR2_EL1_GPA3_SHIFT }, + { "apa3", ID_AA64ISAR2_EL1_APA3_SHIFT }, {} }, }; diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index 46cf9dec21ba..fa6e466ed57f 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -193,8 +193,8 @@ ) #define PVM_ID_AA64ISAR2_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) \ + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \ ) u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id); diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 5b77bc1cca0c..6b94c3e6ff26 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -186,8 +186,8 @@ static u64 get_pvm_id_aa64isar2(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR2_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); + allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); return id_aa64isar2_el1_sys_val & allow_mask; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index ccd973dc346a..c4fb3874b5e2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1143,10 +1143,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, break; case SYS_ID_AA64ISAR2_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); + val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); if (!cpus_have_final_cap(ARM64_HAS_WFXT)) - val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFxT); + val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); break; case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ From patchwork Wed Jun 22 17:44:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B873C433EF for ; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 16 ---------------- arch/arm64/tools/sysreg | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7f083a2ed7dc..a57b4a79a8e9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -461,7 +461,6 @@ #define SMIDR_EL1_SMPS_SHIFT 15 #define SMIDR_EL1_AFFINITY_SHIFT 0 -#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) @@ -1082,21 +1081,6 @@ #define MVFR2_FPMISC_SHIFT 4 #define MVFR2_SIMDMISC_SHIFT 0 -#define CTR_EL0_L1Ip_VPIPT 0 -#define CTR_EL0_L1Ip_VIPT 2 -#define CTR_EL0_L1Ip_PIPT 3 - -#define CTR_EL0_L1Ip_SHIFT 14 -#define CTR_EL0_L1Ip_MASK 3 -#define CTR_EL0_DminLine_SHIFT 16 -#define CTR_EL0_IminLine_SHIFT 0 -#define CTR_EL0_IminLine_MASK 0xf -#define CTR_EL0_ERG_SHIFT 20 -#define CTR_EL0_CWG_SHIFT 24 -#define CTR_EL0_CWG_MASK 15 -#define CTR_EL0_IDC_SHIFT 28 -#define CTR_EL0_DIC_SHIFT 29 - #define DCZID_EL0_DZP_SHIFT 4 #define DCZID_EL0_BS_SHIFT 0 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ff5e552f7420..a9f4c157c4be 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -273,6 +273,27 @@ Field 3:1 Level Field 0 InD EndSysreg +Sysreg CTR_EL0 3 3 0 0 1 +Res0 63:38 +Field 37:32 TminLine +Res1 31 +Res0 30 +Field 29 DIC +Field 28 IDC +Field 27:24 CWG +Field 23:20 ERG +Field 19:16 DminLine +Enum 15:14 L1Ip + 0b00 VPIPT + # This is named as AIVIVT in the ARM but documented as reserved + 0b01 RESERVED + 0b10 VIPT + 0b11 PIPT +EndEnum +Res0 13:4 +Field 3:0 IminLine +EndSysreg + Sysreg SVCR 3 3 4 2 2 Res0 63:2 Field 1 ZA From patchwork Wed Jun 22 17:44:06 2022 Content-Type: text/plain; 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Wed, 22 Jun 2022 17:53:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920398; bh=0r43Rd/5FEtAH6xPKSSvi30aspVPOQVMJBS/5uj8Mak=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JvvDxe0HOIY9NBEIHu0rpQ5FK/dxDVAMteQYIl/rGrVy2HTU5cr9F3NK2FpA0Orgg Xzdl4Dr86qcwk0Kp3OdcAvo//CLHjyNttKathWmuKaM6XVz6hFL7rDQAp2d2pkdM3C jR3lDBxsDl1uPLlINaDtLPtaDDlx6N0W5C0oy6X7bW0x8+xJKTP+EvEaWdjKmjXnBf J7bwJW1FILV4JOduuZXhFUvg4ihAwrGj+Kn7oy8ErZ2/ZdNC1uJ6FXlpv3wH2baW+D y5x10wQ6PJiC6aXcITc02PQVqDkeUt8ZGyNHTAWhwvBlHb6O/o+XT+wjK2xAR8YYx7 XCuE/gu6Zspzg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 17/27] arm64/sysreg: Convert DCZID_EL0 to automatic generation Date: Wed, 22 Jun 2022 18:44:06 +0100 Message-Id: <20220622174416.1406282-18-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 5 ----- arch/arm64/tools/sysreg | 6 ++++++ 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index a57b4a79a8e9..e71f85b57cdb 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -461,8 +461,6 @@ #define SMIDR_EL1_SMPS_SHIFT 15 #define SMIDR_EL1_AFFINITY_SHIFT 0 -#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) - #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) @@ -1081,9 +1079,6 @@ #define MVFR2_FPMISC_SHIFT 4 #define MVFR2_SIMDMISC_SHIFT 0 -#define DCZID_EL0_DZP_SHIFT 4 -#define DCZID_EL0_BS_SHIFT 0 - #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a9f4c157c4be..c286b62958ea 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -294,6 +294,12 @@ Res0 13:4 Field 3:0 IminLine EndSysreg +Sysreg DCZID_EL0 3 3 0 0 7 +Res0 63:5 +Field 4 DZP +Field 3:0 BS +EndSysreg + Sysreg SVCR 3 3 4 2 2 Res0 63:2 Field 1 ZA From patchwork Wed Jun 22 17:44:07 2022 Content-Type: text/plain; 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Wed, 22 Jun 2022 17:53:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920400; bh=K2cD99EHEwcSbsVuDgG+XiRoHI9IsrwSrNaRTXZhWUs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BqzIHnrLQJZv5iwhHhbK8OHb1rUw+yIiOQbd9bCZx21sNZr12d/GwQ2CHIbKbyq10 6YRcWXQZ+14B8FI64xi4ytrCZ4gpIEruTIQF0lQcoSm6+qBc5axhcaAT7Idh2rowqy jomMSmvEGdjtBimMG1tKVItoSjj3BAepBTxhspo2PkOtFCLpNvTxbN9BaxaJQgaGqP Fkf0d5Ll8/Pq7dMTXqoa+YKsiUoh3t6zxfPLWjin4GWf9Vx2PylFZGSJhzkIb90VDl zWpXbjTfQhawdwAUxFZdQQ8JKBdG+d5JFgKHMswrpFO207EmIpVAqLDcKGD8uMbp2v 45qYZXtbWrCTg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 18/27] arm64/sysreg: Convert GMID to automatic generation Date: Wed, 22 Jun 2022 18:44:07 +0100 Message-Id: <20220622174416.1406282-19-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1147; h=from:subject; bh=K2cD99EHEwcSbsVuDgG+XiRoHI9IsrwSrNaRTXZhWUs=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1TnL+nI9IMCM5pjgIPMkjiTQ1/7ySrltNi8ZWPh BdPM3huJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU5wAKCRAk1otyXVSH0OpWB/ 9XxX49t5d3WRx8S0VirHjWlGP5xSs3xun/7T/PC5JexAJss9uDMP2JZQDhzGUl1ZmYTeyd9mHXFYwr VUJgFBDc791ska6tOwDSAJM/9bzb0fHrAQ0gLPdcS34+H46a9JlquuyTJ9CllxPQQlagJIg4aRzztR nZbSoAo0gIBKBVHvymHKj8Egrj3+EBd1jfFF0Uq9wYR3EdCeX+/TLxF93Vu39f5WBnDng/BPn3dZ3e 3/qa+Y8Z2VhCsEio071v0z1M7i/7Gclr66jMj4p4yZxtYQ5z1Zmtqp8Cr0F1a8hLykxg1S7qY2yvAR fJz7yKCB2jbOi3eUSOB9dVaalhuVwe X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105321_476633_80F321B4 X-CRM114-Status: GOOD ( 11.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Automatically generate the register definitions for GMID as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e71f85b57cdb..a7ebfa17893a 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -454,7 +454,6 @@ #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) -#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4) #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) #define SMIDR_EL1_IMPLEMENTER_SHIFT 24 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c286b62958ea..ea3520a347b1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -257,6 +257,11 @@ Field 5:3 Ctype2 Field 2:0 Ctype1 EndSysreg +Sysreg GMID_EL1 3 1 0 0 4 +Res0 63:4 +Field 3:0 BS +EndSysreg + Sysreg SMIDR_EL1 3 1 0 0 6 Res0 63:32 Field 31:24 IMPLEMENTER From patchwork Wed Jun 22 17:44:08 2022 Content-Type: text/plain; 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Wed, 22 Jun 2022 17:53:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920402; bh=K28erd6/ibXgPkR1G1qy+SGGzB3enMJXf5uKLfCU3GQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=okluaTanUmNPSgwGMqnCcbz+v7NkI5dD7IsG66krJytXhM4hlQaqhy87E2GOYRIuC EnuKjU5lUVOFALp/V3VMyvlAtFvygR1DKLYgrkxBFDc0lda1NcoOdD6aK9xmvAUk0e Qg+9qoE63kywf3h3YtX06Zf6u78e8Qp1YKwxmn1VEHZ0TeznQSNLD9VNTcW+SO4H0s Gmg3gup6U7XEoJbE4QsrOFCvnJatL9wx4M7t+OK4hMN2dstexF6oAqWT+xNkesfBbH eBxPjcuCc2cYGe5CXoU7g235D1hrtBKisr1zdoSKi9NvhcyILfasl5M+ag2tF2/WNL Uw/3fFv6SUwCg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 19/27] arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation Date: Wed, 22 Jun 2022 18:44:08 +0100 Message-Id: <20220622174416.1406282-20-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3863; h=from:subject; bh=K28erd6/ibXgPkR1G1qy+SGGzB3enMJXf5uKLfCU3GQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1ToYLw+F8lknKCFqAIA19UpucqEbxpNybd46UAl tjV/xYGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU6AAKCRAk1otyXVSH0E2vB/ 9TZPtmSUCfFYnIHwQHlzPnQGLbTzawYGEseapITMyROjAvgBotGvixY5r8km8OOl/rxgosoEIKLnUL gau69MLAURrD+EdQwhya7QsPVW2DyxJqs32iAWoN0TyVY2U8q9QxPGKf4ck0+ILNYxzvJ6DFGfECuZ IFXKg5u2LJaU0aUpSq0B48itA45O18NyWP4QnCVr7wEPZb4GrKyU963GuxiWDF3fY2E/ypzRdNjdUi tOAd+WPIXI1I09fMTnlm+Q1N8NKMGX1i7y1+66x0Uq+jVy0sOmCsIX7OZFV+h4rc1E0jHQrafLuElz JRMY9HQG5R5uTEoLskGZ/yrFc92xdD X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105323_366403_2E8F2690 X-CRM114-Status: GOOD ( 11.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 34 -------------- arch/arm64/tools/sysreg | 83 +++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+), 34 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index a7ebfa17893a..089e2da3a5a9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -201,7 +201,6 @@ #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) -#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) #define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) @@ -700,39 +699,6 @@ /* Position the attr at the correct index */ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) -/* id_aa64isar1 */ -#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52 -#define ID_AA64ISAR1_EL1_DGH_SHIFT 48 -#define ID_AA64ISAR1_EL1_BF16_SHIFT 44 -#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 -#define ID_AA64ISAR1_EL1_SB_SHIFT 36 -#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 -#define ID_AA64ISAR1_EL1_GPI_SHIFT 28 -#define ID_AA64ISAR1_EL1_GPA_SHIFT 24 -#define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20 -#define ID_AA64ISAR1_EL1_FCMA_SHIFT 16 -#define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12 -#define ID_AA64ISAR1_EL1_API_SHIFT 8 -#define ID_AA64ISAR1_EL1_APA_SHIFT 5 -#define ID_AA64ISAR1_EL1_DPB_SHIFT 0 - -#define ID_AA64ISAR1_EL1_APA_NI 0x0 -#define ID_AA64ISAR1_EL1_APA_PAuth 0x1 -#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC 0x2 -#define ID_AA64ISAR1_EL1_APA_Pauth2 0x3 -#define ID_AA64ISAR1_EL1_APA_FPAC 0x4 -#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_EL1_API_NI 0x0 -#define ID_AA64ISAR1_EL1_API_PAuth 0x1 -#define ID_AA64ISAR1_EL1_API_EPAC 0x2 -#define ID_AA64ISAR1_EL1_API_PAuth2 0x3 -#define ID_AA64ISAR1_EL1_API_FPAC 0x4 -#define ID_AA64ISAR1_EL1_API_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_EL1_GPA_NI 0x0 -#define ID_AA64ISAR1_EL1_GPA_IMP 0x1 -#define ID_AA64ISAR1_EL1_GPI_NI 0x0 -#define ID_AA64ISAR1_EL1_GPI_IMP 0x1 - /* id_aa64isar2 */ #define ID_AA64ISAR2_EL1_BC_SHIFT 28 #define ID_AA64ISAR2_EL1_APA3_SHIFT 12 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ea3520a347b1..164221177079 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -114,6 +114,89 @@ EndEnum Res0 3:0 EndSysreg +Sysreg ID_AA64ISAR1_EL1 3 0 0 6 1 +Enum 63:60 LS64 + 0b0000 NI + 0b0001 LS64 + 0b0010 LS64_V + 0b0011 LS64_ACCDATA +EndEnum +Enum 59:56 XS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 55:52 I8MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 51:48 DGH + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 47:44 BF16 + 0b0000 NI + 0b0001 IMP + 0b0010 EBF16 +EndEnum +Enum 43:40 SPECRES + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 39:36 SB + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 35:32 FRINTTS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 31:28 GPI + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 27:24 GPA + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 LRCPC + 0b0000 NI + 0b0001 IMP + 0b0010 LRCPC2 +EndEnum +Enum 19:16 FCMA + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 JSCVT + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 API + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 7:4 APA + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 3:0 DPB + 0b0000 NI + 0b0001 IMP + 0b0010 DPB2 +EndEnum +EndSysreg + 0b0001 IMP +EndEnum +EndSysreg + Sysreg SCTLR_EL1 3 0 1 0 0 Field 63 TIDCP Field 62 SPINMASK From patchwork Wed Jun 22 17:44:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28C35C433EF for ; Wed, 22 Jun 2022 18:02:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2ORFdndu96Zotq0qrSOcLhSfkanEwnz2JLQQUm1B8Qk=; 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Wed, 22 Jun 2022 17:53:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920404; bh=uabqLngD3iBCdB3UQqaMZK85Fd8b2Tmx2mJoZgxUEcY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q4HYV1vddWWnnCbjvUXWa6QAR66+H3s6jtB78oDJCwI4k6dKEz83HwNm7Mv1cM/CN kp9avkDrH62FGkg30oQHAqCpjeSPN0AMEIJfhld/PGfnCex3Whk0koXzbhnnk7L4z6 YAsPmiRQe0F0NKM5PqFajvVvcfQORCpHwLMs1hryRwRb3A3YKpkfrmaqloVqhdbF3j LX4hnJNodd5d0W1cZbytvsbgJOO6eJwMyttRaxM6we+JBNqUYgCVuvT+Zla+IoBUVX Vd6Bu1pyznOtlpOisi/UDk6sSpSLeM2YHGB3l3+6+BtYC9z2Zt/Nh1DVKeJMSXsGk+ HJ94TA+55wJsw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 20/27] arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation Date: Wed, 22 Jun 2022 18:44:09 +0100 Message-Id: <20220622174416.1406282-21-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2775; h=from:subject; bh=uabqLngD3iBCdB3UQqaMZK85Fd8b2Tmx2mJoZgxUEcY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1TpBCxmGfRMAffOkzp4vcn6SHFj/xBam3TkKi8j 7IZWjsSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU6QAKCRAk1otyXVSH0O8fB/ 0UdePf3s43+X2i8eWNDSZFC+igJUqZAkyTslsRAFWu2RK0IOAG8Mb1FOVgGUqAPu4vLDh3DAhCRb5t WIobo9fjrmn1qeogtvsg4f12GoFcS5SgSrkTypVYAe3i18T+T8hfxYgupLoO/xAP3kv5DfUZOYQErb D8cmA2TFLKd88MgaY9ul9mwZWdxmVOWm8m9ArDb5YW7Euy20Md375u94poTUMWUcFMNVrbIzvHj3mf hQjnU96zoH/L60MfwT2w2MevEmQD3uTFzJj+TyyndSWE9UhHSsAsykhsG0MGpN/bzdnra7Yy5ZYVkf 2OARFMHVZ5qxiKiaeI+FLejP4EB2yx X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105327_116266_4C753C21 X-CRM114-Status: GOOD ( 14.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 27 --------------------------- arch/arm64/tools/sysreg | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 27 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 089e2da3a5a9..a8d882b8e2a2 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -201,8 +201,6 @@ #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) -#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) - #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) @@ -699,31 +697,6 @@ /* Position the attr at the correct index */ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) -/* id_aa64isar2 */ -#define ID_AA64ISAR2_EL1_BC_SHIFT 28 -#define ID_AA64ISAR2_EL1_APA3_SHIFT 12 -#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 -#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 -#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 - -/* - * Value 0x1 has been removed from the architecture, and is - * reserved, but has not yet been removed from the ARM ARM - * as of ARM DDI 0487G.b. - */ -#define ID_AA64ISAR2_EL1_WFxT_NI 0x0 -#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2 - -#define ID_AA64ISAR2_EL1_APA3_NI 0x0 -#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1 -#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2 -#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3 -#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4 -#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5 - -#define ID_AA64ISAR2_EL1_GPA3_NI 0x0 -#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1 - /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 164221177079..da5e925bf624 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -193,8 +193,41 @@ Enum 3:0 DPB 0b0010 DPB2 EndEnum EndSysreg + +Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2 +Res0 63:28 +Enum 27:24 PAC_frac + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 BC + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 19:16 MOPS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 APA3 + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 11:8 GPA3 + 0b0000 NI 0b0001 IMP EndEnum +Enum 7:4 RPRES + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 WFxT + 0b0000 NI + 0b0010 IMP +EndEnum EndSysreg Sysreg SCTLR_EL1 3 0 1 0 0 From patchwork Wed Jun 22 17:44:10 2022 Content-Type: text/plain; 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Wed, 22 Jun 2022 17:53:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920405; bh=nQoKO0wTwFe5zrPuIitqD975L2JBhy6meBpONgILnP4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y4diu2+lgm79rvgO+zOiDJaezTvPqW1BAs98mgyRU4Xmc6kwqKfOhF3Azd+RrtAIo K7Y59Q9nSJANmsz0lPzt1DbPpNrLd1rl/eu3qlGL/BBQCXWvEuPyjMwMdfszZNLmw/ b/pKJQcjS7CcHmsD8yEEZtkEj9FDh2cODQB4nDCb2cXhKPFPjHpTDjR3EUxQYDu6VD 6e2BNDLkzgfHF1nN8t8YLykIep+it0AhAVhiLAR5WgFztBeerlxb2qFKi8QFI4lPFq moovFuRYFvBxsV+mBSbdTpK11vUumi9yJnYRE9SWffL+0Mqu/PZWxQprW7w0arEVcG 4ZKsaisV/MPBg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 21/27] arm64/sysreg: Convert LORSA_EL1 to automatic generation Date: Wed, 22 Jun 2022 18:44:10 +0100 Message-Id: <20220622174416.1406282-22-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 8 ++++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index a8d882b8e2a2..050e9bfb2250 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index da5e925bf624..c1e3a9ceb049 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -515,3 +515,11 @@ EndSysreg Sysreg TTBR1_EL1 3 0 2 0 1 Fields TTBRx_EL1 EndSysreg + +Sysreg LORSA_EL1 3 0 10 4 0 +Res0 63:52 +Field 51:16 SA +Res0 15:1 +Field 0 Valid +EndSysreg + From patchwork Wed Jun 22 17:44:11 2022 Content-Type: text/plain; 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Wed, 22 Jun 2022 17:53:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920407; bh=Gut8jY9ram9lEzLIk/NSZLgLxlEjsqZMDu5ohUenMiE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fP1O5ex+77b9Aj7zBz13uQXBLljJqEcTuSBbB7xfb4bqLo8R4JtWkG7yqFW39Qnbn yl0vk9zhuCvaHG//94H6+CxgSir4ahMm1WSM+xvCw8t83ctejCrZA3J1yrcOKaKyYP FFZzhRKS0ZIA8aVvVv3kTy3YcDpbVk9vALmLulJnql2BgoheeQOLpicIT7O/zMD1yd ijfPkh/4igXf9lOA29MzaBKD3AeRK43104tTXc1GTbLS1bzC+Azm8EjZmttWPIREqN Y5iI5CeHVJiqlM67TTtxFmrL3oanBt1VHtzjTtA0Vt9PtmsjJWKlz4zRc8TOlISYjg pngfwEQ5WRN+g== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 22/27] arm64/sysreg: Convert LOREA_EL1 to automatic generation Date: Wed, 22 Jun 2022 18:44:11 +0100 Message-Id: <20220622174416.1406282-23-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 6 ++++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 050e9bfb2250..19d29b02b6b7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c1e3a9ceb049..4c23c65e53d1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -523,3 +523,9 @@ Res0 15:1 Field 0 Valid EndSysreg +Sysreg LOREA_EL1 3 0 10 4 1 +Res0 63:52 +Field 51:48 EA_51_48 +Field 47:16 EA_47_16 +Res0 15:0 +EndSysreg From patchwork Wed Jun 22 17:44:12 2022 Content-Type: text/plain; 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Wed, 22 Jun 2022 17:53:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920409; bh=wc+5Of+rgAB5VBgzMyV6K37QSqToFsZOpIKPy+Fmy4E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E5cgiE+SLnqFeaZKbQ0+kJu+oDYfnV4k1iaj+6GTS16ktdNJqeNElM7p7a2z42mMw GO4F6EkdJ74aS6Mo3LG/ykAnrOm0478aBGhs9ynFfemOmB/rK1UcJCsNUnIImA3bCe 0RppIgKetYf6pClm/5KnJ+sMANN48WQjbnumbRq3irkrP8mkoR9Zj64kNeaBvU9IDs O8tSISUeJNUBvLk0j8zLaZ/KO7nynQp9PW7loFMeL2UCAo6w7kOGvedo9o04b0ZxLi 7hmoIIN5ZOcJ8jOISc39ABsixIGqwH/TiVq982Jvk02OrJanEGNFhU2paBohFJs2wL qzCD/Yxm0gQ2w== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 23/27] arm64/sysreg: Convert LORN_EL1 to automatic generation Date: Wed, 22 Jun 2022 18:44:12 +0100 Message-Id: <20220622174416.1406282-24-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 19d29b02b6b7..2d844cdbe52c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4c23c65e53d1..ec84a76fe66e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -529,3 +529,8 @@ Field 51:48 EA_51_48 Field 47:16 EA_47_16 Res0 15:0 EndSysreg + +Sysreg LORN_EL1 3 0 10 4 2 +Res0 63:8 +Field 7:0 Num +EndSysreg From patchwork Wed Jun 22 17:44:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D023C433EF for ; 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Wed, 22 Jun 2022 18:02:43 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o44Xm-00Blkm-1Y for linux-arm-kernel@lists.infradead.org; Wed, 22 Jun 2022 17:53:35 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id AE9F1B82073; Wed, 22 Jun 2022 17:53:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 01197C3411D; Wed, 22 Jun 2022 17:53:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920411; bh=6rBL5xPbXkSPt3BsYvlXPfVjEm34vulwqXmbEtanudU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OQSh/5BZ2lnBKPoaLpRWFV9ZAcwTWEESKvPnhm3vO2z5E6eIs2wCcSiRh58YCF4Wv jpXjsujI69fv8bu+4kBmgFwzB4VUCkW45ruP/SLqXVWx0Ac0TaBZBFg2eF0ZP4cJb8 gwI/61Hm4N6bxtDVZiuc6CKW02e5quKqRkG3aYpBRxzFazQeS3bmd6Qyh25GaSrEwb /3vE6OYCMND+J3gDTh4m3SoQhJ+E5oG4ue4/YrPoJXbvsHcgSpQwMW46d+JLYam+8o Bg0JDM1zpZnN1qQPkGsOVfkYypl6lTZRWGUG7Pn2kspeeF8NQBXrb9cPJPLRo2A1Oe wpfixA7ztpw7g== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 24/27] arm64/sysreg: Convert LORC_EL1 to automatic generation Date: Wed, 22 Jun 2022 18:44:13 +0100 Message-Id: <20220622174416.1406282-25-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2d844cdbe52c..4b393913be40 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ec84a76fe66e..95fcad79b917 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -534,3 +534,10 @@ Sysreg LORN_EL1 3 0 10 4 2 Res0 63:8 Field 7:0 Num EndSysreg + +Sysreg LORC_EL1 3 0 10 4 3 +Res0 63:10 +Field 9:2 DS +Res0 1 +Field 0 EN +EndSysreg From patchwork Wed Jun 22 17:44:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D4B9C433EF for ; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 2 -- arch/arm64/tools/sysreg | 7 +++++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 4b393913be40..6be54e9bdfaf 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,8 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) - #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 95fcad79b917..13b8f85682af 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -541,3 +541,10 @@ Field 9:2 DS Res0 1 Field 0 EN EndSysreg + +Sysreg LORID_EL1 3 0 10 4 7 +Res0 63:24 +Field 23:16 LD +Res0 15:8 +Field 7:0 LR +EndSysreg From patchwork Wed Jun 22 17:44:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12891273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AAC5FC433EF for ; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 18 ---------------- arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 18 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6be54e9bdfaf..6496550ec0c0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -193,7 +193,6 @@ #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) -#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) @@ -760,23 +759,6 @@ #define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 #define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 -/* id_aa64smfr0 */ -#define ID_AA64SMFR0_EL1_FA64_SHIFT 63 -#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52 -#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48 -#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36 -#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35 -#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34 -#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32 - -#define ID_AA64SMFR0_EL1_FA64_IMP 0x1 -#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf -#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1 -#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf -#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1 -#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1 -#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 #define ID_AA64MMFR0_FGT_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 13b8f85682af..b5c4251c6796 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -46,6 +46,43 @@ # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration # item ACCDATA) though it may be more taseful to do something else. +Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5 +Enum 63 FA64 + 0b0 NI + 0b1 IMP +EndEnum +Res0 62:60 +Field 59:56 SMEver +Enum 55:52 I16I64 + 0b0000 NI + 0b1111 IMP +EndEnum +Res0 51:49 +Enum 48 F64F64 + 0b0 NI + 0b1 IMP +EndEnum +Res0 47:40 +Enum 39:36 I8I32 + 0b0000 NI + 0b1111 IMP +EndEnum +Enum 35 F16F32 + 0b0 NI + 0b1 IMP +EndEnum +Enum 34 B16F32 + 0b0 NI + 0b1 IMP +EndEnum +Res0 33 +Enum 32 F32F32 + 0b0 NI + 0b1 IMP +EndEnum +Res0 31:0 +EndSysreg + Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0 Enum 63:60 RNDR 0b0000 NI From patchwork Wed Jun 22 17:44:16 2022 Content-Type: text/plain; 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Wed, 22 Jun 2022 17:53:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655920416; bh=bxzFQ9Ff7aTbDFTL8+R3cy/4LEkQfh/s3oL8F415Uik=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SdNIBIDyoq9xLHE1/DNK6wH5W5mMzdQnQlEKYDLF+8LH2wPg1YAhDjVL1bm0O1FK0 KY+6j717l+zZsSEqBSu497paJaU/wXfh80hFmO48aotsxCwQ4Jmu5TvNfNvbkt+5bb vCa9/XfOXWEdI2Pu6ls4ExZhQhdJqaMW05yWeW2QlKS1hw1UShsVXkOHHDOt5HTiiR mNmM5FAHCTvl01B1YIX7F5LYHpKjaM3s0w4kTnYrlxTgh9pvc0GQkQ0ZzofrvHcpHc mL3YU9pu4LXwlc+88vILQCbn6/FUK79CPxLNXLPfXx9g7PzHN8p/LSawwKl5HK+pzR 81GV0hxRS55+g== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v5 27/27] arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation Date: Wed, 22 Jun 2022 18:44:16 +0100 Message-Id: <20220622174416.1406282-28-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220622174416.1406282-1-broonie@kernel.org> References: <20220622174416.1406282-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2877; h=from:subject; bh=bxzFQ9Ff7aTbDFTL8+R3cy/4LEkQfh/s3oL8F415Uik=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBis1Tu7LtxaoHTl2mRgOlgFGHRUEx94GcZkk8GDNS/ 4aZjpF2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYrNU7gAKCRAk1otyXVSH0K0iB/ 97CGIAnQ+mjwfb0KaTr/N3nSsyYUGXWXz0gVgY6GV0xSP3hmtAT2cLfZPcgNBobGywm/qzbGvppylC owtv5A+vjLAr+z3xyXkyg6N8ZWSGlDfcc5p6hL+ORfQZTX3WoS2Z5bwGwIIYCO8w/Ip/nbZP8g7823 3HhK4MAWA7anTaC+9wuDOXXSjFgnGbHFAb9yheCqIdL9OpYTB7o+JPxawu1jzecBKsJ1oYFrTnjpmt OI7pLEHXee1tS+gUQSfXzvm4pEP97rVg/GpGKDVdcltt9RdfRd5fI1Ih4tcp0IZlLQsEsVK2HA7/wc ldrSMH7VVp1iXDJIwto+KZ9oSYDv9v X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220622_105340_013793_2F9F0771 X-CRM114-Status: GOOD ( 11.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 23 ----------------- arch/arm64/tools/sysreg | 46 +++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 23 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6496550ec0c0..b7503b9782d0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -192,7 +192,6 @@ #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) -#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) @@ -737,28 +736,6 @@ #define ID_AA64PFR1_MTE 0x2 #define ID_AA64PFR1_MTE_ASYMM 0x3 -/* id_aa64zfr0 */ -#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56 -#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52 -#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44 -#define ID_AA64ZFR0_EL1_SM4_SHIFT 40 -#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32 -#define ID_AA64ZFR0_EL1_BF16_SHIFT 20 -#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16 -#define ID_AA64ZFR0_EL1_AES_SHIFT 4 -#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0 - -#define ID_AA64ZFR0_EL1_F64MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_F32MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_I8MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_BF16_IMP 0x1 -#define ID_AA64ZFR0_EL1_SM4_IMP 0x1 -#define ID_AA64ZFR0_EL1_SHA3_IMP 0x1 -#define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1 -#define ID_AA64ZFR0_EL1_AES_IMP 0x1 -#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 -#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 #define ID_AA64MMFR0_FGT_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b5c4251c6796..9ae483ec1e56 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -46,6 +46,52 @@ # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration # item ACCDATA) though it may be more taseful to do something else. +Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4 +Res0 63:60 +Enum 59:56 F64MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 55:52 F32MM + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 51:48 +Enum 47:44 I8MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 43:40 SM4 + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 39:36 +Enum 35:32 SHA3 + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 31:24 +Enum 23:20 BF16 + 0b0000 NI + 0b0001 IMP + 0b0010 EBF16 +EndEnum +Enum 19:16 BitPerm + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 15:8 +Enum 7:4 AES + 0b0000 NI + 0b0001 IMP + 0b0010 PMULL128 +EndEnum +Enum 3:0 SVEver + 0b0000 IMP + 0b0001 SVE2 +EndEnum +EndSysreg + Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5 Enum 63 FA64 0b0 NI