From patchwork Fri Jun 24 07:28:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12894038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76286CCA473 for ; Fri, 24 Jun 2022 07:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230523AbiFXH2e (ORCPT ); Fri, 24 Jun 2022 03:28:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230475AbiFXH2a (ORCPT ); Fri, 24 Jun 2022 03:28:30 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32DD93B3C1; Fri, 24 Jun 2022 00:28:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656055709; x=1687591709; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=pD5T2GHRDXOmK7blcqnSVtVWdsWp0Al8SFNHo9/sv08=; b=hcRNYYEttKsvR4QI10/jCFHfH0TDuUFdi66+IGHnjHt9Ay5Xq4/LpFYD UTgkolN4txogCd7R5VwkiwhZhgdoUiiYdHMKTodNeTI45W3EqxO63VmON Z620RhmcIjPub3eJ89EroEg372NQm/xIebr9xD0LpQXj1zgM5kPU3zyxA M=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 24 Jun 2022 00:28:29 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 24 Jun 2022 00:28:27 -0700 X-QCInternal: smtphost Received: from hu-krichai-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.110.37]) by ironmsg02-blr.qualcomm.com with ESMTP; 24 Jun 2022 12:58:07 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 266D73CFB; Fri, 24 Jun 2022 12:58:06 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, Krishna chaitanya chundru , Andy Gross , Bjorn Andersson , Stanimir Varbanov , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas Subject: [PATCH v1 1/2] PCI: qcom: Add system PM support Date: Fri, 24 Jun 2022 12:58:01 +0530 Message-Id: <1656055682-18817-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656055682-18817-1-git-send-email-quic_krichai@quicinc.com> References: <1656055682-18817-1-git-send-email-quic_krichai@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add suspend and resume pm callbacks. When system suspends, and if the link is in L1ss, disable the clocks so that system enters into low power state to save the maximum power. And when the system resumes, enable the clocks back if they are disabled in the suspend path. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 6ab9089..b3029ca 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -41,6 +41,9 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) +#define PCIE20_PARF_PM_STTS 0x24 +#define PCIE20_PARF_PM_STTS_LINKST_IN_L1SUB BIT(8) + #define PCIE20_PARF_PHY_CTRL 0x40 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) @@ -190,6 +193,8 @@ struct qcom_pcie_ops { void (*post_deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); + int (*enable_clks)(struct qcom_pcie *pcie); + int (*disable_clks)(struct qcom_pcie *pcie); }; struct qcom_pcie_cfg { @@ -199,6 +204,8 @@ struct qcom_pcie_cfg { unsigned int has_ddrss_sf_tbu_clk:1; unsigned int has_aggre0_clk:1; unsigned int has_aggre1_clk:1; + unsigned int support_pm_ops:1; + unsigned int is_suspended:1; }; struct qcom_pcie { @@ -1308,6 +1315,23 @@ static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) clk_disable_unprepare(res->pipe_clk); } +static int qcom_pcie_enable_clks_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + + return clk_bulk_prepare_enable(res->num_clks, res->clks); +} + +static int qcom_pcie_disable_clks_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + + clk_bulk_disable_unprepare(res->num_clks, res->clks); + + return 0; +} + + static int qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -1485,6 +1509,8 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .post_init = qcom_pcie_post_init_2_7_0, .post_deinit = qcom_pcie_post_deinit_2_7_0, + .enable_clks = qcom_pcie_enable_clks_2_7_0, + .disable_clks = qcom_pcie_disable_clks_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1548,6 +1574,7 @@ static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, .has_tbu_clk = true, .pipe_clk_need_muxing = true, + .support_pm_ops = true, }; static const struct dw_pcie_ops dw_pcie_ops = { @@ -1591,6 +1618,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) pcie->cfg = pcie_cfg; + pcie->cfg->is_suspended = false; + pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); if (IS_ERR(pcie->reset)) { ret = PTR_ERR(pcie->reset); @@ -1645,6 +1674,56 @@ static int qcom_pcie_probe(struct platform_device *pdev) return ret; } +static int __maybe_unused qcom_pcie_pm_suspend(struct device *dev) +{ + struct qcom_pcie *pcie = dev_get_drvdata(dev); + + if (!pcie->cfg->support_pm_ops) + return 0; + + /* if the link is not in l1ss don't turn off clocks */ + val = readl(pcie->parf + PCIE20_PARF_PM_STTS); + if (!(val & PCIE20_PARF_PM_STTS_LINKST_IN_L1SUB)) { + dev_err(dev, "Link is not in L1ss\n"); + return 0; + } + + if (pcie->cfg->ops->disable_clks) + pcie->cfg->ops->disable_clks(pcie); + + if (pcie->cfg->ops->post_deinit) + pcie->cfg->ops->post_deinit(pcie); + + pcie->cfg->is_suspended = true; + + return 0; +} + +static int __maybe_unused qcom_pcie_pm_resume(struct device *dev) +{ + struct qcom_pcie *pcie = dev_get_drvdata(dev); + + if (!pcie->cfg->support_pm_ops) + return 0; + + if (!pcie->cfg->is_suspended) + return 0; + + if (pcie->cfg->ops->enable_clks) + pcie->ops->enable_clks(pcie); + + if (pcie->cfg->ops->post_init) + pcie->ops->post_init(pcie); + + pcie->cfg->is_suspended = false; + + return 0; +} + +static const struct dev_pm_ops qcom_pcie_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_pm_suspend, qcom_pcie_pm_resume) +}; + static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg }, { .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg }, @@ -1679,6 +1758,7 @@ static struct platform_driver qcom_pcie_driver = { .probe = qcom_pcie_probe, .driver = { .name = "qcom-pcie", + .pm = &qcom_pcie_pm_ops, .suppress_bind_attrs = true, .of_match_table = qcom_pcie_match, }, From patchwork Fri Jun 24 07:28:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12894037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10CCFC43334 for ; Fri, 24 Jun 2022 07:28:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230477AbiFXH2a (ORCPT ); Fri, 24 Jun 2022 03:28:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230404AbiFXH23 (ORCPT ); Fri, 24 Jun 2022 03:28:29 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45E8527FCE; Fri, 24 Jun 2022 00:28:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656055708; x=1687591708; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=8jsU1rwYjx0ZdhewYCgxwzh1sgTDUCTIf+ExHA3Cyg0=; b=Y+UB+f/dGJ8cTYNdJWE+5HcJqR25k9qzFRCSQ8FrH4PAloapi7887NkU ARu/JOsBv5Q3DPPG5bJQU/L5UTgoLLcDC004cTzYBVA42eMk2IBM91orI yrfCdQEtqWTAvRzZ+dKLaM8HfD77WTU6pZRwqDi9pEchlXjwWQ3QDWXry 8=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 24 Jun 2022 00:28:27 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 24 Jun 2022 00:28:25 -0700 X-QCInternal: smtphost Received: from hu-krichai-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.110.37]) by ironmsg02-blr.qualcomm.com with ESMTP; 24 Jun 2022 12:58:07 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 655003D33; Fri, 24 Jun 2022 12:58:06 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, Krishna chaitanya chundru , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Andy Gross , Bjorn Andersson , Stanimir Varbanov Subject: [PATCH v1 2/2] PCI: qcom: Restrict pci transactions after pci suspend Date: Fri, 24 Jun 2022 12:58:02 +0530 Message-Id: <1656055682-18817-3-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656055682-18817-1-git-send-email-quic_krichai@quicinc.com> References: <1656055682-18817-1-git-send-email-quic_krichai@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If the endpoint device state is D0 and irq's are not freed, then kernel try to mask interrupts by writing in to the vector table (for MSIX interrupts) and config space (for MSI's). These transactions are initiated after clocks are getting disabled as part of PM suspend call. Due to it, these transactions are resulting in un-clocked access and eventual to crashes. So added a logic in qcom driver to restrict the unclocked access. And updated the logic to check the link state before masking or unmasking the interrupts. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 12 ++++++-- drivers/pci/controller/dwc/pcie-qcom.c | 35 +++++++++++++++++++++-- 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2fa86f3..52ed865 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -29,13 +29,21 @@ static void dw_msi_ack_irq(struct irq_data *d) static void dw_msi_mask_irq(struct irq_data *d) { - pci_msi_mask_irq(d); + struct pcie_port *pp = irq_data_get_irq_chip_data(d->parent_data); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + if (dw_pcie_link_up(pci)) + pci_msi_mask_irq(d); irq_chip_mask_parent(d); } static void dw_msi_unmask_irq(struct irq_data *d) { - pci_msi_unmask_irq(d); + struct pcie_port *pp = irq_data_get_irq_chip_data(d->parent_data); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + if (dw_pcie_link_up(pci)) + pci_msi_unmask_irq(d); irq_chip_unmask_parent(d); } diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index b3029ca..af05fa7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1331,12 +1331,41 @@ static int qcom_pcie_disable_clks_2_7_0(struct qcom_pcie *pcie) return 0; } +static u32 qcom_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + u32 val; + + if (pcie->cfg->is_suspended) + return PCIBIOS_BAD_REGISTER_NUMBER; + + dw_pcie_read(base + reg, size, &val); + return val; +} + +static void qcom_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + + if (pcie->cfg->is_suspended) + return; + + dw_pcie_write(base + reg, size, val); +} static int qcom_pcie_link_up(struct dw_pcie *pci) { - u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + struct qcom_pcie *pcie = to_qcom_pcie(pci); + u16 offset; + u16 val; + + if (pcie->cfg->is_suspended) + return false; + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); return !!(val & PCI_EXP_LNKSTA_DLLLA); } @@ -1580,6 +1609,8 @@ static const struct qcom_pcie_cfg sc7280_cfg = { static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, + .read_dbi = qcom_pcie_read_dbi, + .write_dbi = qcom_pcie_write_dbi, }; static int qcom_pcie_probe(struct platform_device *pdev)