From patchwork Mon Jun 27 12:24:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82AD7CCA473 for ; Mon, 27 Jun 2022 12:24:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240508AbiF0MYb (ORCPT ); Mon, 27 Jun 2022 08:24:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233475AbiF0MYb (ORCPT ); Mon, 27 Jun 2022 08:24:31 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C0FBDBCA7; Mon, 27 Jun 2022 05:24:29 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="125807832" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:28 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7A1514290415; Mon, 27 Jun 2022 21:24:28 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 01/13] PCI: Add PCI_EXP_LNKCAP_MLW macros Date: Mon, 27 Jun 2022 21:24:05 +0900 Message-Id: <20220627122417.809615-2-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add macros defining Maximum Link Width bits in Link Capabilities Register. Signed-off-by: Yoshihiro Shimoda --- include/uapi/linux/pci_regs.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 108f8523fa04..c619b108df06 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -538,6 +538,13 @@ #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */ +#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */ +#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */ +#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */ +#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */ +#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */ +#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */ +#define PCI_EXP_LNKCAP_MLW_X32 0x00000200 /* Maximum Link Width x32 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */ From patchwork Mon Jun 27 12:24:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F76DC43334 for ; Mon, 27 Jun 2022 12:24:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233475AbiF0MYd (ORCPT ); Mon, 27 Jun 2022 08:24:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240523AbiF0MYb (ORCPT ); Mon, 27 Jun 2022 08:24:31 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 29B819580; Mon, 27 Jun 2022 05:24:30 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="124258809" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:28 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A1FC94290418; Mon, 27 Jun 2022 21:24:28 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 02/13] PCI: controller: dwc: Expose dw_pcie_ep_exit() to module Date: Mon, 27 Jun 2022 21:24:06 +0900 Message-Id: <20220627122417.809615-3-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Expose dw_pcie_ep_exit() to module. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 0eda8236c125..5dc73f766c38 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -617,6 +617,7 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) pci_epc_mem_exit(epc); } +EXPORT_SYMBOL_GPL(dw_pcie_ep_exit); static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) { From patchwork Mon Jun 27 12:24:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89C3ECCA483 for ; Mon, 27 Jun 2022 12:24:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240688AbiF0MYc (ORCPT ); Mon, 27 Jun 2022 08:24:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240524AbiF0MYb (ORCPT ); Mon, 27 Jun 2022 08:24:31 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 570A9BF4A; Mon, 27 Jun 2022 05:24:30 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="125807835" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:28 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id CA0C64290412; Mon, 27 Jun 2022 21:24:28 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 03/13] PCI: dwc: Add ep_pre_init() callback to dw_pcie_ep_ops Date: Mon, 27 Jun 2022 21:24:07 +0900 Message-Id: <20220627122417.809615-4-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some PCIe endpoint controller needs vendor-specific initialization before the common code initialization. Add a nwe callback function ep_pre_init() for it. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware-ep.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 5dc73f766c38..72158e6af378 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -709,6 +709,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) } } + if (ep->ops->ep_pre_init) + ep->ops->ep_pre_init(ep); + dw_pcie_iatu_detect(pci); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index b5f528536358..02dcc47749de 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -207,6 +207,7 @@ enum dw_pcie_as_type { }; struct dw_pcie_ep_ops { + void (*ep_pre_init)(struct dw_pcie_ep *ep); void (*ep_init)(struct dw_pcie_ep *ep); int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, enum pci_epc_irq_type type, u16 interrupt_num); From patchwork Mon Jun 27 12:24:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B1BECCA485 for ; Mon, 27 Jun 2022 12:24:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240694AbiF0MYf (ORCPT ); Mon, 27 Jun 2022 08:24:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240691AbiF0MYd (ORCPT ); Mon, 27 Jun 2022 08:24:33 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F05B0BF4C; Mon, 27 Jun 2022 05:24:31 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="124258812" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:29 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id F211D4290415; Mon, 27 Jun 2022 21:24:28 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 04/13] PCI: dwc: Add reset_all_bars flag Date: Mon, 27 Jun 2022 21:24:08 +0900 Message-Id: <20220627122417.809615-5-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some PCIe endpoint drivers reset all BARs in each ep_init() ops. So, we can reset the BARs into the common code if the flag is set. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware-ep.c | 10 ++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 72158e6af378..439f92d7d284 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -85,6 +85,14 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) } EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar); +static void dw_pcie_ep_reset_all_bars(struct dw_pcie *pci) +{ + enum pci_barno bar; + + for (bar = BAR_0; bar < PCI_STD_NUM_BARS; bar++) + dw_pcie_ep_reset_bar(pci, bar); +} + static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no, u8 cap_ptr, u8 cap) { @@ -773,6 +781,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ep->ops->ep_init) ep->ops->ep_init(ep); + if (ep->reset_all_bars) + dw_pcie_ep_reset_all_bars(pci); ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, ep->page_size); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 02dcc47749de..7018c2a7ca3b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -243,6 +243,7 @@ struct dw_pcie_ep { void __iomem *msi_mem; phys_addr_t msi_mem_phys; struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; + bool reset_all_bars; }; struct dw_pcie_ops { From patchwork Mon Jun 27 12:24:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22022CCA48C for ; Mon, 27 Jun 2022 12:24:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240699AbiF0MYe (ORCPT ); Mon, 27 Jun 2022 08:24:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240680AbiF0MYc (ORCPT ); Mon, 27 Jun 2022 08:24:32 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5E826BCA7; Mon, 27 Jun 2022 05:24:31 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="125807838" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:29 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1CE0F4290415; Mon, 27 Jun 2022 21:24:29 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 05/13] PCI: dwc: endpoint: Read num-lanes property before ep_pre_init() Date: Mon, 27 Jun 2022 21:24:09 +0900 Message-Id: <20220627122417.809615-6-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Vendor-specific initialization needs this information so that read it before ep_pre_init(). Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware-ep.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 439f92d7d284..3760857c1f81 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -717,6 +717,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) } } + of_property_read_u32(np, "num-lanes", &pci->num_lanes); + if (ep->ops->ep_pre_init) ep->ops->ep_pre_init(ep); From patchwork Mon Jun 27 12:24:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDBAEC43334 for ; Mon, 27 Jun 2022 12:24:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240706AbiF0MYg (ORCPT ); Mon, 27 Jun 2022 08:24:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240692AbiF0MYd (ORCPT ); Mon, 27 Jun 2022 08:24:33 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 274B8BF4A; Mon, 27 Jun 2022 05:24:32 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="124258815" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:29 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 442584290418; Mon, 27 Jun 2022 21:24:29 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 06/13] PCI: dwc: host: Read num-lanes property before host_init() Date: Mon, 27 Jun 2022 21:24:10 +0900 Message-Id: <20220627122417.809615-7-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Vendor-specific initialization needs this information so that read it before host_init(). And then, we can assume that dw_pcie_{ep,host}_init() gets the property so that dw_pcie_setup() doesn't need to get it again. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 ++ drivers/pci/controller/dwc/pcie-designware.c | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 1e3972c487b5..cf875bdcfabb 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -336,6 +336,8 @@ int dw_pcie_host_init(struct pcie_port *pp) if (pci->link_gen < 1) pci->link_gen = of_pci_get_max_link_speed(np); + of_property_read_u32(np, "num-lanes", &pci->num_lanes); + /* Set default bus ops */ bridge->ops = &dw_pcie_ops; bridge->child_ops = &dw_child_pcie_ops; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d92c8a25094f..101e892e22e8 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -726,7 +726,6 @@ void dw_pcie_setup(struct dw_pcie *pci) val |= PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - of_property_read_u32(np, "num-lanes", &pci->num_lanes); if (!pci->num_lanes) { dev_dbg(pci->dev, "Using h/w default number of lanes\n"); return; From patchwork Mon Jun 27 12:24:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC449CCA483 for ; Mon, 27 Jun 2022 12:24:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240707AbiF0MYh (ORCPT ); Mon, 27 Jun 2022 08:24:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240690AbiF0MYd (ORCPT ); Mon, 27 Jun 2022 08:24:33 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BAA8BBF53; Mon, 27 Jun 2022 05:24:31 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="125807841" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:29 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 61D534290412; Mon, 27 Jun 2022 21:24:29 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 07/13] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Date: Mon, 27 Jun 2022 21:24:11 +0900 Message-Id: <20220627122417.809615-8-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0) PCIe host module. Signed-off-by: Yoshihiro Shimoda --- .../bindings/pci/rcar-gen4-pci-host.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml new file mode 100644 index 000000000000..8ac4c2041a81 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Gen4 PCIe Host + +maintainers: + - Yoshihiro Shimoda + +allOf: + - $ref: snps,dw-pcie.yaml# + +properties: + compatible: + items: + - const: renesas,r8a779f0-pcie # R-Car S4-8 + - const: renesas,rcar-gen4-pcie # R-Car Gen4 + + interrupts: + maxItems: 7 + + interrupt-names: + items: + - const: others + - const: dma + - const: correctable + - const: fatal + - const: nonfatal + - const: lp + - const: vndmsg + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@e65d0000 { + compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>, + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "atu", "app", "config"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0 0xfe000000 0 0x00010000 + 0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "others", "dma", "correctable", "fatal", + "nonfatal", "lp", "vndmsg"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + snps,enable-cdm-check; + max-link-speed = <2>; + }; + }; From patchwork Mon Jun 27 12:24:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB046CCA489 for ; Mon, 27 Jun 2022 12:24:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240698AbiF0MYi (ORCPT ); Mon, 27 Jun 2022 08:24:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240693AbiF0MYd (ORCPT ); Mon, 27 Jun 2022 08:24:33 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4BDFCBF62; Mon, 27 Jun 2022 05:24:32 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="124258818" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:29 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 806344290412; Mon, 27 Jun 2022 21:24:29 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 08/13] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Date: Mon, 27 Jun 2022 21:24:12 +0900 Message-Id: <20220627122417.809615-9-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0) PCIe endpoint module. Signed-off-by: Yoshihiro Shimoda --- .../bindings/pci/rcar-gen4-pci-ep.yaml | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml new file mode 100644 index 000000000000..3850e7038620 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Gen4 PCIe Endpoint + +maintainers: + - Yoshihiro Shimoda + +allOf: + - $ref: snps,dw-pcie-ep.yaml# + +properties: + compatible: + items: + - const: renesas,r8a779f0-pcie-ep # R-Car S4-8 + - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4 + + reg: + maxItems: 4 + + reg-names: + items: + - const: dbi + - const: atu + - const: appl + - const: addr_space + + interrupts: + maxItems: 7 + + interrupt-names: + items: + - const: others + - const: dma + - const: correctable + - const: fatal + - const: nonfatal + - const: lp + - const: vndmsg + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + max-link-speed: true + + num-lanes: true + +required: + - compatible + - reg + - reg-names + - interrupts + - resets + - power-domains + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_ep: pcie-ep@e65d0000 { + compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d1000 0 0x1000>, + <0 0xe65d3000 0 0x2000>, <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "atu", "appl", "addr_space"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "others", "dma", "correctable", "fatal", + "nonfatal", "lp", "vndmsg"; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + max-link-speed = <2>; + }; + }; From patchwork Mon Jun 27 12:24:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BBE0CCA493 for ; Mon, 27 Jun 2022 12:24:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240710AbiF0MYh (ORCPT ); Mon, 27 Jun 2022 08:24:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240698AbiF0MYe (ORCPT ); Mon, 27 Jun 2022 08:24:34 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F0658BF5D; Mon, 27 Jun 2022 05:24:31 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="125807844" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:29 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9F0C34290415; Mon, 27 Jun 2022 21:24:29 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 09/13] PCI: renesas: Add R-Car Gen4 PCIe Host support Date: Mon, 27 Jun 2022 21:24:13 +0900 Message-Id: <20220627122417.809615-10-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add R-Car Gen4 PCIe Host support. This controller is based on Synopsys DesignWare PCIe. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 2 + .../pci/controller/dwc/pcie-rcar-gen4-host.c | 205 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-rcar-gen4.c | 172 +++++++++++++++ drivers/pci/controller/dwc/pcie-rcar-gen4.h | 63 ++++++ 5 files changed, 451 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 62ce3abf0f19..bee273968720 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -384,4 +384,13 @@ config PCIE_FU740 Say Y here if you want PCIe controller support for the SiFive FU740. +config PCIE_RCAR_GEN4 + tristate "Renesas R-Car Gen4 PCIe Host controller" + depends on ARCH_RENESAS || COMPILE_TEST + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs. + This uses the DesignWare core. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 8ba7b67f5e50..108fcbc61d9b 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -25,6 +25,8 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o +pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c new file mode 100644 index 000000000000..7c81973956d0 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include + +#include "pcie-rcar-gen4.h" +#include "pcie-designware.h" + +static int rcar_gen4_pcie_host_init(struct pcie_port *pp) +{ + struct dw_pcie *dw = to_dw_pcie_from_pp(pp); + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + int ret; + u32 val; + + rcar_gen4_pcie_set_device_type(rcar, true, dw->num_lanes); + + dw_pcie_dbi_ro_wr_en(dw); + + /* Enable L1 Substates */ + val = dw_pcie_readl_dbi(dw, L1PSCAP(PCI_L1SS_CTL1)); + val &= ~PCI_L1SS_CTL1_L1SS_MASK; + val |= PCI_L1SS_CTL1_PCIPM_L1_2 | PCI_L1SS_CTL1_PCIPM_L1_1 | + PCI_L1SS_CTL1_ASPM_L1_2 | PCI_L1SS_CTL1_ASPM_L1_1; + dw_pcie_writel_dbi(dw, L1PSCAP(PCI_L1SS_CTL1), val); + + rcar_gen4_pcie_disable_bar(dw, BAR0MASKF); + rcar_gen4_pcie_disable_bar(dw, BAR1MASKF); + + /* Set Root Control */ + val = dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_RTCTL)); + val |= PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | + PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE | + PCI_EXP_RTCTL_CRSSVE; + dw_pcie_writel_dbi(dw, EXPCAP(PCI_EXP_RTCTL), val); + + /* Set Interrupt Disable, SERR# Enable, Parity Error Response */ + val = dw_pcie_readl_dbi(dw, PCI_COMMAND); + val |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | + PCI_COMMAND_INTX_DISABLE; + dw_pcie_writel_dbi(dw, PCI_COMMAND, val); + + /* Enable SERR */ + val = dw_pcie_readb_dbi(dw, PCI_BRIDGE_CONTROL); + val |= PCI_BRIDGE_CTL_SERR; + dw_pcie_writeb_dbi(dw, PCI_BRIDGE_CONTROL, val); + + /* Device control */ + val = dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_DEVCTL)); + val |= PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | + PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE; + dw_pcie_writel_dbi(dw, EXPCAP(PCI_EXP_DEVCTL), val); + + dw_pcie_dbi_ro_wr_dis(dw); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + /* Enable MSI interrupt signal */ + val = rcar_gen4_pcie_readl(rcar, PCIEINTSTS0EN); + val |= MSI_CTRL_INT; + rcar_gen4_pcie_writel(rcar, PCIEINTSTS0EN, val); + } + + dw_pcie_setup_rc(pp); + + dw_pcie_dbi_ro_wr_en(dw); + rcar_gen4_pcie_set_max_link_width(dw, dw->num_lanes); + dw_pcie_dbi_ro_wr_dis(dw); + + if (!dw_pcie_link_up(dw)) { + ret = dw->ops->start_link(dw); + if (ret) + return ret; + } + + /* Ignore errors, the link may come up later */ + if (dw_pcie_wait_for_link(dw)) + dev_info(dw->dev, "PCIe link down\n"); + + return 0; +} + +static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = { + .host_init = rcar_gen4_pcie_host_init, +}; + +static int rcar_gen4_add_pcie_port(struct rcar_gen4_pcie *rcar, + struct platform_device *pdev) +{ + struct dw_pcie *dw = &rcar->dw; + struct pcie_port *pp = &dw->pp; + int ret; + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + pp->msi_irq = platform_get_irq_byname(pdev, "others"); + if (pp->msi_irq < 0) + return pp->msi_irq; + } + + pp->ops = &rcar_gen4_pcie_host_ops; + + ret = dw_pcie_host_init(pp); + if (ret) { + dev_err(&pdev->dev, "Failed to initialize host\n"); + return ret; + } + + return 0; +} + +static void rcar_gen4_remove_pcie_port(struct rcar_gen4_pcie *rcar) +{ + dw_pcie_host_deinit(&rcar->dw.pp); +} + +static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar, + struct platform_device *pdev) +{ + struct dw_pcie *dw = &rcar->dw; + + /* Renesas-specific registers */ + rcar->base = devm_platform_ioremap_resource_byname(pdev, "app"); + if (IS_ERR(rcar->base)) + return PTR_ERR(rcar->base); + + return rcar_gen4_pcie_devm_reset_get(rcar, dw->dev); +} + +static int rcar_gen4_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rcar_gen4_pcie *rcar; + int err; + + rcar = rcar_gen4_pcie_devm_alloc(dev); + if (!rcar) + return -ENOMEM; + + err = rcar_gen4_pcie_pm_runtime_enable(dev); + if (err < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + return err; + } + + err = rcar_gen4_pcie_get_resources(rcar, pdev); + if (err < 0) { + dev_err(dev, "failed to request resource: %d\n", err); + goto err_pm_put; + } + + platform_set_drvdata(pdev, rcar); + + err = rcar_gen4_pcie_prepare(rcar); + if (err < 0) + goto err_pm_put; + + err = rcar_gen4_add_pcie_port(rcar, pdev); + if (err < 0) + goto err_host_disable; + + return 0; + +err_host_disable: + rcar_gen4_pcie_unprepare(rcar); + +err_pm_put: + rcar_gen4_pcie_pm_runtime_disable(dev); + + return err; +} + +static int rcar_gen4_pcie_remove(struct platform_device *pdev) +{ + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev); + + rcar_gen4_remove_pcie_port(rcar); + rcar_gen4_pcie_unprepare(rcar); + rcar_gen4_pcie_pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id rcar_gen4_pcie_of_match[] = { + { .compatible = "renesas,rcar-gen4-pcie", }, + {}, +}; + +static struct platform_driver rcar_gen4_pcie_driver = { + .driver = { + .name = "pcie-rcar-gen4", + .of_match_table = rcar_gen4_pcie_of_match, + }, + .probe = rcar_gen4_pcie_probe, + .remove = rcar_gen4_pcie_remove, +}; +module_platform_driver(rcar_gen4_pcie_driver); + +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe host controller driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c new file mode 100644 index 000000000000..fa9588ed75e0 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include + +#include "pcie-rcar-gen4.h" +#include "pcie-designware.h" + +/* Renesas-specific */ +#define PCIERSTCTRL1 0x0014 +#define APP_HOLD_PHY_RST BIT(16) +#define APP_LTSSM_ENABLE BIT(0) + +#define DWC_VERSION 0x520a + +u32 rcar_gen4_pcie_readl(struct rcar_gen4_pcie *rcar, u32 reg) +{ + return readl(rcar->base + reg); +} + +void rcar_gen4_pcie_writel(struct rcar_gen4_pcie *rcar, u32 reg, u32 val) +{ + writel(val, rcar->base + reg); +} + +static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar, + bool enable) +{ + u32 val; + + val = rcar_gen4_pcie_readl(rcar, PCIERSTCTRL1); + if (enable) { + val |= APP_LTSSM_ENABLE; + val &= ~APP_HOLD_PHY_RST; + } else { + val &= ~APP_LTSSM_ENABLE; + val |= APP_HOLD_PHY_RST; + } + rcar_gen4_pcie_writel(rcar, PCIERSTCTRL1, val); +} + +static int rcar_gen4_pcie_link_up(struct dw_pcie *dw) +{ + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + u32 val, mask; + + val = rcar_gen4_pcie_readl(rcar, PCIEINTSTS0); + mask = RDLH_LINK_UP | SMLH_LINK_UP; + + return (val & mask) == mask; +} + +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) +{ + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + + rcar_gen4_pcie_ltssm_enable(rcar, true); + + return 0; +} + +static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw) +{ + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + + rcar_gen4_pcie_ltssm_enable(rcar, false); +} + +void rcar_gen4_pcie_set_device_type(struct rcar_gen4_pcie *rcar, bool rc, + int num_lanes) +{ + u32 val; + + val = rcar_gen4_pcie_readl(rcar, PCIEMSR0); + if (rc) + val |= DEVICE_TYPE_RC; + else + val |= DEVICE_TYPE_EP; + if (num_lanes < 4) + val |= BIFUR_MOD_SET_ON; + rcar_gen4_pcie_writel(rcar, PCIEMSR0, val); +} + +void rcar_gen4_pcie_disable_bar(struct dw_pcie *dw, u32 bar_mask_reg) +{ + dw_pcie_writel_dbi(dw, SHADOW_REG(bar_mask_reg), 0x0); +} + +void rcar_gen4_pcie_set_max_link_width(struct dw_pcie *dw, int num_lanes) +{ + u32 val = dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_LNKCAP)); + + val &= ~PCI_EXP_LNKCAP_MLW; + switch (num_lanes) { + case 1: + val |= PCI_EXP_LNKCAP_MLW_X1; + break; + case 2: + val |= PCI_EXP_LNKCAP_MLW_X2; + break; + case 4: + val |= PCI_EXP_LNKCAP_MLW_X4; + break; + default: + dev_info(dw->dev, "invalid num-lanes %d\n", num_lanes); + val |= PCI_EXP_LNKCAP_MLW_X1; + break; + } + dw_pcie_writel_dbi(dw, EXPCAP(PCI_EXP_LNKCAP), val); +} + +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar) +{ + return reset_control_deassert(rcar->rst); +} + +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar) +{ + reset_control_assert(rcar->rst); +} + +int rcar_gen4_pcie_pm_runtime_enable(struct device *dev) +{ + pm_runtime_enable(dev); + return pm_runtime_get_sync(dev); +} + +void rcar_gen4_pcie_pm_runtime_disable(struct device *dev) +{ + pm_runtime_put(dev); + pm_runtime_disable(dev); +} + +int rcar_gen4_pcie_devm_reset_get(struct rcar_gen4_pcie *rcar, + struct device *dev) +{ + rcar->rst = devm_reset_control_get(dev, NULL); + if (IS_ERR(rcar->rst)) { + dev_err(dev, "failed to get Cold-reset\n"); + return PTR_ERR(rcar->rst); + } + + return 0; +} + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = rcar_gen4_pcie_start_link, + .stop_link = rcar_gen4_pcie_stop_link, + .link_up = rcar_gen4_pcie_link_up, +}; + +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct device *dev) +{ + struct rcar_gen4_pcie *rcar; + + rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL); + if (!rcar) + return NULL; + + rcar->dw.dev = dev; + rcar->dw.ops = &dw_pcie_ops; + rcar->dw.version = DWC_VERSION; + + return rcar; +} diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h new file mode 100644 index 000000000000..638f536d364f --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#ifndef _PCIE_RCAR_GEN4_H_ +#define _PCIE_RCAR_GEN4_H_ + +#include +#include +#include + +#include "pcie-designware.h" + +/* PCI Express capability */ +#define EXPCAP(x) (0x0070 + (x)) +/* ASPM L1 PM Substates */ +#define L1PSCAP(x) (0x01bc + (x)) +/* PCI Shadow offset */ +#define SHADOW_REG(x) (0x2000 + (x)) +/* BAR Mask registers */ +#define BAR0MASKF 0x0010 +#define BAR1MASKF 0x0014 +#define BAR2MASKF 0x0018 +#define BAR3MASKF 0x001c +#define BAR4MASKF 0x0020 +#define BAR5MASKF 0x0024 + +/* Renesas-specific */ +#define PCIEMSR0 0x0000 +#define BIFUR_MOD_SET_ON BIT(0) +#define DEVICE_TYPE_EP 0 +#define DEVICE_TYPE_RC BIT(4) + +#define PCIEINTSTS0 0x0084 +#define PCIEINTSTS0EN 0x0310 +#define MSI_CTRL_INT BIT(26) +#define SMLH_LINK_UP BIT(7) +#define RDLH_LINK_UP BIT(6) + +struct rcar_gen4_pcie { + struct dw_pcie dw; + void __iomem *base; + struct reset_control *rst; +}; +#define to_rcar_gen4_pcie(x) dev_get_drvdata((x)->dev) + +u32 rcar_gen4_pcie_readl(struct rcar_gen4_pcie *pcie, u32 reg); +void rcar_gen4_pcie_writel(struct rcar_gen4_pcie *pcie, u32 reg, u32 val); +void rcar_gen4_pcie_set_device_type(struct rcar_gen4_pcie *rcar, bool rc, + int num_lanes); +void rcar_gen4_pcie_disable_bar(struct dw_pcie *dw, u32 bar_mask_reg); +void rcar_gen4_pcie_set_max_link_width(struct dw_pcie *pci, int num_lanes); +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *pcie); +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *pcie); +int rcar_gen4_pcie_pm_runtime_enable(struct device *dev); +void rcar_gen4_pcie_pm_runtime_disable(struct device *dev); +int rcar_gen4_pcie_devm_reset_get(struct rcar_gen4_pcie *pcie, + struct device *dev); +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct device *dev); + +#endif /* _PCIE_RCAR_GEN4_H_ */ From patchwork Mon Jun 27 12:24:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 847CACCA487 for ; Mon, 27 Jun 2022 12:24:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240700AbiF0MYk (ORCPT ); Mon, 27 Jun 2022 08:24:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240703AbiF0MYf (ORCPT ); Mon, 27 Jun 2022 08:24:35 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9ECF6BF40; Mon, 27 Jun 2022 05:24:33 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="124258821" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:29 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id BD9BB4290412; Mon, 27 Jun 2022 21:24:29 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 10/13] PCI: renesas: Add R-Car Gen4 PCIe Endpoint support Date: Mon, 27 Jun 2022 21:24:14 +0900 Message-Id: <20220627122417.809615-11-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add R-Car Gen4 PCIe Endpoint support. This controller is based on Synopsys DesignWare PCIe. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 2 + .../pci/controller/dwc/pcie-rcar-gen4-ep.c | 192 ++++++++++++++++++ 3 files changed, 203 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index bee273968720..e8ded6d486f9 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -393,4 +393,13 @@ config PCIE_RCAR_GEN4 Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs. This uses the DesignWare core. +config PCIE_RCAR_GEN4_EP + tristate "Renesas R-Car Gen4 PCIe Endpoint controller" + depends on ARCH_RENESAS || COMPILE_TEST + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Say Y here if you want PCIe endpoint controller support on R-Car Gen4 + SoCs. This uses the DesignWare core. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 108fcbc61d9b..925a32a1f772 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -27,6 +27,8 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o +pcie-rcar-gen4-ep-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-ep.o +obj-$(CONFIG_PCIE_RCAR_GEN4_EP) += pcie-rcar-gen4-ep-drv.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c new file mode 100644 index 000000000000..4f11e3c37182 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe Endpoint driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include + +#include "pcie-rcar-gen4.h" +#include "pcie-designware.h" + +/* Configuration */ +#define PCICONF3 0x000c +#define MULTI_FUNC BIT(23) + +static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *dw = to_dw_pcie_from_ep(ep); + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + int val; + + rcar_gen4_pcie_set_device_type(rcar, false, dw->num_lanes); + + dw_pcie_dbi_ro_wr_en(dw); + + /* Single function */ + val = dw_pcie_readl_dbi(dw, PCICONF3); + val &= ~MULTI_FUNC; + dw_pcie_writel_dbi(dw, PCICONF3, val); + + rcar_gen4_pcie_disable_bar(dw, BAR2MASKF); + rcar_gen4_pcie_disable_bar(dw, BAR3MASKF); + + rcar_gen4_pcie_set_max_link_width(dw, dw->num_lanes); + + dw_pcie_dbi_ro_wr_dis(dw); +} + +static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *dw = to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + return dw_pcie_ep_raise_legacy_irq(ep, func_no); + case PCI_EPC_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + default: + dev_err(dw->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } + + return 0; +} + +static const struct pci_epc_features rcar_gen4_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, + .align = SZ_1M, +}; + +static const struct pci_epc_features* +rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep) +{ + return &rcar_gen4_pcie_epc_features; +} + +static const struct dw_pcie_ep_ops pcie_ep_ops = { + .ep_pre_init = rcar_gen4_pcie_ep_pre_init, + .raise_irq = rcar_gen4_pcie_ep_raise_irq, + .get_features = rcar_gen4_pcie_ep_get_features, +}; + +static int rcar_gen4_add_pcie_ep(struct rcar_gen4_pcie *rcar, + struct platform_device *pdev) +{ + struct dw_pcie *dw = &rcar->dw; + struct dw_pcie_ep *ep; + int ret; + + ep = &dw->ep; + ep->ops = &pcie_ep_ops; + ep->reset_all_bars = true; + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(&pdev->dev, "failed to initialize endpoint\n"); + return ret; + } + + dw->ops->start_link(dw); + + return 0; +} + +static void rcar_gen4_remove_pcie_ep(struct rcar_gen4_pcie *rcar) +{ + dw_pcie_ep_exit(&rcar->dw.ep); +} + +static int rcar_gen4_pcie_ep_get_resources(struct rcar_gen4_pcie *rcar, + struct platform_device *pdev) +{ + struct dw_pcie *dw = &rcar->dw; + struct device *dev = dw->dev; + + /* Renesas-specific registers */ + rcar->base = devm_platform_ioremap_resource_byname(pdev, "appl"); + if (IS_ERR(rcar->base)) + return PTR_ERR(rcar->base); + + return rcar_gen4_pcie_devm_reset_get(rcar, dev); +} + +static int rcar_gen4_pcie_ep_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rcar_gen4_pcie *rcar; + int err; + + rcar = rcar_gen4_pcie_devm_alloc(dev); + if (!rcar) + return -ENOMEM; + + err = rcar_gen4_pcie_pm_runtime_enable(dev); + if (err < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + return err; + } + + err = rcar_gen4_pcie_ep_get_resources(rcar, pdev); + if (err < 0) { + dev_err(dev, "failed to request resource: %d\n", err); + goto err_pm_put; + } + + platform_set_drvdata(pdev, rcar); + + err = rcar_gen4_pcie_prepare(rcar); + if (err < 0) + goto err_pm_put; + + err = rcar_gen4_add_pcie_ep(rcar, pdev); + if (err < 0) + goto err_ep_disable; + + return 0; + +err_ep_disable: + rcar_gen4_pcie_unprepare(rcar); + +err_pm_put: + rcar_gen4_pcie_pm_runtime_disable(dev); + + return err; +} + +static int rcar_gen4_pcie_ep_remove(struct platform_device *pdev) +{ + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev); + + rcar_gen4_remove_pcie_ep(rcar); + rcar_gen4_pcie_unprepare(rcar); + rcar_gen4_pcie_pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id rcar_gen4_pcie_of_match[] = { + { .compatible = "renesas,rcar-gen4-pcie-ep", }, + {}, +}; + +static struct platform_driver rcar_gen4_pcie_ep_driver = { + .driver = { + .name = "pcie-rcar-gen4-ep", + .of_match_table = rcar_gen4_pcie_of_match, + }, + .probe = rcar_gen4_pcie_ep_probe, + .remove = rcar_gen4_pcie_ep_remove, +}; +module_platform_driver(rcar_gen4_pcie_ep_driver); + +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe endpoint controller driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Jun 27 12:24:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E081CCA473 for ; Mon, 27 Jun 2022 12:24:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240680AbiF0MYf (ORCPT ); Mon, 27 Jun 2022 08:24:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240694AbiF0MYd (ORCPT ); Mon, 27 Jun 2022 08:24:33 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8FADB9580; Mon, 27 Jun 2022 05:24:32 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="125807847" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:30 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id DB2964290412; Mon, 27 Jun 2022 21:24:29 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 11/13] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Date: Mon, 27 Jun 2022 21:24:15 +0900 Message-Id: <20220627122417.809615-12-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update this entry for R-Car Gen4's source code. Signed-off-by: Yoshihiro Shimoda --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4004bf912c40..e7f8b14b08e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15333,6 +15333,7 @@ L: linux-renesas-soc@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pci/*rcar* F: drivers/pci/controller/*rcar* +F: drivers/pci/controller/dwc/*rcar* PCI DRIVER FOR SAMSUNG EXYNOS M: Jingoo Han From patchwork Mon Jun 27 12:24:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 344E9CCA48A for ; Mon, 27 Jun 2022 12:24:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240715AbiF0MYj (ORCPT ); Mon, 27 Jun 2022 08:24:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240700AbiF0MYf (ORCPT ); Mon, 27 Jun 2022 08:24:35 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9EC73BCA7; Mon, 27 Jun 2022 05:24:33 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="124258824" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:30 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0E1524290418; Mon, 27 Jun 2022 21:24:30 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 12/13] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Date: Mon, 27 Jun 2022 21:24:16 +0900 Message-Id: <20220627122417.809615-13-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIe Host and Endpoint nodes for R-Car S4-8 (R8A779F0). Signed-off-by: Yoshihiro Shimoda --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 118 ++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 384817ffa4de..a223f6bdc84a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -504,6 +504,124 @@ hscif3: serial@e66a0000 { status = "disabled"; }; + pciec0: pcie@e65d0000 { + compatible = "renesas,r8a779f0-pcie", + "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>, + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "atu", "app", "config"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "others", "dma", "correctable", + "fatal", "nonfatal", "lp", "vndmsg"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + snps,enable-cdm-check; + max-link-speed = <2>; + status = "disabled"; + }; + + pciec1: pcie@e65d8000 { + compatible = "renesas,r8a779f0-pcie", + "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d8000 0 0x3000>, <0 0xe65db000 0 0x2000>, + <0 0xe65de200 0 0x0e00>, <0 0xee900000 0 0x400000>; + reg-names = "dbi", "atu", "app", "config"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x82000000 0 0xc0000000 0 0xc0000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "others", "dma", "correctable", + "fatal", "nonfatal", "lp", "vndmsg"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 625>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + num-lanes = <2>; + snps,enable-cdm-check; + max-link-speed = <2>; + status = "disabled"; + }; + + pciec0_ep: pcie-ep@e65d0000 { + compatible = "renesas,r8a779f0-pcie-ep", + "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>, + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "atu", "appl", "addr_space"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "others", "dma", "correctable", + "fatal", "nonfatal", "lp", "vndmsg"; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + max-link-speed = <2>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@e65d8000 { + compatible = "renesas,r8a779f0-pcie-ep", + "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d8000 0 0x3000>, <0 0xe65db000 0 0x2000>, + <0 0xe65de200 0 0x0e00>, <0 0xee900000 0 0x400000>; + reg-names = "dbi", "atu", "appl", "addr_space"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "others", "dma", "correctable", + "fatal", "nonfatal", "lp", "vndmsg"; + clocks = <&cpg CPG_MOD 625>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + num-lanes = <2>; + max-link-speed = <2>; + status = "disabled"; + }; + ufs: ufs@e6860000 { compatible = "renesas,r8a779f0-ufs"; reg = <0 0xe6860000 0 0x100>; From patchwork Mon Jun 27 12:24:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 12896590 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9AE9CCA48C for ; Mon, 27 Jun 2022 12:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240693AbiF0MYj (ORCPT ); Mon, 27 Jun 2022 08:24:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240685AbiF0MYe (ORCPT ); Mon, 27 Jun 2022 08:24:34 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9D36A2AF6; Mon, 27 Jun 2022 05:24:33 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,226,1650898800"; d="scan'208";a="125807850" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jun 2022 21:24:30 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2A5474290412; Mon, 27 Jun 2022 21:24:30 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 13/13] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Date: Mon, 27 Jun 2022 21:24:17 +0900 Message-Id: <20220627122417.809615-14-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> References: <20220627122417.809615-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable PCIe Host controller channel 0 on R-Car S4-8 Spider board. Signed-off-by: Yoshihiro Shimoda --- .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 81d178e69527..34db1b902af8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ +#include #include "r8a779f0.dtsi" / { @@ -31,6 +32,28 @@ &extalr_clk { clock-frequency = <32768>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gpio_exp_20: gpio@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + pcie-perst-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE_PERSTn"; + }; + }; +}; + &i2c4 { pinctrl-0 = <&i2c4_pins>; pinctrl-names = "default"; @@ -46,15 +69,31 @@ eeprom@50 { }; }; +&pciec0 { + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + i2c4_pins: i2c4 { groups = "i2c4"; function = "i2c4"; }; + pcie0_pins: pcie0 { + groups = "pcie0_clkreq_n"; + function = "pcie"; + }; + scif3_pins: scif3 { groups = "scif3_data", "scif3_ctrl"; function = "scif3";