From patchwork Tue Jun 28 10:17:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12898047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 978DAC433EF for ; Tue, 28 Jun 2022 10:21:41 +0000 (UTC) Received: from localhost ([::1]:51450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o68Lk-0007Bb-Mh for qemu-devel@archiver.kernel.org; Tue, 28 Jun 2022 06:21:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o68IB-0001e3-B1 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 06:17:59 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:54217) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o68I9-00080A-OI for qemu-devel@nongnu.org; Tue, 28 Jun 2022 06:17:59 -0400 Received: by mail-pj1-x1032.google.com with SMTP id d14so12132827pjs.3 for ; Tue, 28 Jun 2022 03:17:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6J7gL6BfZeqHNBCJK+8rR2sxXz+yKeHStI/GCp5riaI=; b=e1l52a3A5W9i2d+leHreiEezlpZsiQA0I4kG2W0+mv9G6jmYCnp2stOxIkCzxYnnE3 +HHwmq3O9RrXEEZ8/KKDRmvOggnKsLxQfyhF51HOnuSAaBdypnQICq/EK4pW6aOmBqlo R9NGdOgEv+Zk/zgcJ1DquskeJoBQl7EocxBys/ZsTxPG5UG2UCXOOjW2Xb9rrqy5gi6q 0PBYLdgJyuZB/OIog/nK2iwjOA2hsLwXnc9TEPmURFkIVi3g8LvuC2mV0suJ+pkSm54W qnUyxZH4LDBXaiFLZ5bXhUJCDU97s3/NOEdR0e9sy5tFzQCu4IordSshylK20D5/7JwG Cwow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6J7gL6BfZeqHNBCJK+8rR2sxXz+yKeHStI/GCp5riaI=; b=ePswAGz42Miq9glzv/5LCmVS66aXGPJ0GyuirVFGlPUx7BL5VCNVT2EH0fNw01TQgj bcrr0/EgoxLjzqkgnhBvjT+lJ6cDbjZARHjn7ggK1RTfpJ5So1uPxzTYZdcrX3K0VBuB CzH7inL18rvzFpjBA1eDfQAIFBBWiHg9bZ1rcmf61Mx2QwfmV5ocbhxRLT+880ccoT3f PA6DcsQAlezOA6woR1r7z8o156c6GqbGU45EgLNDELX4pUiF6rwXcv1qiI7NkaeOX8c9 V2EEqLae/89fmvAUsK2h9rVb14fRL2IhGXzQwQtGnhZG9bUP3M3mIZJEjNV5Wyjy1yxW IktQ== X-Gm-Message-State: AJIora/RCQ0qFb9szD8rl7T4GvQRhLyhEJMcQvFuBU9q0jMq+XwxWaeH ZOvvXUQmkcA+Oi9dT5fEIN/Zpw== X-Google-Smtp-Source: AGRyM1tR5+4WaYBVmOK8NVYE0QPtvkookvUq4J1DWDW/+yosrovLT9WGYB1ZsbBPaDdzgi+cNbg1oQ== X-Received: by 2002:a17:90a:f8d6:b0:1ee:e6b1:d52 with SMTP id l22-20020a17090af8d600b001eee6b10d52mr9197619pjd.158.1656411476359; Tue, 28 Jun 2022 03:17:56 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([117.96.230.192]) by smtp.gmail.com with ESMTPSA id bj28-20020a056a00319c00b0051bc36b7995sm8909621pfb.62.2022.06.28.03.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 03:17:55 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v8 1/4] Revert "target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher" Date: Tue, 28 Jun 2022 15:47:34 +0530 Message-Id: <20220628101737.786681-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628101737.786681-1-apatel@ventanamicro.com> References: <20220628101737.786681-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This reverts commit 33cc1c0b69e457f5c526f64297353cba6f7bfdb4 because commit eab4776b2badd4088a4f807c9bb3dc453c53dc23 already implements proper mcountinhibit CSR emulation. Signed-off-by: Anup Patel --- target/riscv/cpu_bits.h | 3 --- target/riscv/csr.c | 2 -- 2 files changed, 5 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8724b45c08..b3f7fa7130 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -159,9 +159,6 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 -/* Machine Counter Setup */ -#define CSR_MCOUNTINHIBIT 0x320 - /* 32-bit only */ #define CSR_MSTATUSH 0x310 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b5734957cf..d65318dcc6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3642,8 +3642,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, - [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_zero, write_ignore, - .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, From patchwork Tue Jun 28 10:17:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12898052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28972C433EF for ; Tue, 28 Jun 2022 10:24:25 +0000 (UTC) Received: from localhost ([::1]:33170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o68OO-0005Q4-3u for qemu-devel@archiver.kernel.org; Tue, 28 Jun 2022 06:24:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o68IE-0001om-Ux for qemu-devel@nongnu.org; Tue, 28 Jun 2022 06:18:02 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:44886) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o68ID-00080Z-Cz for qemu-devel@nongnu.org; Tue, 28 Jun 2022 06:18:02 -0400 Received: by mail-pg1-x529.google.com with SMTP id v126so7584975pgv.11 for ; Tue, 28 Jun 2022 03:18:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mHMyNrMsO1iP4VbXnd4aidt4qEDuWWfhMdOb3QrB/+M=; b=P2GkkGSTPyKWPCYP8ibB7inMLU03vDHIwt5wEOJ+rDqeO9DvYnZwWJ7w6SSYvQnLhu aakGsBbhzb0pB/hib+UM282ZJFH/6b6ZHxjtiYQY34JTOzqYT7zGpo9ukKcPSkHtMF4s ddxtcX1xYVstchivxM9L6uF9G0z8r2UL8u2U2XkOEKlWsnUCPkiaA1/EemyFC+W7RkIj +e4HSq2YmjtiSi21jhQVYql+dpQTavd0KAqmDgR1Xe5beKQ9GTeSxDjnhO4fxYGUXb7l 8gJsIN5wUhvRJQi6k9uQLczuWaDsPp+nP1inE06KtFD6uPlh9O/1OeF5Vw7OAfhWEKB9 1BrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mHMyNrMsO1iP4VbXnd4aidt4qEDuWWfhMdOb3QrB/+M=; b=EMEOo+0fS4H0h7Hwbbwbpr58/k0++u0AKS81x30iCM+krwzsWa56ejckWDrRl3h8Xo Tj3mTfxJJNFohm1NAAc8Az73ae2GeP+90zLvrwz5yMvU61w/1Q4RXOeLd6vb9Juz0TdB XH7+wdFDGImHL0lS3sZYk9Q0xqvIzSY8TEG/LPrja/RK6Rr8InXGOOu4fcY0YdjJzy4Z 1pI0LoINjXUsJ+tKcKKIGTfDgXHwU12PYE1AFRn9j1LJGQtq9nNiE3tkeyIySqs7YIoC dct3t7sDXNW74rkpUQzyDNDYXMwZom/P/54UA+5uNv42UqVM2dEZrdpNu5fM34LAZB33 Hocw== X-Gm-Message-State: AJIora+NFJBgeTlw1cnTnWwFd22gZe/7944kLCajMvyVVSIBCWINE4Tt 9Fr6lLguTjz1T/s3UFBqCp4fVA== X-Google-Smtp-Source: AGRyM1tsMrkVDtWdcCS+TpnRousmkMYXbxuJ1wCu744IeN/i3x74h2kl97wo+rileJsFEaOU4hlqOA== X-Received: by 2002:a05:6a00:170f:b0:525:467c:3516 with SMTP id h15-20020a056a00170f00b00525467c3516mr2885081pfc.22.1656411480024; Tue, 28 Jun 2022 03:18:00 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([117.96.230.192]) by smtp.gmail.com with ESMTPSA id bj28-20020a056a00319c00b0051bc36b7995sm8909621pfb.62.2022.06.28.03.17.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 03:17:59 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v8 2/4] target/riscv: Set minumum priv spec version for mcountinhibit Date: Tue, 28 Jun 2022 15:47:35 +0530 Message-Id: <20220628101737.786681-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628101737.786681-1-apatel@ventanamicro.com> References: <20220628101737.786681-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The minimum priv spec versino for mcountinhibit to v1.11 so that it is not available for v1.10 (or lower). Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d65318dcc6..f7bfd2eab5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3944,7 +3944,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { write_mhpmcounter }, [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, - write_mcountinhibit }, + write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, write_mhpmevent }, From patchwork Tue Jun 28 10:17:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12898051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFF52C433EF for ; Tue, 28 Jun 2022 10:23:59 +0000 (UTC) Received: from localhost ([::1]:60358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o68Ny-0004k7-U4 for qemu-devel@archiver.kernel.org; Tue, 28 Jun 2022 06:23:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o68IL-000202-MQ for qemu-devel@nongnu.org; Tue, 28 Jun 2022 06:18:13 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:39905) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o68II-00081F-38 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 06:18:09 -0400 Received: by mail-pj1-x1033.google.com with SMTP id b12-20020a17090a6acc00b001ec2b181c98so15374838pjm.4 for ; Tue, 28 Jun 2022 03:18:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eRIZAyGRAvPAYkmb5d7BxSmaN3+9ZOGUj7ZkDc35fCU=; b=FwQEQ1Vc2eKdwGN+fIlHRixxk1p33yQoQcscu0XivJi/2Y8X0BAsG7Dlcw/XcrT8WY s0TfLHWf2Eao6KLouVhjU23EHsWHKBi19+xN02rS+ajH1ImarGouhcFWx+HyHDMtOEiJ I9mveOLWoICbHZOlw/MTXP2SupnsM0JTbgF71tqDiX8PIZg1f6pBWXbwTY4nUvLBER7I 75Mzyy2dmlHI4MBg85bSRDeu9ljCzFH704sDYHgdeqerllYVULqC37G7Mq+sSkSj1d3E xFrwXwl3cqmj4Y96608WeAR/WWuJtot9a2QU9CwUR3/cZ+IpMczm+NIOGSFsm/Eu//YZ Ra7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eRIZAyGRAvPAYkmb5d7BxSmaN3+9ZOGUj7ZkDc35fCU=; b=2rCJVnBf8Zc6XQeubcO+ybO8t/CHdtRMIURReAI5XqJtoF0VpPgJNdHaAIBzqXFw1a Dpr/YmkyOA7+z1AphMHYMaMLcIHKmgXqLQkaqTFfhNp2N514o4WeHmE6TwTXrrCiVaqL EZcogZhQoWlARgqPeBWeXfgyBa6SYbZ8VTF4wajWInw238XGJIa03sV4nf3ug/jdnVAi eL26Cc8kDXpMvLRdbE+hjeHwF9P7pPoXbiDSy0L5w5/pWFCpUXsoYB48SFH0zs9paoth e24CmtfmT+3VemFZ6L7yOC5b0PWa93HGaJR1yrmhmP+VNTjZOC304kRO8d44gRyfICR2 RqLQ== X-Gm-Message-State: AJIora85fA32gVhS98l5qnKvCMYzs7OHVFbUUfXjOCkZHJgqVVXtgyJK VAvkrN00YEfU1PffsSVjTrRsaA== X-Google-Smtp-Source: AGRyM1thmHJsTBcteVl+QOy6/vEqhXCX9PrxVk4SvP1F5YNJJJa6CM/HljWJLdqbjckzMnJbKlTIow== X-Received: by 2002:a17:902:8211:b0:16a:43ad:b832 with SMTP id x17-20020a170902821100b0016a43adb832mr4052096pln.165.1656411484172; Tue, 28 Jun 2022 03:18:04 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([117.96.230.192]) by smtp.gmail.com with ESMTPSA id bj28-20020a056a00319c00b0051bc36b7995sm8909621pfb.62.2022.06.28.03.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 03:18:03 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis Subject: [PATCH v8 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Date: Tue, 28 Jun 2022 15:47:36 +0530 Message-Id: <20220628101737.786681-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628101737.786681-1-apatel@ventanamicro.com> References: <20220628101737.786681-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Reviewed-by: Alistair Francis Signed-off-by: Anup Patel --- target/riscv/cpu.h | 5 + target/riscv/cpu_helper.c | 235 +++++++++++++++++++++++++++++++++++++- target/riscv/instmap.h | 45 ++++++++ 3 files changed, 279 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c7acc055a..ffb1a18873 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,6 +285,11 @@ struct CPUArchState { /* Signals whether the current exception occurred with two-stage address translation active. */ bool two_stage_lookup; + /* + * Signals whether the current exception occurred while doing two-stage + * address translation for the VS-stage page table walk. + */ + bool two_stage_indirect_lookup; target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4a6700c890..d11198f4f9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" +#include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" @@ -1057,7 +1058,8 @@ restart: static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violation, - bool first_stage, bool two_stage) + bool first_stage, bool two_stage, + bool two_stage_indirect) { CPUState *cs = env_cpu(env); int page_fault_exceptions, vm; @@ -1107,6 +1109,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, } env->badaddr = address; env->two_stage_lookup = two_stage; + env->two_stage_indirect_lookup = two_stage_indirect; } hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -1152,6 +1155,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, env->badaddr = addr; env->two_stage_lookup = riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); } @@ -1177,6 +1181,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, env->badaddr = addr; env->two_stage_lookup = riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); } @@ -1192,6 +1197,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool pmp_violation = false; bool first_stage_error = true; bool two_stage_lookup = false; + bool two_stage_indirect_error = false; int ret = TRANSLATE_FAIL; int mode = mmu_idx; /* default TLB page size */ @@ -1229,6 +1235,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, */ if (ret == TRANSLATE_G_STAGE_FAIL) { first_stage_error = false; + two_stage_indirect_error = true; access_type = MMU_DATA_LOAD; } @@ -1312,12 +1319,201 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(mmu_idx)); + riscv_cpu_two_stage_lookup(mmu_idx), + two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } return true; } + +static target_ulong riscv_transformed_insn(CPURISCVState *env, + target_ulong insn, + target_ulong taddr) +{ + target_ulong xinsn = 0, xinsn_access_rs1 = 0, xinsn_access_size = 0; + + /* + * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to + * be uncompressed. The Quadrant 1 of RVC instruction space need + * not be transformed because these instructions won't generate + * any load/store trap. + */ + + if ((insn & 0x3) != 0x3) { + /* Transform 16bit instruction into 32bit instruction */ + switch (GET_C_OP(insn)) { + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLD_LQ: + if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ + xinsn = OPC_RISC_FLD; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn_access_rs1 = GET_C_RS1S(insn); + xinsn_access_size = 8; + } + break; + case OPC_RISC_C_FUNC_LW: /* C.LW */ + xinsn = OPC_RISC_LW; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn_access_rs1 = GET_C_RS1S(insn); + xinsn_access_size = 4; + break; + case OPC_RISC_C_FUNC_FLW_LD: + if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ + xinsn = OPC_RISC_FLW; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn_access_rs1 = GET_C_RS1S(insn); + xinsn_access_size = 4; + } else { /* C.LD (RV64/RV128) */ + xinsn = OPC_RISC_LD; + xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn_access_rs1 = GET_C_RS1S(insn); + xinsn_access_size = 8; + } + break; + case OPC_RISC_C_FUNC_FSD_SQ: + if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ + xinsn = OPC_RISC_FSD; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn_access_rs1 = GET_C_RS1S(insn); + xinsn_access_size = 8; + } + break; + case OPC_RISC_C_FUNC_SW: /* C.SW */ + xinsn = OPC_RISC_SW; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn_access_rs1 = GET_C_RS1S(insn); + xinsn_access_size = 4; + break; + case OPC_RISC_C_FUNC_FSW_SD: + if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ + xinsn = OPC_RISC_FSW; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn_access_rs1 = GET_C_RS1S(insn); + xinsn_access_size = 4; + } else { /* C.SD (RV64/RV128) */ + xinsn = OPC_RISC_SD; + xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn_access_rs1 = GET_C_RS1S(insn); + xinsn_access_size = 8; + } + break; + default: + break; + } + break; + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLDSP_LQSP: + if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ + xinsn = OPC_RISC_FLD; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn_access_rs1 = 2; + xinsn_access_size = 8; + } + break; + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ + xinsn = OPC_RISC_LW; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn_access_rs1 = 2; + xinsn_access_size = 4; + break; + case OPC_RISC_C_FUNC_FLWSP_LDSP: + if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ + xinsn = OPC_RISC_FLW; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn_access_rs1 = 2; + xinsn_access_size = 4; + } else { /* C.LDSP (RV64/RV128) */ + xinsn = OPC_RISC_LD; + xinsn = SET_RD(xinsn, GET_C_RD(insn)); + xinsn_access_rs1 = 2; + xinsn_access_size = 8; + } + break; + case OPC_RISC_C_FUNC_FSDSP_SQSP: + if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ + xinsn = OPC_RISC_FSD; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn_access_rs1 = 2; + xinsn_access_size = 8; + } + break; + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ + xinsn = OPC_RISC_SW; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn_access_rs1 = 2; + xinsn_access_size = 4; + break; + case 7: + if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ + xinsn = OPC_RISC_FSW; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn_access_rs1 = 2; + xinsn_access_size = 4; + } else { /* C.SDSP (RV64/RV128) */ + xinsn = OPC_RISC_SD; + xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn_access_rs1 = 2; + xinsn_access_size = 8; + } + break; + default: + break; + } + break; + default: + break; + } + + /* + * Clear Bit1 of transformed instruction to indicate that + * original insruction was a 16bit instruction + */ + xinsn &= ~((target_ulong)0x2); + } else { + /* Transform 32bit (or wider) instructions */ + switch (MASK_OP_MAJOR(insn)) { + case OPC_RISC_ATOMIC: + xinsn = insn; + xinsn_access_rs1 = GET_RS1(xinsn); + xinsn_access_size = 1 << GET_FUNCT3(xinsn); + break; + case OPC_RISC_LOAD: + case OPC_RISC_FP_LOAD: + xinsn = insn; + xinsn_access_rs1 = GET_RS1(xinsn); + xinsn_access_size = 1 << GET_FUNCT3(xinsn); + xinsn = SET_I_IMM(xinsn, 0); + break; + case OPC_RISC_STORE: + case OPC_RISC_FP_STORE: + xinsn = insn; + xinsn_access_rs1 = GET_RS1(xinsn); + xinsn_access_size = 1 << GET_FUNCT3(xinsn); + xinsn = SET_S_IMM(xinsn, 0); + break; + case OPC_RISC_SYSTEM: + if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { + xinsn = insn; + xinsn_access_rs1 = GET_RS1(xinsn); + xinsn_access_size = 1 << ((GET_FUNCT7(xinsn) >> 1) & 0x3); + xinsn_access_size = 1 << xinsn_access_size; + } + break; + default: + break; + } + } + + if (xinsn_access_size) { + xinsn = SET_RS1(xinsn, (taddr - env->gpr[xinsn_access_rs1]) & + (xinsn_access_size - 1)); + } + + return xinsn; +} #endif /* !CONFIG_USER_ONLY */ /* @@ -1342,6 +1538,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg = async ? env->mideleg : env->medeleg; target_ulong tval = 0; + target_ulong tinst = 0; target_ulong htval = 0; target_ulong mtval2 = 0; @@ -1357,20 +1554,43 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { - case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_ADDR_MIS: - case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_STORE_AMO_ADDR_MIS: case RISCV_EXCP_LOAD_ACCESS_FAULT: case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: write_gva = env->two_stage_lookup; tval = env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; + } else { + /* + * The "Addr. Offset" field in transformed instruction is + * non-zero only for misaligned access. + */ + tinst = riscv_transformed_insn(env, env->bins, tval); + } + break; + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_INST_ACCESS_FAULT: + case RISCV_EXCP_INST_PAGE_FAULT: + write_gva = env->two_stage_lookup; + tval = env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; + } break; case RISCV_EXCP_ILLEGAL_INST: case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: @@ -1450,6 +1670,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->sepc = env->pc; env->stval = tval; env->htval = htval; + env->htinst = tinst; env->pc = (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); @@ -1480,6 +1701,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc = env->pc; env->mtval = tval; env->mtval2 = mtval2; + env->mtinst = tinst; env->pc = (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); @@ -1492,6 +1714,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) */ env->two_stage_lookup = false; + env->two_stage_indirect_lookup = false; #endif cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ } diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index 40b6d2b64d..f877530576 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -184,6 +184,8 @@ enum { OPC_RISC_CSRRWI = OPC_RISC_SYSTEM | (0x5 << 12), OPC_RISC_CSRRSI = OPC_RISC_SYSTEM | (0x6 << 12), OPC_RISC_CSRRCI = OPC_RISC_SYSTEM | (0x7 << 12), + + OPC_RISC_HLVHSV = OPC_RISC_SYSTEM | (0x4 << 12), }; #define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) @@ -310,12 +312,20 @@ enum { | (extract32(inst, 12, 8) << 12) \ | (sextract64(inst, 31, 1) << 20)) +#define GET_FUNCT3(inst) extract32(inst, 12, 3) +#define GET_FUNCT7(inst) extract32(inst, 25, 7) #define GET_RM(inst) extract32(inst, 12, 3) #define GET_RS3(inst) extract32(inst, 27, 5) #define GET_RS1(inst) extract32(inst, 15, 5) #define GET_RS2(inst) extract32(inst, 20, 5) #define GET_RD(inst) extract32(inst, 7, 5) #define GET_IMM(inst) sextract64(inst, 20, 12) +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val) +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val) +#define SET_RD(inst, val) deposit32(inst, 7, 5, val) +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val) +#define SET_S_IMM(inst, val) \ + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5) /* RVC decoding macros */ #define GET_C_IMM(inst) (extract32(inst, 2, 5) \ @@ -346,6 +356,8 @@ enum { | (extract32(inst, 5, 1) << 6)) #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ | (extract16(inst, 5, 2) << 6)) +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst) +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst) #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ | (extract32(inst, 11, 1) << 4) \ | (extract32(inst, 2, 1) << 5) \ @@ -366,4 +378,37 @@ enum { #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) +#define GET_C_FUNC(inst) extract32(inst, 13, 3) +#define GET_C_OP(inst) extract32(inst, 0, 2) + +enum { + /* RVC Quadrants */ + OPC_RISC_C_OP_QUAD0 = 0x0, + OPC_RISC_C_OP_QUAD1 = 0x1, + OPC_RISC_C_OP_QUAD2 = 0x2 +}; + +enum { + /* RVC Quadrant 0 */ + OPC_RISC_C_FUNC_ADDI4SPN = 0x0, + OPC_RISC_C_FUNC_FLD_LQ = 0x1, + OPC_RISC_C_FUNC_LW = 0x2, + OPC_RISC_C_FUNC_FLW_LD = 0x3, + OPC_RISC_C_FUNC_FSD_SQ = 0x5, + OPC_RISC_C_FUNC_SW = 0x6, + OPC_RISC_C_FUNC_FSW_SD = 0x7 +}; + +enum { + /* RVC Quadrant 2 */ + OPC_RISC_C_FUNC_SLLI_SLLI64 = 0x0, + OPC_RISC_C_FUNC_FLDSP_LQSP = 0x1, + OPC_RISC_C_FUNC_LWSP = 0x2, + OPC_RISC_C_FUNC_FLWSP_LDSP = 0x3, + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD = 0x4, + OPC_RISC_C_FUNC_FSDSP_SQSP = 0x5, + OPC_RISC_C_FUNC_SWSP = 0x6, + OPC_RISC_C_FUNC_FSWSP_SDSP = 0x7 +}; + #endif From patchwork Tue Jun 28 10:17:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12898049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F232C433EF for ; Tue, 28 Jun 2022 10:22:54 +0000 (UTC) Received: from localhost ([::1]:55440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o68Mv-0001WZ-9b for qemu-devel@archiver.kernel.org; Tue, 28 Jun 2022 06:22:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o68IO-00020M-5k for qemu-devel@nongnu.org; Tue, 28 Jun 2022 06:18:14 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:40915) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o68IL-00082H-W7 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 06:18:11 -0400 Received: by mail-pl1-x62a.google.com with SMTP id b2so3652840plx.7 for ; Tue, 28 Jun 2022 03:18:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jXsfoRJoFy8eowC34vbywLaVEMgoFF/TBBpgUmrTXTM=; b=dy3A5Xd6MgLARtuAl8I86OUHFrO+roSYAX6p7dbWx+d9febmv/2H0a/DZrpNdW7rJE dz06DvQDC4616fc/rGLqikV50j9/LFODCaxb2HYOeCJzj25XlJY9B1rlgs8YBV+zq1xQ 9tyLZYOeEajOgHo8C47fDEQf60i6mvoPrPNo/yx7PefCMJzVgJnyLZkPHBk5XeK6LnGr LZRSHxUhparqqQvqxegpFlh26HLWbyBVIDAaRil7Q3eOcaFTy/jPzxcCTr32LrxF0Kzy Y9L/AQekZ+7EMykAYZ3XPWnQjx4k7jW7hvVlyI7lpEOjDls5WjecPp9tMeaG+f4ONbsZ SsaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jXsfoRJoFy8eowC34vbywLaVEMgoFF/TBBpgUmrTXTM=; b=AhFL6qr//dUIikyfgEWeKjuaU6soesEwfHJWy+z07Q1q5wtBgIrTAKTQGC8Y7AK6dr xz3qmEw9snqok7s71cnuRrkr2LwzpZk3hmC6H1jEXK64jK1nSp13icykYgxMZY3XwDQ2 du8acrtxsO+5+w+FVkawuQjbouDWZTugSWFwfY4L0JKLX19bAq02uznpBAuv2KG82iRI 0oOjIx7OrZ6ZlXD5qZ1IK9rwI9L/AvT/39cA5vNwvyDYJm+bETpJh1dFTXH7I792xteJ A8RZzQe0zb7n7PJvm7cYK4V5GWf1oWWWJMgDniYxTDLJLIyrAonn3sium3KjMhYURhBt qQ3g== X-Gm-Message-State: AJIora+T11kflg/GbeLV9etKXzaAXBXhTu93nUFdAGVCox/a2HlnyfKc 0zQ+iZ+yBzZPZoocMCQXs4CMew== X-Google-Smtp-Source: AGRyM1vY4jPRiB/LSDdvo42lZ1ixzpNngk5KPiiYgVS86zI5w9QbKEgZM+9oYHPVam2d7VEM4MokCQ== X-Received: by 2002:a17:902:c94f:b0:16a:7337:6c82 with SMTP id i15-20020a170902c94f00b0016a73376c82mr2957450pla.55.1656411488352; Tue, 28 Jun 2022 03:18:08 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([117.96.230.192]) by smtp.gmail.com with ESMTPSA id bj28-20020a056a00319c00b0051bc36b7995sm8909621pfb.62.2022.06.28.03.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 03:18:07 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis , Rahul Pathak Subject: [PATCH v8 4/4] target/riscv: Force disable extensions if priv spec version does not match Date: Tue, 28 Jun 2022 15:47:37 +0530 Message-Id: <20220628101737.786681-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628101737.786681-1-apatel@ventanamicro.com> References: <20220628101737.786681-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the device tree") Reviewed-by: Alistair Francis Signed-off-by: Anup Patel Signed-off-by: Rahul Pathak --- target/riscv/cpu.c | 150 ++++++++++++++++++++++++++++----------------- 1 file changed, 94 insertions(+), 56 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e7ca6cd4a..9bc4ef0685 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -43,9 +43,82 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; struct isa_ext_data { const char *name; - bool enabled; + bool multi_letter; + int min_version; + int ext_enable_offset; }; +#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ +{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + +/** + * Here are the ordering rules of extension naming defined by RISC-V + * specification : + * 1. All extensions should be separated from other multi-letter extensions + * by an underscore. + * 2. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they should be ordered first + * by category, then alphabetically within a category. + * 3. Standard supervisor-level extensions (starts with 'S') should be + * listed after standard unprivileged extensions. If multiple + * supervisor-level extensions are listed, they should be ordered + * alphabetically. + * 4. Non-standard extensions (starts with 'X') must be listed after all + * standard extensions. They must be separated from other multi-letter + * extensions by an underscore. + */ +static const struct isa_ext_data isa_edata_arr[] = { + ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), + ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), + ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), + ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), + ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), + ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), + ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), + ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), + ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), + ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), + ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), + ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), + ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), + ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), + ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), + ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), + ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), + ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), + ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), + ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), + ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), + ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), + ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), + ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), + ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), + ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), + ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), +}; + +static bool isa_ext_is_enabled(RISCVCPU *cpu, + const struct isa_ext_data *edata) +{ + bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; + + return *ext_enabled; +} + +static void isa_ext_update_enabled(RISCVCPU *cpu, + const struct isa_ext_data *edata, bool en) +{ + bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; + + *ext_enabled = en; +} + const char * const riscv_int_regnames[] = { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -530,7 +603,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); CPUClass *cc = CPU_CLASS(mcc); - int priv_version = -1; + int i, priv_version = -1; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -558,6 +631,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_priv_version(env, priv_version); } + /* Force disable extensions if priv spec version does not match */ + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + (env->priv_ver < isa_edata_arr[i].min_version)) { + isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x%lx because " + "privilege spec version does not match", + isa_edata_arr[i].name, (unsigned long)env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + isa_edata_arr[i].name); +#endif + } + } + if (cpu->cfg.mmu) { riscv_set_feature(env, RISCV_FEATURE_MMU); } @@ -1049,67 +1139,15 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_props(dc, riscv_cpu_properties); } -#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} - static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { char *old = *isa_str; char *new = *isa_str; int i; - /** - * Here are the ordering rules of extension naming defined by RISC-V - * specification : - * 1. All extensions should be separated from other multi-letter extensions - * by an underscore. - * 2. The first letter following the 'Z' conventionally indicates the most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they should be ordered first - * by category, then alphabetically within a category. - * 3. Standard supervisor-level extensions (starts with 'S') should be - * listed after standard unprivileged extensions. If multiple - * supervisor-level extensions are listed, they should be ordered - * alphabetically. - * 4. Non-standard extensions (starts with 'X') must be listed after all - * standard extensions. They must be separated from other multi-letter - * extensions by an underscore. - */ - struct isa_ext_data isa_edata_arr[] = { - ISA_EDATA_ENTRY(zicsr, ext_icsr), - ISA_EDATA_ENTRY(zifencei, ext_ifencei), - ISA_EDATA_ENTRY(zmmul, ext_zmmul), - ISA_EDATA_ENTRY(zfh, ext_zfh), - ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), - ISA_EDATA_ENTRY(zfinx, ext_zfinx), - ISA_EDATA_ENTRY(zdinx, ext_zdinx), - ISA_EDATA_ENTRY(zba, ext_zba), - ISA_EDATA_ENTRY(zbb, ext_zbb), - ISA_EDATA_ENTRY(zbc, ext_zbc), - ISA_EDATA_ENTRY(zbkb, ext_zbkb), - ISA_EDATA_ENTRY(zbkc, ext_zbkc), - ISA_EDATA_ENTRY(zbkx, ext_zbkx), - ISA_EDATA_ENTRY(zbs, ext_zbs), - ISA_EDATA_ENTRY(zk, ext_zk), - ISA_EDATA_ENTRY(zkn, ext_zkn), - ISA_EDATA_ENTRY(zknd, ext_zknd), - ISA_EDATA_ENTRY(zkne, ext_zkne), - ISA_EDATA_ENTRY(zknh, ext_zknh), - ISA_EDATA_ENTRY(zkr, ext_zkr), - ISA_EDATA_ENTRY(zks, ext_zks), - ISA_EDATA_ENTRY(zksed, ext_zksed), - ISA_EDATA_ENTRY(zksh, ext_zksh), - ISA_EDATA_ENTRY(zkt, ext_zkt), - ISA_EDATA_ENTRY(zve32f, ext_zve32f), - ISA_EDATA_ENTRY(zve64f, ext_zve64f), - ISA_EDATA_ENTRY(zhinx, ext_zhinx), - ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), - ISA_EDATA_ENTRY(svinval, ext_svinval), - ISA_EDATA_ENTRY(svnapot, ext_svnapot), - ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), - }; - for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].enabled) { + if (isa_edata_arr[i].multi_letter && + isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old = new;