From patchwork Tue Jun 28 15:16:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BBA9C433EF for ; Tue, 28 Jun 2022 15:14:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348076AbiF1PO4 (ORCPT ); Tue, 28 Jun 2022 11:14:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347400AbiF1POu (ORCPT ); Tue, 28 Jun 2022 11:14:50 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B92312E0A9; Tue, 28 Jun 2022 08:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429281; x=1687965281; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IgGvk89Bc+42ZUiXvrFHgLkYiCceXITtHh8Rf1Vwam0=; b=QaCFKa5V0LRgGfcLDVlcHN801qop42E1nakRxRx8Sy8S+EMW8alF98Ws GzOCEFDRM5zrb13K95mt3JIhbvU7bgLx8PJ2l9v/KtnFUxzUFjoROadVZ NN/CeklqAdyVxXbBdQyFnsMyA49rQ2wt+ILWeLxKiTH/SIQK/helUesc1 gwr/Tq2jD+Jrwm3znnmEavrg7IK8/7D/G2m2dALD0mzcYCD5AdaZ4qtfn LZW8Nc0AM//B9EIK87VrAEDWJnntM9l3J2SjgRejgQTn7s61eiibckTQ9 K1VQpXgAkfMWYok7+lttVJAm1z1c0ZdGlfj7Sb2Qu1s1tTQIgUtaFBCac g==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="162420824" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:14:19 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:15 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:12 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 01/19] iio: adc: at91-sama5d2_adc: fix AT91_SAMA5D2_MR_TRACKTIM_MAX Date: Tue, 28 Jun 2022 18:16:13 +0300 Message-ID: <20220628151631.3116454-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org All ADC HW versions handled by this driver (SAMA5D2, SAM9X60, SAMA7G5) have MR.TRACKTIM on 4 bits. Fix AT91_SAMA5D2_MR_TRACKTIM_MAX to reflect this. Fixes: 27e177190891 ("iio:adc:at91_adc8xx: introduce new atmel adc driver") Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index b764823ce57e..32b6f157b803 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -77,7 +77,7 @@ struct at91_adc_reg_layout { #define AT91_SAMA5D2_MR_ANACH BIT(23) /* Tracking Time */ #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) -#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff +#define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf /* Transfer Time */ #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3 From patchwork Tue Jun 28 15:16:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97367CCA47F for ; Tue, 28 Jun 2022 15:14:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347662AbiF1PO3 (ORCPT ); Tue, 28 Jun 2022 11:14:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347435AbiF1POX (ORCPT ); Tue, 28 Jun 2022 11:14:23 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68B752DD47; Tue, 28 Jun 2022 08:14:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429260; x=1687965260; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NNq6gdlQsaf7ue8ni5xZBhwoM33UgV11nIU8tW4lZbk=; b=XyxeKBNeFO5fhWxGNWjo66qZVkCk9FtDP4heW6HqYU9UVZaT6N7yTYr8 xj50ZoC6NS/iHzqBaey220eOa8cdGqOw6M6SJzhTtg73ldjWdCqQw9Siq vIaaMQgZrwMLPjLIya9ko17qCA8QKkrjVbPAQHT42sYEUYhMOIx4BEnQJ DB9gNrxwF3y6BWLDJ4TW4ep3ux6WnPcD3pLSFJvxrWbQywivDz+jVIyTc r+VZV32GSSVqD+lVzr9HEGqWL6dTGhy3ewQyCYDRW1ywi7/8KU/kwcTxf RWRp3UpcD029RRzRQv4tqJ0RCwFmjMCFcf7Fow43DaqsVkCAKNOGM240v A==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="170219090" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:14:19 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:19 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:16 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 02/19] iio: adc: at91-sama5d2_adc: check return status for pressure and touch Date: Tue, 28 Jun 2022 18:16:14 +0300 Message-ID: <20220628151631.3116454-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Check return status of at91_adc_read_position() and at91_adc_read_pressure() in at91_adc_read_info_raw(). Fixes: 6794e23fa3fe ("iio: adc: at91-sama5d2_adc: add support for oversampling resolution") Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 32b6f157b803..c3301c749164 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -1544,8 +1544,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, *val = tmp_val; mutex_unlock(&st->lock); iio_device_release_direct_mode(indio_dev); + if (ret > 0) + ret = at91_adc_adjust_val_osr(st, val); - return at91_adc_adjust_val_osr(st, val); + return ret; } if (chan->type == IIO_PRESSURE) { ret = iio_device_claim_direct_mode(indio_dev); @@ -1558,8 +1560,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, *val = tmp_val; mutex_unlock(&st->lock); iio_device_release_direct_mode(indio_dev); + if (ret > 0) + ret = at91_adc_adjust_val_osr(st, val); - return at91_adc_adjust_val_osr(st, val); + return ret; } /* in this case we have a voltage channel */ From patchwork Tue Jun 28 15:16:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCA1AC433EF for ; Tue, 28 Jun 2022 15:14:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346166AbiF1PO0 (ORCPT ); Tue, 28 Jun 2022 11:14:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347648AbiF1POY (ORCPT ); Tue, 28 Jun 2022 11:14:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 940E92D1CE; Tue, 28 Jun 2022 08:14:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429263; x=1687965263; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q7FahIoKfYcG6zpF9uJ/ng+YHB8nrWgCQyPp3cp9kiw=; b=H1ZZ+AtEqQq46RlOFH4t/z9YW+O9UdvQk5Tt2ejzU422aJRFqgvsShiv FRSrwc8ip//n6dBAPT9PYHQK4P9EJbjpvAl4+6hzFPcgoUndlnL+55jGh 3H/+73rsWaj/zeqN5xEh/O0syeb1o1JFysk1Nqo5dc6ne53pCXHV7SB7/ 8C+A4NOpIG5lLsBMk0lzrk+aHIsPxZTienWzyAGlvU7dSTZ3OuYa/HMg1 3GOvfUiDivDDtWvHIIVRMbBi36vssF11mDVVDAzOWIerCknZ2iPOwvGo2 ezGW6AAJl1mIWqmwYmXDfhBDHTdAKl5j6WGFE562sYqp9dgTXt+W/CZnI g==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="165465254" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:14:23 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:22 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:19 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 03/19] iio: adc: at91-sama5d2_adc: lock around oversampling and sample freq Date: Tue, 28 Jun 2022 18:16:15 +0300 Message-ID: <20220628151631.3116454-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org .read_raw()/.write_raw() could be called asynchronously from user space or other in kernel drivers. Without locking on st->lock these could be called asynchronously while there is a conversion in progress. Read will be harmless but changing registers while conversion is in progress may lead to inconsistent results. Thus, to avoid this lock st->lock. Fixes: 27e177190891 ("iio:adc:at91_adc8xx: introduce new atmel adc driver") Fixes: 6794e23fa3fe ("iio: adc: at91-sama5d2_adc: add support for oversampling resolution") Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index c3301c749164..40a95d2fd5c8 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -1542,10 +1542,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, ret = at91_adc_read_position(st, chan->channel, &tmp_val); *val = tmp_val; - mutex_unlock(&st->lock); - iio_device_release_direct_mode(indio_dev); if (ret > 0) ret = at91_adc_adjust_val_osr(st, val); + mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); return ret; } @@ -1558,10 +1558,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, ret = at91_adc_read_pressure(st, chan->channel, &tmp_val); *val = tmp_val; - mutex_unlock(&st->lock); - iio_device_release_direct_mode(indio_dev); if (ret > 0) ret = at91_adc_adjust_val_osr(st, val); + mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); return ret; } @@ -1650,16 +1650,20 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, /* if no change, optimize out */ if (val == st->oversampling_ratio) return 0; + mutex_lock(&st->lock); st->oversampling_ratio = val; /* update ratio */ at91_adc_config_emr(st); + mutex_unlock(&st->lock); return 0; case IIO_CHAN_INFO_SAMP_FREQ: if (val < st->soc_info.min_sample_rate || val > st->soc_info.max_sample_rate) return -EINVAL; + mutex_lock(&st->lock); at91_adc_setup_samp_freq(indio_dev, val); + mutex_unlock(&st->lock); return 0; default: return -EINVAL; From patchwork Tue Jun 28 15:16:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C152CCA485 for ; Tue, 28 Jun 2022 15:14:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347875AbiF1POa (ORCPT ); Tue, 28 Jun 2022 11:14:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347785AbiF1PO2 (ORCPT ); Tue, 28 Jun 2022 11:14:28 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C20A22D1D2; Tue, 28 Jun 2022 08:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429266; x=1687965266; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OXG7YlbsOZ3z/WgmYcYRa9YBKV8mMjd6Oe/SsZqOqYE=; b=jWJnBVryta3aRa1IW3REBpozbQDOXoKuDHvtkrDgl0xiuoZkiBDLnHb/ NUocSLrotxc5NekcPwDsHVapjWsyrNj5f52IaXbqzUFfU18A9lcaQ0lWO qOMQsJFKLbJjGOCERorNXtKARe9ySuWVn/oHKHRV/ER1W8XVStCxFwieg MOeMZ7c1FEBerHudI0cbjYX7aWukZFVw4BY9DrPlECVZ/dCKQ3b2XJNjR YGkRRDpBldXnN0NO4/aYSXY9ohuHi2GSWMIq0HaDVtFZujECeN6+/TGKt oJXQshgJsEYeKRwE/hR9fuykSAxlFik/b/5R8ko/4st+rCtfUlt+3UYF+ g==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="170219131" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:14:26 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:26 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:23 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 04/19] iio: adc: at91-sama5d2_adc: disable/prepare buffer on suspend/resume Date: Tue, 28 Jun 2022 18:16:16 +0300 Message-ID: <20220628151631.3116454-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org In case triggered buffers are enabled while system is suspended they will not work anymore after resume. For this call at91_adc_buffer_postdisable() on suspend and at91_adc_buffer_prepare() on resume. On tests it has been seen that at91_adc_buffer_postdisable() call is not necessary but it has been kept because it also does the book keeping for DMA. On resume path there is no need to call at91_adc_configure_touch() as it is embedded in at91_adc_buffer_prepare(). Fixes: 073c662017f2f ("iio: adc: at91-sama5d2_adc: add support for DMA") Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 40a95d2fd5c8..2c087d52f164 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -2116,6 +2116,9 @@ static __maybe_unused int at91_adc_suspend(struct device *dev) struct iio_dev *indio_dev = dev_get_drvdata(dev); struct at91_adc_state *st = iio_priv(indio_dev); + if (iio_buffer_enabled(indio_dev)) + at91_adc_buffer_postdisable(indio_dev); + /* * Do a sofware reset of the ADC before we go to suspend. * this will ensure that all pins are free from being muxed by the ADC @@ -2159,14 +2162,11 @@ static __maybe_unused int at91_adc_resume(struct device *dev) if (!iio_buffer_enabled(indio_dev)) return 0; - /* check if we are enabling triggered buffer or the touchscreen */ - if (at91_adc_current_chan_is_touch(indio_dev)) - return at91_adc_configure_touch(st, true); - else - return at91_adc_configure_trigger(st->trig, true); + ret = at91_adc_buffer_prepare(indio_dev); + if (ret) + goto vref_disable_resume; - /* not needed but more explicit */ - return 0; + return at91_adc_configure_trigger(st->trig, true); vref_disable_resume: regulator_disable(st->vref); From patchwork Tue Jun 28 15:16:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6AFBC433EF for ; Tue, 28 Jun 2022 15:15:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347965AbiF1PPE (ORCPT ); Tue, 28 Jun 2022 11:15:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348020AbiF1POu (ORCPT ); Tue, 28 Jun 2022 11:14:50 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E17E72E6A3; Tue, 28 Jun 2022 08:14:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429282; x=1687965282; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Jcvo0wu+k5u2pzIapeqAAgKTFCFIWAriQznaF6vAo8M=; b=SHwJPv09ys6XqBp0lMsUsytOkBQclmbgBL2YnW2m1ll8ELAY664hdct2 Q6psuygsKC+gET2k0F9GEE0jzm9Rtg6Es7P3IE8xJlLIT1NA6Ti7y6Czq +8k0KzoAWNW5GleyAODNOKCjEfIDO3bQo+AvTpIdYLoIIOEeZpHhiOCWd rh7DJz2Py1hA7iisUe1RXqXpHR6A2Wsa9Edp57G1O2XEIQ/d0BczIrYpA myxI5qlDNFNfttRd3ExApG+yILda8IEc4RhpVlgJ7SupNKPHYRrjleS7j h6xb4Nx7/dltCoHMvzFFgwY5xQ4nDq2PfOLhdJMpGijdTBM36IptB4TzA A==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="162420840" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:14:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:29 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:26 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 05/19] iio: adc: at91-sama5d2_adc: exit from write_raw() when buffers are enabled Date: Tue, 28 Jun 2022 18:16:17 +0300 Message-ID: <20220628151631.3116454-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org When buffers are enabled conversion may start asynchronously thus allowing changes on actual hardware could lead to bad behavior. Thus do not allow changing oversampling ratio and sample frequency when if iio_device_claim_direct_mode() returns with error. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 2c087d52f164..cd2b8190a8da 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -1641,6 +1641,7 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, int val, int val2, long mask) { struct at91_adc_state *st = iio_priv(indio_dev); + int ret; switch (mask) { case IIO_CHAN_INFO_OVERSAMPLING_RATIO: @@ -1650,20 +1651,29 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, /* if no change, optimize out */ if (val == st->oversampling_ratio) return 0; + + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; mutex_lock(&st->lock); st->oversampling_ratio = val; /* update ratio */ at91_adc_config_emr(st); mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); return 0; case IIO_CHAN_INFO_SAMP_FREQ: if (val < st->soc_info.min_sample_rate || val > st->soc_info.max_sample_rate) return -EINVAL; + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; mutex_lock(&st->lock); at91_adc_setup_samp_freq(indio_dev, val); mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); return 0; default: return -EINVAL; From patchwork Tue Jun 28 15:16:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B807CCA483 for ; Tue, 28 Jun 2022 15:14:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347979AbiF1POg (ORCPT ); Tue, 28 Jun 2022 11:14:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347972AbiF1POf (ORCPT ); Tue, 28 Jun 2022 11:14:35 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D8EE2DA9A; Tue, 28 Jun 2022 08:14:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429274; x=1687965274; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HWcDf5a5gBp8qOH5HkYU1nMmwszw1YOekY+IkOXMEF4=; b=sFfUV9+seoy54VUmDT4gbmeywCGoZ5lOfuPSsOqLCldBNVRpIO8OkHpR +BT/xrmKYD1ISf1w2h7FB5dAHIM3A5S3Gc9Jxt6/Jv89QUPYELckQTTAI U2DRXkDzWGbw4ezJZgclcRtSJiWYnv91JvHcUqqhnd9Qa3yzlizp7aseR EVDwcvNR27DF6f4uzUJoe6nBG4c1iYuzC4esyIEDw0wSH4tPVPVFzIUUM Szqa1jl0xR9Wx8Buc/tnEgGp801/thiBr8oFDpAGRdNbRQ1RxUgD65UVA 7NNXGFOyR0VnS2S6yRDpdRzpO6pMBB/dLfpRwLx8vWMdagucIlOlPW7j1 w==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="165465314" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:14:33 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:33 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:29 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 06/19] iio: adc: at91-sama5d2_adc: handle different EMR.OSR for different hw versions Date: Tue, 28 Jun 2022 18:16:18 +0300 Message-ID: <20220628151631.3116454-7-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org SAMA7G5 introduces 64 and 256 oversampling rates. Due to this EMR.OSR is 3 bits long. Change the code to reflect this. Commit prepares the code for the addition of 64 and 256 oversampling rates. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 31 +++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index cd2b8190a8da..692707b6e3e3 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -138,8 +138,7 @@ struct at91_adc_reg_layout { /* Extended Mode Register */ u16 EMR; /* Extended Mode Register - Oversampling rate */ -#define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) -#define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) +#define AT91_SAMA5D2_EMR_OSR(V, M) (((V) << 16) & (M)) #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 @@ -403,6 +402,7 @@ static const struct at91_adc_reg_layout sama7g5_layout = { * @max_index: highest channel index (highest index may be higher * than the total channel number) * @hw_trig_cnt: number of possible hardware triggers + * @osr_mask: oversampling ratio bitmask on EMR register */ struct at91_adc_platform { const struct at91_adc_reg_layout *layout; @@ -414,6 +414,7 @@ struct at91_adc_platform { unsigned int max_channels; unsigned int max_index; unsigned int hw_trig_cnt; + unsigned int osr_mask; }; /** @@ -612,6 +613,7 @@ static const struct at91_adc_platform sama5d2_platform = { .max_index = AT91_SAMA5D2_MAX_CHAN_IDX, #define AT91_SAMA5D2_HW_TRIG_CNT 3 .hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT, + .osr_mask = GENMASK(17, 16), }; static const struct at91_adc_platform sama7g5_platform = { @@ -627,6 +629,7 @@ static const struct at91_adc_platform sama7g5_platform = { .max_index = AT91_SAMA7G5_MAX_CHAN_IDX, #define AT91_SAMA7G5_HW_TRIG_CNT 3 .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT, + .osr_mask = GENMASK(18, 16), }; static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -725,30 +728,32 @@ static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) at91_adc_writel(st, EOC_IER, BIT(channel)); } -static void at91_adc_config_emr(struct at91_adc_state *st) +static void at91_adc_config_emr(struct at91_adc_state *st, + u32 oversampling_ratio) { /* configure the extended mode register */ unsigned int emr = at91_adc_readl(st, EMR); + unsigned int osr_mask = st->soc_info.platform->osr_mask; /* select oversampling per single trigger event */ emr |= AT91_SAMA5D2_EMR_ASTE(1); /* delete leftover content if it's the case */ - emr &= ~AT91_SAMA5D2_EMR_OSR_MASK; + emr &= ~osr_mask; /* select oversampling ratio from configuration */ - switch (st->oversampling_ratio) { + switch (oversampling_ratio) { case AT91_OSR_1SAMPLES: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) & - AT91_SAMA5D2_EMR_OSR_MASK; + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES, + osr_mask); break; case AT91_OSR_4SAMPLES: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) & - AT91_SAMA5D2_EMR_OSR_MASK; + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES, + osr_mask); break; case AT91_OSR_16SAMPLES: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) & - AT91_SAMA5D2_EMR_OSR_MASK; + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, + osr_mask); break; } @@ -1658,7 +1663,7 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, mutex_lock(&st->lock); st->oversampling_ratio = val; /* update ratio */ - at91_adc_config_emr(st); + at91_adc_config_emr(st, val); mutex_unlock(&st->lock); iio_device_release_direct_mode(indio_dev); return 0; @@ -1838,7 +1843,7 @@ static void at91_adc_hw_init(struct iio_dev *indio_dev) at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate); /* configure extended mode register */ - at91_adc_config_emr(st); + at91_adc_config_emr(st, st->oversampling_ratio); } static ssize_t at91_adc_get_fifo_state(struct device *dev, From patchwork Tue Jun 28 15:16:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C39A5CCA47E for ; Tue, 28 Jun 2022 15:14:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347985AbiF1POw (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="102111302" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:14:38 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:37 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:33 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 07/19] iio: adc: at91-sama5d2_adc: move the check of oversampling in its function Date: Tue, 28 Jun 2022 18:16:19 +0300 Message-ID: <20220628151631.3116454-8-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Oversampling values are checked anyway in at91_adc_emr_config(). Remove the checking of these from at91_adc_write_raw() and return -EINVAL instead in at91_adc_emr_config(). Suggested-by: Jonathan Cameron Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 692707b6e3e3..a0661f097ccb 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -728,8 +728,8 @@ static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) at91_adc_writel(st, EOC_IER, BIT(channel)); } -static void at91_adc_config_emr(struct at91_adc_state *st, - u32 oversampling_ratio) +static int at91_adc_config_emr(struct at91_adc_state *st, + u32 oversampling_ratio) { /* configure the extended mode register */ unsigned int emr = at91_adc_readl(st, EMR); @@ -755,9 +755,13 @@ static void at91_adc_config_emr(struct at91_adc_state *st, emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, osr_mask); break; + default: + return -EINVAL; } at91_adc_writel(st, EMR, emr); + + return 0; } static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) @@ -1650,9 +1654,6 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_OVERSAMPLING_RATIO: - if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) && - (val != AT91_OSR_16SAMPLES)) - return -EINVAL; /* if no change, optimize out */ if (val == st->oversampling_ratio) return 0; @@ -1661,12 +1662,13 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, if (ret) return ret; mutex_lock(&st->lock); - st->oversampling_ratio = val; /* update ratio */ - at91_adc_config_emr(st, val); + ret = at91_adc_config_emr(st, val); + if (!ret) + st->oversampling_ratio = val; mutex_unlock(&st->lock); iio_device_release_direct_mode(indio_dev); - return 0; + return ret; case IIO_CHAN_INFO_SAMP_FREQ: if (val < st->soc_info.min_sample_rate || val > st->soc_info.max_sample_rate) From patchwork Tue Jun 28 15:16:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 800E7CCA47E for ; Tue, 28 Jun 2022 15:15:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348095AbiF1PPE (ORCPT ); Tue, 28 Jun 2022 11:15:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348064AbiF1POv (ORCPT ); Tue, 28 Jun 2022 11:14:51 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21C262ED6E; Tue, 28 Jun 2022 08:14:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429287; x=1687965287; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LLBwFT7zOlDjghvY8E7gpM+cnMMcAX2zZH4sbXs+m74=; b=IdA514FByh/o4Fz194d1VHILaEFLrvW383sQIxx9X0F6uTSjHXxFA/OW tz9fMDtnudJllCe4YR+RzE3iikbDo8WtFsAqarSAfum0Nk4K5f3nsvVmM q6iGm13H+1/TEIMl0zn0d5GMJB7qb2yxnussKoDfwov6TpQfM/d/zCgfo AFAwzYv3gQ1FEO10NHTiaI3pwYVzIdHZWjysMoaw6oCvFZ6OUy9xbLv5o mztKE+JCg+xzyzUQFv43mIDnxNo4RG8YetWImlcMWKFR1EgAUT40XKdbi NBIMGKZaAqNSduWgfqcV7/aMUHAx02wUN27qY6yhDpoGyI0EiazWc7qDt Q==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="169940861" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:14:47 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:40 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:37 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 08/19] iio: adc: at91-sama5d2_adc: drop AT91_OSR_XSAMPLES defines Date: Tue, 28 Jun 2022 18:16:20 +0300 Message-ID: <20220628151631.3116454-9-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Drop AT91_OSR_1SAMPLES, AT91_OSR_4SAMPLES, AT91_OSR_16SAMPLES defines and insted use their values inline. Suggested-by: Jonathan Cameron Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index a0661f097ccb..1dd64e1d999e 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -304,11 +304,6 @@ static const struct at91_adc_reg_layout sama7g5_layout = { #define AT91_HWFIFO_MAX_SIZE_STR "128" #define AT91_HWFIFO_MAX_SIZE 128 -/* Possible values for oversampling ratio */ -#define AT91_OSR_1SAMPLES 1 -#define AT91_OSR_4SAMPLES 4 -#define AT91_OSR_16SAMPLES 16 - #define AT91_SAMA5D2_CHAN_SINGLE(index, num, addr) \ { \ .type = IIO_VOLTAGE, \ @@ -743,15 +738,15 @@ static int at91_adc_config_emr(struct at91_adc_state *st, /* select oversampling ratio from configuration */ switch (oversampling_ratio) { - case AT91_OSR_1SAMPLES: + case 1: emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES, osr_mask); break; - case AT91_OSR_4SAMPLES: + case 4: emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES, osr_mask); break; - case AT91_OSR_16SAMPLES: + case 16: emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, osr_mask); break; @@ -766,13 +761,13 @@ static int at91_adc_config_emr(struct at91_adc_state *st, static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) { - if (st->oversampling_ratio == AT91_OSR_1SAMPLES) { + if (st->oversampling_ratio == 1) { /* * in this case we only have 12 bits of real data, but channel * is registered as 14 bits, so shift left two bits */ *val <<= 2; - } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) { + } else if (st->oversampling_ratio == 4) { /* * in this case we have 13 bits of real data, but channel * is registered as 14 bits, so left shift one bit @@ -1875,9 +1870,9 @@ static IIO_CONST_ATTR(hwfifo_watermark_min, "2"); static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); static IIO_CONST_ATTR(oversampling_ratio_available, - __stringify(AT91_OSR_1SAMPLES) " " - __stringify(AT91_OSR_4SAMPLES) " " - __stringify(AT91_OSR_16SAMPLES)); + __stringify(1) " " + __stringify(4) " " + __stringify(16)); static struct attribute *at91_adc_attributes[] = { &iio_const_attr_oversampling_ratio_available.dev_attr.attr, @@ -1973,7 +1968,7 @@ static int at91_adc_probe(struct platform_device *pdev) bitmap_set(&st->touch_st.channels_bitmask, st->soc_info.platform->touch_chan_p, 1); - st->oversampling_ratio = AT91_OSR_1SAMPLES; + st->oversampling_ratio = 1; ret = of_property_read_u32(pdev->dev.of_node, "atmel,min-sample-rate-hz", From patchwork Tue Jun 28 15:16:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 553E2CCA479 for ; Tue, 28 Jun 2022 15:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348114AbiF1PPK (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="162420900" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:14:46 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:44 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:41 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 09/19] iio: adc: at91-sama5d2_adc: add .read_avail() chan_info ops Date: Tue, 28 Jun 2022 18:16:21 +0300 Message-ID: <20220628151631.3116454-10-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add .read_avail() to chan_info ops which will retrieve the available oversampling ratio. Suggested-by: Jonathan Cameron Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 50 +++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 15 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 1dd64e1d999e..2242ee8dde68 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -319,6 +319,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = { .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .datasheet_name = "CH"#num, \ .indexed = 1, \ } @@ -340,6 +342,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = { .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .datasheet_name = "CH"#num"-CH"#num2, \ .indexed = 1, \ } @@ -359,6 +363,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = { .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .datasheet_name = name, \ } #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \ @@ -374,6 +380,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = { .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .datasheet_name = name, \ } @@ -398,6 +406,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = { * than the total channel number) * @hw_trig_cnt: number of possible hardware triggers * @osr_mask: oversampling ratio bitmask on EMR register + * @oversampling_avail: available oversampling values + * @oversampling_avail_no: number of available oversampling values */ struct at91_adc_platform { const struct at91_adc_reg_layout *layout; @@ -410,6 +420,8 @@ struct at91_adc_platform { unsigned int max_index; unsigned int hw_trig_cnt; unsigned int osr_mask; + unsigned int oversampling_avail[3]; + unsigned int oversampling_avail_no; }; /** @@ -609,6 +621,8 @@ static const struct at91_adc_platform sama5d2_platform = { #define AT91_SAMA5D2_HW_TRIG_CNT 3 .hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT, .osr_mask = GENMASK(17, 16), + .oversampling_avail = { 1, 4, 16, }, + .oversampling_avail_no = 3, }; static const struct at91_adc_platform sama7g5_platform = { @@ -625,6 +639,8 @@ static const struct at91_adc_platform sama7g5_platform = { #define AT91_SAMA7G5_HW_TRIG_CNT 3 .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT, .osr_mask = GENMASK(18, 16), + .oversampling_avail = { 1, 4, 16, }, + .oversampling_avail_no = 3, }; static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -1682,6 +1698,24 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, } } +static int at91_adc_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + struct at91_adc_state *st = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals = (int *)st->soc_info.platform->oversampling_avail; + *type = IIO_VAL_INT; + *length = st->soc_info.platform->oversampling_avail_no; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + static void at91_adc_dma_init(struct at91_adc_state *st) { struct device *dev = &st->indio_dev->dev; @@ -1869,20 +1903,6 @@ static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, static IIO_CONST_ATTR(hwfifo_watermark_min, "2"); static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); -static IIO_CONST_ATTR(oversampling_ratio_available, - __stringify(1) " " - __stringify(4) " " - __stringify(16)); - -static struct attribute *at91_adc_attributes[] = { - &iio_const_attr_oversampling_ratio_available.dev_attr.attr, - NULL, -}; - -static const struct attribute_group at91_adc_attribute_group = { - .attrs = at91_adc_attributes, -}; - static const struct attribute *at91_adc_fifo_attributes[] = { &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, @@ -1892,7 +1912,7 @@ static const struct attribute *at91_adc_fifo_attributes[] = { }; static const struct iio_info at91_adc_info = { - .attrs = &at91_adc_attribute_group, + .read_avail = &at91_adc_read_avail, .read_raw = &at91_adc_read_raw, .write_raw = &at91_adc_write_raw, .update_scan_mode = &at91_adc_update_scan_mode, From patchwork Tue Jun 28 15:16:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3101BCCA47F for ; Tue, 28 Jun 2022 15:15:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348117AbiF1PPK (ORCPT ); Tue, 28 Jun 2022 11:15:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348068AbiF1POw (ORCPT ); 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28 Jun 2022 08:14:49 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:47 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:44 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 10/19] iio: adc: at91-sama5d2_adc: adjust osr based on specific platform data Date: Tue, 28 Jun 2022 18:16:22 +0300 Message-ID: <20220628151631.3116454-11-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org ADC captures data on 12 bits (if oversampling is not enabled). When using oversampling captured data could go up to 14 bits for SAMA5D2 or up to 16 bits for SAMA7G5 (depending on oversampling settings). All the channels that are subject of oversampling are registered as 14 or 16 real bits. Depending on the oversampling settings the ADC converted value need to be shifted up to 14 or 16 to cope with realbits value registered to IIO subsystem. Commit adds platform specific information to know if we run on a system with up to 14 or 16 bits ADC converted data. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 32 ++++++++++++++++++------------ 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 2242ee8dde68..f12f46708f22 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -408,6 +408,7 @@ static const struct at91_adc_reg_layout sama7g5_layout = { * @osr_mask: oversampling ratio bitmask on EMR register * @oversampling_avail: available oversampling values * @oversampling_avail_no: number of available oversampling values + * @chan_realbits: realbits for registered channels */ struct at91_adc_platform { const struct at91_adc_reg_layout *layout; @@ -422,6 +423,7 @@ struct at91_adc_platform { unsigned int osr_mask; unsigned int oversampling_avail[3]; unsigned int oversampling_avail_no; + unsigned int chan_realbits; }; /** @@ -623,6 +625,7 @@ static const struct at91_adc_platform sama5d2_platform = { .osr_mask = GENMASK(17, 16), .oversampling_avail = { 1, 4, 16, }, .oversampling_avail_no = 3, + .chan_realbits = 14, }; static const struct at91_adc_platform sama7g5_platform = { @@ -641,6 +644,7 @@ static const struct at91_adc_platform sama7g5_platform = { .osr_mask = GENMASK(18, 16), .oversampling_avail = { 1, 4, 16, }, .oversampling_avail_no = 3, + .chan_realbits = 16, }; static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -777,19 +781,21 @@ static int at91_adc_config_emr(struct at91_adc_state *st, static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) { - if (st->oversampling_ratio == 1) { - /* - * in this case we only have 12 bits of real data, but channel - * is registered as 14 bits, so shift left two bits - */ - *val <<= 2; - } else if (st->oversampling_ratio == 4) { - /* - * in this case we have 13 bits of real data, but channel - * is registered as 14 bits, so left shift one bit - */ - *val <<= 1; - } + int nbits, diff; + + if (st->oversampling_ratio == 1) + nbits = 12; + else if (st->oversampling_ratio == 4) + nbits = 13; + else if (st->oversampling_ratio == 16) + nbits = 14; + + /* + * We have nbits of real data and channel is registered as + * st->soc_info.platform->chan_realbits, so shift left diff bits. + */ + diff = st->soc_info.platform->chan_realbits - nbits; + *val <<= diff; return IIO_VAL_INT; } From patchwork Tue Jun 28 15:16:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE92CC433EF for ; Tue, 28 Jun 2022 15:15:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348085AbiF1PPN (ORCPT ); Tue, 28 Jun 2022 11:15:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348073AbiF1PO4 (ORCPT ); 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28 Jun 2022 08:14:53 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:50 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:47 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 11/19] iio: adc: at91-sama5d2_adc: add 64 and 256 oversampling ratio Date: Tue, 28 Jun 2022 18:16:23 +0300 Message-ID: <20220628151631.3116454-12-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add 64 and 256 oversampling ratio support. It is necessary for temperature sensor. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 31 +++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index f12f46708f22..254c084f7198 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -142,6 +142,8 @@ struct at91_adc_reg_layout { #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 +#define AT91_SAMA5D2_EMR_OSR_64SAMPLES 3 +#define AT91_SAMA5D2_EMR_OSR_256SAMPLES 4 /* Extended Mode Register - Averaging on single trigger event */ #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) @@ -421,7 +423,7 @@ struct at91_adc_platform { unsigned int max_index; unsigned int hw_trig_cnt; unsigned int osr_mask; - unsigned int oversampling_avail[3]; + unsigned int oversampling_avail[5]; unsigned int oversampling_avail_no; unsigned int chan_realbits; }; @@ -642,8 +644,8 @@ static const struct at91_adc_platform sama7g5_platform = { #define AT91_SAMA7G5_HW_TRIG_CNT 3 .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT, .osr_mask = GENMASK(18, 16), - .oversampling_avail = { 1, 4, 16, }, - .oversampling_avail_no = 3, + .oversampling_avail = { 1, 4, 16, 64, 256, }, + .oversampling_avail_no = 5, .chan_realbits = 16, }; @@ -749,6 +751,15 @@ static int at91_adc_config_emr(struct at91_adc_state *st, /* configure the extended mode register */ unsigned int emr = at91_adc_readl(st, EMR); unsigned int osr_mask = st->soc_info.platform->osr_mask; + int i; + + /* Check against supported oversampling values. */ + for (i = 0; i < st->soc_info.platform->oversampling_avail_no; i++) { + if (oversampling_ratio == st->soc_info.platform->oversampling_avail[i]) + break; + } + if (i == st->soc_info.platform->oversampling_avail_no) + return -EINVAL; /* select oversampling per single trigger event */ emr |= AT91_SAMA5D2_EMR_ASTE(1); @@ -770,8 +781,14 @@ static int at91_adc_config_emr(struct at91_adc_state *st, emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, osr_mask); break; - default: - return -EINVAL; + case 64: + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_64SAMPLES, + osr_mask); + break; + case 256: + emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_256SAMPLES, + osr_mask); + break; } at91_adc_writel(st, EMR, emr); @@ -789,6 +806,10 @@ static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) nbits = 13; else if (st->oversampling_ratio == 16) nbits = 14; + else if (st->oversampling_ratio == 64) + nbits = 15; + else if (st->oversampling_ratio == 256) + nbits = 16; /* * We have nbits of real data and channel is registered as From patchwork Tue Jun 28 15:16:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF3E5CCA479 for ; Tue, 28 Jun 2022 15:15:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348154AbiF1PP1 (ORCPT ); Tue, 28 Jun 2022 11:15:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348092AbiF1PPD (ORCPT ); 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28 Jun 2022 08:14:56 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:54 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:51 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 12/19] iio: adc: at91-sama5d2_adc: move oversampling storage in its function Date: Tue, 28 Jun 2022 18:16:24 +0300 Message-ID: <20220628151631.3116454-13-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Move the storage of oversampling_ratio in at91_adc_config_emr(). This prepares for the next commits. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 254c084f7198..57c78cd23634 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -793,6 +793,8 @@ static int at91_adc_config_emr(struct at91_adc_state *st, at91_adc_writel(st, EMR, emr); + st->oversampling_ratio = oversampling_ratio; + return 0; } @@ -1702,8 +1704,6 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, mutex_lock(&st->lock); /* update ratio */ ret = at91_adc_config_emr(st, val); - if (!ret) - st->oversampling_ratio = val; mutex_unlock(&st->lock); iio_device_release_direct_mode(indio_dev); return ret; From patchwork Tue Jun 28 15:16:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898452 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82E09C433EF for ; Tue, 28 Jun 2022 15:15:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348064AbiF1PPf (ORCPT ); Tue, 28 Jun 2022 11:15:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347240AbiF1PPM (ORCPT ); Tue, 28 Jun 2022 11:15:12 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE163313A4; Tue, 28 Jun 2022 08:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429302; x=1687965302; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wAqMM+KZBfprtJESuWG3hz8002LSWCuMMQEWX6yP8PQ=; b=0fWP/WhbKVUcZ+NZe77FPkuA54mwTB+SFyqJH3HfqQZPz5kqkfZoGuvO tjLk9aWvjzgDvx2HByGcpqqd7cntelekX7deXxjXwXgTL+H4rHl+8DlKC LSDEx8AyuDMb7K5rG6TNdh7qODTiZmRXyIZFuFbAr1mkHHaCqBc4rW3ZU I4OStvyXnuQCAGZ5b7+NrSSn7F4s477EoWgliLZ/ELxGWIpsMt/9Btf9S hF+Hg7HpoCFyEbo+lCuaX7wMUrkP2MfoEA3onouz1b0UC+f4BvoGQu4Yp HM0UikK71r3/JfI3tl5vVoqLJlahd4lxd8jKCPPQsf7EE1asmijB4XNIG Q==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="162421037" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:15:01 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:14:57 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:54 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 13/19] iio: adc: at91-sama5d2_adc: update trackx on emr Date: Tue, 28 Jun 2022 18:16:25 +0300 Message-ID: <20220628151631.3116454-14-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add support for updating trackx bits of EMR register. Having different values of EMR.TRACKX when measuring temperature give a better accuracy. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 57c78cd23634..ee67f944b58c 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -145,6 +145,10 @@ struct at91_adc_reg_layout { #define AT91_SAMA5D2_EMR_OSR_64SAMPLES 3 #define AT91_SAMA5D2_EMR_OSR_256SAMPLES 4 +/* Extended Mode Register - TRACKX */ +#define AT91_SAMA5D2_TRACKX_MASK GENMASK(23, 22) +#define AT91_SAMA5D2_TRACKX(x) (((x) << 22) & \ + AT91_SAMA5D2_TRACKX_MASK) /* Extended Mode Register - Averaging on single trigger event */ #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) @@ -746,7 +750,7 @@ static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) } static int at91_adc_config_emr(struct at91_adc_state *st, - u32 oversampling_ratio) + u32 oversampling_ratio, u32 trackx) { /* configure the extended mode register */ unsigned int emr = at91_adc_readl(st, EMR); @@ -765,7 +769,7 @@ static int at91_adc_config_emr(struct at91_adc_state *st, emr |= AT91_SAMA5D2_EMR_ASTE(1); /* delete leftover content if it's the case */ - emr &= ~osr_mask; + emr &= ~(osr_mask | AT91_SAMA5D2_TRACKX_MASK); /* select oversampling ratio from configuration */ switch (oversampling_ratio) { @@ -791,6 +795,8 @@ static int at91_adc_config_emr(struct at91_adc_state *st, break; } + /* Update trackx. */ + emr |= AT91_SAMA5D2_TRACKX(trackx); at91_adc_writel(st, EMR, emr); st->oversampling_ratio = oversampling_ratio; @@ -1703,7 +1709,7 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, return ret; mutex_lock(&st->lock); /* update ratio */ - ret = at91_adc_config_emr(st, val); + ret = at91_adc_config_emr(st, val, 0); mutex_unlock(&st->lock); iio_device_release_direct_mode(indio_dev); return ret; @@ -1901,7 +1907,7 @@ static void at91_adc_hw_init(struct iio_dev *indio_dev) at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate); /* configure extended mode register */ - at91_adc_config_emr(st, st->oversampling_ratio); + at91_adc_config_emr(st, st->oversampling_ratio, 0); } static ssize_t at91_adc_get_fifo_state(struct device *dev, From patchwork Tue Jun 28 15:16:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BE69C43334 for ; Tue, 28 Jun 2022 15:15:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348089AbiF1PPl (ORCPT ); Tue, 28 Jun 2022 11:15:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348073AbiF1PP0 (ORCPT ); Tue, 28 Jun 2022 11:15:26 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3ED1A31935; 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Tue, 28 Jun 2022 08:15:01 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:14:58 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 14/19] iio: adc: at91-sama5d2_adc: add startup and tracktim as parameter for at91_adc_setup_samp_freq() Date: Tue, 28 Jun 2022 18:16:26 +0300 Message-ID: <20220628151631.3116454-15-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add startup and tracktim as parameter for at91_adc_setup_samp_freq() function. In case of temperature sensor being enabled these parameters will be configured on temperature read request to improve the accuracy of the read temperature. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index ee67f944b58c..3de5d1cb8a12 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -1432,7 +1432,9 @@ static unsigned at91_adc_startup_time(unsigned startup_time_min, return i; } -static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq) +static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq, + unsigned int startup_time, + unsigned int tracktim) { struct at91_adc_state *st = iio_priv(indio_dev); unsigned f_per, prescal, startup, mr; @@ -1440,17 +1442,17 @@ static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq) f_per = clk_get_rate(st->per_clk); prescal = (f_per / (2 * freq)) - 1; - startup = at91_adc_startup_time(st->soc_info.startup_time, - freq / 1000); + startup = at91_adc_startup_time(startup_time, freq / 1000); mr = at91_adc_readl(st, MR); mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK); mr |= AT91_SAMA5D2_MR_STARTUP(startup); mr |= AT91_SAMA5D2_MR_PRESCAL(prescal); + mr |= AT91_SAMA5D2_MR_TRACKTIM(tracktim); at91_adc_writel(st, MR, mr); - dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n", - freq, startup, prescal); + dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u, tracktim=%u\n", + freq, startup, prescal, tracktim); st->current_sample_rate = freq; } @@ -1722,7 +1724,8 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev, if (ret) return ret; mutex_lock(&st->lock); - at91_adc_setup_samp_freq(indio_dev, val); + at91_adc_setup_samp_freq(indio_dev, val, + st->soc_info.startup_time, 0); mutex_unlock(&st->lock); iio_device_release_direct_mode(indio_dev); return 0; @@ -1904,7 +1907,8 @@ static void at91_adc_hw_init(struct iio_dev *indio_dev) at91_adc_writel(st, MR, AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH); - at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate); + at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate, + st->soc_info.startup_time, 0); /* configure extended mode register */ at91_adc_config_emr(st, st->oversampling_ratio, 0); From patchwork Tue Jun 28 15:16:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898454 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2D40CCA47E for ; Tue, 28 Jun 2022 15:15:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348137AbiF1PPo (ORCPT ); Tue, 28 Jun 2022 11:15:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348148AbiF1PP1 (ORCPT ); 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28 Jun 2022 08:15:07 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:15:04 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:15:01 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 15/19] iio: adc: at91-sama5d2_adc: lock around at91_adc_read_info_raw() Date: Tue, 28 Jun 2022 18:16:27 +0300 Message-ID: <20220628151631.3116454-16-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Remove iio_device_{claim, release}_direct_mode() and lock/unlock to &st->lock from at91_adc_read_info_raw(). Instead add a wrapper around at91_adc_read_info_raw() and do there the lock/unlock. This will allow using the at91_adc_read_info_raw() in patch that add support for temperature sensor. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 39 +++++++++++++++--------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 3de5d1cb8a12..04c44b2d574c 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -1579,6 +1579,7 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private) return IRQ_HANDLED; } +/* This needs to be called with direct mode claimed and st->lock locked. */ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { @@ -1591,45 +1592,26 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, * if external trigger is enabled */ if (chan->type == IIO_POSITIONRELATIVE) { - ret = iio_device_claim_direct_mode(indio_dev); - if (ret) - return ret; - mutex_lock(&st->lock); - ret = at91_adc_read_position(st, chan->channel, &tmp_val); *val = tmp_val; if (ret > 0) ret = at91_adc_adjust_val_osr(st, val); - mutex_unlock(&st->lock); - iio_device_release_direct_mode(indio_dev); return ret; } if (chan->type == IIO_PRESSURE) { - ret = iio_device_claim_direct_mode(indio_dev); - if (ret) - return ret; - mutex_lock(&st->lock); - ret = at91_adc_read_pressure(st, chan->channel, &tmp_val); *val = tmp_val; if (ret > 0) ret = at91_adc_adjust_val_osr(st, val); - mutex_unlock(&st->lock); - iio_device_release_direct_mode(indio_dev); return ret; } /* in this case we have a voltage channel */ - ret = iio_device_claim_direct_mode(indio_dev); - if (ret) - return ret; - mutex_lock(&st->lock); - st->chan = chan; at91_adc_cor(st, chan); @@ -1658,9 +1640,25 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, /* Needed to ACK the DRDY interruption */ at91_adc_readl(st, LCDR); + return ret; +} + +static int at91_adc_read_info_locked(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val) +{ + struct at91_adc_state *st = iio_priv(indio_dev); + int ret; + + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + mutex_lock(&st->lock); + ret = at91_adc_read_info_raw(indio_dev, chan, val); mutex_unlock(&st->lock); iio_device_release_direct_mode(indio_dev); + return ret; } @@ -1672,7 +1670,8 @@ static int at91_adc_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_RAW: - return at91_adc_read_info_raw(indio_dev, chan, val); + return at91_adc_read_info_locked(indio_dev, chan, val); + case IIO_CHAN_INFO_SCALE: *val = st->vref_uv / 1000; if (chan->differential) From patchwork Tue Jun 28 15:16:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB985CCA482 for ; Tue, 28 Jun 2022 15:15:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348174AbiF1PPr (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="179860215" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:15:16 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:15:08 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:15:05 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , , Rob Herring Subject: [PATCH v2 16/19] dt-bindings: iio: adc: at91-sama5d2_adc: add id for temperature channel Date: Tue, 28 Jun 2022 18:16:28 +0300 Message-ID: <20220628151631.3116454-17-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add ID for temperature channel of AT91 SAMA5D2 ADC. Signed-off-by: Claudiu Beznea Acked-by: Rob Herring --- include/dt-bindings/iio/adc/at91-sama5d2_adc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/iio/adc/at91-sama5d2_adc.h b/include/dt-bindings/iio/adc/at91-sama5d2_adc.h index 70f99dbdbb42..866d36530583 100644 --- a/include/dt-bindings/iio/adc/at91-sama5d2_adc.h +++ b/include/dt-bindings/iio/adc/at91-sama5d2_adc.h @@ -13,4 +13,7 @@ /* pressure channel index */ #define AT91_SAMA5D2_ADC_P_CHANNEL 26 +/* SAMA7G5 Temperature sensor channel index. */ +#define AT91_SAMA7G5_ADC_TEMP_CHANNEL 31 + #endif From patchwork Tue Jun 28 15:16:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9861CCA47F for ; Tue, 28 Jun 2022 15:15:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348073AbiF1PPp (ORCPT ); Tue, 28 Jun 2022 11:15:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348090AbiF1PP1 (ORCPT ); Tue, 28 Jun 2022 11:15:27 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57E782F655; Tue, 28 Jun 2022 08:15:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429316; x=1687965316; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EbzZOT1QCDQDn8y+2wFiSqWIjXAYahWoMFVyVYWsjPk=; b=oI4fwklBRAbC814nLB1y6f9/ysUnlGJHo11k3wGkFE2Ox/Ajn+d60B5V 24KF9CaJFDTUVBIKoCjHWtSRwSdMaY/K6nd0mt+bFszwsVo7ZDvJjyvdE 0E/4647+Tqgd3fYH9weCxAhww2xVFeUgiLoh/Pgjyaix+CHuxL2pjckiz XJoFzuv+BvzeQ/f8Oj+KWl19bcmEz5t6P7DUwJK1eZ6n2WlG/LybAoyd3 X1XoO8SIyfe3gK2jukLmjBu3EJr0UlpP62kfJP8hMPvucWGMagb+Ox80w VPjT9BKoNUfsnUyhUdYDqau+FCsw8vsHmzfxP2KTtmoni/yA+Eqe7WakK w==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="169941051" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:15:15 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:15:12 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:15:09 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 17/19] iio: adc: at91-sama5d2_adc: add support for temperature sensor Date: Tue, 28 Jun 2022 18:16:29 +0300 Message-ID: <20220628151631.3116454-18-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org The ADC on SAMA7G5 has a dedicated channel (channel 31) for measuring in-SoC temperature. 2 inputs are multiplexed on channel 31, VTEMP and VBG as follows: ` | \ +-----+ VBG --->| | ch31 | | Vtemp --->| |----->| ADC | | / | | | / +-----+ . where: - VTEMP is proportional to the absolute temperature voltage - VBG is a quasi-temperature independent voltage Both VBG and VTEMP are needed to determine the correct in-SoC temperature. At a moment of time only one of these could be measured, the selection being done with bit SRCLCH bit of ACR register. The formula to calculate the temperature is as follows: P1 + (Vref * (VTEMP - P6 - P4 * VBG)) / (VBG * VTEMP_DT) where: - P1, P4, P6 are calibration data retrieved from OTP memory - Vref is the reference voltage for ADC - VTEMP_DT is the voltage sensitivity to temperature and is constant - VTEMP, VBG are the measured values from channel 31 For better resolution before reading the temperature certain settings for oversampling ratio, sample frequency, EMR.TRACKX, MR.TRACKTIM are applied. The initial settings are reapplied at the end of temperature reading. Current support is not integrated with trigger buffers channel 31 not being enabled/disabled in functions at91_adc_buffer_prepare(), at91_adc_buffer_postdisable() thus the conversion for channel 31 is not done in case trigger buffers are enabled. In case of trigger buffers are enabled and temperature requests are received in the driver though at91_adc_read_temp() the at91_adc_read_temp() will return with an error code. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 255 ++++++++++++++++++++++++++++- 1 file changed, 248 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 04c44b2d574c..0e2dab544311 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -26,9 +26,12 @@ #include #include #include +#include #include #include +#include + struct at91_adc_reg_layout { /* Control Register */ u16 CR; @@ -73,10 +76,13 @@ struct at91_adc_reg_layout { /* Startup Time */ #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16) #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16) +/* Minimum startup time for temperature sensor */ +#define AT91_SAMA5D2_MR_STARTUP_TS_MIN (50) /* Analog Change */ #define AT91_SAMA5D2_MR_ANACH BIT(23) /* Tracking Time */ #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) +#define AT91_SAMA5D2_MR_TRACKTIM_TS 6 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xf /* Transfer Time */ #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) @@ -149,6 +155,9 @@ struct at91_adc_reg_layout { #define AT91_SAMA5D2_TRACKX_MASK GENMASK(23, 22) #define AT91_SAMA5D2_TRACKX(x) (((x) << 22) & \ AT91_SAMA5D2_TRACKX_MASK) +/* TRACKX for temperature sensor. */ +#define AT91_SAMA5D2_TRACKX_TS (1) + /* Extended Mode Register - Averaging on single trigger event */ #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) @@ -164,6 +173,8 @@ struct at91_adc_reg_layout { u16 ACR; /* Analog Control Register - Pen detect sensitivity mask */ #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) +/* Analog Control Register - Source last channel */ +#define AT91_SAMA5D2_ACR_SRCLCH BIT(16) /* Touchscreen Mode Register */ u16 TSMR; @@ -231,6 +242,10 @@ struct at91_adc_reg_layout { u16 WPSR; /* Version Register */ u16 VERSION; +/* Temperature Sensor Mode Register */ + u16 TEMPMR; +/* Temperature Sensor Mode - Temperature sensor on */ +#define AT91_SAMA5D2_TEMPMR_TEMPON BIT(0) }; static const struct at91_adc_reg_layout sama5d2_layout = { @@ -285,6 +300,7 @@ static const struct at91_adc_reg_layout sama7g5_layout = { .EOC_IDR = 0x38, .EOC_IMR = 0x3c, .EOC_ISR = 0x40, + .TEMPMR = 0x44, .OVER = 0x4c, .EMR = 0x50, .CWR = 0x54, @@ -391,6 +407,21 @@ static const struct at91_adc_reg_layout sama7g5_layout = { .datasheet_name = name, \ } +#define AT91_SAMA5D2_CHAN_TEMP(num, name, addr) \ + { \ + .type = IIO_TEMP, \ + .channel = num, \ + .address = addr, \ + .scan_index = num, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ + .info_mask_shared_by_all = \ + BIT(IIO_CHAN_INFO_PROCESSED) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .datasheet_name = name, \ + } + #define at91_adc_readl(st, reg) \ readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg) #define at91_adc_read_chan(st, reg) \ @@ -415,6 +446,8 @@ static const struct at91_adc_reg_layout sama7g5_layout = { * @oversampling_avail: available oversampling values * @oversampling_avail_no: number of available oversampling values * @chan_realbits: realbits for registered channels + * @temp_chan: temperature channel index + * @temp_sensor: temperature sensor supported */ struct at91_adc_platform { const struct at91_adc_reg_layout *layout; @@ -430,20 +463,54 @@ struct at91_adc_platform { unsigned int oversampling_avail[5]; unsigned int oversampling_avail_no; unsigned int chan_realbits; + unsigned int temp_chan; + bool temp_sensor; }; +/** + * struct at91_adc_temp_sensor_clb - at91-sama5d2 temperature sensor + * calibration data structure + * @p1: P1 calibration temperature + * @p4: P4 calibration voltage + * @p6: P6 calibration voltage + */ +struct at91_adc_temp_sensor_clb { + u32 p1; + u32 p4; + u32 p6; +}; + +/** + * enum at91_adc_ts_clb_idx - calibration indexes in NVMEM buffer + * @AT91_ADC_TS_CLB_IDX_P1: index for P1 + * @AT91_ADC_TS_CLB_IDX_P4: index for P4 + * @AT91_ADC_TS_CLB_IDX_P6: index for P6 + * @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet in OTP + */ +enum at91_adc_ts_clb_idx { + AT91_ADC_TS_CLB_IDX_P1 = 2, + AT91_ADC_TS_CLB_IDX_P4 = 5, + AT91_ADC_TS_CLB_IDX_P6 = 7, + AT91_ADC_TS_CLB_IDX_MAX = 19, +}; + +/* Temperature sensor calibration - Vtemp voltage sensitivity to temperature. */ +#define AT91_ADC_TS_VTEMP_DT (2080U) + /** * struct at91_adc_soc_info - at91-sama5d2 soc information struct * @startup_time: device startup time * @min_sample_rate: minimum sample rate in Hz * @max_sample_rate: maximum sample rate in Hz * @platform: pointer to the platform structure + * @temp_sensor_clb: temperature sensor calibration data structure */ struct at91_adc_soc_info { unsigned startup_time; unsigned min_sample_rate; unsigned max_sample_rate; const struct at91_adc_platform *platform; + struct at91_adc_temp_sensor_clb temp_sensor_clb; }; struct at91_adc_trigger { @@ -491,6 +558,18 @@ struct at91_adc_touch { struct work_struct workq; }; +/** + * struct at91_adc_temp - at91-sama5d2 temperature information structure + * @sample_period_val: sample period value + * @saved_sample_rate: saved sample rate + * @saved_oversampling: saved oversampling + */ +struct at91_adc_temp { + u16 sample_period_val; + u16 saved_sample_rate; + u16 saved_oversampling; +}; + /* * Buffer size requirements: * No channels * bytes_per_channel(2) + timestamp bytes (8) @@ -518,6 +597,7 @@ struct at91_adc_state { wait_queue_head_t wq_data_available; struct at91_adc_dma dma_st; struct at91_adc_touch touch_st; + struct at91_adc_temp temp_st; struct iio_dev *indio_dev; /* Ensure naturally aligned timestamp */ u16 buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8); @@ -607,6 +687,7 @@ static const struct iio_chan_spec at91_sama7g5_adc_channels[] = { AT91_SAMA5D2_CHAN_DIFF(22, 12, 13, 0x90), AT91_SAMA5D2_CHAN_DIFF(23, 14, 15, 0x98), IIO_CHAN_SOFT_TIMESTAMP(24), + AT91_SAMA5D2_CHAN_TEMP(AT91_SAMA7G5_ADC_TEMP_CHANNEL, "temp", 0xdc), }; static const struct at91_adc_platform sama5d2_platform = { @@ -639,10 +720,13 @@ static const struct at91_adc_platform sama7g5_platform = { .adc_channels = &at91_sama7g5_adc_channels, #define AT91_SAMA7G5_SINGLE_CHAN_CNT 16 #define AT91_SAMA7G5_DIFF_CHAN_CNT 8 +#define AT91_SAMA7G5_TEMP_CHAN_CNT 1 .nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT + - AT91_SAMA7G5_DIFF_CHAN_CNT, + AT91_SAMA7G5_DIFF_CHAN_CNT + + AT91_SAMA7G5_TEMP_CHAN_CNT, #define AT91_SAMA7G5_MAX_CHAN_IDX (AT91_SAMA7G5_SINGLE_CHAN_CNT + \ - AT91_SAMA7G5_DIFF_CHAN_CNT) + AT91_SAMA7G5_DIFF_CHAN_CNT + \ + AT91_SAMA7G5_TEMP_CHAN_CNT) .max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels), .max_index = AT91_SAMA7G5_MAX_CHAN_IDX, #define AT91_SAMA7G5_HW_TRIG_CNT 3 @@ -651,6 +735,8 @@ static const struct at91_adc_platform sama7g5_platform = { .oversampling_avail = { 1, 4, 16, 64, 256, }, .oversampling_avail_no = 5, .chan_realbits = 16, + .temp_sensor = true, + .temp_chan = AT91_SAMA7G5_ADC_TEMP_CHANNEL, }; static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -1190,7 +1276,8 @@ static int at91_adc_buffer_prepare(struct iio_dev *indio_dev) continue; /* these channel types cannot be handled by this trigger */ if (chan->type == IIO_POSITIONRELATIVE || - chan->type == IIO_PRESSURE) + chan->type == IIO_PRESSURE || + chan->type == IIO_TEMP) continue; at91_adc_cor(st, chan); @@ -1232,7 +1319,8 @@ static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) continue; /* these channel types are virtual, no need to do anything */ if (chan->type == IIO_POSITIONRELATIVE || - chan->type == IIO_PRESSURE) + chan->type == IIO_PRESSURE || + chan->type == IIO_TEMP) continue; at91_adc_writel(st, CHDR, BIT(chan->channel)); @@ -1610,12 +1698,19 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, return ret; } - /* in this case we have a voltage channel */ + /* in this case we have a voltage or temperature channel */ st->chan = chan; at91_adc_cor(st, chan); at91_adc_writel(st, CHER, BIT(chan->channel)); + /* + * TEMPMR.TEMPON needs to update after CHER otherwise if none + * of the channels are enabled and TEMPMR.TEMPON = 1 will + * trigger DRDY interruption while preparing for temperature read. + */ + if (chan->type == IIO_TEMP) + at91_adc_writel(st, TEMPMR, AT91_SAMA5D2_TEMPMR_TEMPON); at91_adc_eoc_ena(st, chan->channel); at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START); @@ -1635,6 +1730,8 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, } at91_adc_eoc_dis(st, st->chan->channel); + if (chan->type == IIO_TEMP) + at91_adc_writel(st, TEMPMR, 0U); at91_adc_writel(st, CHDR, BIT(chan->channel)); /* Needed to ACK the DRDY interruption */ @@ -1662,6 +1759,89 @@ static int at91_adc_read_info_locked(struct iio_dev *indio_dev, return ret; } +static void at91_adc_temp_sensor_configure(struct at91_adc_state *st, + bool start) +{ + u32 sample_rate, oversampling_ratio; + u32 startup_time, tracktim, trackx; + + if (start) { + /* + * Configure the sensor for best accuracy: 10MHz frequency, + * oversampling rate of 256, tracktim=0xf and trackx=1. + */ + sample_rate = 10000000U; + oversampling_ratio = 256; + startup_time = AT91_SAMA5D2_MR_STARTUP_TS_MIN; + tracktim = AT91_SAMA5D2_MR_TRACKTIM_TS; + trackx = AT91_SAMA5D2_TRACKX_TS; + + st->temp_st.saved_sample_rate = st->current_sample_rate; + st->temp_st.saved_oversampling = st->oversampling_ratio; + } else { + /* Go back to previous settings. */ + sample_rate = st->temp_st.saved_sample_rate; + oversampling_ratio = st->temp_st.saved_oversampling; + startup_time = st->soc_info.startup_time; + tracktim = 0; + trackx = 0; + } + + at91_adc_setup_samp_freq(st->indio_dev, sample_rate, startup_time, + tracktim); + at91_adc_config_emr(st, oversampling_ratio, trackx); +} + +static int at91_adc_read_temp(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val) +{ + struct at91_adc_state *st = iio_priv(indio_dev); + struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb; + u64 div1, div2; + u32 tmp; + int ret, vbg, vtemp; + + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + mutex_lock(&st->lock); + + at91_adc_temp_sensor_configure(st, true); + + /* Read VBG. */ + tmp = at91_adc_readl(st, ACR); + tmp |= AT91_SAMA5D2_ACR_SRCLCH; + at91_adc_writel(st, ACR, tmp); + ret = at91_adc_read_info_raw(indio_dev, chan, &vbg); + if (ret < 0) + goto restore_config; + + /* Read VTEMP. */ + tmp &= ~AT91_SAMA5D2_ACR_SRCLCH; + at91_adc_writel(st, ACR, tmp); + ret = at91_adc_read_info_raw(indio_dev, chan, &vtemp); + +restore_config: + /* Revert previous settings. */ + at91_adc_temp_sensor_configure(st, false); + mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); + if (ret < 0) + return ret; + + /* + * Temp[milli] = p1[milli] + (vtemp * clb->p6 - clb->p4 * vbg)/ + * (vbg * AT91_ADC_TS_VTEMP_DT) + */ + div1 = DIV_ROUND_CLOSEST_ULL(((u64)vtemp * clb->p6), vbg); + div1 = DIV_ROUND_CLOSEST_ULL((div1 * 1000), AT91_ADC_TS_VTEMP_DT); + div2 = DIV_ROUND_CLOSEST_ULL((u64)clb->p4, AT91_ADC_TS_VTEMP_DT); + div2 *= 1000; + *val = clb->p1 + (int)div1 - (int)div2; + + return ret; +} + static int at91_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -1679,6 +1859,11 @@ static int at91_adc_read_raw(struct iio_dev *indio_dev, *val2 = chan->scan_type.realbits; return IIO_VAL_FRACTIONAL_LOG2; + case IIO_CHAN_INFO_PROCESSED: + if (chan->type != IIO_TEMP) + return -EINVAL; + return at91_adc_read_temp(indio_dev, chan, val); + case IIO_CHAN_INFO_SAMP_FREQ: *val = at91_adc_get_sample_freq(st); return IIO_VAL_INT; @@ -1994,12 +2179,61 @@ static int at91_adc_buffer_and_trigger_init(struct device *dev, return 0; } +static int at91_adc_temp_sensor_init(struct at91_adc_state *st, + struct device *dev) +{ + struct at91_adc_temp_sensor_clb *clb = &st->soc_info.temp_sensor_clb; + struct nvmem_cell *temp_calib; + u32 *buf; + size_t len; + int ret = 0; + + if (!st->soc_info.platform->temp_sensor) + return 0; + + /* Get the calibration data from NVMEM. */ + temp_calib = devm_nvmem_cell_get(dev, "temperature_calib"); + if (IS_ERR(temp_calib)) { + ret = PTR_ERR(temp_calib); + if (ret != -ENOENT) + dev_err(dev, "Failed to get temperature_calib cell!\n"); + return ret; + } + + buf = nvmem_cell_read(temp_calib, &len); + if (IS_ERR(buf)) { + dev_err(dev, "Failed to read calibration data!\n"); + return PTR_ERR(buf); + } + if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) { + dev_err(dev, "Invalid calibration data!\n"); + ret = -EINVAL; + goto free_buf; + } + + /* Store calibration data for later use. */ + clb->p1 = buf[AT91_ADC_TS_CLB_IDX_P1]; + clb->p4 = buf[AT91_ADC_TS_CLB_IDX_P4]; + clb->p6 = buf[AT91_ADC_TS_CLB_IDX_P6]; + + /* + * We prepare here the conversion to milli and also add constant + * factor (5 degrees Celsius) to p1 here to avoid doing it on + * hotpath. + */ + clb->p1 = clb->p1 * 1000 + 5000; + +free_buf: + kfree(buf); + return ret; +} + static int at91_adc_probe(struct platform_device *pdev) { struct iio_dev *indio_dev; struct at91_adc_state *st; struct resource *res; - int ret, i; + int ret, i, num_channels; u32 edge_type = IRQ_TYPE_NONE; indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); @@ -2011,11 +2245,18 @@ static int at91_adc_probe(struct platform_device *pdev) st->soc_info.platform = of_device_get_match_data(&pdev->dev); + ret = at91_adc_temp_sensor_init(st, &pdev->dev); + /* Don't register temperature channel if initialization failed. */ + if (ret) + num_channels = st->soc_info.platform->max_channels - 1; + else + num_channels = st->soc_info.platform->max_channels; + indio_dev->name = dev_name(&pdev->dev); indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; indio_dev->info = &at91_adc_info; indio_dev->channels = *st->soc_info.platform->adc_channels; - indio_dev->num_channels = st->soc_info.platform->max_channels; + indio_dev->num_channels = num_channels; bitmap_set(&st->touch_st.channels_bitmask, st->soc_info.platform->touch_chan_x, 1); From patchwork Tue Jun 28 15:16:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6FFFCCA47E for ; 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X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="165465605" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:15:23 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:15:16 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:15:13 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 18/19] iio: adc: at91-sama5d2_adc: add empty line after functions Date: Tue, 28 Jun 2022 18:16:30 +0300 Message-ID: <20220628151631.3116454-19-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add empty line after function. Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 0e2dab544311..3f47ca643496 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -1367,6 +1367,7 @@ static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio, return trig; } + static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, struct iio_poll_func *pf) { From patchwork Tue Jun 28 15:16:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12898458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5351FC43334 for ; Tue, 28 Jun 2022 15:16:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348111AbiF1PP7 (ORCPT ); Tue, 28 Jun 2022 11:15:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348168AbiF1PPd (ORCPT ); Tue, 28 Jun 2022 11:15:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 507783207E; Tue, 28 Jun 2022 08:15:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656429325; x=1687965325; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=owjqT53cCW8sPUIEHydqILHK6GaPDlfzqdQrDpWN6a4=; b=vtjJBR7TCGT8Q22mewaEoFlaZ8tgKegO1g5IE143NYy7LWVDRMk7wMjI ZoPAHA4CRKy7uNpjl4ZW7LDn+F6KrhWTq2xElAd3c4DV25d95jl3DZJn2 aOhBduyZQ/MobYuE9twXt0VsBIhPGiwZ28TVM+Oag8ZIjUj2OQy+SfOau +YSzSKoxj3S76TznqX1bN84t35BGIqXGoB+femlB8kqgJOOckc9hPBIY8 V0M76CdR/2VNnzJuR0D7eiwU5UdxWjPi54fMVakx0CcBY/RDs4TqHmiSc 3TMuwHZkQsg2T96/uFb+sXqXhYTI/VvPQKTXdBPpIZ7RMB+TRdsnNG3cs Q==; X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="162421252" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 Jun 2022 08:15:24 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Jun 2022 08:15:20 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 28 Jun 2022 08:15:16 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Subject: [PATCH v2 19/19] iio: adc: at91-sama5d2_adc: add runtime pm support Date: Tue, 28 Jun 2022 18:16:31 +0300 Message-ID: <20220628151631.3116454-20-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220628151631.3116454-1-claudiu.beznea@microchip.com> References: <20220628151631.3116454-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add runtime PM support by disabling/enabling ADC's peripheral clock. On simple conversion the ADC's clock is kept enabled just while the conversion is in progress. This includes also temperature conversion. For triggered buffers and touch conversions the ADC clock is kept enabled while the triggered buffers or touch are enabled. Along with it removed the __maybe_unused on suspend() and resume() ops as the dev_pm_ops object members are now filled with SYSTEM_SLEEP_PM_OPS(). Signed-off-by: Claudiu Beznea --- drivers/iio/adc/at91-sama5d2_adc.c | 211 +++++++++++++++++++++++------ 1 file changed, 168 insertions(+), 43 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 3f47ca643496..5be38d6b067b 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -599,6 +600,7 @@ struct at91_adc_state { struct at91_adc_touch touch_st; struct at91_adc_temp temp_st; struct iio_dev *indio_dev; + struct device *dev; /* Ensure naturally aligned timestamp */ u16 buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8); /* @@ -839,9 +841,9 @@ static int at91_adc_config_emr(struct at91_adc_state *st, u32 oversampling_ratio, u32 trackx) { /* configure the extended mode register */ - unsigned int emr = at91_adc_readl(st, EMR); + unsigned int emr, osr; unsigned int osr_mask = st->soc_info.platform->osr_mask; - int i; + int i, ret; /* Check against supported oversampling values. */ for (i = 0; i < st->soc_info.platform->oversampling_avail_no; i++) { @@ -851,40 +853,46 @@ static int at91_adc_config_emr(struct at91_adc_state *st, if (i == st->soc_info.platform->oversampling_avail_no) return -EINVAL; - /* select oversampling per single trigger event */ - emr |= AT91_SAMA5D2_EMR_ASTE(1); - - /* delete leftover content if it's the case */ - emr &= ~(osr_mask | AT91_SAMA5D2_TRACKX_MASK); - /* select oversampling ratio from configuration */ switch (oversampling_ratio) { case 1: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES, - osr_mask); + osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES, + osr_mask); break; case 4: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES, - osr_mask); + osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES, + osr_mask); break; case 16: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, - osr_mask); + osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES, + osr_mask); break; case 64: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_64SAMPLES, - osr_mask); + osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_64SAMPLES, + osr_mask); break; case 256: - emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_256SAMPLES, - osr_mask); + osr = AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_256SAMPLES, + osr_mask); break; } - /* Update trackx. */ - emr |= AT91_SAMA5D2_TRACKX(trackx); + ret = pm_runtime_resume_and_get(st->dev); + if (ret < 0) + return ret; + + emr = at91_adc_readl(st, EMR); + /* select oversampling per single trigger event */ + emr |= AT91_SAMA5D2_EMR_ASTE(1); + /* delete leftover content if it's the case */ + emr &= ~(osr_mask | AT91_SAMA5D2_TRACKX_MASK); + /* Update osr and trackx. */ + emr |= osr | AT91_SAMA5D2_TRACKX(trackx); at91_adc_writel(st, EMR, emr); + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); + st->oversampling_ratio = oversampling_ratio; return 0; @@ -940,15 +948,22 @@ static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf, static int at91_adc_configure_touch(struct at91_adc_state *st, bool state) { u32 clk_khz = st->current_sample_rate / 1000; - int i = 0; + int i = 0, ret; u16 pendbc; u32 tsmr, acr; - if (!state) { + if (state) { + ret = pm_runtime_resume_and_get(st->dev); + if (ret < 0) + return ret; + } else { /* disabling touch IRQs and setting mode to no touch enabled */ at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN); at91_adc_writel(st, TSMR, 0); + + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); return 0; } /* @@ -1089,10 +1104,9 @@ static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val) return IIO_VAL_INT; } -static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) +static void at91_adc_configure_trigger_registers(struct at91_adc_state *st, + bool state) { - struct iio_dev *indio = iio_trigger_get_drvdata(trig); - struct at91_adc_state *st = iio_priv(indio); u32 status = at91_adc_readl(st, TRGR); /* clear TRGMOD */ @@ -1103,6 +1117,26 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) /* set/unset hw trigger */ at91_adc_writel(st, TRGR, status); +} + +static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) +{ + struct iio_dev *indio = iio_trigger_get_drvdata(trig); + struct at91_adc_state *st = iio_priv(indio); + int ret; + + if (state) { + ret = pm_runtime_resume_and_get(st->dev); + if (ret < 0) + return ret; + } + + at91_adc_configure_trigger_registers(st, state); + + if (!state) { + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); + } return 0; } @@ -1261,11 +1295,15 @@ static int at91_adc_buffer_prepare(struct iio_dev *indio_dev) if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES)) return -EINVAL; + ret = pm_runtime_resume_and_get(st->dev); + if (ret < 0) + return ret; + /* we continue with the triggered buffer */ ret = at91_adc_dma_start(indio_dev); if (ret) { dev_err(&indio_dev->dev, "buffer prepare failed\n"); - return ret; + goto pm_runtime_put; } for_each_set_bit(bit, indio_dev->active_scan_mask, @@ -1288,12 +1326,16 @@ static int at91_adc_buffer_prepare(struct iio_dev *indio_dev) if (at91_adc_buffer_check_use_irq(indio_dev, st)) at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY); - return 0; +pm_runtime_put: + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); + return ret; } static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) { struct at91_adc_state *st = iio_priv(indio_dev); + int ret; u8 bit; /* check if we are disabling triggered buffer or the touchscreen */ @@ -1304,6 +1346,10 @@ static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) if (!(iio_device_get_current_mode(indio_dev) & INDIO_ALL_TRIGGERED_MODES)) return -EINVAL; + ret = pm_runtime_resume_and_get(st->dev); + if (ret < 0) + return ret; + /* * For each enable channel we must disable it in hardware. * In the case of DMA, we must read the last converted value @@ -1339,6 +1385,9 @@ static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) if (st->dma_st.dma_chan) dmaengine_terminate_sync(st->dma_st.dma_chan); + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); + return 0; } @@ -1527,12 +1576,17 @@ static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq, { struct at91_adc_state *st = iio_priv(indio_dev); unsigned f_per, prescal, startup, mr; + int ret; f_per = clk_get_rate(st->per_clk); prescal = (f_per / (2 * freq)) - 1; startup = at91_adc_startup_time(startup_time, freq / 1000); + ret = pm_runtime_resume_and_get(st->dev); + if (ret < 0) + return; + mr = at91_adc_readl(st, MR); mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK); mr |= AT91_SAMA5D2_MR_STARTUP(startup); @@ -1540,6 +1594,9 @@ static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq, mr |= AT91_SAMA5D2_MR_TRACKTIM(tracktim); at91_adc_writel(st, MR, mr); + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); + dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u, tracktim=%u\n", freq, startup, prescal, tracktim); st->current_sample_rate = freq; @@ -1676,6 +1733,10 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, u16 tmp_val; int ret; + ret = pm_runtime_resume_and_get(st->dev); + if (ret < 0) + return ret; + /* * Keep in mind that we cannot use software trigger or touchscreen * if external trigger is enabled @@ -1687,7 +1748,7 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, if (ret > 0) ret = at91_adc_adjust_val_osr(st, val); - return ret; + goto pm_runtime_put; } if (chan->type == IIO_PRESSURE) { ret = at91_adc_read_pressure(st, chan->channel, @@ -1696,7 +1757,7 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, if (ret > 0) ret = at91_adc_adjust_val_osr(st, val); - return ret; + goto pm_runtime_put; } /* in this case we have a voltage or temperature channel */ @@ -1738,6 +1799,9 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, /* Needed to ACK the DRDY interruption */ at91_adc_readl(st, LCDR); +pm_runtime_put: + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); return ret; } @@ -1807,6 +1871,10 @@ static int at91_adc_read_temp(struct iio_dev *indio_dev, return ret; mutex_lock(&st->lock); + ret = pm_runtime_resume_and_get(st->dev); + if (ret < 0) + goto unlock; + at91_adc_temp_sensor_configure(st, true); /* Read VBG. */ @@ -1825,6 +1893,9 @@ static int at91_adc_read_temp(struct iio_dev *indio_dev, restore_config: /* Revert previous settings. */ at91_adc_temp_sensor_configure(st, false); + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); +unlock: mutex_unlock(&st->lock); iio_device_release_direct_mode(indio_dev); if (ret < 0) @@ -2369,13 +2440,19 @@ static int at91_adc_probe(struct platform_device *pdev) if (ret) goto vref_disable; - at91_adc_hw_init(indio_dev); - platform_set_drvdata(pdev, indio_dev); + st->dev = &pdev->dev; + pm_runtime_set_autosuspend_delay(st->dev, 500); + pm_runtime_use_autosuspend(st->dev); + pm_runtime_set_active(st->dev); + pm_runtime_enable(st->dev); + pm_runtime_get_noresume(st->dev); + + at91_adc_hw_init(indio_dev); ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev); if (ret < 0) - goto per_clk_disable_unprepare; + goto err_pm_disable; if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32))) dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n"); @@ -2391,11 +2468,18 @@ static int at91_adc_probe(struct platform_device *pdev) dev_info(&pdev->dev, "version: %x\n", readl_relaxed(st->base + st->soc_info.platform->layout->VERSION)); + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); + return 0; dma_disable: at91_adc_dma_disable(st); -per_clk_disable_unprepare: +err_pm_disable: + pm_runtime_put_noidle(st->dev); + pm_runtime_disable(st->dev); + pm_runtime_set_suspended(st->dev); + pm_runtime_dont_use_autosuspend(st->dev); clk_disable_unprepare(st->per_clk); vref_disable: regulator_disable(st->vref); @@ -2413,6 +2497,8 @@ static int at91_adc_remove(struct platform_device *pdev) at91_adc_dma_disable(st); + pm_runtime_disable(st->dev); + pm_runtime_set_suspended(st->dev); clk_disable_unprepare(st->per_clk); regulator_disable(st->vref); @@ -2421,10 +2507,15 @@ static int at91_adc_remove(struct platform_device *pdev) return 0; } -static __maybe_unused int at91_adc_suspend(struct device *dev) +static int at91_adc_suspend(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct at91_adc_state *st = iio_priv(indio_dev); + int ret; + + ret = pm_runtime_resume_and_get(st->dev); + if (ret < 0) + return ret; if (iio_buffer_enabled(indio_dev)) at91_adc_buffer_postdisable(indio_dev); @@ -2437,6 +2528,8 @@ static __maybe_unused int at91_adc_suspend(struct device *dev) */ at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST); + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_noidle(st->dev); clk_disable_unprepare(st->per_clk); regulator_disable(st->vref); regulator_disable(st->reg); @@ -2444,7 +2537,7 @@ static __maybe_unused int at91_adc_suspend(struct device *dev) return pinctrl_pm_select_sleep_state(dev); } -static __maybe_unused int at91_adc_resume(struct device *dev) +static int at91_adc_resume(struct device *dev) { struct iio_dev *indio_dev = dev_get_drvdata(dev); struct at91_adc_state *st = iio_priv(indio_dev); @@ -2466,18 +2559,28 @@ static __maybe_unused int at91_adc_resume(struct device *dev) if (ret) goto vref_disable_resume; + pm_runtime_get_noresume(st->dev); + at91_adc_hw_init(indio_dev); /* reconfiguring trigger hardware state */ - if (!iio_buffer_enabled(indio_dev)) - return 0; + if (iio_buffer_enabled(indio_dev)) { + ret = at91_adc_buffer_prepare(indio_dev); + if (ret) + goto pm_runtime_put; - ret = at91_adc_buffer_prepare(indio_dev); - if (ret) - goto vref_disable_resume; + at91_adc_configure_trigger_registers(st, true); + } + + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_autosuspend(st->dev); - return at91_adc_configure_trigger(st->trig, true); + return 0; +pm_runtime_put: + pm_runtime_mark_last_busy(st->dev); + pm_runtime_put_noidle(st->dev); + clk_disable_unprepare(st->per_clk); vref_disable_resume: regulator_disable(st->vref); reg_disable_resume: @@ -2487,7 +2590,29 @@ static __maybe_unused int at91_adc_resume(struct device *dev) return ret; } -static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); +static int at91_adc_runtime_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct at91_adc_state *st = iio_priv(indio_dev); + + clk_disable(st->per_clk); + + return 0; +} + +static int at91_adc_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct at91_adc_state *st = iio_priv(indio_dev); + + return clk_enable(st->per_clk); +} + +static const struct dev_pm_ops at91_adc_pm_ops = { + SYSTEM_SLEEP_PM_OPS(at91_adc_suspend, at91_adc_resume) + RUNTIME_PM_OPS(at91_adc_runtime_suspend, at91_adc_runtime_resume, + NULL) +}; static const struct of_device_id at91_adc_dt_match[] = { { @@ -2508,7 +2633,7 @@ static struct platform_driver at91_adc_driver = { .driver = { .name = "at91-sama5d2_adc", .of_match_table = at91_adc_dt_match, - .pm = &at91_adc_pm_ops, + .pm = pm_ptr(&at91_adc_pm_ops), }, }; module_platform_driver(at91_adc_driver)