From patchwork Wed Jun 29 12:58:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 12900048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 649D1C433EF for ; Wed, 29 Jun 2022 13:03:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=9zAL0u4DQhopnuc2tUFhbWdNqMwqfIN2GAhL1X239jA=; b=GqFydkn4fsN5bV sJyV9k7JTvzkHv4htmm4OwABwXiAL8hittgT3oaEnhAsm0/V2GR7RoKtWvqro0h0vOXv85Gt3bmfm FMmM01Tv4myzXHkl0HIBtr1rxRW86cPLZt4+LBWg+Ks71FnCQ0rzC7w1Yvn2v3y64hq18+kU0km6C ltq77ipKWvvkYhuiTE1s8IGAFRCfuZ2LGVgO8S33MUjhb69EkNRc0P7mknBgw1gfZK78BQZt6MHtN D0A72tg6EBm8yT8Lg8YujJez4K4o16uIeTqbhvcWaUS67GhJ1PAnGx2ltHVSy0uomzfHxRPdGGUcp fSGSFxPBJElqYemdA6aQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6XKI-00C2qe-KM; Wed, 29 Jun 2022 13:01:52 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6XKA-00C2lf-DU for linux-arm-kernel@lists.infradead.org; Wed, 29 Jun 2022 13:01:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1656507702; x=1688043702; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=XQI/NCJ05Qj6ATNW0MliX+9pwqsKL8TzUkGsAn8/txw=; b=rm/BeFjfzfbpOPeNEIXqKNuTxsA5quKgL/AE7f+txDtS9QFzoq/DnbFV AOUO/LVPU0X3rjyXBny+JXC3WBJPb5d3vAPKRB3hbpboj0jTdEVeINcLn 1XAjunn76SSLzwUJZ0A4Y/cBNtw3aNyotJ5N3npvtfgW3MKesW1nT8tpK wTmq4xCi//Yj87b/+lC7YcaZGntOIW/UNPM+NOOH5JkZb778FQE2LpAG9 xWFG//QYv98TSOkdlU4hqVAK144jQyOBsqouhYIZx2VrYWq+3PuvCx5T4 /UsS4oinykl2kG3kRyX4ogRp06eBN9wwxr18ruLLNqJBhvrakDlSYSzUC g==; X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="162577998" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2022 06:01:37 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 29 Jun 2022 06:01:36 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 29 Jun 2022 06:01:32 -0700 From: Sergiu Moga To: , , , , , CC: , , , , , , "Sergiu Moga" Subject: [PATCH] dt-bindings: spi: convert spi_atmel to json-schema Date: Wed, 29 Jun 2022 15:58:04 +0300 Message-ID: <20220629125804.137099-1-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220629_060142_618917_FBF4C76D X-CRM114-Status: GOOD ( 14.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert SPI binding for Atmel/Microchip SoCs to Device Tree Schema format. Signed-off-by: Sergiu Moga --- .../devicetree/bindings/spi/atmel,spi.yaml | 82 +++++++++++++++++++ .../devicetree/bindings/spi/spi_atmel.txt | 36 -------- 2 files changed, 82 insertions(+), 36 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/atmel,spi.yaml delete mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt diff --git a/Documentation/devicetree/bindings/spi/atmel,spi.yaml b/Documentation/devicetree/bindings/spi/atmel,spi.yaml new file mode 100644 index 000000000000..751618a47235 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/atmel,spi.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/atmel,spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel SPI device + +maintainers: + - Mark Brown + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + oneOf: + - items: + - const: atmel,at91rm9200-spi + - items: + - const: microchip,sam9x60-spi + - items: + - const: microchip,sam9x60-spi + - const: atmel,at91rm9200-spi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cs-gpios: true + + clock-names: + description: + Tuple listing input clock names, "spi_clk" is a required element. + contains: + const: spi_clk + additionalItems: true + + clocks: + maxItems: 1 + + atmel,fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum number of data the RX and TX FIFOs can store for FIFO + capable SPI controllers. + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi1: spi@fffcc000 { + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x4000>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&spi1_clk>; + clock-names = "spi_clk", "str2"; + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; + atmel,fifo-size = <32>; + + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; /* CD */ + spi-max-frequency = <25000000>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt deleted file mode 100644 index 5bb4a8f1df7a..000000000000 --- a/Documentation/devicetree/bindings/spi/spi_atmel.txt +++ /dev/null @@ -1,36 +0,0 @@ -Atmel SPI device - -Required properties: -- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi". -- reg: Address and length of the register set for the device -- interrupts: Should contain spi interrupt -- cs-gpios: chipselects (optional for SPI controller version >= 2 with the - Chip Select Active After Transfer feature). -- clock-names: tuple listing input clock names. - Required elements: "spi_clk" -- clocks: phandles to input clocks. - -Optional properties: -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable SPI controllers. - -Example: - -spi1: spi@fffcc000 { - compatible = "atmel,at91rm9200-spi"; - reg = <0xfffcc000 0x4000>; - interrupts = <13 4 5>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&spi1_clk>; - clock-names = "spi_clk"; - cs-gpios = <&pioB 3 0>; - atmel,fifo-size = <32>; - - mmc-slot@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - gpios = <&pioC 4 0>; /* CD */ - spi-max-frequency = <25000000>; - }; -};