From patchwork Wed Jun 29 19:06:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12900628 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED6DFC43334 for ; Wed, 29 Jun 2022 19:11:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DB41F10EC0E; Wed, 29 Jun 2022 19:11:08 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 75C3C10E102; Wed, 29 Jun 2022 19:11:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656529867; x=1688065867; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=jfAmqb1dthI7paSz0YGOo7/6U7hEbwBWAqRUCGjchtk=; b=Ea0duXJOQ8GTwtmyuUeis2fOmicVUV3E1kSsysv4BD4lH+faUfwlNR7z kQMeUdWBgrLk3T7zNqnE/6rQKgTI0jyA6/HIeB70tLYLW7vVMl8an/6LC sKN/F7SL4t5VrREeU9GmTAc9NjD/7Few2oY2iciMBY7nrpgkKYCsUyHq9 DGeCbcevAiHxDvLYQbXehFuyXMNAHmBanzqA2we7l3Gs79GGjMxepq8Ly TJEcmdhjfPQn8qQ/7ZfsriMO/z5riRTdvEXqK+WCcFw1bjPUl7U1AUtNX HmCfbxqbRsOcbPe6cf7OzcCxd2KMJsLdk3jUsX806kVBHO7MwPMQZNRhs Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="368439052" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="368439052" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:11 -0700 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="733297096" Received: from nwalsh-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.202.136]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:10 -0700 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Wed, 29 Jun 2022 20:06:50 +0100 Message-Id: <20220629190658.395463-1-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For now dump into i915_drm_local.h. Once the uapi on the kernel side is merged, and is part of drm-next, we can sync the kernel headers and remove this. Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das --- lib/i915/i915_drm_local.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h index 9a2273c4..ac35abf6 100644 --- a/lib/i915/i915_drm_local.h +++ b/lib/i915/i915_drm_local.h @@ -23,6 +23,27 @@ extern "C" { #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6 +/* + * Signal to the kernel that the object will need to be accessed via + * the CPU. + * + * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only + * strictly required on platforms where only some of the device memory + * is directly visible or mappable through the CPU, like on DG2+. + * + * One of the placements MUST also be I915_MEMORY_CLASS_SYSTEM, to + * ensure we can always spill the allocation to system memory, if we + * can't place the object in the mappable part of + * I915_MEMORY_CLASS_DEVICE. + * + * Without this hint, the kernel will assume that non-mappable + * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the + * kernel can still migrate the object to the mappable part, as a last + * resort, if userspace ever CPU faults this object, but this might be + * expensive, and so ideally should be avoided. + */ +#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0) + #if defined(__cplusplus) } #endif From patchwork Wed Jun 29 19:06:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12900627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36645C433EF for ; Wed, 29 Jun 2022 19:11:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B00FE10E555; Wed, 29 Jun 2022 19:11:07 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id DEEF710E102; Wed, 29 Jun 2022 19:11:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656529867; x=1688065867; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4R9kNwJRT6503etWl+DK0lW99iyOfJqEud2bG68agnc=; b=Gu+A+nmpLUeJ4S5FffGQbiBwPdW3DT03CZGd1MhddFFbouJP8QM7Cpc0 PWdmGjDSD+bTkxqXG8aMiQGBNfzzmSfUH01xjAYtnQf8x1HGEsqxKrvGu mNHr/GMvA409nbYjQ0L3rKm+b7tSNd9UotrjU30THl1pL8d1D/RUBLkuE sVJhIKNOS7DoLuQ7JDGlNydzLZV3/sFDGcz6eljVTc79eFNpynGWChPOb 87lOqk8Z0v4hbBHrG5sj/FUoz8Vf61lJ5mRwHosepZBlTmsyhFtXf3sty IuXug/JLxIr1cj1F81jsIPgrOREfQDZbZ/25ZGEKgwE45KpQeMbdpvVTc w==; X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="368439064" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="368439064" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:12 -0700 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="733297106" Received: from nwalsh-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.202.136]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:11 -0700 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Wed, 29 Jun 2022 20:06:51 +0100 Message-Id: <20220629190658.395463-2-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629190658.395463-1-matthew.auld@intel.com> References: <20220629190658.395463-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 2/9] lib/i915: wire up optional flags for gem_create_ext X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For now limit to direct callers. Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das --- lib/i915/gem_create.c | 9 ++++++--- lib/i915/gem_create.h | 5 +++-- lib/i915/intel_memory_region.c | 2 +- tests/i915/gem_create.c | 24 ++++++++++++------------ tests/i915/gem_pxp.c | 2 +- 5 files changed, 23 insertions(+), 19 deletions(-) diff --git a/lib/i915/gem_create.c b/lib/i915/gem_create.c index 605c4513..1f9b7fcc 100644 --- a/lib/i915/gem_create.c +++ b/lib/i915/gem_create.c @@ -61,11 +61,12 @@ uint32_t gem_create(int fd, uint64_t size) return handle; } -int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle, +int __gem_create_ext(int fd, uint64_t *size, uint32_t flags, uint32_t *handle, struct i915_user_extension *ext) { struct drm_i915_gem_create_ext create = { .size = *size, + .flags = flags, .extensions = to_user_pointer(ext), }; int err = 0; @@ -86,6 +87,7 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle, * gem_create_ext: * @fd: open i915 drm file descriptor * @size: desired size of the buffer + * @flags: optional flags * @ext: optional extensions chain * * This wraps the GEM_CREATE_EXT ioctl, which allocates a new gem buffer object @@ -93,11 +95,12 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle, * * Returns: The file-private handle of the created buffer object */ -uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext) +uint32_t gem_create_ext(int fd, uint64_t size, uint32_t flags, + struct i915_user_extension *ext) { uint32_t handle; - igt_assert_eq(__gem_create_ext(fd, &size, &handle, ext), 0); + igt_assert_eq(__gem_create_ext(fd, &size, flags, &handle, ext), 0); return handle; } diff --git a/lib/i915/gem_create.h b/lib/i915/gem_create.h index c32a815d..47a9a16d 100644 --- a/lib/i915/gem_create.h +++ b/lib/i915/gem_create.h @@ -12,9 +12,10 @@ int __gem_create(int fd, uint64_t *size, uint32_t *handle); uint32_t gem_create(int fd, uint64_t size); -int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle, +int __gem_create_ext(int fd, uint64_t *size, uint32_t flags, uint32_t *handle, struct i915_user_extension *ext); -uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext); +uint32_t gem_create_ext(int fd, uint64_t size, uint32_t flags, + struct i915_user_extension *ext); void gem_pool_init(void); void gem_pool_dump(void); diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c index 8c5c2df8..ce04c6a3 100644 --- a/lib/i915/intel_memory_region.c +++ b/lib/i915/intel_memory_region.c @@ -208,7 +208,7 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, }; int ret; - ret = __gem_create_ext(fd, size, handle, &ext_regions.base); + ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base); /* * Provide fallback for stable kernels if region passed in the array diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c index b61c594b..7198c6ed 100644 --- a/tests/i915/gem_create.c +++ b/tests/i915/gem_create.c @@ -330,38 +330,38 @@ static void create_ext_placement_sanity_check(int fd) * behaviour. */ size = PAGE_SIZE; - igt_assert_eq(__gem_create_ext(fd, &size, &handle, 0), 0); + igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle, 0), 0); gem_close(fd, handle); /* Try some uncreative invalid combinations */ setparam_region.regions = to_user_pointer(®ion_smem); setparam_region.num_regions = 0; size = PAGE_SIZE; - igt_assert_neq(__gem_create_ext(fd, &size, &handle, + igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); setparam_region.regions = to_user_pointer(®ion_smem); setparam_region.num_regions = regions->num_regions + 1; size = PAGE_SIZE; - igt_assert_neq(__gem_create_ext(fd, &size, &handle, + igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); setparam_region.regions = to_user_pointer(®ion_smem); setparam_region.num_regions = -1; size = PAGE_SIZE; - igt_assert_neq(__gem_create_ext(fd, &size, &handle, + igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); setparam_region.regions = to_user_pointer(®ion_invalid); setparam_region.num_regions = 1; size = PAGE_SIZE; - igt_assert_neq(__gem_create_ext(fd, &size, &handle, + igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); setparam_region.regions = to_user_pointer(®ion_invalid); setparam_region.num_regions = 0; size = PAGE_SIZE; - igt_assert_neq(__gem_create_ext(fd, &size, &handle, + igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); uregions = calloc(regions->num_regions + 1, sizeof(uint32_t)); @@ -372,7 +372,7 @@ static void create_ext_placement_sanity_check(int fd) setparam_region.regions = to_user_pointer(uregions); setparam_region.num_regions = regions->num_regions + 1; size = PAGE_SIZE; - igt_assert_neq(__gem_create_ext(fd, &size, &handle, + igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); if (regions->num_regions > 1) { @@ -385,7 +385,7 @@ static void create_ext_placement_sanity_check(int fd) setparam_region.regions = to_user_pointer(dups); setparam_region.num_regions = 2; size = PAGE_SIZE; - igt_assert_neq(__gem_create_ext(fd, &size, &handle, + igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); } } @@ -395,7 +395,7 @@ static void create_ext_placement_sanity_check(int fd) setparam_region.regions = to_user_pointer(uregions); setparam_region.num_regions = regions->num_regions; size = PAGE_SIZE; - igt_assert_neq(__gem_create_ext(fd, &size, &handle, + igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); free(uregions); @@ -411,7 +411,7 @@ static void create_ext_placement_sanity_check(int fd) to_user_pointer(&setparam_region_next); size = PAGE_SIZE; - igt_assert_neq(__gem_create_ext(fd, &size, &handle, + igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); setparam_region.base.next_extension = 0; } @@ -443,7 +443,7 @@ static void create_ext_placement_all(int fd) setparam_region.num_regions = regions->num_regions; size = PAGE_SIZE; - igt_assert_eq(__gem_create_ext(fd, &size, &handle, + igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); gem_close(fd, handle); free(uregions); @@ -472,7 +472,7 @@ static void create_ext_placement_each(int fd) setparam_region.num_regions = 1; size = PAGE_SIZE; - igt_assert_eq(__gem_create_ext(fd, &size, &handle, + igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle, &setparam_region.base), 0); gem_close(fd, handle); } diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c index 5f269bab..65618556 100644 --- a/tests/i915/gem_pxp.c +++ b/tests/i915/gem_pxp.c @@ -40,7 +40,7 @@ static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32 ext = &protected_ext.base; *bo_out = 0; - ret = __gem_create_ext(i915, &size64, bo_out, ext); + ret = __gem_create_ext(i915, &size64, 0, bo_out, ext); return ret; } From patchwork Wed Jun 29 19:06:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12900629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17178C43334 for ; Wed, 29 Jun 2022 19:11:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DAB910EC65; Wed, 29 Jun 2022 19:11:14 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 93E4F10EC4B; Wed, 29 Jun 2022 19:11:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656529872; x=1688065872; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I9/q0/wN9fLoA5X4ltpLiFzBB05RC2mm4NrLgHfuIUI=; b=EtHYIi8Aaud89OZ+NRqecr+cPP7OP/k2jyfF+Z+y4q9m4HhAJrcVcfh8 z8VLfmctoLEBaubW8fOdVf8pSdSE4UVr7dG1P3SIfq2ZTB2mro9cEaN74 ffVGfAgyC42vTyHiHpxttmueay/OnGGcwf4zihSIx8V79wxs8y374c2ds 5s7oXdG4Br0l06vlDWwZUOlwpnYLZGZpOT4Yj9kodxJi+9DBvTZ62p4B0 9GtQrSu66gaQf6ccmG7kIciZBz9YcbUXenkkvb2rJKoUv2V/ByNLatuWH gAW9OieKU/a472PPBkWnWyyosA+zuySTVMlT7vbI/erxVZxHCjO13cH7i Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="368439089" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="368439089" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:13 -0700 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="733297115" Received: from nwalsh-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.202.136]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:12 -0700 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Wed, 29 Jun 2022 20:06:52 +0100 Message-Id: <20220629190658.395463-3-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629190658.395463-1-matthew.auld@intel.com> References: <20220629190658.395463-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 3/9] tests/i915/gem_create: exercise NEEDS_CPU_ACCESS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add some basic tests for this new flag. Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das --- tests/i915/gem_create.c | 309 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 308 insertions(+), 1 deletion(-) diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c index 7198c6ed..1b694c6a 100644 --- a/tests/i915/gem_create.c +++ b/tests/i915/gem_create.c @@ -43,6 +43,8 @@ #include #include #include +#include +#include #include "drm.h" #include "drmtest.h" @@ -317,8 +319,8 @@ static void create_ext_placement_sanity_check(int fd) .memory_class = -1, .memory_instance = -1, }; + uint32_t handle, create_ext_supported_flags; uint64_t size; - uint32_t handle; int i; regions = gem_get_query_memory_regions(fd); @@ -334,6 +336,11 @@ static void create_ext_placement_sanity_check(int fd) gem_close(fd, handle); /* Try some uncreative invalid combinations */ + create_ext_supported_flags = + I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS; + igt_assert_neq(__gem_create_ext(fd, &size, ~create_ext_supported_flags, + &handle, 0), 0); + setparam_region.regions = to_user_pointer(®ion_smem); setparam_region.num_regions = 0; size = PAGE_SIZE; @@ -480,6 +487,295 @@ static void create_ext_placement_each(int fd) free(regions); } +static bool supports_needs_cpu_access(int fd) +{ + struct drm_i915_gem_memory_class_instance regions[] = { + { I915_MEMORY_CLASS_DEVICE, }, + { I915_MEMORY_CLASS_SYSTEM, }, + }; + struct drm_i915_gem_create_ext_memory_regions setparam_region = { + .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, + .regions = to_user_pointer(®ions), + .num_regions = ARRAY_SIZE(regions), + }; + uint64_t size = PAGE_SIZE; + uint32_t handle; + int ret; + + ret = __gem_create_ext(fd, &size, + I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS, + &handle, &setparam_region.base); + if (!ret) { + gem_close(fd, handle); + igt_assert(gem_has_lmem(fd)); /* Should be dgpu only */ + } + + return ret == 0; +} + +static uint32_t batch_create_size(int fd, uint64_t size) +{ + const uint32_t bbe = MI_BATCH_BUFFER_END; + uint32_t handle; + + handle = gem_create(fd, size); + gem_write(fd, handle, 0, &bbe, sizeof(bbe)); + + return handle; +} + +static int upload(int fd, uint32_t handle) +{ + struct drm_i915_gem_exec_object2 exec[2] = {}; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&exec), + .buffer_count = 2, + }; + + /* + * To be reasonably sure that we are not being swindled, let's make + * sure to 'touch' the pages from the GPU first to ensure the object is + * for sure placed in one of requested regions. + */ + exec[0].handle = handle; + exec[1].handle = batch_create_size(fd, PAGE_SIZE); + + return __gem_execbuf(fd, &execbuf); +} + +static int alloc_lmem(int fd, uint32_t *handle, + struct drm_i915_gem_memory_class_instance ci, + uint64_t size, bool cpu_access, bool do_upload) +{ + struct drm_i915_gem_memory_class_instance regions[] = { + ci, { I915_MEMORY_CLASS_SYSTEM, }, + }; + struct drm_i915_gem_create_ext_memory_regions setparam_region = { + .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, + .regions = to_user_pointer(®ions), + }; + uint32_t flags; + + igt_assert_eq(ci.memory_class, I915_MEMORY_CLASS_DEVICE); + + flags = 0; + setparam_region.num_regions = 1; + if (cpu_access) { + flags = I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS, + setparam_region.num_regions = 2; + } + + *handle = gem_create_ext(fd, size, flags, &setparam_region.base); + + if (do_upload) + return upload(fd, *handle); + + return 0; +} + +static void create_ext_cpu_access_sanity_check(int fd) +{ + struct drm_i915_gem_create_ext_memory_regions setparam_region = { + .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS }, + }; + struct drm_i915_query_memory_regions *regions; + uint64_t size = PAGE_SIZE; + uint32_t handle; + int i; + + /* + * The ABI is that FLAG_NEEDS_CPU_ACCESS can only be applied to LMEM + + * SMEM objects. Make sure the kernel follows that, while also checking + * the basic CPU faulting behavour. + */ + + /* Implicit placement; should fail */ + igt_assert_eq(__gem_create_ext(fd, &size, + I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS, + &handle, NULL), -EINVAL); + + regions = gem_get_query_memory_regions(fd); + igt_assert(regions); + igt_assert(regions->num_regions); + + for (i = 0; i < regions->num_regions; i++) { + struct drm_i915_gem_memory_class_instance ci_regions[2] = { + regions->regions[i].region, + { I915_MEMORY_CLASS_SYSTEM, }, + }; + uint32_t *ptr; + + setparam_region.regions = to_user_pointer(ci_regions); + setparam_region.num_regions = 1; + + /* Single explicit placement; should fail */ + igt_assert_eq(__gem_create_ext(fd, &size, + I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS, + &handle, &setparam_region.base), + -EINVAL); + + if (ci_regions[0].memory_class == I915_MEMORY_CLASS_SYSTEM) + continue; + + /* + * Now combine with system memory; should pass. We should also + * be able to fault it. + */ + setparam_region.num_regions = 2; + igt_assert_eq(__gem_create_ext(fd, &size, + I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS, + &handle, &setparam_region.base), + 0); + upload(fd, handle); + ptr = gem_mmap_offset__fixed(fd, handle, 0, size, + PROT_READ | PROT_WRITE); + ptr[0] = 0xdeadbeaf; + gem_close(fd, handle); + + /* + * It should also work just fine without the flag, where in the + * worst case we need to migrate it when faulting it. + */ + igt_assert_eq(__gem_create_ext(fd, &size, + 0, + &handle, &setparam_region.base), + 0); + upload(fd, handle); + ptr = gem_mmap_offset__fixed(fd, handle, 0, size, + PROT_READ | PROT_WRITE); + ptr[0] = 0xdeadbeaf; + gem_close(fd, handle); + } + + free(regions); +} + +static jmp_buf jmp; + +__noreturn static void sigtrap(int sig) +{ + siglongjmp(jmp, sig); +} + +static void trap_sigbus(uint32_t *ptr) +{ + sighandler_t old_sigbus; + + old_sigbus = signal(SIGBUS, sigtrap); + switch (sigsetjmp(jmp, SIGBUS)) { + case SIGBUS: + break; + case 0: + *ptr = 0xdeadbeaf; + default: + igt_assert(!"reached"); + break; + } + signal(SIGBUS, old_sigbus); +} + +/** + * XXX: Remove this once we can safely sync the uapi header with the kernel. + * Should be source compatible either way though. + */ +#define probed_cpu_visible_size rsvd1[0] +static void create_ext_cpu_access_big(int fd) +{ + struct drm_i915_query_memory_regions *regions; + int i; + + /* + * Sanity check that we can still CPU map an overly large object, even + * if it happens to be larger the CPU visible portion of LMEM. Also + * check that an overly large allocation, which can't be spilled into + * system memory does indeed fail. + */ + + regions = gem_get_query_memory_regions(fd); + igt_assert(regions); + igt_assert(regions->num_regions); + + for (i = 0; i < regions->num_regions; i++) { + struct drm_i915_memory_region_info qmr = regions->regions[i]; + struct drm_i915_gem_memory_class_instance ci = qmr.region; + uint64_t size, visible_size, lmem_size; + uint32_t handle; + uint32_t *ptr; + + if (ci.memory_class == I915_MEMORY_CLASS_SYSTEM) + continue; + + lmem_size = qmr.probed_size; + visible_size = qmr.probed_cpu_visible_size; + igt_assert_neq(visible_size, 0); + + if (visible_size <= (0.70 * lmem_size)) { + /* + * Too big. We should still be able to allocate it just + * fine, but faulting should result in tears. + */ + size = visible_size; + igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, true), 0); + ptr = gem_mmap_offset__fixed(fd, handle, 0, size, + PROT_READ | PROT_WRITE); + trap_sigbus(ptr); + gem_close(fd, handle); + + /* + * Too big again, but this time we can spill to system + * memory when faulting the object. + */ + size = visible_size; + igt_assert_eq(alloc_lmem(fd, &handle, ci, size, true, true), 0); + ptr = gem_mmap_offset__fixed(fd, handle, 0, size, + PROT_READ | PROT_WRITE); + ptr[0] = 0xdeadbeaf; + gem_close(fd, handle); + + /* + * Let's also move the upload to after faulting the + * pages. The current behaviour is that the pages are + * only allocated in device memory when initially + * touched by the GPU. With this in mind we should also + * make sure that the pages are indeed migrated, as + * expected. + */ + size = visible_size; + igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, false), 0); + ptr = gem_mmap_offset__fixed(fd, handle, 0, size, + PROT_READ | PROT_WRITE); + ptr[0] = 0xdeadbeaf; /* temp system memory */ + igt_assert_eq(upload(fd, handle), 0); + trap_sigbus(ptr); /* non-mappable device memory */ + gem_close(fd, handle); + } + + /* + * Should fit. We likely need to migrate to the mappable portion + * on fault though, if this device has a small BAR, given how + * large the initial allocation is. + */ + size = visible_size >> 1; + igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, true), 0); + ptr = gem_mmap_offset__fixed(fd, handle, 0, size, + PROT_READ | PROT_WRITE); + ptr[0] = 0xdeadbeaf; + gem_close(fd, handle); + + /* + * And then with the CPU_ACCESS flag enabled; should also be no + * surprises here. + */ + igt_assert_eq(alloc_lmem(fd, &handle, ci, size, true, true), 0); + ptr = gem_mmap_offset__fixed(fd, handle, 0, size, + PROT_READ | PROT_WRITE); + ptr[0] = 0xdeadbeaf; + gem_close(fd, handle); + } + + free(regions); +} + igt_main { int fd = -1; @@ -531,4 +827,15 @@ igt_main igt_subtest("create-ext-placement-all") create_ext_placement_all(fd); + igt_describe("Verify the basic functionally and expected ABI contract around I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS"); + igt_subtest("create-ext-cpu-access-sanity-check") { + igt_require(supports_needs_cpu_access(fd)); + create_ext_cpu_access_sanity_check(fd); + } + + igt_describe("Verify the extreme cases with very large objects and I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS"); + igt_subtest("create-ext-cpu-access-big") { + igt_require(supports_needs_cpu_access(fd)); + create_ext_cpu_access_big(fd); + } } From patchwork Wed Jun 29 19:06:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12900630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15DB6C43334 for ; Wed, 29 Jun 2022 19:11:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 973DB10EC99; Wed, 29 Jun 2022 19:11:22 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1E69810EC88; Wed, 29 Jun 2022 19:11:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656529881; x=1688065881; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qnuqdOMlRBZMD26Jo6TiQSXBOQUdGfrlIsRrelA+8V8=; b=YJFCuOL8d8M+d7NVV/ByKi4k7mAQ/s8DR5Iau4zwCgWGebmKt956PbZC sMyFszjA5o0plHSdsoxfIMu29jhe5zJAxegEcizxPveJuaPbfdwAzZIUM 1vSUc9Ep6Vzc9PB+FEvwRNqD5amx/qRjrN0B0l6YvNkswFOUiX5gPJqFD FJAI8sg4SMNFNC7NW7J63rn0zGKbLJSDlq7+IMtFpC8pTpvGeTWgo8erQ XQT0iX0+l/v5oaSGFpCWKaGn5qjlIVqiQyfYWlFk8z+1yiWTjdNpUOdwA 3ZVb+biT/8WMSKo0PT9hpRB1/Xn9fTN37lBNbfiloG6j+EiCyq7wgFy/+ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="368439122" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="368439122" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:14 -0700 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="733297124" Received: from nwalsh-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.202.136]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:14 -0700 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Wed, 29 Jun 2022 20:06:53 +0100 Message-Id: <20220629190658.395463-4-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629190658.395463-1-matthew.auld@intel.com> References: <20220629190658.395463-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 4/9] lib/i915: add gem_create_with_cpu_access_in_memory_regions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Most users shouldn't care about such an interface, but where required, this should be useful to aid in setting NEEDS_CPU_ACCESS for a given BO. Underneath we try to smooth over needing to provide an explicit SMEM region, or if this is SMEM-only, we don't want the kernel to throw an error. Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das --- lib/i915/intel_memory_region.c | 10 +++-- lib/i915/intel_memory_region.h | 68 ++++++++++++++++++++++++++++++++-- tests/i915/gem_eio.c | 1 + tests/i915/gem_lmem_swapping.c | 2 +- tests/i915/i915_pm_rpm.c | 6 +-- 5 files changed, 75 insertions(+), 12 deletions(-) diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c index ce04c6a3..3173507f 100644 --- a/lib/i915/intel_memory_region.c +++ b/lib/i915/intel_memory_region.c @@ -197,7 +197,7 @@ bool gem_has_lmem(int fd) /* A version of gem_create_in_memory_region_list which can be allowed to fail so that the object creation can be retried */ -int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, +int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, uint32_t flags, struct drm_i915_gem_memory_class_instance *mem_regions, int num_regions) { @@ -208,7 +208,9 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, }; int ret; - ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base); + ret = __gem_create_ext(fd, size, flags, handle, &ext_regions.base); + if (flags && ret == -EINVAL) + ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base); /* * Provide fallback for stable kernels if region passed in the array @@ -231,12 +233,12 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, * @mem_regions: memory regions array (priority list) * @num_regions: @mem_regions length */ -uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, +uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, uint32_t flags, struct drm_i915_gem_memory_class_instance *mem_regions, int num_regions) { uint32_t handle; - int ret = __gem_create_in_memory_region_list(fd, &handle, &size, + int ret = __gem_create_in_memory_region_list(fd, &handle, &size, flags, mem_regions, num_regions); igt_assert_eq(ret, 0); return handle; diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h index a8741724..40ff832d 100644 --- a/lib/i915/intel_memory_region.h +++ b/lib/i915/intel_memory_region.h @@ -22,6 +22,7 @@ */ #include "i915_drm.h" #include "igt_collection.h" +#include "i915_drm_local.h" #ifndef INTEL_MEMORY_REGION_H #define INTEL_MEMORY_REGION_H @@ -63,11 +64,11 @@ unsigned int gem_get_lmem_region_count(int fd); bool gem_has_lmem(int fd); -int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, +int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, uint32_t flags, struct drm_i915_gem_memory_class_instance *mem_regions, int num_regions); -uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, +uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, uint32_t flags, struct drm_i915_gem_memory_class_instance *mem_regions, int num_regions); @@ -83,7 +84,7 @@ uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \ arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \ } \ - __gem_create_in_memory_region_list(fd, handle, size, arr_query__, ARRAY_SIZE(arr_query__)); \ + __gem_create_in_memory_region_list(fd, handle, size, 0, arr_query__, ARRAY_SIZE(arr_query__)); \ }) #define gem_create_in_memory_regions(fd, size, regions...) ({ \ unsigned int arr__[] = { regions }; \ @@ -92,7 +93,66 @@ uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \ arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \ } \ - gem_create_in_memory_region_list(fd, size, arr_query__, ARRAY_SIZE(arr_query__)); \ + gem_create_in_memory_region_list(fd, size, 0, arr_query__, ARRAY_SIZE(arr_query__)); \ +}) + +/* + * Create an object that requires CPU access. This only becomes interesting on + * platforms that have a small BAR for LMEM CPU access. Without this the object + * might need to be migrated when CPU faulting the object, or if that is not + * possible we hit SIGBUS. Most users should be fine with this. If enabled the + * kernel will never allocate this object in the non-CPU visible portion of + * LMEM. + * + * Underneath this just enables the I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS + * flag, if we also have an LMEM placement. Also since the kernel requires SMEM + * as a potential placement, we automatically attach that as a possible + * placement, if not already provided. If this happens to be an SMEM-only + * placement then we don't supply the flag, and instead just treat as normal + * allocation. + */ + +#define __gem_create_with_cpu_access_in_memory_regions(fd, handle, size, regions...) ({ \ + unsigned int arr__[] = { regions }; \ + struct drm_i915_gem_memory_class_instance arr_query__[ARRAY_SIZE(arr__) + 1]; \ + int i__, arr_query_size__ = ARRAY_SIZE(arr__); \ + uint32_t ext_flags__ = 0; \ + bool ext_found_smem__ = false; \ + for (i__ = 0; i__ < arr_query_size__; ++i__) { \ + arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \ + if (arr_query__[i__].memory_class == I915_MEMORY_CLASS_DEVICE) \ + ext_flags__ = I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS; \ + else \ + ext_found_smem__ = true; \ + arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \ + } \ + if (ext_flags__ && !ext_found_smem__) { \ + arr_query__[i__].memory_class = I915_MEMORY_CLASS_SYSTEM; \ + arr_query__[i__].memory_instance = 0; \ + arr_query_size__++; \ + } \ + __gem_create_in_memory_region_list(fd, handle, size, ext_flags__, arr_query__, arr_query_size__); \ +}) +#define gem_create_with_cpu_access_in_memory_regions(fd, size, regions...) ({ \ + unsigned int arr__[] = { regions }; \ + struct drm_i915_gem_memory_class_instance arr_query__[ARRAY_SIZE(arr__) + 1]; \ + int i__, arr_query_size__ = ARRAY_SIZE(arr__); \ + uint32_t ext_flags__ = 0; \ + bool ext_found_smem__ = false; \ + for (i__ = 0; i__ < arr_query_size__; ++i__) { \ + arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \ + if (arr_query__[i__].memory_class == I915_MEMORY_CLASS_DEVICE) \ + ext_flags__ = I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS; \ + else \ + ext_found_smem__ = true; \ + arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \ + } \ + if (ext_flags__ && !ext_found_smem__) { \ + arr_query__[i__].memory_class = I915_MEMORY_CLASS_SYSTEM; \ + arr_query__[i__].memory_instance = 0; \ + arr_query_size__++; \ + } \ + gem_create_in_memory_region_list(fd, size, ext_flags__, arr_query__, arr_query_size__); \ }) struct igt_collection * diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c index 6cbae6eb..70e82b81 100644 --- a/tests/i915/gem_eio.c +++ b/tests/i915/gem_eio.c @@ -146,6 +146,7 @@ static void test_create_ext(int fd) igt_assert_eq(__gem_create_in_memory_region_list(fd, &handle, &size, + 0, &r->ci, 1), 0); diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c index 21c2bf72..1a4f4ca5 100644 --- a/tests/i915/gem_lmem_swapping.c +++ b/tests/i915/gem_lmem_swapping.c @@ -131,7 +131,7 @@ static uint32_t create_bo(int i915, int ret; retry: - ret = __gem_create_in_memory_region_list(i915, &handle, size, region, 1); + ret = __gem_create_in_memory_region_list(i915, &handle, size, 0, region, 1); if (do_oom_test && ret == -ENOMEM) goto retry; igt_assert_eq(ret, 0); diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c index bf145b6c..e95875dc 100644 --- a/tests/i915/i915_pm_rpm.c +++ b/tests/i915/i915_pm_rpm.c @@ -1117,7 +1117,7 @@ static void gem_mmap_args(const struct mmap_offset *t, /* Create, map and set data while the device is active. */ enable_one_screen_or_forcewake_get_and_wait(&ms_data); - handle = gem_create_in_memory_region_list(drm_fd, buf_size, mem_regions, 1); + handle = gem_create_in_memory_region_list(drm_fd, buf_size, 0, mem_regions, 1); gem_buf = __gem_mmap_offset(drm_fd, handle, 0, buf_size, PROT_READ | PROT_WRITE, t->type); @@ -1348,7 +1348,7 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r /* Create and set data while the device is active. */ enable_one_screen_or_forcewake_get_and_wait(&ms_data); - handle = gem_create_in_memory_region_list(drm_fd, dst_size, mem_regions, 1); + handle = gem_create_in_memory_region_list(drm_fd, dst_size, 0, mem_regions, 1); cpu_buf = malloc(dst_size); igt_assert(cpu_buf); @@ -1453,7 +1453,7 @@ gem_execbuf_stress_subtest(int rounds, int wait_flags, if (wait_flags & WAIT_PC8_RES) handle = gem_create(drm_fd, batch_size); else - handle = gem_create_in_memory_region_list(drm_fd, batch_size, mem_regions, 1); + handle = gem_create_in_memory_region_list(drm_fd, batch_size, 0, mem_regions, 1); gem_write(drm_fd, handle, 0, batch_buf, batch_size); From patchwork Wed Jun 29 19:06:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12900631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F8A7C43334 for ; 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a="368439141" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="368439141" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:15 -0700 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="733297135" Received: from nwalsh-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.202.136]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:15 -0700 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Wed, 29 Jun 2022 20:06:54 +0100 Message-Id: <20220629190658.395463-5-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629190658.395463-1-matthew.auld@intel.com> References: <20220629190658.395463-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 5/9] tests/i915/query: sanity check the probed_cpu_visible_size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add some basic sanity checks for this, like checking if this falls within the probed_size. On older kernels the value reported here should be zero. Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das --- tests/i915/i915_query.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index b545fb4a..ea99dc8d 100644 --- a/tests/i915/i915_query.c +++ b/tests/i915/i915_query.c @@ -514,6 +514,11 @@ static bool query_regions_supported(int fd) return __i915_query_items(fd, &item, 1) == 0 && item.length > 0; } +/** + * XXX: Remove these once we can safely sync the uapi header with the kernel. + * Should be source compatible either way though. + */ +#define probed_cpu_visible_size rsvd1[0] static void test_query_regions_garbage_items(int fd) { struct drm_i915_query_memory_regions *regions; @@ -552,7 +557,10 @@ static void test_query_regions_garbage_items(int fd) igt_assert_eq_u32(info.rsvd0, 0); - for (j = 0; j < ARRAY_SIZE(info.rsvd1); j++) + /* + * rsvd1[0] : probed_cpu_visible_size + */ + for (j = 1; j < ARRAY_SIZE(info.rsvd1); j++) igt_assert_eq_u32(info.rsvd1[j], 0); } @@ -587,13 +595,18 @@ static void test_query_regions_sanity_check(int fd) found_system = false; for (i = 0; i < regions->num_regions; i++) { - struct drm_i915_gem_memory_class_instance r1 = - regions->regions[i].region; + struct drm_i915_memory_region_info info = regions->regions[i]; + struct drm_i915_gem_memory_class_instance r1 = info.region; int j; if (r1.memory_class == I915_MEMORY_CLASS_SYSTEM) { igt_assert_eq(r1.memory_instance, 0); found_system = true; + + igt_assert(info.probed_cpu_visible_size == 0 || + info.probed_cpu_visible_size == info.probed_size); + } else { + igt_assert(info.probed_cpu_visible_size <= info.probed_size); } igt_assert(r1.memory_class == I915_MEMORY_CLASS_SYSTEM || From patchwork Wed Jun 29 19:06:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12900632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86C65C43334 for ; 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a="368439176" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="368439176" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:17 -0700 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="733297146" Received: from nwalsh-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.202.136]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:16 -0700 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Wed, 29 Jun 2022 20:06:55 +0100 Message-Id: <20220629190658.395463-6-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629190658.395463-1-matthew.auld@intel.com> References: <20220629190658.395463-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 6/9] tests/i915/query: sanity check the unallocated tracking X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Sanity both the unallocated_size & unallocated_cpu_visible_size tracking. v2(Petri): always use from_user_pointer() Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das --- tests/i915/i915_query.c | 274 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 273 insertions(+), 1 deletion(-) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index ea99dc8d..2bbcfa97 100644 --- a/tests/i915/i915_query.c +++ b/tests/i915/i915_query.c @@ -23,6 +23,8 @@ #include "igt.h" #include "intel_hwconfig_types.h" +#include "i915/gem.h" +#include "i915/gem_create.h" #include @@ -519,6 +521,36 @@ static bool query_regions_supported(int fd) * Should be source compatible either way though. */ #define probed_cpu_visible_size rsvd1[0] +#define unallocated_cpu_visible_size rsvd1[1] +static bool query_regions_unallocated_supported(int fd) +{ + struct drm_i915_query_memory_regions *regions; + struct drm_i915_query_item item; + int i, ret = false; + + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_MEMORY_REGIONS; + i915_query_items(fd, &item, 1); + igt_assert(item.length > 0); + + regions = calloc(1, item.length); + + item.data_ptr = to_user_pointer(regions); + i915_query_items(fd, &item, 1); + + for (i = 0; i < regions->num_regions; i++) { + struct drm_i915_memory_region_info info = regions->regions[i]; + + if (info.unallocated_cpu_visible_size) { + ret = true; + break; + } + } + + free(regions); + return ret; +} + static void test_query_regions_garbage_items(int fd) { struct drm_i915_query_memory_regions *regions; @@ -559,8 +591,9 @@ static void test_query_regions_garbage_items(int fd) /* * rsvd1[0] : probed_cpu_visible_size + * rsvd1[1] : unallocated_cpu_visible_size */ - for (j = 1; j < ARRAY_SIZE(info.rsvd1); j++) + for (j = 2; j < ARRAY_SIZE(info.rsvd1); j++) igt_assert_eq_u32(info.rsvd1[j], 0); } @@ -573,6 +606,46 @@ static void test_query_regions_garbage_items(int fd) free(regions); } +struct object_handle { + uint32_t handle; + struct igt_list_head link; +}; + +static uint32_t batch_create_size(int fd, uint64_t size) +{ + const uint32_t bbe = MI_BATCH_BUFFER_END; + uint32_t handle; + + handle = gem_create(fd, size); + gem_write(fd, handle, 0, &bbe, sizeof(bbe)); + + return handle; +} + +static void upload(int fd, struct igt_list_head *handles, uint32_t num_handles) +{ + struct drm_i915_gem_exec_object2 *exec; + struct drm_i915_gem_execbuffer2 execbuf = {}; + struct object_handle *iter; + uint32_t i; + + exec = calloc(num_handles + 1, + sizeof(struct drm_i915_gem_exec_object2)); + + i = 0; + igt_list_for_each_entry(iter, handles, link) + exec[i++].handle = iter->handle; + + exec[i].handle = batch_create_size(fd, 4096); + + execbuf.buffers_ptr = to_user_pointer(exec); + execbuf.buffer_count = num_handles + 1; + + gem_execbuf(fd, &execbuf); + gem_close(fd, exec[i].handle); + free(exec); +} + static void test_query_regions_sanity_check(int fd) { struct drm_i915_query_memory_regions *regions; @@ -605,8 +678,20 @@ static void test_query_regions_sanity_check(int fd) igt_assert(info.probed_cpu_visible_size == 0 || info.probed_cpu_visible_size == info.probed_size); + igt_assert(info.unallocated_size == info.probed_size); + igt_assert(info.unallocated_cpu_visible_size == 0 || + info.unallocated_cpu_visible_size == + info.unallocated_size); } else { igt_assert(info.probed_cpu_visible_size <= info.probed_size); + igt_assert(info.unallocated_size <= info.probed_size); + if (info.probed_cpu_visible_size < info.probed_size) { + igt_assert(info.unallocated_cpu_visible_size < + info.unallocated_size); + } else { + igt_assert(info.unallocated_cpu_visible_size == + info.unallocated_size); + } } igt_assert(r1.memory_class == I915_MEMORY_CLASS_SYSTEM || @@ -623,6 +708,58 @@ static void test_query_regions_sanity_check(int fd) igt_assert(!(r1.memory_class == r2.memory_class && r1.memory_instance == r2.memory_instance)); } + + { + struct igt_list_head handles; + struct object_handle oh = {}; + + IGT_INIT_LIST_HEAD(&handles); + + oh.handle = + gem_create_with_cpu_access_in_memory_regions + (fd, 4096, + INTEL_MEMORY_REGION_ID(r1.memory_class, + r1.memory_instance)); + igt_list_add(&oh.link, &handles); + upload(fd, &handles, 1); + + /* + * System wide metrics should be censored if we + * lack the correct permissions. + */ + igt_fork(child, 1) { + igt_drop_root(); + + memset(regions, 0, item.length); + i915_query_items(fd, &item, 1); + info = regions->regions[i]; + + igt_assert(info.unallocated_cpu_visible_size == + info.probed_cpu_visible_size); + igt_assert(info.unallocated_size == + info.probed_size); + } + + igt_waitchildren(); + + memset(regions, 0, item.length); + i915_query_items(fd, &item, 1); + info = regions->regions[i]; + + if (r1.memory_class == I915_MEMORY_CLASS_DEVICE) { + igt_assert(info.unallocated_cpu_visible_size < + info.probed_cpu_visible_size); + igt_assert(info.unallocated_size < + info.probed_size); + } else { + igt_assert(info.unallocated_cpu_visible_size == + info.probed_cpu_visible_size); + igt_assert(info.unallocated_size == + info.probed_size); + } + + gem_close(fd, oh.handle); + } } /* All devices should at least have system memory */ @@ -631,6 +768,134 @@ static void test_query_regions_sanity_check(int fd) free(regions); } +#define rounddown(x, y) (x - (x % y)) +#define SZ_64K (1ULL << 16) + +static void fill_unallocated(int fd, struct drm_i915_query_item *item, int idx, + bool cpu_access) +{ + struct drm_i915_memory_region_info new_info, old_info; + struct drm_i915_query_memory_regions *regions; + struct drm_i915_gem_memory_class_instance ci; + struct object_handle *iter, *tmp; + struct igt_list_head handles; + uint32_t num_handles; + uint64_t rem, total; + int id; + + srand(time(NULL)); + + IGT_INIT_LIST_HEAD(&handles); + + regions = from_user_pointer(item->data_ptr); + memset(regions, 0, item->length); + i915_query_items(fd, item, 1); + new_info = regions->regions[idx]; + ci = new_info.region; + + id = INTEL_MEMORY_REGION_ID(ci.memory_class, ci.memory_instance); + + if (cpu_access) + rem = new_info.unallocated_cpu_visible_size / 4; + else + rem = new_info.unallocated_size / 4; + + rem = rounddown(rem, SZ_64K); + igt_assert_neq(rem, 0); + num_handles = 0; + total = 0; + do { + struct object_handle *oh; + uint64_t size; + + size = rand() % rem; + size = rounddown(size, SZ_64K); + size = max_t(uint64_t, size, SZ_64K); + + oh = malloc(sizeof(struct object_handle)); + if (cpu_access) + oh->handle = gem_create_with_cpu_access_in_memory_regions(fd, size, id); + else + oh->handle = gem_create_in_memory_region_list(fd, size, 0, &ci, 1); + igt_list_add(&oh->link, &handles); + + num_handles++; + total += size; + rem -= size; + } while (rem); + + upload(fd, &handles, num_handles); + + old_info = new_info; + memset(regions, 0, item->length); + i915_query_items(fd, item, 1); + new_info = regions->regions[idx]; + + igt_assert_lte(new_info.unallocated_size, + new_info.probed_size - total); + igt_assert_lt(new_info.unallocated_size, old_info.unallocated_size); + if (new_info.probed_cpu_visible_size == + new_info.probed_size) { /* full BAR */ + igt_assert_eq(new_info.unallocated_cpu_visible_size, + new_info.unallocated_size); + } else if (cpu_access) { + igt_assert_lt(new_info.unallocated_cpu_visible_size, + old_info.unallocated_cpu_visible_size); + igt_assert_lte(new_info.unallocated_cpu_visible_size, + new_info.probed_cpu_visible_size - total); + } + + igt_debug("fill completed with idx=%d, total=%"PRIu64"KiB, num_handles=%u\n", + idx, total >> 10, num_handles); + + igt_list_for_each_entry_safe(iter, tmp, &handles, link) { + gem_close(fd, iter->handle); + free(iter); + } + + igt_drop_caches_set(fd, DROP_ALL); + + old_info = new_info; + memset(regions, 0, item->length); + i915_query_items(fd, item, 1); + new_info = regions->regions[idx]; + + igt_assert(new_info.unallocated_size >= + old_info.unallocated_size + total); + if (cpu_access) + igt_assert(new_info.unallocated_cpu_visible_size >= + old_info.unallocated_cpu_visible_size + total); +} + +static void test_query_regions_unallocated(int fd) +{ + struct drm_i915_query_memory_regions *regions; + struct drm_i915_query_item item; + int i; + + memset(&item, 0, sizeof(item)); + item.query_id = DRM_I915_QUERY_MEMORY_REGIONS; + i915_query_items(fd, &item, 1); + igt_assert(item.length > 0); + + regions = calloc(1, item.length); + + item.data_ptr = to_user_pointer(regions); + i915_query_items(fd, &item, 1); + + igt_assert(regions->num_regions); + + for (i = 0; i < regions->num_regions; i++) { + struct drm_i915_memory_region_info info = regions->regions[i]; + struct drm_i915_gem_memory_class_instance ci = info.region; + + if (ci.memory_class == I915_MEMORY_CLASS_DEVICE) { + fill_unallocated(fd, &item, i, true); + fill_unallocated(fd, &item, i, false); + } + } +} + static bool query_engine_info_supported(int fd) { struct drm_i915_query_item item = { @@ -1173,6 +1438,13 @@ igt_main test_query_regions_sanity_check(fd); } + igt_describe("Sanity check the region unallocated tracking"); + igt_subtest("query-regions-unallocated") { + igt_require(query_regions_supported(fd)); + igt_require(query_regions_unallocated_supported(fd)); + test_query_regions_unallocated(fd); + } + igt_subtest_group { igt_fixture { igt_require(query_engine_info_supported(fd)); From patchwork Wed Jun 29 19:06:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12900633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87390C43334 for ; Wed, 29 Jun 2022 19:11:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D89CC10ED1D; Wed, 29 Jun 2022 19:11:36 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD59E10ED1D; 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d="scan'208";a="733297154" Received: from nwalsh-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.202.136]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:17 -0700 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Wed, 29 Jun 2022 20:06:56 +0100 Message-Id: <20220629190658.395463-7-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629190658.395463-1-matthew.auld@intel.com> References: <20220629190658.395463-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 7/9] lib/i915/intel_memory_region: plumb through the cpu_size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Will be useful later. Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das --- lib/i915/intel_memory_region.c | 2 ++ lib/i915/intel_memory_region.h | 1 + 2 files changed, 3 insertions(+) diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c index 3173507f..93a18982 100644 --- a/lib/i915/intel_memory_region.c +++ b/lib/i915/intel_memory_region.c @@ -956,6 +956,8 @@ struct gem_memory_region *__gem_get_memory_regions(int i915) r->ci = info->regions[i].region; r->size = info->regions[i].probed_size; + /* XXX: replace with probed_cpu_visible_size */ + r->cpu_size = info->regions[i].rsvd1[0]; if (r->size == -1ull) r->size = igt_get_avail_ram_mb() << 20; diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h index 40ff832d..e1bfe0ca 100644 --- a/lib/i915/intel_memory_region.h +++ b/lib/i915/intel_memory_region.h @@ -176,6 +176,7 @@ struct gem_memory_region { struct drm_i915_gem_memory_class_instance ci; uint64_t size; + uint64_t cpu_size; }; struct igt_collection * From patchwork Wed Jun 29 19:06:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12900634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6E4BC43334 for ; Wed, 29 Jun 2022 19:11:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D3FD10ED73; Wed, 29 Jun 2022 19:11:47 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id CA0A310ED7B; Wed, 29 Jun 2022 19:11:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656529905; x=1688065905; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0JKK+CNtp+4TCJ/r8eicGjsRTqrPSmhohxLQiuQxA0Y=; b=Cmlbd4zkVrJexJcoAwRSgZIeoyCMW5oNU5eYSgmRfVtCG0c0csIG/yC6 UqxkrdpB2ZrQqQBCZyFiN8EZ3wWWnIacVsQKEM9XWINfsA+gVRm7hEsDr aiPXnDKyLTkZbW7HAiPun+QCBbzige4W7NnlQMjH9rWdOZSUZRtKq07kD jp22avmkmI/3v53wIIA8VwLjRCUEiWSJ5sqJholnODiVB4Gw3fe9FViTJ 7SLh59QFLac++hf4rdGJ/dnvAEDJ6wEmx/g/xDoAAB2Cv++qIDuxDfv6D RIfnxDgRomBv/fhgzMD1h2SrRzPlbGa3BUUFWyfoEokv5cvVg1y01EtJW g==; X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="368439223" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="368439223" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:19 -0700 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="733297162" Received: from nwalsh-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.202.136]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:18 -0700 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Wed, 29 Jun 2022 20:06:57 +0100 Message-Id: <20220629190658.395463-8-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629190658.395463-1-matthew.auld@intel.com> References: <20220629190658.395463-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 8/9] tests/i915/capture: handle uapi changes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We should mark the objects that need to be captured with NEEDS_CPU_ACCESS to ensure we can capture them if they are allocated in lmem. We also need to consider that capture only properly works on non-recoverable context, for discrete platforms. We can now also expect CPU invisible objects to be skipped, for now at least. v2: try to make it backwards compat Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das --- tests/i915/gem_exec_capture.c | 176 ++++++++++++++++++++++++++++++++-- 1 file changed, 169 insertions(+), 7 deletions(-) diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c index 89534146..c2639082 100644 --- a/tests/i915/gem_exec_capture.c +++ b/tests/i915/gem_exec_capture.c @@ -268,13 +268,13 @@ static void __capture1(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx, saved_engine = configure_hangs(fd, e, ctx->id); memset(obj, 0, sizeof(obj)); - obj[SCRATCH].handle = gem_create_in_memory_regions(fd, 4096, region); + obj[SCRATCH].handle = gem_create_with_cpu_access_in_memory_regions(fd, 4096, region); obj[SCRATCH].flags = EXEC_OBJECT_WRITE; obj[CAPTURE].handle = target; obj[CAPTURE].flags = EXEC_OBJECT_CAPTURE; obj[NOCAPTURE].handle = gem_create(fd, 4096); - obj[BATCH].handle = gem_create_in_memory_regions(fd, 4096, region); + obj[BATCH].handle = gem_create_with_cpu_access_in_memory_regions(fd, 4096, region); obj[BATCH].relocs_ptr = (uintptr_t)reloc; obj[BATCH].relocation_count = !ahnd ? ARRAY_SIZE(reloc) : 0; @@ -389,7 +389,7 @@ static void capture(int fd, int dir, const intel_ctx_t *ctx, uint32_t handle; uint64_t ahnd, obj_size = 4096; - igt_assert_eq(__gem_create_in_memory_regions(fd, &handle, &obj_size, region), 0); + igt_assert_eq(__gem_create_with_cpu_access_in_memory_regions(fd, &handle, &obj_size, region), 0); ahnd = get_reloc_ahnd(fd, ctx->id); __capture1(fd, dir, ahnd, ctx, e, handle, obj_size, region); @@ -415,7 +415,8 @@ static struct offset * __captureN(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx, const struct intel_execution_engine2 *e, unsigned int size, int count, - unsigned int flags, int *_fence_out) + unsigned int flags, int *_fence_out, uint32_t region, + bool force_cpu_access) #define INCREMENTAL 0x1 #define ASYNC 0x2 { @@ -441,7 +442,10 @@ __captureN(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx, obj[0].flags = EXEC_OBJECT_WRITE | (ahnd ? EXEC_OBJECT_PINNED : 0); for (i = 0; i < count; i++) { - obj[i + 1].handle = gem_create(fd, size); + if (force_cpu_access) + obj[i + 1].handle = gem_create_with_cpu_access_in_memory_regions(fd, size, region); + else + obj[i + 1].handle = gem_create_in_memory_regions(fd, size, region); obj[i + 1].offset = get_offset(ahnd, obj[i + 1].handle, size, 0); obj[i + 1].flags = EXEC_OBJECT_CAPTURE | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; @@ -574,6 +578,41 @@ __captureN(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx, return offsets; } +/* + * FIXME: remove once the kernel changes have landed and everything has settled. + * The change here is non-backwards compatible, and we don't want to upset CI. +*/ +#define probed_cpu_visible_size rsvd1[0] +static bool kernel_supports_probed_size(int fd) +{ + struct drm_i915_query_memory_regions *regions; + int i, ret = false; + + regions = gem_get_query_memory_regions(fd); + igt_assert(regions); + igt_assert(regions->num_regions); + + for (i = 0; i < regions->num_regions; i++) { + struct drm_i915_memory_region_info info = regions->regions[i]; + + if (info.probed_cpu_visible_size) { + ret = true; + break; + } + } + + free(regions); + return ret; +} + +static bool needs_recoverable_ctx(int fd) +{ + if (!kernel_supports_probed_size(fd)) + return false; + + return gem_has_lmem(fd) || intel_display_ver(intel_get_drm_devid(fd)) > 12; +} + #define find_first_available_engine(fd, ctx, e, saved) \ do { \ ctx = intel_ctx_create_all_physical(fd); \ @@ -595,6 +634,15 @@ static void many(int fd, int dir, uint64_t size, unsigned int flags) struct gem_engine_properties saved_engine; find_first_available_engine(fd, ctx, e, saved_engine); + if (needs_recoverable_ctx(fd)) { + struct drm_i915_gem_context_param param = { + .ctx_id = ctx->id, + .param = I915_CONTEXT_PARAM_RECOVERABLE, + .value = 0, + }; + + gem_context_set_param(fd, ¶m); + } gtt = gem_aperture_size(fd) / size; ram = (igt_get_avail_ram_mb() << 20) / size; @@ -607,7 +655,8 @@ static void many(int fd, int dir, uint64_t size, unsigned int flags) igt_require_memory(count, size, CHECK_RAM); ahnd = get_reloc_ahnd(fd, ctx->id); - offsets = __captureN(fd, dir, ahnd, ctx, e, size, count, flags, NULL); + offsets = __captureN(fd, dir, ahnd, ctx, e, size, count, flags, NULL, + REGION_SMEM, true); blobs = check_error_state(dir, offsets, count, size, !!(flags & INCREMENTAL)); igt_info("Captured %lu %"PRId64"-blobs out of a total of %lu\n", @@ -677,7 +726,8 @@ static void prioinv(int fd, int dir, const intel_ctx_t *ctx, /* Reopen the allocator in the new process. */ ahnd = get_reloc_ahnd(fd, ctx2->id); - free(__captureN(fd, dir, ahnd, ctx2, e, size, count, ASYNC, &fence_out)); + free(__captureN(fd, dir, ahnd, ctx2, e, size, count, ASYNC, + &fence_out, REGION_SMEM, true)); put_ahnd(ahnd); write(link[1], &fd, sizeof(fd)); /* wake the parent up */ @@ -720,6 +770,15 @@ static void userptr(int fd, int dir) struct gem_engine_properties saved_engine; find_first_available_engine(fd, ctx, e, saved_engine); + if (needs_recoverable_ctx(fd)) { + struct drm_i915_gem_context_param param = { + .ctx_id = ctx->id, + .param = I915_CONTEXT_PARAM_RECOVERABLE, + .value = 0, + }; + + gem_context_set_param(fd, ¶m); + } igt_assert(posix_memalign(&ptr, obj_size, obj_size) == 0); memset(ptr, 0, obj_size); @@ -735,6 +794,84 @@ static void userptr(int fd, int dir) gem_engine_properties_restore(fd, &saved_engine); } +static uint32_t batch_create_size(int fd, uint64_t size) +{ + const uint32_t bbe = MI_BATCH_BUFFER_END; + uint32_t handle; + + handle = gem_create(fd, size); + gem_write(fd, handle, 0, &bbe, sizeof(bbe)); + + return handle; +} + +static void capture_recoverable_discrete(int fd) +{ + struct drm_i915_gem_exec_object2 exec[2] = {}; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&exec), + .buffer_count = 2, + }; + + /* + * I915_CONTEXT_PARAM_RECOVERABLE should be enabled by default. On + * discrete the kernel will only capture objects associated with the + * batch, if the context we is configured as non-recoverable. + */ + + exec[0].handle = gem_create(fd, 4096); + exec[0].flags = EXEC_OBJECT_CAPTURE; + exec[1].handle = batch_create_size(fd, 4096); + + igt_assert_neq(__gem_execbuf(fd, &execbuf), 0); +} + +static void capture_invisible(int fd, int dir, const intel_ctx_t *ctx, + struct gem_memory_region *mr) +{ + struct gem_engine_properties saved_engine; + struct drm_i915_gem_context_param param = { + .param = I915_CONTEXT_PARAM_RECOVERABLE, + .value = 0, + }; + const struct intel_execution_engine2 *e; + struct offset *offsets; + uint64_t ahnd; + char *error; + + find_first_available_engine(fd, ctx, e, saved_engine); + param.ctx_id = ctx->id, + gem_context_set_param(fd, ¶m); + + ahnd = get_reloc_ahnd(fd, ctx->id); + + igt_assert_eq(mr->ci.memory_class, I915_MEMORY_CLASS_DEVICE); + + offsets = __captureN(fd, dir, ahnd, ctx, e, 1u << 16, 100, 0, NULL, + INTEL_MEMORY_REGION_ID(mr->ci.memory_class, + mr->ci.memory_instance), + false); + + /* + * Make sure the error capture code doesn't crash-and-burn if it + * encounters an lmem object that can't be copied using the CPU. In such + * cases such objects will be skipped, otherwise we should see crashes + * here. Allocating a number of small objects should be enough to + * ensure that at least one or more end being allocated in the CPU + * invisible portion. + */ + + error = igt_sysfs_get(dir, "error"); + igt_sysfs_set(dir, "error", "Begone!"); + igt_assert(error); + igt_assert(errno != ENOMEM); + + gem_engine_properties_restore(fd, &saved_engine); + + free(offsets); + put_ahnd(ahnd); +} + static bool has_capture(int fd) { drm_i915_getparam_t gp; @@ -781,6 +918,15 @@ igt_main gem_require_mmap_device_coherent(fd); igt_require(has_capture(fd)); ctx = intel_ctx_create_all_physical(fd); + if (needs_recoverable_ctx(fd)) { + struct drm_i915_gem_context_param param = { + .ctx_id = ctx->id, + .param = I915_CONTEXT_PARAM_RECOVERABLE, + .value = 0, + }; + + gem_context_set_param(fd, ¶m); + } igt_allow_hang(fd, ctx->id, HANG_ALLOW_CAPTURE | HANG_WANT_ENGINE_RESET); dir = igt_sysfs_open(fd); @@ -803,6 +949,22 @@ igt_main } } + igt_describe("Check that the kernel doesn't crash if the pages can't be copied from the CPU during error capture."); + igt_subtest_with_dynamic("capture-invisible") { + for_each_memory_region(r, fd) { + igt_dynamic_f("%s", r->name) { + igt_require(r->cpu_size && r->cpu_size < r->size); + capture_invisible(fd, dir, ctx, r); + } + } + } + + igt_describe("Verify that the kernel rejects EXEC_OBJECT_CAPTURE with recoverable contexts."); + igt_subtest_f("capture-recoverable") { + igt_require(needs_recoverable_ctx(fd)); + capture_recoverable_discrete(fd); + } + igt_subtest_f("many-4K-zero") { igt_require(gem_can_store_dword(fd, 0)); many(fd, dir, 1<<12, 0); From patchwork Wed Jun 29 19:06:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12900635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B37B8C433EF for ; Wed, 29 Jun 2022 19:11:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1070D10ED94; Wed, 29 Jun 2022 19:11:49 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 86E8910ED34; Wed, 29 Jun 2022 19:11:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656529906; x=1688065906; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9vMACVS+tUfgpQ8RA/xGcGR2d8E9t3AiKd2S59YHMsM=; b=mzx9Tb9V7Lc7REF9uj/WeUEsFB3TMMFBLl/9W4wgAZi0otuNvDEBwupa Rcqmd9NXj217nvmxkkiRyP4idKKegFg0J1jWCONnoqKhtr27NEozDcLDD AaleNszNmU6JCPv6xpRBQuQxxKDLs45+0W3VySiTb1QLX4uub4pozXiED StVljHq6btmP4DZNNiOEkIPji/3s4BsM3psb8V214Ql82W1LMfWeXpwt/ kyvq3AzSbXD+aMWD5FyJYJIKTPCXH5h8wtGS4o2CHrHGdp/fnYdpQ5+y9 jsCLKWTc47D386XKADih1oVR+Y7IAU/qhfnBV+SjjLR3OoZCsURwVmKeI w==; X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="368439257" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="368439257" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:20 -0700 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="733297173" Received: from nwalsh-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.202.136]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 12:07:19 -0700 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Wed, 29 Jun 2022 20:06:58 +0100 Message-Id: <20220629190658.395463-9-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220629190658.395463-1-matthew.auld@intel.com> References: <20220629190658.395463-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" kms_frontbuffer_tracking@basic falls over if the fb needs to be migrated from non-mappable device memory, to the mappable part, due to being temporarily pinned for scanout, when hitting the CPU fault handler, which just gives us SIGBUS. If the device has a small BAR let's attempt to use the mappable portion, if possible. Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Nirmoy Das --- lib/ioctl_wrappers.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c index 09eb3ce7..7713e78b 100644 --- a/lib/ioctl_wrappers.c +++ b/lib/ioctl_wrappers.c @@ -635,7 +635,8 @@ uint32_t gem_buffer_create_fb_obj(int fd, uint64_t size) uint32_t handle; if (gem_has_lmem(fd)) - handle = gem_create_in_memory_regions(fd, size, REGION_LMEM(0)); + handle = gem_create_with_cpu_access_in_memory_regions(fd, size, + REGION_LMEM(0)); else handle = gem_create(fd, size);