From patchwork Thu Jun 30 14:07:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 12901924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79DC0C433EF for ; Thu, 30 Jun 2022 14:21:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=vS8j8tr/L9658CwJ6TJ7LwzJNK9rLvaLPY2uc2iLpL4=; b=4zI1o2izyPyNd5 mrF/+nATlTwGiMV0LbVvBOQbxafZNXxxyaYQb7s58zOxGyobrVah+gbRIGBAE9rh9nnIrJklKV4Zb UaW7sEMza3vfxBRpyo9We7xAbdt6PCbTba8i/YxF/LTG4KVPaNmEHx9Tlw4MMth4uNpguhdghVLHi RhoSP2Xu9F4fgdjhvfEaynXgHHzUbGIsg6beqAqHPFWtg2dakoKJF0RUbM3gWzoBm/70R0h9oNDba Dd0cYCrgvpX2F8QkmeHfMjat85G4nfebuBaf8rwJOGUTsKEdi2v004TMIcEZPtwzfIy8z1gPqLpvF T9gC5NTQuJHkujAOr04A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6v1F-0002Nr-N3; Thu, 30 Jun 2022 14:19:46 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6upN-00HWlR-Tw for linux-arm-kernel@lists.infradead.org; Thu, 30 Jun 2022 14:07:31 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6BBD362271; Thu, 30 Jun 2022 14:07:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6BB0AC34115; Thu, 30 Jun 2022 14:07:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656598048; bh=H9sM6/G6fhKbQZpR3Y3pMS2INidzJ2rCOJ5cXNyNYhE=; h=From:To:Cc:Subject:Date:From; b=fYFcgyn+QVSycCotaKuYAfe6+C75M1q17dkwFVKfypcBxlRASDhKL/0W4uUfBfuFu J20YfoUrhCo8bZAEHS8DnHkj2Txo3yjtssLT+527sDvc8O/T7om9aAfGcVm9qNqPNS 8jfM/odg6gr3c7ptOGaa9kj0SGwh/SpReG0ANbsi5LPDmrZph2wfaI1rZSTdtLb0Ie REyRijg9UqcQqE7u9+Zl7TATMTRyHWvinkr+s2WlLn1NVVru4kCL7Pj0nVvJ2jk1I7 R5P0xuwfRpOngqps29gkAko6UN7VPaW6VMXNwE5YlAqC5k0SmkBJHkHR3WWikwrdK+ uy8Vekg4xBqFA== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: Ard Biesheuvel , Will Deacon , Anshuman Khandual , Mark Rutland , Joey Gouly Subject: [PATCH v2] arm64: mm: fix booting with 52-bit address space Date: Thu, 30 Jun 2022 16:07:23 +0200 Message-Id: <20220630140723.2264380-1-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3230; h=from:subject; bh=H9sM6/G6fhKbQZpR3Y3pMS2INidzJ2rCOJ5cXNyNYhE=; b=owEB7QES/pANAwAKAcNPIjmS2Y8kAcsmYgBiva4aWHBIa++BLK3APM8PpJQ/MdNrNEqWRACCCiAz mCnY9LGJAbMEAAEKAB0WIQT72WJ8QGnJQhU3VynDTyI5ktmPJAUCYr2uGgAKCRDDTyI5ktmPJGMhC/ 9j/l1uotwSCvd7l2jLChVsfil6mJkpafO5LXRjOi6jYvDGFtWEx9MIvdKT9yuOiGxHiToEbA+Cx4qx B57YkbeirFlRXV0YfCfuMmVbWrAXji8O7uzY/riOs/XbGHG1OFQDH2b5vPII2u2UZd90sg1BvOupUk 4cl44pU3LKzwHwJwJ3TXFnI1Q3NiAVEbNW2u1yJpVW1Wq7mg16gCduKxGCauLJnXD9dEQ9R0oE9HCn tWy1f2c25ZEt0Qdho+ASquXYcZ2WrQpMpCI81P/rXdQXpX380HScGsCh5C2qa5oTbKfV8NTQ1TN8uw /MUIjlM2u+S32rwCXOc/RRw6K0fWePUjHYDoSwCrerglu5iR0E1UhDirNXk58jYjPHnkVqUoaI9FmZ StVzJQeAtkF8PvRMfM7ziVWZsyea0uxItOVLkmfg3s3insSftSisB6p3gHg+jwJUqNeOAztv+lkpJn 1SgL4af4oEZKkyXI/NaDpXMzM9A1jgnu8EqAuBoqgZ0OU= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220630_070730_062272_26E5CA54 X-CRM114-Status: GOOD ( 16.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Joey reports that booting 52-bit VA capable builds on 52-bit VA capable CPUs is broken since commit 0d9b1ffefabe ("arm64: mm: make vabits_actual a build time constant if possible"). This is due to the fact that the primary CPU reads the vabits_actual variable before it has been assigned. The reason for deferring the assignment of vabits_actual was that we try to perform as few stores to memory as we can with the MMU and caches off, due to the cache coherency issues it creates. Since __cpu_setup() [which is where the read of vabits_actual occurs] is also called on the secondary boot path, we cannot just read the CPU ID registers directly, given that the size of the VA space is decided by the capabilities of the primary CPU. So let's read vabits_actual only on the secondary boot path, and read the CPU ID registers directly on the primary boot path, by making it a function parameter of __cpu_setup(). Cc: Will Deacon Cc: Anshuman Khandual Cc: Mark Rutland Fixes: 0d9b1ffefabe ("arm64: mm: make vabits_actual a build time constant if possible") Reported-by: Joey Gouly Co-developed-by: Joey Gouly Signed-off-by: Joey Gouly Signed-off-by: Ard Biesheuvel Tested-by: Anshuman Khandual --- This is a follow-up to Joey's v1, after discussing over IRC https://lore.kernel.org/linux-arm-kernel/20220630110016.31441-1-joey.gouly@arm.com/ arch/arm64/kernel/head.S | 10 ++++++++++ arch/arm64/mm/proc.S | 5 +++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index cea86b982e6a..ad67386df598 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -107,6 +107,13 @@ SYM_CODE_START(primary_entry) * On return, the CPU will be ready for the MMU to be turned on and * the TCR will have been set. */ +#if VA_BITS > 48 + mrs_s x0, SYS_ID_AA64MMFR2_EL1 + tst x0, #0xf << ID_AA64MMFR2_LVA_SHIFT + mov x0, #VA_BITS_MIN + mov x1, #VA_BITS + csel x0, x0, x1, eq +#endif bl __cpu_setup // initialise processor b __primary_switch SYM_CODE_END(primary_entry) @@ -587,6 +594,9 @@ SYM_FUNC_START_LOCAL(secondary_startup) mov x20, x0 // preserve boot mode bl switch_to_vhe bl __cpu_secondary_check52bitva +#if VA_BITS > 48 + ldr_l x0, vabits_actual +#endif bl __cpu_setup // initialise processor adrp x1, swapper_pg_dir adrp x2, idmap_pg_dir diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 5d6c494070d1..656c78f82a17 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -397,6 +397,8 @@ SYM_FUNC_END(idmap_kpti_install_ng_mappings) * * Initialise the processor for turning the MMU on. * + * Input: + * x0 - actual number of VA bits (ignored unless VA_BITS > 48) * Output: * Return in x0 the value of the SCTLR_EL1 register. */ @@ -466,8 +468,7 @@ SYM_FUNC_START(__cpu_setup) tcr_clear_errata_bits tcr, x9, x5 #ifdef CONFIG_ARM64_VA_BITS_52 - ldr_l x9, vabits_actual - sub x9, xzr, x9 + sub x9, xzr, x0 add x9, x9, #64 tcr_set_t1sz tcr, x9 #else