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Set corresponding DMA mask to avoid falling back to SWTLBIO usage in dma_map_single() because of failed dma_capable() check. The original code for this fix was suggested by Marek. Originally-by: Marek Szyprowski Signed-off-by: Sam Protsenko --- drivers/iommu/exynos-iommu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 71f2018e23fe..28f8c8d93aa3 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -647,6 +647,14 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) } } + if (MMU_MAJ_VER(data->version) >= 5) { + ret = dma_set_mask(dev, DMA_BIT_MASK(36)); + if (ret) { + dev_err(dev, "Unable to set DMA mask: %d\n", ret); + return ret; + } + } + /* * use the first registered sysmmu device for performing * dma mapping operations on iommu page tables (cpu cache flush) From patchwork Sat Jul 2 21:37:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 12904095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6EA0C433EF for ; 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Sat, 02 Jul 2022 14:37:27 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , Sumit Semwal , iommu@lists.linux-foundation.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] iommu/exynos: Check if SysMMU v7 has VM registers Date: Sun, 3 Jul 2022 00:37:22 +0300 Message-Id: <20220702213724.3949-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220702213724.3949-1-semen.protsenko@linaro.org> References: <20220702213724.3949-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220702_143730_623487_95569A47 X-CRM114-Status: GOOD ( 18.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SysMMU v7 can have Virtual Machine registers, which implement multiple translation domains. The driver should know if it's true or not, as VM registers shouldn't be accessed if not present. Read corresponding capabilities register to obtain that info, and store it in driver data. Signed-off-by: Sam Protsenko --- drivers/iommu/exynos-iommu.c | 42 ++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 28f8c8d93aa3..df6ddbebbe2b 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -135,6 +135,9 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ +#define CAPA0_CAPA1_EXIST BIT(11) +#define CAPA1_VCR_ENABLED BIT(14) + /* common registers */ #define REG_MMU_CTRL 0x000 #define REG_MMU_CFG 0x004 @@ -171,6 +174,10 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define REG_V5_FAULT_AR_VA 0x070 #define REG_V5_FAULT_AW_VA 0x080 +/* v7.x registers */ +#define REG_V7_CAPA0 0x870 +#define REG_V7_CAPA1 0x874 + #define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) static struct device *dma_dev; @@ -274,6 +281,9 @@ struct sysmmu_drvdata { unsigned int version; /* our version */ struct iommu_device iommu; /* IOMMU core handle */ + + /* v7 fields */ + bool has_vcr; /* virtual machine control register */ }; static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) @@ -364,11 +374,7 @@ static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data) static void __sysmmu_get_version(struct sysmmu_drvdata *data) { - u32 ver; - - __sysmmu_enable_clocks(data); - - ver = readl(data->sfrbase + REG_MMU_VERSION); + const u32 ver = readl(data->sfrbase + REG_MMU_VERSION); /* controllers on some SoCs don't report proper version */ if (ver == 0x80000001u) @@ -378,6 +384,29 @@ static void __sysmmu_get_version(struct sysmmu_drvdata *data) dev_dbg(data->sysmmu, "hardware version: %d.%d\n", MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); +} + +static bool __sysmmu_has_capa1(struct sysmmu_drvdata *data) +{ + const u32 capa0 = readl(data->sfrbase + REG_V7_CAPA0); + + return capa0 & CAPA0_CAPA1_EXIST; +} + +static void __sysmmu_get_vcr(struct sysmmu_drvdata *data) +{ + const u32 capa1 = readl(data->sfrbase + REG_V7_CAPA1); + + data->has_vcr = capa1 & CAPA1_VCR_ENABLED; +} + +static void sysmmu_get_hw_info(struct sysmmu_drvdata *data) +{ + __sysmmu_enable_clocks(data); + + __sysmmu_get_version(data); + if (MMU_MAJ_VER(data->version) >= 7 && __sysmmu_has_capa1(data)) + __sysmmu_get_vcr(data); __sysmmu_disable_clocks(data); } @@ -623,6 +652,8 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) data->sysmmu = dev; spin_lock_init(&data->lock); + sysmmu_get_hw_info(data); + ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, dev_name(data->sysmmu)); if (ret) @@ -634,7 +665,6 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) platform_set_drvdata(pdev, data); - __sysmmu_get_version(data); if (PG_ENT_SHIFT < 0) { if (MMU_MAJ_VER(data->version) < 5) { PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; From patchwork Sat Jul 2 21:37:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 12904098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7071FC43334 for ; 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Sat, 02 Jul 2022 14:37:28 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , Sumit Semwal , iommu@lists.linux-foundation.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] iommu/exynos: Use lookup based approach to access v7 registers Date: Sun, 3 Jul 2022 00:37:23 +0300 Message-Id: <20220702213724.3949-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220702213724.3949-1-semen.protsenko@linaro.org> References: <20220702213724.3949-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220702_143730_767159_75A1187D X-CRM114-Status: GOOD ( 15.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SysMMU v7 might have different register layouts (VM capable or non-VM capable). Check which layout is implemented in current SysMMU module and prepare the corresponding register table for futher usage. This way is faster and more elegant than checking corresponding condition (if it's VM or non-VM SysMMU) each time before accessing v7 registers. For now the register table contains only most basic registers needed to add the SysMMU v7 support. This patch is based on downstream work of next authors: - Janghyuck Kim - Daniel Mentz Signed-off-by: Sam Protsenko --- drivers/iommu/exynos-iommu.c | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index df6ddbebbe2b..47017e8945c5 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -180,6 +180,47 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) +#define MMU_REG(data, idx) \ + ((data)->sfrbase + (data)->regs[idx].off) +#define MMU_VM_REG(data, idx, vmid) \ + (MMU_REG(data, idx) + (vmid) * (data)->regs[idx].mult) + +enum { + REG_SET_NON_VM, + REG_SET_VM, + MAX_REG_SET +}; + +enum { + IDX_CTRL_VM, + IDX_CFG_VM, + IDX_FLPT_BASE, + IDX_ALL_INV, + MAX_REG_IDX +}; + +struct sysmmu_vm_reg { + unsigned int off; /* register offset */ + unsigned int mult; /* VM index offset multiplier */ +}; + +static const struct sysmmu_vm_reg sysmmu_regs[MAX_REG_SET][MAX_REG_IDX] = { + /* Default register set (non-VM) */ + { + /* + * SysMMUs without VM support do not have CTRL_VM and CFG_VM + * registers. Setting the offsets to 1 will trigger an unaligned + * access exception. + */ + {0x1}, {0x1}, {0x000c}, {0x0010}, + }, + /* VM capable register set */ + { + {0x8000, 0x1000}, {0x8004, 0x1000}, {0x800c, 0x1000}, + {0x8010, 0x1000}, + }, +}; + static struct device *dma_dev; static struct kmem_cache *lv2table_kmem_cache; static sysmmu_pte_t *zero_lv2_table; @@ -284,6 +325,7 @@ struct sysmmu_drvdata { /* v7 fields */ bool has_vcr; /* virtual machine control register */ + const struct sysmmu_vm_reg *regs; /* register set */ }; static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) @@ -407,6 +449,10 @@ static void sysmmu_get_hw_info(struct sysmmu_drvdata *data) __sysmmu_get_version(data); if (MMU_MAJ_VER(data->version) >= 7 && __sysmmu_has_capa1(data)) __sysmmu_get_vcr(data); + if (data->has_vcr) + data->regs = sysmmu_regs[REG_SET_VM]; + else + data->regs = sysmmu_regs[REG_SET_NON_VM]; __sysmmu_disable_clocks(data); } From patchwork Sat Jul 2 21:37:24 2022 Content-Type: text/plain; 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Sat, 02 Jul 2022 14:37:30 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id f22-20020a17090631d600b0072a3958ed33sm5021648ejf.63.2022.07.02.14.37.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Jul 2022 14:37:29 -0700 (PDT) From: Sam Protsenko To: Marek Szyprowski , Krzysztof Kozlowski Cc: Joerg Roedel , Will Deacon , Robin Murphy , Janghyuck Kim , Cho KyongHo , Daniel Mentz , Sumit Semwal , iommu@lists.linux-foundation.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] iommu/exynos: Add minimal support for SysMMU v7 with VM registers Date: Sun, 3 Jul 2022 00:37:24 +0300 Message-Id: <20220702213724.3949-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220702213724.3949-1-semen.protsenko@linaro.org> References: <20220702213724.3949-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220702_143731_514427_53FC3AFF X-CRM114-Status: GOOD ( 17.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add minimal viable support for SysMMU v7.x, which can be found in modern Exynos chips (like Exynos850). SysMMU v7.x may implement VM register set, and those registers should be initialized properly if present. Usually 8 translation domains are supported via VM registers (0..7), but only n=0 (default) is used for now. Changes are as follows: - add enabling the default VID instance before enabling SysMMU - use v7 VM register for setting the page table base address - use v7 VM register for invalidation Insights for those changes were taken by comparing the I/O dump (writel() / readl() operations) for vendor driver and this upstream driver. It was tested on E850-96 board, which has SysMMU v7.4 with VM registers present. The testing was done using "Emulated Translation" registers. That allows initiating translations with no actual users of that IOMMU, and checking the result by reading the TLB info from corresponding registers. Thanks to Marek, who did let me know it only takes a slight change of registers to make this driver work with v7. Signed-off-by: Sam Protsenko --- drivers/iommu/exynos-iommu.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 47017e8945c5..b7b4833161bc 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -135,6 +135,8 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ +#define CTRL_VM_ENABLE BIT(0) +#define CTRL_VM_FAULT_MODE_STALL BIT(3) #define CAPA0_CAPA1_EXIST BIT(11) #define CAPA1_VCR_ENABLED BIT(14) @@ -358,8 +360,10 @@ static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) { if (MMU_MAJ_VER(data->version) < 5) writel(0x1, data->sfrbase + REG_MMU_FLUSH); - else + else if (MMU_MAJ_VER(data->version) < 7) writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL); + else + writel(0x1, MMU_VM_REG(data, IDX_ALL_INV, 0)); } static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, @@ -391,9 +395,11 @@ static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) { if (MMU_MAJ_VER(data->version) < 5) writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); - else + else if (MMU_MAJ_VER(data->version) < 7) writel(pgd >> PAGE_SHIFT, data->sfrbase + REG_V5_PT_BASE_PFN); + else + writel(pgd >> SPAGE_ORDER, MMU_VM_REG(data, IDX_FLPT_BASE, 0)); __sysmmu_tlb_invalidate(data); } @@ -571,6 +577,12 @@ static void __sysmmu_enable(struct sysmmu_drvdata *data) writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); __sysmmu_init_config(data); __sysmmu_set_ptbase(data, data->pgtable); + if (MMU_MAJ_VER(data->version) >= 7 && data->has_vcr) { + u32 ctrl = readl(MMU_VM_REG(data, IDX_CTRL_VM, 0)); + + ctrl |= CTRL_VM_ENABLE | CTRL_VM_FAULT_MODE_STALL; + writel(ctrl, MMU_VM_REG(data, IDX_CTRL_VM, 0)); + } writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); data->active = true; spin_unlock_irqrestore(&data->lock, flags);