From patchwork Sun Jul 3 11:20:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18A4CC433EF for ; Sun, 3 Jul 2022 11:20:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231533AbiGCLUP (ORCPT ); Sun, 3 Jul 2022 07:20:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232503AbiGCLUO (ORCPT ); Sun, 3 Jul 2022 07:20:14 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7780295B5; Sun, 3 Jul 2022 04:20:13 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id v14so9469610wra.5; Sun, 03 Jul 2022 04:20:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oky3YgKKfNXCQVslFZi4xoyuek1RvMVadIY0VBZTguA=; b=lpOSvTd0mAYDGb//x5zEvoOwU/rHy4WR7/+BvxY2xqoMfI8LB+oT+ohMUO/f8j4qM7 dE2F9Ff12mPlOEVNc6RtRdX17AShgCaMrdY52lwQt6OU/HWDCI7qVCffL4IMxeiTWhoc 9Z76m1THTAyAmF7rQF8vdM75dnE9dk9eEOkWNpuqMFamUOGhgLiS6Ub6r8NkVq27k6bf jBYHvzhJ+om5mANoOw/RDJdv9tde7s5rRqKEp2BjxEhD+sIH5CHNUrGg9oEcEB4ONN/0 h3iTGqzA88M9vBj0zI3PNGu1sKnc9phq39Xu7fTk6fXMAQ0BRdQlCEiJF6wBHfz2YPdL JWOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oky3YgKKfNXCQVslFZi4xoyuek1RvMVadIY0VBZTguA=; b=PYHfeZlzmxTcwnY5klbft2/qUu92Arxqietl7TngcArv22Dk+G93aSmBojGrZW+XK1 rkQgMU+dSEDsk4JMR/qDDmXxHcK9ibJqTevJQwFdKIWIc15y/iOe8cFmkTSiL6XaqwHp dxVuXW+yNL0VRj8uFwOZe6FQUQsVO+BwQbiQ+PCX376hW+iYyQa1tjGkwdDYxOjvDwCg pQnUXKHw1WYEx8JRm83uTWXrBmgqadvKrit8h5HazxSTHg5mkfGT5xHDQcIE+9WudeJL N8ohMxwIQJtM2yMYMsxTEFHhE6iPs7hhAy8JYVmwX6THLyIXb2MowIKUhHtDbdlI2w8z yfFg== X-Gm-Message-State: AJIora9R/QVBxtCiRYfy7Uef+3MT+xvkvvFoAutYy8a5pPP6jgQk3n9G RIFdUtepcINv6t5s0uLCJOg= X-Google-Smtp-Source: AGRyM1sw2ixdXyl8YxX0sNYLCwi3+d2i86gtrFRsb0J/c4Y5b7ori14ll7nRTGrDw1Q0JsaQ0yHPVw== X-Received: by 2002:a05:6000:38f:b0:21b:aded:e791 with SMTP id u15-20020a056000038f00b0021badede791mr20980183wrf.225.1656847212119; Sun, 03 Jul 2022 04:20:12 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id c8-20020a05600c0a4800b003a02f957245sm10437466wmq.26.2022.07.03.04.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:11 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 01/12] regmap-irq: Convert bool bitfields to unsigned int Date: Sun, 3 Jul 2022 12:20:50 +0100 Message-Id: <20220703112101.24493-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Use 'unsigned int' for bitfields for consistency with most other kernel code. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 2 +- include/linux/regmap.h | 26 +++++++++++++------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index a6db605707b0..a58b29e9c7c7 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -43,7 +43,7 @@ struct regmap_irq_chip_data { unsigned int irq_reg_stride; unsigned int type_reg_stride; - bool clear_status:1; + unsigned int clear_status:1; }; static int sub_irq_reg(struct regmap_irq_chip_data *data, diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 8952fa3d0d59..7c5e4a20e9cf 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1518,19 +1518,19 @@ struct regmap_irq_chip { unsigned int type_base; unsigned int *virt_reg_base; unsigned int irq_reg_stride; - bool mask_writeonly:1; - bool init_ack_masked:1; - bool mask_invert:1; - bool use_ack:1; - bool ack_invert:1; - bool clear_ack:1; - bool wake_invert:1; - bool runtime_pm:1; - bool type_invert:1; - bool type_in_mask:1; - bool clear_on_unmask:1; - bool not_fixed_stride:1; - bool status_invert:1; + unsigned int mask_writeonly:1; + unsigned int init_ack_masked:1; + unsigned int mask_invert:1; + unsigned int use_ack:1; + unsigned int ack_invert:1; + unsigned int clear_ack:1; + unsigned int wake_invert:1; + unsigned int runtime_pm:1; + unsigned int type_invert:1; + unsigned int type_in_mask:1; + unsigned int clear_on_unmask:1; + unsigned int not_fixed_stride:1; + unsigned int status_invert:1; int num_regs; From patchwork Sun Jul 3 11:20:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31445C43334 for ; Sun, 3 Jul 2022 11:20:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232615AbiGCLUT (ORCPT ); Sun, 3 Jul 2022 07:20:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232565AbiGCLUQ (ORCPT ); Sun, 3 Jul 2022 07:20:16 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CE7195BA; Sun, 3 Jul 2022 04:20:15 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id j7so3824110wmp.2; Sun, 03 Jul 2022 04:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1j/DIF/Fnv8RPcb6VzAvPxanMn+C+wmq9yB73HToH5Q=; b=UsTYyk+6Jr2BmuDqwpyKYS8/Jig7Kaihh6axH9wvlIYALIplq7Bz+GIraW26OfVH2G CkW8ws2xwGlHI6YrTHZFN0yXonND/mxxKMb1Ct6rwqAyxAdfB5gye7wzMHsnBUHJhVhy lAZHRzEv1IlW5sEt/DBntYY87O/hd6dmGtgc9o3WBbxMfG+wNH8y2EDk99p3gWHhAh7M Q9zeh5uCnEKn0bLjnZ61tDeI4Q/R/VjFCwxEck+6gXAjufkeR67PjyMxVGEtHIvs3yKY uFFZTotEjyCu6Jf13z3APjs6w/Q+W5bnn5dqSeTl7m2YX8k8FOPqut15qIVkwk90j5gr zZow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1j/DIF/Fnv8RPcb6VzAvPxanMn+C+wmq9yB73HToH5Q=; b=JCt1oazWZ6t5gjIXM5kT2Ld8nQCEOLb88IzEaoPCIUgmLLPYm/aREVNWTG6tu2+NuP 1yWXvzrZgi7Z6Op0F5JvA6WdcLdBuQY+xW4vE668vg6eJ0wIg1lY7dM/YZCO5+3mhLjf t5iodMh1HLEz9plmZ192DXJ62LKnL77GYCgNvpLIk/hT14KR3FmkcE0mRVX7dHcsOy+R +UcAvBZ9UHTs/1bKRpTCxwg3P1VzwXlxiqb4aducckI/Z2Ai7zJi4nUDtpHU6GsahrpN qGGb16Ya0BvaF2QFBmCW++oY6KrXITBHwkt/TG+bFClCKZzFski5OE7ztXg8kMHjIntB gIfw== X-Gm-Message-State: AJIora/45o/QnYCKg8UvifYRx7tqUyecTYGy4ZjCTGFkC6b0jAXRGsZA tOmIWlGnScngMt0z3wKD/z0n2vSwy3w= X-Google-Smtp-Source: AGRyM1uwZvWD027BAhy4r7enluUTY5m/fwRJdDNoUNTe0KUJRHVRu5ipTusVaOHouuBGxQ1ovAbSWw== X-Received: by 2002:a05:600c:4254:b0:3a1:6c19:f3aa with SMTP id r20-20020a05600c425400b003a16c19f3aamr24877321wmm.205.1656847213729; Sun, 03 Jul 2022 04:20:13 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id a8-20020a05600c348800b00397623ff335sm16936118wmq.10.2022.07.03.04.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:13 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 02/12] regmap-irq: Remove unused type_reg_stride field Date: Sun, 3 Jul 2022 12:20:51 +0100 Message-Id: <20220703112101.24493-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org It appears that no chip ever required a nonzero type_reg_stride and commit 1066cfbdfa3f ("regmap-irq: Extend sub-irq to support non-fixed reg strides") broke support. Just remove the field. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 6 ------ include/linux/regmap.h | 3 --- 2 files changed, 9 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index a58b29e9c7c7..475a959e2b8b 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -41,7 +41,6 @@ struct regmap_irq_chip_data { unsigned int **virt_buf; unsigned int irq_reg_stride; - unsigned int type_reg_stride; unsigned int clear_status:1; }; @@ -743,11 +742,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, else d->irq_reg_stride = 1; - if (chip->type_reg_stride) - d->type_reg_stride = chip->type_reg_stride; - else - d->type_reg_stride = 1; - if (!map->use_single_read && map->reg_stride == 1 && d->irq_reg_stride == 1) { d->status_reg_buf = kmalloc_array(chip->num_regs, diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 7c5e4a20e9cf..f75911239977 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1487,8 +1487,6 @@ struct regmap_irq_sub_irq_map { * @num_type_reg: Number of type registers. * @num_virt_regs: Number of non-standard irq configuration registers. * If zero unsupported. - * @type_reg_stride: Stride to use for chips where type registers are not - * contiguous. * @handle_pre_irq: Driver specific callback to handle interrupt from device * before regmap_irq_handler process the interrupts. * @handle_post_irq: Driver specific callback to handle interrupt from device @@ -1539,7 +1537,6 @@ struct regmap_irq_chip { int num_type_reg; int num_virt_regs; - unsigned int type_reg_stride; int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); From patchwork Sun Jul 3 11:20:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0F15C433EF for ; Sun, 3 Jul 2022 11:20:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232648AbiGCLUW (ORCPT ); Sun, 3 Jul 2022 07:20:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232603AbiGCLUR (ORCPT ); Sun, 3 Jul 2022 07:20:17 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EB899FCB; Sun, 3 Jul 2022 04:20:16 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id j7so3824135wmp.2; Sun, 03 Jul 2022 04:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7iiZ1g2foyg+pIBZL+lLC+0n9kDHXAVzLQyCSVfDJ08=; b=AF3/N+VlWriwsqQjDN0LQU4rlOeuHMpEIODcmvPhddblcXdFnt7gcZz8sTZKyXH6wb 7OaHzDG5Rs29DCZvquL6MAG8grJ3gIAwWn8emtVMV5TIP4Sk+LgC4EATGWipAKmv9zfj /LJXfw04Pe4RqHYCL2EqcgrhKikHVlnWIKgiMP+z9D76j2Ju4DMe4kcAP/lSh1W9bTq+ pOy6iCn0qCsDEOFUL2IxFAPNIIiQr2x88iZ+bhaxPIyftWN7kfDdGGCLYQFOMjNvf1hU v2QMbiV90ZCkXg/Tg/wj+ijCC9qm4xlnDhDhpD6hmp76sfqZILNTAvYZfl8AhTRtQ8XH zuWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7iiZ1g2foyg+pIBZL+lLC+0n9kDHXAVzLQyCSVfDJ08=; b=FHeRcrShpdzNtckc20GMGkn4/lmgOjWWACIPRxr2PCwql4hH7Mf4WDA4z8sZOcpa2a SX3/ovDnz8oVpBYe4VARHrBNaQoOkEGfpc4ke8KTKE29HKYYr8LHzGdeY71YXh1LsotA NbplrlRInMMk/Z3b10S/4WM35rSmprBpTtICAe3o0iaVOfwLLYkxCxaJcNFnSgUS1Z/0 PO5AXJ+fTJAACwvunLog5/L9cQBRJlZcm7xmQhT+uettjfl/ssx7ZK365SpGaXTx+3iy eVFT0qwQ8s3hHkLtdkUFQ/bRXf3PqRudDwSGCfZSphG93cC2eO5J56lVyTmYwErcPPhM 3muQ== X-Gm-Message-State: AJIora++joiob4OHYuLzxpR6FE0kcjlYPgoZ7lnCRtXQw0HLcfpTgAMu 24i30MkJBUDDM45mxSs2hjk= X-Google-Smtp-Source: AGRyM1uNt9ZqHL3Y8zHeW7d3UlPenLhPi6dVF1jSG88DC1y8dXGqolI6pe2pXJMV6Ei3zPJVL4ZPuw== X-Received: by 2002:a05:600c:a02:b0:39c:97cc:82e3 with SMTP id z2-20020a05600c0a0200b0039c97cc82e3mr27666501wmp.97.1656847215255; Sun, 03 Jul 2022 04:20:15 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id m9-20020a05600c3b0900b003a04d19dab3sm15194653wms.3.2022.07.03.04.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:14 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 03/12] regmap-irq: Cleanup sizeof(...) use in memory allocation Date: Sun, 3 Jul 2022 12:20:52 +0100 Message-Id: <20220703112101.24493-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Instead of mentioning unsigned int directly, use a sizeof(...) involving the buffer we're allocating to ensure the types don't get out of sync. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 475a959e2b8b..dca27b4e29d3 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -670,30 +670,30 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, if (chip->num_main_regs) { d->main_status_buf = kcalloc(chip->num_main_regs, - sizeof(unsigned int), + sizeof(*d->main_status_buf), GFP_KERNEL); if (!d->main_status_buf) goto err_alloc; } - d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int), + d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf), GFP_KERNEL); if (!d->status_buf) goto err_alloc; - d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int), + d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf), GFP_KERNEL); if (!d->mask_buf) goto err_alloc; - d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int), + d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def), GFP_KERNEL); if (!d->mask_buf_def) goto err_alloc; if (chip->wake_base) { - d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int), + d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf), GFP_KERNEL); if (!d->wake_buf) goto err_alloc; @@ -702,11 +702,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg; if (num_type_reg) { d->type_buf_def = kcalloc(num_type_reg, - sizeof(unsigned int), GFP_KERNEL); + sizeof(*d->type_buf_def), GFP_KERNEL); if (!d->type_buf_def) goto err_alloc; - d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int), + d->type_buf = kcalloc(num_type_reg, sizeof(*d->type_buf), GFP_KERNEL); if (!d->type_buf) goto err_alloc; @@ -723,7 +723,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, for (i = 0; i < chip->num_virt_regs; i++) { d->virt_buf[i] = kcalloc(chip->num_regs, - sizeof(unsigned int), + sizeof(**d->virt_buf), GFP_KERNEL); if (!d->virt_buf[i]) goto err_alloc; From patchwork Sun Jul 3 11:20:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C04C6CCA47C for ; Sun, 3 Jul 2022 11:20:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232503AbiGCLUX (ORCPT ); Sun, 3 Jul 2022 07:20:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232608AbiGCLUT (ORCPT ); Sun, 3 Jul 2022 07:20:19 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44DCA9FCD; Sun, 3 Jul 2022 04:20:18 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id s1so9447480wra.9; Sun, 03 Jul 2022 04:20:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VqID5x/tjmobIccvt6tf2g3gXW+2/FDTRjd9KrrHqF4=; b=d4PXzIx1PJErn9Uy2EDzGRD+E2Nbcs6RZpo0yI7IrkhA/iuGU9MPm1VK2MIDxJH1/v tWgyTeJSwsvuzYOtBU4sda1lmwDv/7V5Pabdqktqke0MACJuSu6Mm+a7dQWbUvrbXERp 5DyfWU+Y7R/2CUitPzIB7LpSCFu08IySB58MdH3RUtlO39NRepdPbQe/X42DBksr9s/i vDhLsH6p5mGiGJy6owfZQWfZdJpUOGLYsLbw5Cp+24YGFHxtYds/HlJ+ixktSEVm4Lhw I+xRW7RvEkbgy2uyA2wYw3bXnap8iVzgmpw1coOHHnmJdmgP3EVdBFD+W+uGOX6kNISF 2sZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VqID5x/tjmobIccvt6tf2g3gXW+2/FDTRjd9KrrHqF4=; b=2GyyLze8KGR6PFbLqcOOPHeptQVeIp1mSVltjXxIVnHBE6i1Vs5p2M+LxzeOWtfg4O UKecFANlusCmdXkVr1xFpXtS6Z7uZYQXN3+DUuyNt5+mH1Fn1A4M68qEifd68QZZg0ng QNHURBaz+DiBJeCr9t0aW63Ofa7daLe+5NF3qZqaTl92S5kTrfqlCrX2hxqR6i3nNPUp oqXQtZTlDIhPtG5/oQ5BNFr9/1sRgx0xaqURHmpbTKfWqQ3KiOP9aTGRQng6uc1g0jpR +UzlontQ4+c17aG7GH3zTzKxFToVAEtzbLioIFaHXiyP2w9R1H5ioAKN2zODog4HlCha RMNA== X-Gm-Message-State: AJIora8J/YSBP3Af3Do1BAviTeoGQ6jt5bhGZo9sBa0qb3afSxhtoCQs V5yGLgESlNFDWFA7dTPdScA= X-Google-Smtp-Source: AGRyM1ucoV4eygJAYC4FPKlfYevd8mXuhGpdVsvgf2tZwNZTwxXLapGZfa9mDAfenf7w1WTVZNgp6Q== X-Received: by 2002:a5d:664c:0:b0:21d:2d0d:e729 with SMTP id f12-20020a5d664c000000b0021d2d0de729mr21101920wrw.585.1656847216859; Sun, 03 Jul 2022 04:20:16 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id t5-20020a1c4605000000b0039db31f6372sm12531769wma.2.2022.07.03.04.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:16 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 04/12] regmap-irq: Remove an unnecessary restriction on type_in_mask Date: Sun, 3 Jul 2022 12:20:53 +0100 Message-Id: <20220703112101.24493-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Check types_supported instead of checking type_rising/falling_val when using type_in_mask interrupts. This makes the intent clearer and allows a type_in_mask irq to support level or edge triggers, rather than only edge triggers. Update the documentation and comments to reflect the new behavior. This shouldn't affect existing drivers, because if they didn't set types_supported properly the type buffer wouldn't be updated. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 19 ++++++++----------- include/linux/regmap.h | 8 +++++--- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index dca27b4e29d3..fd7c4315d16b 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -252,22 +252,19 @@ static void regmap_irq_enable(struct irq_data *data) struct regmap *map = d->map; const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); unsigned int reg = irq_data->reg_offset / map->reg_stride; - unsigned int mask, type; - - type = irq_data->type.type_falling_val | irq_data->type.type_rising_val; + unsigned int mask; /* * The type_in_mask flag means that the underlying hardware uses - * separate mask bits for rising and falling edge interrupts, but - * we want to make them into a single virtual interrupt with - * configurable edge. + * separate mask bits for each interrupt trigger type, but we want + * to have a single logical interrupt with a configurable type. * - * If the interrupt we're enabling defines the falling or rising - * masks then instead of using the regular mask bits for this - * interrupt, use the value previously written to the type buffer - * at the corresponding offset in regmap_irq_set_type(). + * If the interrupt we're enabling defines any supported types + * then instead of using the regular mask bits for this interrupt, + * use the value previously written to the type buffer at the + * corresponding offset in regmap_irq_set_type(). */ - if (d->chip->type_in_mask && type) + if (d->chip->type_in_mask && irq_data->type.types_supported) mask = d->type_buf[reg] & irq_data->mask; else mask = irq_data->mask; diff --git a/include/linux/regmap.h b/include/linux/regmap.h index f75911239977..106ca1172d3d 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1468,9 +1468,11 @@ struct regmap_irq_sub_irq_map { * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts. * @wake_invert: Inverted wake register: cleared bits are wake enabled. * @type_invert: Invert the type flags. - * @type_in_mask: Use the mask registers for controlling irq type. For - * interrupts defining type_rising/falling_mask use mask_base - * for edge configuration and never update bits in type_base. + * @type_in_mask: Use the mask registers for controlling irq type. Use this if + * the hardware provides separate bits for rising/falling edge + * or low/high level interrupts and they should be combined into + * a single logical interrupt. Use &struct regmap_irq_type data + * to define the mask bit for each irq type. * @clear_on_unmask: For chips with interrupts cleared on read: read the status * registers before unmasking interrupts to clear any bits * set when they were masked. From patchwork Sun Jul 3 11:20:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C022C433EF for ; Sun, 3 Jul 2022 11:20:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232640AbiGCLUZ (ORCPT ); Sun, 3 Jul 2022 07:20:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232623AbiGCLUV (ORCPT ); Sun, 3 Jul 2022 07:20:21 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0DA99FC7; Sun, 3 Jul 2022 04:20:19 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id q9so9456141wrd.8; Sun, 03 Jul 2022 04:20:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+qGHCihlNL7T5T1G7aMDu8MmDKY14zb9oDODHpK/qzo=; b=mDSFIrmEh3iCggKyQQ342Lh7aDiPqeH6ELx3zx81FkUZA2xWShm82noN5JDWSXKfd0 lroYsULAVn7MnlCzEvor26gXErCbaAo5y2GHuwtxWHN00fM8QgVFcqOHZksHGmJmdnFv pAFPiH6TuRKdJqRVilw8g4014k1BE8qx2xh4KVTtW96q+XaVaqNNaRxmhfuyP7HGqfFp qdQ5GM16CBi/TzuogVPFg5S/OxvAUzNAyrGKMZtgtPCilT6rDeJ9KmZQXAm/IGq2KZ3I 4WV8/UIhGx6RmaP6irKxKL0BWP4IOu8BULLHQV3oh+TKoBSjboGK65eHgc124K6Hd/rF IgCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+qGHCihlNL7T5T1G7aMDu8MmDKY14zb9oDODHpK/qzo=; b=lKdAG/sQIwsMDaPsPyyR3dtVL+T7i3eykZiuLJ+c4KTEylKJlZckMUX9VlBVEVbQmT W1IhcxwkxS30L2As3BpiDnaG+aVSTAQv21aZ8/ayG/d/EqY2SUMu2N7hZiLNJ6sIRpud KKyfcTxv9x19bSAAgoNXAPD8sQGSPHBnEqrxUnu6aPAU9L3eDQKZhuAMnZe77TmdIHtv FtHanTUy8bw5BR7NVQGUEt/dYpXT05O079M4TWDo1jxyf/Ss0Rv3k0LMhehmpv295aED rPzQAahhg+0hn+Cwl5MFkohvMEP1bGKh+FSlUM7MH4oN/euLGGLGUwJIaPutzDM5gV+6 f0/g== X-Gm-Message-State: AJIora9X0o51/piiolnaDAA8nJeESBY/+7iwNUJovgi1AUAWcEmgUCJN g4PXdaLeEoA+i5dKwTwg4m0= X-Google-Smtp-Source: AGRyM1s0pSQbc35l3UIcCC5dxYRuJKUNwus2ZoTRJTvM1QfVMbun5o/ZzSvDe7WKsCprPPHG/fylnA== X-Received: by 2002:adf:dbc1:0:b0:219:e994:6ba7 with SMTP id e1-20020adfdbc1000000b00219e9946ba7mr21880459wrj.229.1656847218368; Sun, 03 Jul 2022 04:20:18 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id n7-20020a5d67c7000000b0021b9e8d4c22sm27314305wrw.61.2022.07.03.04.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:18 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 05/12] regmap-irq: Remove inappropriate uses of regmap_irq_update_bits() Date: Sun, 3 Jul 2022 12:20:54 +0100 Message-Id: <20220703112101.24493-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org regmap_irq_update_bits() is misnamed and should only be used for updating mask registers, since it checks the mask_writeonly flag. However, it was also used for updating wake and type registers. It's safe to replace these uses with regmap_update_bits() because there are no users of the mask_writeonly flag. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index fd7c4315d16b..cb20ce6f91e7 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -158,11 +158,11 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg = sub_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { if (d->chip->wake_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->wake_buf[i]); else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->wake_buf[i]); if (ret != 0) @@ -205,10 +205,10 @@ static void regmap_irq_sync_unlock(struct irq_data *data) continue; reg = sub_irq_reg(d, d->chip->type_base, i); if (d->chip->type_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->type_buf_def[i], ~d->type_buf[i]); else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->type_buf_def[i], d->type_buf[i]); if (ret != 0) dev_err(d->map->dev, "Failed to sync type in %x\n", @@ -825,11 +825,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, reg = sub_irq_reg(d, d->chip->wake_base, i); if (chip->wake_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], 0); else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->wake_buf[i]); if (ret != 0) { From patchwork Sun Jul 3 11:20:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E5A8CCA473 for ; Sun, 3 Jul 2022 11:20:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232650AbiGCLU0 (ORCPT ); Sun, 3 Jul 2022 07:20:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232679AbiGCLUW (ORCPT ); Sun, 3 Jul 2022 07:20:22 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47DAC95BA; Sun, 3 Jul 2022 04:20:21 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id r14so3675338wrg.1; Sun, 03 Jul 2022 04:20:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BEQIwlQTc4kPghW2wNEhgQMVH2n26SLzg8zoPvmRxGU=; b=jf/lFRst6UFUH21MpR8E90vea7crjb6XxvlT/OyLjocpaos3O/SMROskcbtS9x8I/T z7ypXsukvAEmsFdM5t0ALf5dsoJFs0YGtLEUr3EhU1v15aEd2SjTpx17C/JowaIR44wp KqIOLs17XmwH58Gy4F2O/9ev9YkkGor6np3/dOH/2itC7onnj/Rj0UTKLkiGrnbkw13L qreWE4gsoLdsXrVBDNLOqb+MZ5IXL4pE1YEocbiQNRJPoHhsCmtb5P8p2ozLDAkvLKcb mhIwTaq1m+d3QjtwNEki4s5gEVM4q+ou2DiPgIJb9yOWAGD2O4c51Xro6ksStNjzg51B njtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BEQIwlQTc4kPghW2wNEhgQMVH2n26SLzg8zoPvmRxGU=; b=A3tBH/MaDdfQ6iCFRXRYLaz4O50D3ChnEnkg4zq11bc89Z9vlogqGv1M4bbpga8asH 4h5/FOju/ExslOna1JG7AS9k5WKl5YusHQJxS3aAanOb7esA0Rm9GVdIcPa5qmHsiYzP NM85RfofE6HWVFYOt114DFBpncJGR0pMiaOGDvQqptcMShOIdxY9l2Cg3H9fgmdHXLqA oAGZ7TqWH508Hoy9pFORMWi/Q0C3FpMDfj7ayc8VLlZFjGewglqyJL5t2TADHbNTiZJW YMwgtKUp400LxEpsPsVDIyrvWSs3BV2l6ZQ9c5mECJgQ2D5LyFZxPhX4Mr0sY4hxzs42 fw1A== X-Gm-Message-State: AJIora8eK809lUBRfiHfOJ6Jp+ls7cK6V8RlO2Z7xgFIpL4D+vj3LQCa Jth0zyp7UwxbZITVi3OVATM= X-Google-Smtp-Source: AGRyM1uWuIWWAG7w7PwDhCMz+5larkbJP4ggYW9BJ7CluyIvf+ZF7lyAtrgkEm5cD1EoJJNmsnMOZA== X-Received: by 2002:a05:6000:1888:b0:21d:151c:92a0 with SMTP id a8-20020a056000188800b0021d151c92a0mr21519051wri.609.1656847219868; Sun, 03 Jul 2022 04:20:19 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id f18-20020adfb612000000b002185631adf0sm28301183wre.23.2022.07.03.04.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:19 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 06/12] regmap-irq: Remove mask_writeonly and regmap_irq_update_bits() Date: Sun, 3 Jul 2022 12:20:55 +0100 Message-Id: <20220703112101.24493-7-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Commit a71411dbf6c8 ("regmap: irq: add chip option mask_writeonly") introduced the mask_writeonly option, but it isn't used now and it appears it's never been used by any in-tree drivers. The motivation for the option is mentioned in the commit message, Some irq controllers have writeonly/multipurpose register layouts. In those cases we read invalid data back. [...] The option causes mask register updates to use regmap_write_bits() instead of regmap_update_bits(). However, regmap_write_bits() doesn't solve the reading invalid data problem. It's still a read-modify-write op like regmap_update_bits(). The difference is that 'update bits' will only write the new value if it is different from the current value, while 'write bits' will write the new value unconditionally, even if it's the same as the current value. This seems like a bit of a specialized use case and probably isn't that useful for regmap-irq, so let's just remove the option and go back to using an 'update bits' op for the mask registers. We can always add the option back if some driver ends up needing it in the future. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 24 +++++++----------------- include/linux/regmap.h | 2 -- 2 files changed, 7 insertions(+), 19 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index cb20ce6f91e7..7e93dd8af56b 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -80,16 +80,6 @@ static void regmap_irq_lock(struct irq_data *data) mutex_lock(&d->lock); } -static int regmap_irq_update_bits(struct regmap_irq_chip_data *d, - unsigned int reg, unsigned int mask, - unsigned int val) -{ - if (d->chip->mask_writeonly) - return regmap_write_bits(d->map, reg, mask, val); - else - return regmap_update_bits(d->map, reg, mask, val); -} - static void regmap_irq_sync_unlock(struct irq_data *data) { struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); @@ -130,11 +120,11 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg = sub_irq_reg(d, d->chip->mask_base, i); if (d->chip->mask_invert) { - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); } else if (d->chip->unmask_base) { /* set mask with mask_base register */ - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret < 0) dev_err(d->map->dev, @@ -143,12 +133,12 @@ static void regmap_irq_sync_unlock(struct irq_data *data) unmask_offset = d->chip->unmask_base - d->chip->mask_base; /* clear mask with unmask_base register */ - ret = regmap_irq_update_bits(d, + ret = regmap_update_bits(d->map, reg + unmask_offset, d->mask_buf_def[i], d->mask_buf[i]); } else { - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->mask_buf[i]); } if (ret != 0) @@ -763,17 +753,17 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, reg = sub_irq_reg(d, d->chip->mask_base, i); if (chip->mask_invert) - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf[i], ~d->mask_buf[i]); else if (d->chip->unmask_base) { unmask_offset = d->chip->unmask_base - d->chip->mask_base; - ret = regmap_irq_update_bits(d, + ret = regmap_update_bits(d->map, reg + unmask_offset, d->mask_buf[i], d->mask_buf[i]); } else - ret = regmap_irq_update_bits(d, reg, + ret = regmap_update_bits(d->map, reg, d->mask_buf[i], d->mask_buf[i]); if (ret != 0) { dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 106ca1172d3d..d21eb8ad2675 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1452,7 +1452,6 @@ struct regmap_irq_sub_irq_map { * * @status_base: Base status register address. * @mask_base: Base mask register address. - * @mask_writeonly: Base mask register is write only. * @unmask_base: Base unmask register address. for chips who have * separate mask and unmask registers * @ack_base: Base ack address. If zero then the chip is clear on read. @@ -1518,7 +1517,6 @@ struct regmap_irq_chip { unsigned int type_base; unsigned int *virt_reg_base; unsigned int irq_reg_stride; - unsigned int mask_writeonly:1; unsigned int init_ack_masked:1; unsigned int mask_invert:1; unsigned int use_ack:1; From patchwork Sun Jul 3 11:20:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67177C433EF for ; Sun, 3 Jul 2022 11:20:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232565AbiGCLU1 (ORCPT ); Sun, 3 Jul 2022 07:20:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232694AbiGCLUX (ORCPT ); Sun, 3 Jul 2022 07:20:23 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2899A458; Sun, 3 Jul 2022 04:20:22 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id o4so9471974wrh.3; Sun, 03 Jul 2022 04:20:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yGdqQ4oAuggJEmpNM1D1Sw+hLvuTVREq9oE+Alw71tA=; b=EG+vkCFgVJoNQmekAArWwhAIumrg5B9uWzpello5Vp+bS2/wq4tdmTeIUPTizpCB75 ZKndRpeWlUGYYWnRKCkM3mUqQ03DggomNogks1Tk0/PmueWOvqbBSiNtmri1j87Ga0+B ZbB3tj6DXGApQCCQRFGbSWja7kdb8NVRKlz6/hhGePxSA/NrMJz5YcqhyRugr8coFW5S nKutK5XQq+JMPOVWBH3JyJY9JJpH7LUmmOPIJfLVEkUnKiaLURHIKRJlRDuw22MAZCdj KBEVD1bvV2LdHFIt7qimYhPKGhivQFDaMGTFix6jdNQU8hniPzLclR4YG+zh2l7N9ydx d2Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yGdqQ4oAuggJEmpNM1D1Sw+hLvuTVREq9oE+Alw71tA=; b=o/N6fSIu/RXxrHnfnt2XmoAIS+A5NzvLL7KHBBbj1mh5jBJYO+LvmiJLB1cOjQj7ha pwztGnxG6eduVd7mrz3MxWJPqojoBaN036GBpg4AiUkinjVPSCnQKT5vtPlPhfvCNoas z3ZxsHjRK8w05Bg5ALTtYH13q0vK5Gn4noBUzt759912CfLUXP/eu0OMECyD6NOhEdQ7 a1lGHWtYAqJ3haXeCTj7hObwgU47TUklHv5kSo4ttbAGd0AK0fB30Yg5MGXpDIHAi772 LXobbuxL49YoK1ifepOAs+Q0+zCxaN7oYR/s5XLHWS9eRaYH428XFgcoy3y2WxSuCPD/ wk4A== X-Gm-Message-State: AJIora9IoT2FVTzCmvqh5fFnadu3j+JG/lWzmVBfpAPavOHqthCcoYMV yHnQrPJjk1+9AyrUrvSml/M= X-Google-Smtp-Source: AGRyM1ujFOaT8twkJWv+8aYHlazN6/7EE9xBdAmm4iYAMFxEvQ353Bu1GuiUrBByM7FG1VBhjY3HjQ== X-Received: by 2002:a5d:4d8e:0:b0:21d:68d4:56eb with SMTP id b14-20020a5d4d8e000000b0021d68d456ebmr1571358wru.40.1656847221425; Sun, 03 Jul 2022 04:20:21 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id q5-20020adff945000000b0021b9585276dsm26735987wrr.101.2022.07.03.04.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:20 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 07/12] regmap-irq: Refactor checks for status bulk read support Date: Sun, 3 Jul 2022 12:20:56 +0100 Message-Id: <20220703112101.24493-8-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org There are several conditions that must be satisfied to support bulk read of status registers. Move the check into a function to avoid duplicating it in two places. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 7e93dd8af56b..5f9a5856c45e 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -73,6 +73,14 @@ struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, return &data->chip->irqs[irq]; } +static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data) +{ + struct regmap *map = data->map; + + return data->irq_reg_stride == 1 && map->reg_stride == 1 && + !map->use_single_read; +} + static void regmap_irq_lock(struct irq_data *data) { struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); @@ -467,8 +475,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } } - } else if (!map->use_single_read && map->reg_stride == 1 && - data->irq_reg_stride == 1) { + } else if (regmap_irq_can_bulk_read_status(data)) { u8 *buf8 = data->status_reg_buf; u16 *buf16 = data->status_reg_buf; @@ -729,8 +736,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, else d->irq_reg_stride = 1; - if (!map->use_single_read && map->reg_stride == 1 && - d->irq_reg_stride == 1) { + if (regmap_irq_can_bulk_read_status(d)) { d->status_reg_buf = kmalloc_array(chip->num_regs, map->format.val_bytes, GFP_KERNEL); From patchwork Sun Jul 3 11:20:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D21DBCCA481 for ; Sun, 3 Jul 2022 11:20:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232699AbiGCLU1 (ORCPT ); Sun, 3 Jul 2022 07:20:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232704AbiGCLUZ (ORCPT ); Sun, 3 Jul 2022 07:20:25 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A0529FC7; Sun, 3 Jul 2022 04:20:23 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id v14so9469984wra.5; Sun, 03 Jul 2022 04:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pFicCXDe5rb79PhZKoaZ8t2q32vOWXf1ocVF975OVTs=; b=jc0OGUmynb6jwZrKYBfWwRpKcuOpLxgO8q+AHDcRPyMjE19YNsyHjM0WFzUnS5v+hO EcA/4fXSZg7Iz7FTus7FyVyCckr5lZLXwSjJLy+dM5i+sbSL1uBN5qVAmH3j5jEvZVCS dlKnBxnmUjwpiiWvzZbLE+kbkxiKAFZKKKoLSAgFCCB4Kx9xBl5R+21FsfbFKwMIXbHU KvVx13U8G6YLO6YpFpoDeLFkA4bwhQZtWnEyu/HhvNs5BOYhKPWCVWwCtcwbYevrcqrR 9XvMO+qP0eICqXPawyqFIa6KdN321HDS+f9I8n55FzRZKfIjYBSA7kdhKmDYwKrzXV4o b7cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pFicCXDe5rb79PhZKoaZ8t2q32vOWXf1ocVF975OVTs=; b=oQuJmklQvzUVaO5ShLlrlhUMFyctwDbMyfa/exiECYzR/rIJ6QXGZREcVL0Oek6OcG RnWwkcCvY/7nfBZQKS6ICQ4SPKhbaql2sgAgSmZAuvztGev449hMrhGhnpBXaQ8MiB6W W3SVVP+92Nc6uFW3lU3ibvxkLjFtMtqhKDl62H1sd79j5H5WjQ68vwkLO+6w/ZdIZpK0 qVXpDJBhsHNronsJ4IQloA7rRDdtky+poayOnrWnxjkrKSsOZcezUuK3FgesB+NzIhKf dVoDSxh0LxJghrZaP5cNAtyZhen+wqYq0+Ax14/476DVtI2g/giZ+wZtAlAqk57uaMgk B13A== X-Gm-Message-State: AJIora+XM1XJAUViCSbMzWjUqenCikIfqcOkkBwZbJs21ysHqmYbw/hB NFA6S+0j+JQTS3PrPsf2SziWqJ0hdwE= X-Google-Smtp-Source: AGRyM1sRlCztSwp2ypeh1frjYx1U9FX9yzApDKpO186Zi4agM1u91H3vbZA0hch3Yuc/IJNKH+x+gw== X-Received: by 2002:a5d:53c9:0:b0:21d:62f8:f99f with SMTP id a9-20020a5d53c9000000b0021d62f8f99fmr5134304wrw.214.1656847223120; Sun, 03 Jul 2022 04:20:23 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id bn14-20020a056000060e00b0021d20a43523sm16473857wrb.42.2022.07.03.04.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:22 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 08/12] regmap-irq: Introduce config registers for irq types Date: Sun, 3 Jul 2022 12:20:57 +0100 Message-Id: <20220703112101.24493-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Config registers provide a more uniform approach to handling irq type registers. They are essentially an extension of the virtual registers used by the qcom-pm8008 driver. Config registers can be represented as a 2D array: config_base[0] reg0,0 reg0,1 reg0,2 reg0,3 config_base[1] reg1,0 reg1,1 reg1,2 reg1,3 config_base[2] reg2,0 reg2,1 reg2,2 reg2,3 There are 'num_config_bases' base registers, each of which is used to address 'num_config_regs' registers. The addresses are calculated in the same way as for other bases. It is assumed that an irq's type is controlled by one column of registers; that column is identified by the irq's 'type_reg_offset'. The set_type_config() callback is responsible for updating the config register contents. It receives an array of buffers (each represents a row of registers) and the index of the column to update, along with the 'struct regmap_irq' description and requested irq type. Buffered values are written to registers in regmap_irq_sync_unlock(). Note that the entire register contents are overwritten, which is a minor change in behavior from type registers via 'type_base'. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 115 +++++++++++++++++++++++++++++-- include/linux/regmap.h | 12 ++++ 2 files changed, 122 insertions(+), 5 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 5f9a5856c45e..e3dbf55a561f 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -39,6 +39,7 @@ struct regmap_irq_chip_data { unsigned int *type_buf; unsigned int *type_buf_def; unsigned int **virt_buf; + unsigned int **config_buf; unsigned int irq_reg_stride; @@ -228,6 +229,17 @@ static void regmap_irq_sync_unlock(struct irq_data *data) } } + for (i = 0; i < d->chip->num_config_bases; i++) { + for (j = 0; j < d->chip->num_config_regs; j++) { + reg = sub_irq_reg(d, d->chip->config_base[i], j); + ret = regmap_write(map, reg, d->config_buf[i][j]); + if (ret) + dev_err(d->map->dev, + "Failed to write config %x: %d\n", + reg, ret); + } + } + if (d->chip->runtime_pm) pm_runtime_put(map->dev); @@ -287,7 +299,7 @@ static int regmap_irq_set_type(struct irq_data *data, unsigned int type) struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); struct regmap *map = d->map; const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); - int reg; + int reg, ret; const struct regmap_irq_type *t = &irq_data->type; if ((t->types_supported & type) != type) @@ -327,9 +339,19 @@ static int regmap_irq_set_type(struct irq_data *data, unsigned int type) return -EINVAL; } - if (d->chip->set_type_virt) - return d->chip->set_type_virt(d->virt_buf, type, data->hwirq, - reg); + if (d->chip->set_type_virt) { + ret = d->chip->set_type_virt(d->virt_buf, type, data->hwirq, + reg); + if (ret) + return ret; + } + + if (d->chip->set_type_config) { + ret = d->chip->set_type_config(d->config_buf, type, + irq_data, reg); + if (ret) + return ret; + } return 0; } @@ -599,6 +621,61 @@ static const struct irq_domain_ops regmap_domain_ops = { .xlate = irq_domain_xlate_onetwocell, }; +/** + * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. + * @buf: Buffer containing configuration register values, this is a 2D array of + * `num_config_bases` rows, each of `num_config_regs` elements. + * @type: The requested IRQ type. + * @irq_data: The IRQ being configured. + * @idx: Index of the irq's config registers within each array `buf[i]` + * + * This is a &struct regmap_irq_chip->set_type_config callback suitable for + * chips with one config register. Register values are updated according to + * the &struct regmap_irq_type data associated with an IRQ. + */ +int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx) +{ + const struct regmap_irq_type *t = &irq_data->type; + + if (t->type_reg_mask) + buf[0][idx] &= ~t->type_reg_mask; + else + buf[0][idx] &= ~(t->type_falling_val | + t->type_rising_val | + t->type_level_low_val | + t->type_level_high_val); + + switch (type) { + case IRQ_TYPE_EDGE_FALLING: + buf[0][idx] |= t->type_falling_val; + break; + + case IRQ_TYPE_EDGE_RISING: + buf[0][idx] |= t->type_rising_val; + break; + + case IRQ_TYPE_EDGE_BOTH: + buf[0][idx] |= (t->type_falling_val | + t->type_rising_val); + break; + + case IRQ_TYPE_LEVEL_HIGH: + buf[0][idx] |= t->type_level_high_val; + break; + + case IRQ_TYPE_LEVEL_LOW: + buf[0][idx] |= t->type_level_low_val; + break; + + default: + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL_GPL(regmap_irq_set_type_config_simple); + /** * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling * @@ -724,6 +801,24 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, } } + if (chip->num_config_bases && chip->num_config_regs) { + /* + * Create config_buf[num_config_bases][num_config_regs] + */ + d->config_buf = kcalloc(chip->num_config_bases, + sizeof(*d->config_buf), GFP_KERNEL); + if (!d->config_buf) + goto err_alloc; + + for (i = 0; i < chip->num_config_regs; i++) { + d->config_buf[i] = kcalloc(chip->num_config_regs, + sizeof(**d->config_buf), + GFP_KERNEL); + if (!d->config_buf[i]) + goto err_alloc; + } + } + d->irq_chip = regmap_irq_chip; d->irq_chip.name = chip->name; d->irq = irq; @@ -894,6 +989,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, kfree(d->virt_buf[i]); kfree(d->virt_buf); } + if (d->config_buf) { + for (i = 0; i < chip->num_config_bases; i++) + kfree(d->config_buf[i]); + kfree(d->config_buf); + } kfree(d); return ret; } @@ -934,7 +1034,7 @@ EXPORT_SYMBOL_GPL(regmap_add_irq_chip); void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) { unsigned int virq; - int hwirq; + int i, hwirq; if (!d) return; @@ -964,6 +1064,11 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) kfree(d->mask_buf); kfree(d->status_reg_buf); kfree(d->status_buf); + if (d->config_buf) { + for (i = 0; i < d->chip->num_config_bases; i++) + kfree(d->config_buf[i]); + kfree(d->config_buf); + } kfree(d); } EXPORT_SYMBOL_GPL(regmap_del_irq_chip); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index d21eb8ad2675..432449f318cb 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1459,6 +1459,7 @@ struct regmap_irq_sub_irq_map { * @wake_base: Base address for wake enables. If zero unsupported. * @type_base: Base address for irq type. If zero unsupported. * @virt_reg_base: Base addresses for extra config regs. + * @config_base: Base address for IRQ type config regs. If null unsupported. * @irq_reg_stride: Stride to use for chips where registers are not contiguous. * @init_ack_masked: Ack all masked interrupts once during initalization. * @mask_invert: Inverted mask register: cleared bits are masked out. @@ -1488,12 +1489,15 @@ struct regmap_irq_sub_irq_map { * @num_type_reg: Number of type registers. * @num_virt_regs: Number of non-standard irq configuration registers. * If zero unsupported. + * @num_config_bases: Number of config base registers. + * @num_config_regs: Number of config registers for each config base register. * @handle_pre_irq: Driver specific callback to handle interrupt from device * before regmap_irq_handler process the interrupts. * @handle_post_irq: Driver specific callback to handle interrupt from device * after handling the interrupts in regmap_irq_handler(). * @set_type_virt: Driver specific callback to extend regmap_irq_set_type() * and configure virt regs. + * @set_type_config: Callback used for configuring irq types. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. * @@ -1516,6 +1520,7 @@ struct regmap_irq_chip { unsigned int wake_base; unsigned int type_base; unsigned int *virt_reg_base; + const unsigned int *config_base; unsigned int irq_reg_stride; unsigned int init_ack_masked:1; unsigned int mask_invert:1; @@ -1537,16 +1542,23 @@ struct regmap_irq_chip { int num_type_reg; int num_virt_regs; + int num_config_bases; + int num_config_regs; int (*handle_pre_irq)(void *irq_drv_data); int (*handle_post_irq)(void *irq_drv_data); int (*set_type_virt)(unsigned int **buf, unsigned int type, unsigned long hwirq, int reg); + int (*set_type_config)(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx); void *irq_drv_data; }; struct regmap_irq_chip_data; +int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx); + int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, int irq_base, const struct regmap_irq_chip *chip, struct regmap_irq_chip_data **data); From patchwork Sun Jul 3 11:20:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D4BBC433EF for ; Sun, 3 Jul 2022 11:20:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232716AbiGCLUh (ORCPT ); Sun, 3 Jul 2022 07:20:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232723AbiGCLU2 (ORCPT ); Sun, 3 Jul 2022 07:20:28 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A3FC9FD9; Sun, 3 Jul 2022 04:20:26 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id f2so4092455wrr.6; Sun, 03 Jul 2022 04:20:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nXcllgLFQkv+OtgQlnqQLrSG+8U6QBobVbJQIfbLeDc=; b=ASubR/DorqHNaHOZTMNmJf42AORByMmajCRhw/xu6F9k8A+f2NMIwkcEXKNu3WV+RV F5zT6mcRy3V3xnxgAv48DKjHt1Aa4zWH5mb4aYRp8Aaw7fDq49gqzsUGzUBBO1BMIaVs /eYBOxLm1LxL+nENV6FuigRE12tjcDVBX3IuFQsOz5+tmlv8kBGQL75CwVCJ+cFRHVP8 G3Gj7qv0/7r//MEeoqtpM5F9T3OMj0S+6wtYSKc7/ibJr+C43ZSVngVGtpDYch/ddg2t THFtpNYeM4r7iDdSEIxb/LUs1RAv9NoUfgV20IJO3kFqv4Ihuyy/S1t+kx5Sfl+hDscb FvSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nXcllgLFQkv+OtgQlnqQLrSG+8U6QBobVbJQIfbLeDc=; b=yktceRG1hW3YQHCQN+lJKJGFiSG2jTbHdsMrBC6nbID9vzerNRicmdMsZ3P+CUoTCF jNNxgmQepEVZMsmR563zWQfDYDNE6rP0bnGjZRdsRKwO2zYaTlk2JSjXBAOGHNTzI+MY blakbm+2tCG9AlaemoJv7+qu6gM6gIUm7Kf7Njo9QioUCUIp02FROsKYz5QveRww+WRm YeG1/zMQlC/fDqEDWj0Ga1mZlMzgZYrS4F0vQcydBiAQeARWNmFeEUH5tPnTEUocLRwu 1zTJYdMtq+v/V7Txj7DHAIovwL8hvsKdoW5c9N654MIQXFEuCg3/JyFVfxRkPBjxpQuL fRpg== X-Gm-Message-State: AJIora8YYFdjXFR+RjSoJ8fIyO/8OzUuHfeolYtRD70hdQnd4gr90sZe QGqu5JMOE/oLJuOKAiKziRA7sw88EK8= X-Google-Smtp-Source: AGRyM1swzRxDpf8D0d6n5lH5iXztubINWaOhPoN2s7N/2M4fBoQkUD3hkWUFlBtqauR62tmB/UXOzA== X-Received: by 2002:a5d:5107:0:b0:21b:8c5d:1072 with SMTP id s7-20020a5d5107000000b0021b8c5d1072mr23264520wrt.378.1656847224899; Sun, 03 Jul 2022 04:20:24 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id n23-20020a7bc5d7000000b003a04a9504b0sm13212450wmk.40.2022.07.03.04.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:24 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 09/12] regmap-irq: Deprecate type registers and virtual registers Date: Sun, 3 Jul 2022 12:20:58 +0100 Message-Id: <20220703112101.24493-10-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Config registers can be used to replace both type and virtual registers, so mark both features are deprecated and issue a warning if they're used. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 6 ++++++ include/linux/regmap.h | 18 ++++++++++++------ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index e3dbf55a561f..8cbc62c3d638 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -726,6 +726,12 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, return -EINVAL; } + if (chip->num_type_reg) + dev_warn(map->dev, "type registers are deprecated; use config registers instead"); + + if (chip->num_virt_regs || chip->virt_reg_base || chip->set_type_virt) + dev_warn(map->dev, "virtual registers are deprecated; use config registers instead"); + if (irq_base) { irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); if (irq_base < 0) { diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 432449f318cb..2b5b07f85cc0 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1457,8 +1457,10 @@ struct regmap_irq_sub_irq_map { * @ack_base: Base ack address. If zero then the chip is clear on read. * Using zero value is possible with @use_ack bit. * @wake_base: Base address for wake enables. If zero unsupported. - * @type_base: Base address for irq type. If zero unsupported. - * @virt_reg_base: Base addresses for extra config regs. + * @type_base: Base address for irq type. If zero unsupported. Deprecated, + * use @config_base instead. + * @virt_reg_base: Base addresses for extra config regs. Deprecated, use + * @config_base instead. * @config_base: Base address for IRQ type config regs. If null unsupported. * @irq_reg_stride: Stride to use for chips where registers are not contiguous. * @init_ack_masked: Ack all masked interrupts once during initalization. @@ -1467,7 +1469,8 @@ struct regmap_irq_sub_irq_map { * @ack_invert: Inverted ack register: cleared bits for ack. * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts. * @wake_invert: Inverted wake register: cleared bits are wake enabled. - * @type_invert: Invert the type flags. + * @type_invert: Invert the type flags. Deprecated, use config registers + * instead. * @type_in_mask: Use the mask registers for controlling irq type. Use this if * the hardware provides separate bits for rising/falling edge * or low/high level interrupts and they should be combined into @@ -1486,9 +1489,11 @@ struct regmap_irq_sub_irq_map { * @irqs: Descriptors for individual IRQs. Interrupt numbers are * assigned based on the index in the array of the interrupt. * @num_irqs: Number of descriptors. - * @num_type_reg: Number of type registers. + * @num_type_reg: Number of type registers. Deprecated, use config registers + * instead. * @num_virt_regs: Number of non-standard irq configuration registers. - * If zero unsupported. + * If zero unsupported. Deprecated, use config registers + * instead. * @num_config_bases: Number of config base registers. * @num_config_regs: Number of config registers for each config base register. * @handle_pre_irq: Driver specific callback to handle interrupt from device @@ -1496,7 +1501,8 @@ struct regmap_irq_sub_irq_map { * @handle_post_irq: Driver specific callback to handle interrupt from device * after handling the interrupts in regmap_irq_handler(). * @set_type_virt: Driver specific callback to extend regmap_irq_set_type() - * and configure virt regs. + * and configure virt regs. Deprecated, use @set_type_config + * callback and config registers instead. * @set_type_config: Callback used for configuring irq types. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. From patchwork Sun Jul 3 11:20:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3610C433EF for ; Sun, 3 Jul 2022 11:20:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232793AbiGCLU5 (ORCPT ); Sun, 3 Jul 2022 07:20:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232790AbiGCLUf (ORCPT ); Sun, 3 Jul 2022 07:20:35 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FC35A473; Sun, 3 Jul 2022 04:20:28 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id b26so9491264wrc.2; Sun, 03 Jul 2022 04:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bSfmZia4N88+QuTxam9V/x71AfxUr34uHrXfe8m2m+s=; b=e0+8yuwI5okIBqeg5zNokoRoOPY6/DvUlVK3PEspKrysI9Cm/plvvpX8r2n4JGYxCV AIHBaGq6klA+HnJWjq8f4VrQCkqxak4cPpTS2W5cvsYwrDNaylMYL2hr8RE0h19/gNe4 MJbSLf0lWAZBFbNf/vtT9qDr0MKA+feZNHZ8VW718/xpbAve+7y0u1OuLQ8rhwJH4Efe j5BbxDvbsoP2AODrMXp0/JFhXZw9uZMAQciJBGthoT/09g4THMemx6mPvE0lFtruMtn8 LsHGUnhbr0SLvLhv0pvQv5q1Wh7KebpCT8VYCjSRfK4InZFuB90G7CIsAuvUDP5A6cbD CNUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bSfmZia4N88+QuTxam9V/x71AfxUr34uHrXfe8m2m+s=; b=tSg252AaOU3Lld5Ugd6h5UqLBAPQkt0BFD+a0+zhcoLw3GZzvA3Mu2plkvjQ8jbhvE rqSmEQXdvYLZpr8nC25BPvwIqraDjnLaSN0Am6i2g0ZNtZk31x17xIMcNCQ3U2dIp/Nb yiRRg/lqvBgyoBJTjIH09Emf0ay1mCYqktGH/WcYImNe0B8LnXOzTdeMh2fCcXew7bOx lJDtodh4Ade2KQV/DDhPISBCWvLaIuDX7EZPnE18S+DsCHcWBU+8ZAPvS7zEqprhaaqy 4Vnx160mfPnkeAynTxyxDFGMkDiUdCUAy8X/7JJjAp1qdyBHwa/RMCkEn8KSpeGhVB8V Mhdg== X-Gm-Message-State: AJIora84sSf34Y5cvnaNEoDIENv+LLtNo5A5m6cKt8/2DjJm4zbkNMyJ b7DkGTuJBw0fNPSlqDW5ZSY= X-Google-Smtp-Source: AGRyM1u6zxqrBezWUIlyy0xQlViWwHxIPyUF3G2qIa+Bsp4QteaBXh0kIIkKnDs6SQX8XohcGakrmw== X-Received: by 2002:a5d:59a7:0:b0:21b:cd67:52d9 with SMTP id p7-20020a5d59a7000000b0021bcd6752d9mr22914933wrr.194.1656847226625; Sun, 03 Jul 2022 04:20:26 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id v7-20020adfa1c7000000b0021d6924b777sm626421wrv.115.2022.07.03.04.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:26 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 10/12] regmap-irq: Fix inverted handling of unmask registers Date: Sun, 3 Jul 2022 12:20:59 +0100 Message-Id: <20220703112101.24493-11-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org To me "unmask" suggests that we write 1s to the register when an interrupt is enabled. This also makes sense because it's the opposite of what the "mask" register does (write 1s to disable an interrupt). But regmap-irq does the opposite: for a disabled interrupt, it writes 1s to "unmask" and 0s to "mask". This is surprising and deviates from the usual way mask registers are handled. Additionally, mask_invert didn't interact with unmask registers properly -- it caused them to be ignored entirely. Fix this by making mask and unmask registers orthogonal, using the following behavior: * Mask registers are written with 1s for disabled interrupts. * Unmask registers are written with 1s for enabled interrupts. This behavior supports both normal or inverted mask registers and separate set/clear registers via different combinations of mask_base/unmask_base. The old unmask register behavior is deprecated. Drivers need to opt-in to the new behavior by setting mask_unmask_non_inverted. Warnings are issued if the driver relies on deprecated behavior. Chips that only set one of mask_base/unmask_base don't have to use the mask_unmask_non_inverted flag because that use case was previously not supported. The mask_invert flag is also deprecated in favor of describing inverted mask registers as unmask registers. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 114 +++++++++++++++++++------------ include/linux/regmap.h | 18 ++++- 2 files changed, 84 insertions(+), 48 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 8cbc62c3d638..2c724ae185c4 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -30,6 +30,9 @@ struct regmap_irq_chip_data { int irq; int wake_count; + unsigned int mask_base; + unsigned int unmask_base; + void *status_reg_buf; unsigned int *main_status_buf; unsigned int *status_buf; @@ -95,7 +98,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) struct regmap *map = d->map; int i, j, ret; u32 reg; - u32 unmask_offset; u32 val; if (d->chip->runtime_pm) { @@ -124,35 +126,23 @@ static void regmap_irq_sync_unlock(struct irq_data *data) * suppress pointless writes. */ for (i = 0; i < d->chip->num_regs; i++) { - if (!d->chip->mask_base) - continue; - - reg = sub_irq_reg(d, d->chip->mask_base, i); - if (d->chip->mask_invert) { + if (d->mask_base) { + reg = sub_irq_reg(d, d->mask_base, i); ret = regmap_update_bits(d->map, reg, - d->mask_buf_def[i], ~d->mask_buf[i]); - } else if (d->chip->unmask_base) { - /* set mask with mask_base register */ + d->mask_buf_def[i], d->mask_buf[i]); + if (ret) + dev_err(d->map->dev, "Failed to sync masks in %x\n", + reg); + } + + if (d->unmask_base) { + reg = sub_irq_reg(d, d->unmask_base, i); ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); - if (ret < 0) - dev_err(d->map->dev, - "Failed to sync unmasks in %x\n", + if (ret) + dev_err(d->map->dev, "Failed to sync masks in %x\n", reg); - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; - /* clear mask with unmask_base register */ - ret = regmap_update_bits(d->map, - reg + unmask_offset, - d->mask_buf_def[i], - d->mask_buf[i]); - } else { - ret = regmap_update_bits(d->map, reg, - d->mask_buf_def[i], d->mask_buf[i]); } - if (ret != 0) - dev_err(d->map->dev, "Failed to sync masks in %x\n", - reg); reg = sub_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { @@ -704,7 +694,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, int ret = -ENOMEM; int num_type_reg; u32 reg; - u32 unmask_offset; if (chip->num_regs <= 0) return -EINVAL; @@ -832,6 +821,42 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->chip = chip; d->irq_base = irq_base; + if (chip->mask_base && chip->unmask_base && + !chip->mask_unmask_non_inverted) { + /* + * Chips that specify both mask_base and unmask_base used to + * get inverted mask behavior by default, with no way to ask + * for the normal, non-inverted behavior. This "inverted by + * default" behavior is deprecated, but we have to support it + * until existing drivers have been fixed. + * + * Existing drivers should be updated by swapping mask_base + * and unmask_base and setting mask_unmask_non_inverted=true. + * New drivers should always set the flag. + */ + dev_warn(map->dev, "mask_base and unmask_base are inverted, please fix it"); + + /* Might as well warn about mask_invert while we're at it... */ + if (chip->mask_invert) + dev_warn(map->dev, "mask_invert=true ignored"); + + d->mask_base = chip->unmask_base; + d->unmask_base = chip->mask_base; + } else if (chip->mask_invert) { + /* + * Swap the roles of mask_base and unmask_base if the bits are + * inverted. This is deprecated, drivers should use unmask_base + * directly. + */ + dev_warn(map->dev, "mask_invert=true is deprecated; please switch to unmask_base"); + + d->mask_base = chip->unmask_base; + d->unmask_base = chip->mask_base; + } else { + d->mask_base = chip->mask_base; + d->unmask_base = chip->unmask_base; + } + if (chip->irq_reg_stride) d->irq_reg_stride = chip->irq_reg_stride; else @@ -854,28 +879,27 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, /* Mask all the interrupts by default */ for (i = 0; i < chip->num_regs; i++) { d->mask_buf[i] = d->mask_buf_def[i]; - if (!chip->mask_base) - continue; - - reg = sub_irq_reg(d, d->chip->mask_base, i); - if (chip->mask_invert) + if (d->mask_base) { + reg = sub_irq_reg(d, d->mask_base, i); ret = regmap_update_bits(d->map, reg, - d->mask_buf[i], ~d->mask_buf[i]); - else if (d->chip->unmask_base) { - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; - ret = regmap_update_bits(d->map, - reg + unmask_offset, - d->mask_buf[i], - d->mask_buf[i]); - } else + d->mask_buf_def[i], d->mask_buf[i]); + if (ret) { + dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", + reg, ret); + goto err_alloc; + } + } + + if (d->unmask_base) { + reg = sub_irq_reg(d, d->unmask_base, i); ret = regmap_update_bits(d->map, reg, - d->mask_buf[i], d->mask_buf[i]); - if (ret != 0) { - dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", - reg, ret); - goto err_alloc; + d->mask_buf_def[i], ~d->mask_buf[i]); + if (ret) { + dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", + reg, ret); + goto err_alloc; + } } if (!chip->init_ack_masked) diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 2b5b07f85cc0..708f36dfaeda 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1451,9 +1451,10 @@ struct regmap_irq_sub_irq_map { * main_status set. * * @status_base: Base status register address. - * @mask_base: Base mask register address. - * @unmask_base: Base unmask register address. for chips who have - * separate mask and unmask registers + * @mask_base: Base mask register address. Mask bits are set to 1 when an + * interrupt is masked, 0 when unmasked. + * @unmask_base: Base unmask register address. Unmask bits are set to 1 when + * an interrupt is unmasked and 0 when masked. * @ack_base: Base ack address. If zero then the chip is clear on read. * Using zero value is possible with @use_ack bit. * @wake_base: Base address for wake enables. If zero unsupported. @@ -1465,6 +1466,16 @@ struct regmap_irq_sub_irq_map { * @irq_reg_stride: Stride to use for chips where registers are not contiguous. * @init_ack_masked: Ack all masked interrupts once during initalization. * @mask_invert: Inverted mask register: cleared bits are masked out. + * Deprecated; prefer describing an inverted mask register as + * an unmask register. + * @mask_unmask_non_inverted: Controls mask bit inversion for chips that set + * both @mask_base and @unmask_base. If false, mask and unmask bits are + * inverted (which is deprecated behavior); if true, bits will not be + * inverted and the registers keep their normal behavior. Note that if + * you use only one of @mask_base or @unmask_base, this flag has no + * effect and is unnecessary. Any new drivers that set both @mask_base + * and @unmask_base should set this to true to avoid relying on the + * deprecated behavior. * @use_ack: Use @ack register even if it is zero. * @ack_invert: Inverted ack register: cleared bits for ack. * @clear_ack: Use this to set 1 and 0 or vice-versa to clear interrupts. @@ -1530,6 +1541,7 @@ struct regmap_irq_chip { unsigned int irq_reg_stride; unsigned int init_ack_masked:1; unsigned int mask_invert:1; + unsigned int mask_unmask_non_inverted:1; unsigned int use_ack:1; unsigned int ack_invert:1; unsigned int clear_ack:1; From patchwork Sun Jul 3 11:21:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55262C43334 for ; Sun, 3 Jul 2022 11:21:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232805AbiGCLU6 (ORCPT ); Sun, 3 Jul 2022 07:20:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232795AbiGCLUf (ORCPT ); Sun, 3 Jul 2022 07:20:35 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 109DCB1D1; Sun, 3 Jul 2022 04:20:28 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id f2so4092598wrr.6; Sun, 03 Jul 2022 04:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GChi4+tCRgJw+LC1musq3zeH+IbH940r8tOwxCcgc20=; b=KH+lNSWp5icbsSvzIrti63gZgq6qfJ5amDPqEMaFL3j22W5i2JagulYaN1zDDhVSc9 EYAh6ADL1JB+FUxidaslQoqv26J8LauOiQJLU/GLF4pKFin9qBqkno2suZqPUvFRHawT z+Vh9uKStIX6VDqGApc8p//6e5hfAq+uP1niAez2Zwp9PSfvh/EsTS52BzbTWbUxjb/1 pwhkLDvfFfMnz0kZlhas9qpySklKGibSGixYNfsMCnweP4hx5zKxqLQOzGYDXH6kJvNJ CumqirCt/gGpXO6EaHz3o6E/VNiS8JgmwUJiAIHlomAhBiiWfHb4t/f2H5gX8v6hjhCy YRaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GChi4+tCRgJw+LC1musq3zeH+IbH940r8tOwxCcgc20=; b=v2ob3cNFahHkEN4jEhGo3W70kSMvTpi1VvgPcouDMJDtmDEhum2vuPoGevDXLM9MEY 4FUoOkW0pIgNf7mpIjhgWoQP+MRmtRTIDBT3TRdm7Nd1AV3EPt3lOteDkBm17+Jt5z/i i8Fu+hTLEh3BbpbDY9XyaptUepnBF4EwWgrSDEbgoERwuK74uro8AGDE+8LzvIb95uVE 6h7Aa2m3mXpF689yQzcYn86V7Xarf0Ux2qqoeBH+DbiBtKW9jq6hRvuXOH3dIpXYa/yG 6mkmaoKG1x9Vey1Pq0XHXUjZHhbRHfvNcLnDEqRM9czTKX8OhUuufQIX/GRieFWJsLs8 BGeg== X-Gm-Message-State: AJIora/4CHufk1KG/gz+nnrQmEPk4YqJt421oMCOW78bJfQisXQRtYLZ y7xpyNJ78ABk4IZnGRyXwUo= X-Google-Smtp-Source: AGRyM1vNeQxuFGP8EMom0TT8VVNMieQSTJ/VSkErxzDTortFKgdV9pJ+ja+bzhhXI1wI5epdVcOBfg== X-Received: by 2002:a5d:56cc:0:b0:21d:649c:b520 with SMTP id m12-20020a5d56cc000000b0021d649cb520mr3677651wrw.669.1656847228397; Sun, 03 Jul 2022 04:20:28 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id v192-20020a1cacc9000000b003975c7058bfsm16369180wme.12.2022.07.03.04.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:28 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 11/12] regmap-irq: Add get_irq_reg() callback Date: Sun, 3 Jul 2022 12:21:00 +0100 Message-Id: <20220703112101.24493-12-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Replace the internal sub_irq_reg() function with a public callback that drivers can use when they have more complex register layouts. The default implementation is regmap_irq_get_irq_reg_linear(), used if the chip doesn't provide its own callback. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 126 ++++++++++++++++++++----------- include/linux/regmap.h | 15 +++- 2 files changed, 93 insertions(+), 48 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 2c724ae185c4..ec658755dd1b 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -46,30 +46,12 @@ struct regmap_irq_chip_data { unsigned int irq_reg_stride; + unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, + unsigned int base, int index); + unsigned int clear_status:1; }; -static int sub_irq_reg(struct regmap_irq_chip_data *data, - unsigned int base_reg, int i) -{ - const struct regmap_irq_chip *chip = data->chip; - struct regmap *map = data->map; - struct regmap_irq_sub_irq_map *subreg; - unsigned int offset; - int reg = 0; - - if (!chip->sub_reg_offsets || !chip->not_fixed_stride) { - /* Assume linear mapping */ - reg = base_reg + (i * map->reg_stride * data->irq_reg_stride); - } else { - subreg = &chip->sub_reg_offsets[i]; - offset = subreg->offset[0]; - reg = base_reg + offset; - } - - return reg; -} - static inline const struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, int irq) @@ -81,7 +63,13 @@ static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data) { struct regmap *map = data->map; + /* + * While possible that a user-defined ->get_irq_reg() callback might + * be linear enough to support bulk reads, most of the time it won't. + * Therefore only allow them if the default callback is being used. + */ return data->irq_reg_stride == 1 && map->reg_stride == 1 && + data->get_irq_reg == regmap_irq_get_irq_reg_linear && !map->use_single_read; } @@ -109,7 +97,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) if (d->clear_status) { for (i = 0; i < d->chip->num_regs; i++) { - reg = sub_irq_reg(d, d->chip->status_base, i); + reg = d->get_irq_reg(d, d->chip->status_base, i); ret = regmap_read(map, reg, &val); if (ret) @@ -127,7 +115,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) */ for (i = 0; i < d->chip->num_regs; i++) { if (d->mask_base) { - reg = sub_irq_reg(d, d->mask_base, i); + reg = d->get_irq_reg(d, d->mask_base, i); ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret) @@ -136,7 +124,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) } if (d->unmask_base) { - reg = sub_irq_reg(d, d->unmask_base, i); + reg = d->get_irq_reg(d, d->unmask_base, i); ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret) @@ -144,7 +132,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) reg); } - reg = sub_irq_reg(d, d->chip->wake_base, i); + reg = d->get_irq_reg(d, d->chip->wake_base, i); if (d->wake_buf) { if (d->chip->wake_invert) ret = regmap_update_bits(d->map, reg, @@ -168,7 +156,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) * it'll be ignored in irq handler, then may introduce irq storm */ if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { - reg = sub_irq_reg(d, d->chip->ack_base, i); + reg = d->get_irq_reg(d, d->chip->ack_base, i); /* some chips ack by write 0 */ if (d->chip->ack_invert) @@ -192,7 +180,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) for (i = 0; i < d->chip->num_type_reg; i++) { if (!d->type_buf_def[i]) continue; - reg = sub_irq_reg(d, d->chip->type_base, i); + reg = d->get_irq_reg(d, d->chip->type_base, i); if (d->chip->type_invert) ret = regmap_update_bits(d->map, reg, d->type_buf_def[i], ~d->type_buf[i]); @@ -208,8 +196,8 @@ static void regmap_irq_sync_unlock(struct irq_data *data) if (d->chip->num_virt_regs) { for (i = 0; i < d->chip->num_virt_regs; i++) { for (j = 0; j < d->chip->num_regs; j++) { - reg = sub_irq_reg(d, d->chip->virt_reg_base[i], - j); + reg = d->get_irq_reg(d, d->chip->virt_reg_base[i], + j); ret = regmap_write(map, reg, d->virt_buf[i][j]); if (ret != 0) dev_err(d->map->dev, @@ -221,7 +209,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data) for (i = 0; i < d->chip->num_config_bases; i++) { for (j = 0; j < d->chip->num_config_regs; j++) { - reg = sub_irq_reg(d, d->chip->config_base[i], j); + reg = d->get_irq_reg(d, d->chip->config_base[i], j); ret = regmap_write(map, reg, d->config_buf[i][j]); if (ret) dev_err(d->map->dev, @@ -382,14 +370,17 @@ static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, const struct regmap_irq_chip *chip = data->chip; struct regmap *map = data->map; struct regmap_irq_sub_irq_map *subreg; + unsigned int reg; int i, ret = 0; if (!chip->sub_reg_offsets) { - /* Assume linear mapping */ - ret = regmap_read(map, chip->status_base + - (b * map->reg_stride * data->irq_reg_stride), - &data->status_buf[b]); + reg = data->get_irq_reg(data, chip->status_base, b); + ret = regmap_read(map, reg, &data->status_buf[b]); } else { + /* + * Note we can't use ->get_irq_reg() here because the offsets + * in 'subreg' are *not* interchangeable with indices. + */ subreg = &chip->sub_reg_offsets[b]; for (i = 0; i < subreg->num_regs; i++) { unsigned int offset = subreg->offset[i]; @@ -455,10 +446,18 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) * sake of simplicity. and add bulk reads only if needed */ for (i = 0; i < chip->num_main_regs; i++) { - ret = regmap_read(map, chip->main_status + - (i * map->reg_stride - * data->irq_reg_stride), - &data->main_status_buf[i]); + /* + * For not_fixed_stride, don't use ->get_irq_reg(). + * It would produce an incorrect result. + */ + if (data->chip->not_fixed_stride) + reg = chip->main_status + + i * map->reg_stride * data->irq_reg_stride; + else + reg = data->get_irq_reg(data, + chip->main_status, i); + + ret = regmap_read(map, reg, &data->main_status_buf[i]); if (ret) { dev_err(map->dev, "Failed to read IRQ status %d\n", @@ -523,7 +522,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } else { for (i = 0; i < data->chip->num_regs; i++) { - unsigned int reg = sub_irq_reg(data, + unsigned int reg = data->get_irq_reg(data, data->chip->status_base, i); ret = regmap_read(map, reg, &data->status_buf[i]); @@ -551,7 +550,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) data->status_buf[i] &= ~data->mask_buf[i]; if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { - reg = sub_irq_reg(data, data->chip->ack_base, i); + reg = data->get_irq_reg(data, data->chip->ack_base, i); if (chip->ack_invert) ret = regmap_write(map, reg, @@ -611,6 +610,36 @@ static const struct irq_domain_ops regmap_domain_ops = { .xlate = irq_domain_xlate_onetwocell, }; +/** + * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback. + * @data: Data for the &struct regmap_irq_chip + * @base: Base register + * @index: Register index + * + * Returns the register address corresponding to the given @base and @index + * by the formula ``base + index * regmap_stride * irq_reg_stride``. + */ +unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data, + unsigned int base, int index) +{ + const struct regmap_irq_chip *chip = data->chip; + struct regmap *map = data->map; + + /* + * FIXME: This is for backward compatibility and should be removed + * when not_fixed_stride is dropped (it's only used by qcom-pm8008). + */ + if (chip->not_fixed_stride && chip->sub_reg_offsets) { + struct regmap_irq_sub_irq_map *subreg; + + subreg = &chip->sub_reg_offsets[0]; + return base + subreg->offset[0]; + } + + return base + index * map->reg_stride * data->irq_reg_stride; +} +EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear); + /** * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. * @buf: Buffer containing configuration register values, this is a 2D array of @@ -862,6 +891,11 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, else d->irq_reg_stride = 1; + if (chip->get_irq_reg) + d->get_irq_reg = chip->get_irq_reg; + else + d->get_irq_reg = regmap_irq_get_irq_reg_linear; + if (regmap_irq_can_bulk_read_status(d)) { d->status_reg_buf = kmalloc_array(chip->num_regs, map->format.val_bytes, @@ -881,7 +915,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->mask_buf[i] = d->mask_buf_def[i]; if (d->mask_base) { - reg = sub_irq_reg(d, d->mask_base, i); + reg = d->get_irq_reg(d, d->mask_base, i); ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], d->mask_buf[i]); if (ret) { @@ -892,7 +926,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, } if (d->unmask_base) { - reg = sub_irq_reg(d, d->unmask_base, i); + reg = d->get_irq_reg(d, d->unmask_base, i); ret = regmap_update_bits(d->map, reg, d->mask_buf_def[i], ~d->mask_buf[i]); if (ret) { @@ -906,7 +940,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, continue; /* Ack masked but set interrupts */ - reg = sub_irq_reg(d, d->chip->status_base, i); + reg = d->get_irq_reg(d, d->chip->status_base, i); ret = regmap_read(map, reg, &d->status_buf[i]); if (ret != 0) { dev_err(map->dev, "Failed to read IRQ status: %d\n", @@ -918,7 +952,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, d->status_buf[i] = ~d->status_buf[i]; if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { - reg = sub_irq_reg(d, d->chip->ack_base, i); + reg = d->get_irq_reg(d, d->chip->ack_base, i); if (chip->ack_invert) ret = regmap_write(map, reg, ~(d->status_buf[i] & d->mask_buf[i])); @@ -943,7 +977,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, if (d->wake_buf) { for (i = 0; i < chip->num_regs; i++) { d->wake_buf[i] = d->mask_buf_def[i]; - reg = sub_irq_reg(d, d->chip->wake_base, i); + reg = d->get_irq_reg(d, d->chip->wake_base, i); if (chip->wake_invert) ret = regmap_update_bits(d->map, reg, @@ -963,7 +997,7 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, if (chip->num_type_reg && !chip->type_in_mask) { for (i = 0; i < chip->num_type_reg; ++i) { - reg = sub_irq_reg(d, d->chip->type_base, i); + reg = d->get_irq_reg(d, d->chip->type_base, i); ret = regmap_read(map, reg, &d->type_buf_def[i]); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 708f36dfaeda..ae5f1f7d4b5a 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1424,6 +1424,8 @@ struct regmap_irq_sub_irq_map { unsigned int *offset; }; +struct regmap_irq_chip_data; + /** * struct regmap_irq_chip - Description of a generic regmap irq_chip. * @@ -1515,6 +1517,13 @@ struct regmap_irq_sub_irq_map { * and configure virt regs. Deprecated, use @set_type_config * callback and config registers instead. * @set_type_config: Callback used for configuring irq types. + * @get_irq_reg: Callback for mapping (base register, index) pairs to register + * addresses. The base register will be one of @status_base, + * @mask_base, etc., @main_status, or any of @config_base. + * The index will be in the range [0, num_main_regs[ for the + * main status base, [0, num_type_settings[ for any config + * register base, and [0, num_regs[ for any other base. + * If unspecified then regmap_irq_get_irq_reg_linear() is used. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. * @@ -1569,11 +1578,13 @@ struct regmap_irq_chip { unsigned long hwirq, int reg); int (*set_type_config)(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx); + unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, + unsigned int base, int index); void *irq_drv_data; }; -struct regmap_irq_chip_data; - +unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data, + unsigned int base, int index); int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx); From patchwork Sun Jul 3 11:21:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12904320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CE12CCA473 for ; Sun, 3 Jul 2022 11:21:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232937AbiGCLVA (ORCPT ); Sun, 3 Jul 2022 07:21:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232817AbiGCLUl (ORCPT ); Sun, 3 Jul 2022 07:20:41 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33A16B7C0; Sun, 3 Jul 2022 04:20:31 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id cl1so9474879wrb.4; Sun, 03 Jul 2022 04:20:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JSeaD64riMMLU3xw2mm2bmS0baE0x58eQS41zf6Qnu0=; b=IvngK6zY4QswSanQABqWYGe7YMdqj/q7i3LBZVz+KfDBXbtRp95tNRCS3u0Da4P9Gy V9UVzi+fB1kGbtNSoxjcChcu84rRrl7SMUHzO79shtjCWr2EVcB2yjF6y6dGmK2pn4Mw PvL/d+PkMK5NVFs2PnhIlKL4Nt70wWAF61nCpoAp8qvRrreG6tazQ/9YsUpNYa5lV7yN hDe8zxELwBmaDWTKbyoqxcSaQmsg3jLXk8GFAI4Y+SmN1k/K69yvfVseXNKWIN3pKAz3 LUIGp6MK7sxY2kq26dO/AlkfJNTvmIe76aApRzUK4apWWQ1uDyw4UhOsTZ4UcGZulqip wqNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JSeaD64riMMLU3xw2mm2bmS0baE0x58eQS41zf6Qnu0=; b=DfSJfTP1/hlZM9tnDJus6T7bIenugf8bDJ8/qUdYvkq/wSDqIG78Nl8uTjC9fkMzIt MCYgZQtwga/LM0WPM0tdiLAHTkWaYeHwCrhzJtW/E/jIjz9JLUNe7i7Z7V0NqNXzK2R/ XZ0XOIrLjsAUsDk7vjxUFdKqC+M2xhyPqYFxESIesBbdlS8KYv5h8R/3RMa4/f23az4Y Lli6bnuqp0JjSj8QKvdxRdCb89rHNaPxUWKkB3XchS0IAm7AqBcoc4TwzvjRGg6aszba LN0GNFQM6KYNURvO5Ownwj/yw+wbWVrk4t+/dmDgmw1f1K0wt9seXWi+h7alGdl5SKay qb6w== X-Gm-Message-State: AJIora/M9C70PZFrKATE9WWtB3QbFXJFc2Pp0QkPuvbG856vwc1u2Jmz cxm3ruZI4Y9sdb0Fz2Lx5kDyPv5L1Oc= X-Google-Smtp-Source: AGRyM1vfFRXdcslPSESxqaiTw6RugkIwo3UCXszSV+8qL3sm+Tc+NicFE9/Dr/i+sTavYkRSAzO1pw== X-Received: by 2002:a5d:65c3:0:b0:21b:bca9:83b1 with SMTP id e3-20020a5d65c3000000b0021bbca983b1mr22067425wrw.568.1656847229989; Sun, 03 Jul 2022 04:20:29 -0700 (PDT) Received: from localhost (92.40.202.9.threembb.co.uk. [92.40.202.9]) by smtp.gmail.com with ESMTPSA id ba15-20020a0560001c0f00b0021bae66362esm24186703wrb.58.2022.07.03.04.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 04:20:29 -0700 (PDT) From: Aidan MacDonald To: broonie@kernel.org Cc: gregkh@linuxfoundation.org, rafael@kernel.org, andy.shevchenko@gmail.com, krzk@kernel.org, m.szyprowski@samsung.com, mazziesaccount@gmail.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 12/12] regmap-irq: Deprecate the not_fixed_stride flag Date: Sun, 3 Jul 2022 12:21:01 +0100 Message-Id: <20220703112101.24493-13-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> References: <20220703112101.24493-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This flag is a bit of a hack and the same thing can be accomplished using a custom ->get_irq_reg() callback. Add a warning to catch any use of the flag. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 2 ++ include/linux/regmap.h | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index ec658755dd1b..4ef9488d05cd 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -739,6 +739,8 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, } if (chip->not_fixed_stride) { + dev_warn(map->dev, "not_fixed_stride is deprecated; use ->get_irq_reg() instead"); + for (i = 0; i < chip->num_regs; i++) if (chip->sub_reg_offsets[i].num_regs != 1) return -EINVAL; diff --git a/include/linux/regmap.h b/include/linux/regmap.h index ae5f1f7d4b5a..84ab1c32271f 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1493,8 +1493,10 @@ struct regmap_irq_chip_data; * registers before unmasking interrupts to clear any bits * set when they were masked. * @not_fixed_stride: Used when chip peripherals are not laid out with fixed - * stride. Must be used with sub_reg_offsets containing the - * offsets to each peripheral. + * stride. Must be used with sub_reg_offsets containing the + * offsets to each peripheral. Deprecated; the same thing + * can be accomplished with a @get_irq_reg callback, without + * the need for a @sub_reg_offsets table. * @status_invert: Inverted status register: cleared bits are active interrupts. * @runtime_pm: Hold a runtime PM lock on the device when accessing it. *