From patchwork Mon Jul 4 17:02:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67CF4C43334 for ; Mon, 4 Jul 2022 17:04:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ApWnJlBvvaoeI3jnEn+mjjOLA+osjyrs9fmAna1nw8w=; b=UD8r1nyWzDReqZ 76AeyR5MUtoUUsOIAqiADojV1NJtoBA40NhKbGm0MIjTRuRzbivKeoYRP93k63El07ZwMxgqOCgKr ZZFsuvhoyGsLIIN2BONH8CJoQiluxpSxD9DkTP0+kw+0mkdFcwU2QpXM6JsYe0HfGfJ1NU71J0DRv sRKDpyF00coVxY2MJyo1KQ7mxFZhh1pw1bS/UVwDWB1wLdovD/5eu04tA9KUT5TDOd2z2grxqg6Du /3exGSo0Q93bHqiSn3cPUD6HLe75paX5sV/oNfrYv8mdmeFHPlDGO+DbAAOOEyRwuseh2AyrJskc0 8bgqW1zXtF4whPoXauXA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PUG-00A9Oh-BG; Mon, 04 Jul 2022 17:03:52 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PTw-00A9GT-P8 for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 17:03:34 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 4E210B81174; Mon, 4 Jul 2022 17:03:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8FFDAC341CE; Mon, 4 Jul 2022 17:03:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954207; bh=e9sCeThn+QRq5ltJQsw2gUyA8wjOgLKds6GBUEmN9EQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o8RDwYAmuPvHwH8j81oA8MVWZKPez8Ia+AYhd/Ug7QjYbWUi858p1pbcD7EGCuuJ5 mvgoyxHAtuMKhGSnDvR+HMIcS/8+mEtbCJXWZVdiQxoilcoanf3v1pZUb/jbOajSz4 aSBRN9VONPMAd88fo8ZKvHalTWGQJvhcyWlN04Vh88ln/fUp6kNmFJMRWqVqfdKfQW aWMBc+3puj3qQisfAzxCBxJXP2H12XxhVZrmpJe4XQlDtLttP2tiswd7QQQXh48MxP 9lel+nMaoCI94AvVJnAuVK5nlw+fJEwPFvMXP8OF0cJbiJszF7xjOOBURzSOApDLvD 8yhGs4VzbDnGA== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 01/28] arm64/cpuinfo: Remove references to reserved cache type Date: Mon, 4 Jul 2022 18:02:35 +0100 Message-Id: <20220704170302.2609529-2-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2707; h=from:subject; bh=e9sCeThn+QRq5ltJQsw2gUyA8wjOgLKds6GBUEmN9EQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx0uWbnKwUY3dhWJ/rWiuDZWU/lSF/Y5tGdVe/qL J7tcLlaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdLgAKCRAk1otyXVSH0L4rB/ 0YOapK0nYrbzciFat5XMp5UHf+i0vOuhXgyXgbFCqr7gs6mgkCJpFjnMClbX3qKIe7behGq3gkbJBd 6q9KnQL9iDzpyfeetacK/ETK9qtq/5weLtwyw2w0AsgDg4pxx19pem0fdl2534bpIY0wD9HeH5UBn7 5GD0MgkhsgOTtbofoAZSMzPJarlkQ5flzpCbvwOgxwkRFKFeJOTLOWGOwPt5+FTjyqaS3yWOzOXait B4cbjbw1qlmlOHKxSnXTJQAiDHZy6vcHYeaes+uYbRJ8aOn0TxGGjme2Q0xT6nqKvO0E/EBvGJy4Xm O8o4sO0HX1gCZ0mg6FYlf9z2IahS1p X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100333_140236_A188477C X-CRM114-Status: GOOD ( 17.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In 155433cb365ee466 ("arm64: cache: Remove support for ASID-tagged VIVT I-caches") we removed all the support fir AIVIVT cache types and renamed all references to the field to say "unknown" since support for AIVIVT caches was removed from the architecture. Some confusion has resulted since the corresponding change to the architecture left the value named as AIVIVT but documented it as reserved in v8, refactor the code so we don't define the constant instead. This will help with automatic generation of this register field since it means we care less about the correspondence with the ARM. No functional change, the value displayed to userspace is unchanged. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cache.h | 1 - arch/arm64/kernel/cpuinfo.c | 23 +++++++++++++++-------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 7c2181c72116..0cbe75b9e4e5 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -25,7 +25,6 @@ #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) #define ICACHE_POLICY_VPIPT 0 -#define ICACHE_POLICY_RESERVED 1 #define ICACHE_POLICY_VIPT 2 #define ICACHE_POLICY_PIPT 3 diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 8eff0a34ffd4..deaaa9438fc2 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -33,12 +33,19 @@ DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); static struct cpuinfo_arm64 boot_cpu_data; -static const char *icache_policy_str[] = { - [ICACHE_POLICY_VPIPT] = "VPIPT", - [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", - [ICACHE_POLICY_VIPT] = "VIPT", - [ICACHE_POLICY_PIPT] = "PIPT", -}; +static inline const char *icache_policy_str(int l1ip) +{ + switch (l1ip) { + case ICACHE_POLICY_VPIPT: + return "VPIPT"; + case ICACHE_POLICY_VIPT: + return "VIPT"; + case ICACHE_POLICY_PIPT: + return "PIPT"; + default: + return "RESERVED/UNKNOWN"; + } +} unsigned long __icache_flags; @@ -347,14 +354,14 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) case ICACHE_POLICY_VPIPT: set_bit(ICACHEF_VPIPT, &__icache_flags); break; - case ICACHE_POLICY_RESERVED: case ICACHE_POLICY_VIPT: + default: /* Assume aliasing */ set_bit(ICACHEF_ALIASING, &__icache_flags); break; } - pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); + pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); } static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) From patchwork Mon Jul 4 17:02:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30560C43334 for ; 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Mon, 04 Jul 2022 17:04:15 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PTx-00A9Gc-QM for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 17:03:35 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 316A2B81178; Mon, 4 Jul 2022 17:03:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 739A9C341CD; Mon, 4 Jul 2022 17:03:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954208; bh=rje9ki4TBmrcmghpSyf///UlZbzjkNXhmzqqvglQ6OE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g/5VmBul2va6g0lZMYGAp8Ce/H9+48Znst0z1q88Zh7gbzVKwjX2Lm/71jd4Q05gC lzg0/WrwBWBCMZXHgJznDhCFR1bm16Kiebtv6XLLvgTAD6qAt5Xv6jinG47dpdLnNb h5GyLQwGPmqWisO/wQ4MXRRM53aXoN7KCYrxnH9d+ZNYasvFl/zMc6YEU/xEyT3Bco 4jLAbckv7TFpD2rN8KxkQAwLiwMxmSaXjSH2qwPH0gOVLr4BnwHRFAbVQZGr5d/xcr K+7GWo0vv3WroZ3NXxPSXp0xdjWMQxR9d3jJWll+pk2sIXGHPcdXoZTRhY/NxL5R/3 j9fxnegGlGA4Q== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 02/28] arm64/idreg: Fix tab/space damage Date: Mon, 4 Jul 2022 18:02:36 +0100 Message-Id: <20220704170302.2609529-3-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1655; h=from:subject; bh=rje9ki4TBmrcmghpSyf///UlZbzjkNXhmzqqvglQ6OE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx0v3zAyCq0X7kc0pniRycwoJ4sCc6Fm03jknjyZ kMY02MmJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdLwAKCRAk1otyXVSH0LCyB/ 9yB/WTHoXUdCfW919opwYUU/i9F7EKrfYou4QfuLEuz+jxr7oSFceCHt7JcDCaSDGpmgV67BGgcl1D sglQbpHnqLpHlyhqUb8E3o2RQZB+ASL8xrtGnsCjAd4JgSPJDw2VcbTvM4RazjiyCFY45ZgP7YaZZn N4lUdO6MU8nWaKuw2tn/TbzX9Y2BuNe50E5/jy7Zu1LEktX24K9tptgIkx5wI9/pKTLid4UGRe18Z2 dqyLYB+EQeJiNKsbiSTudVHOxNttIygCXveqQAdxx+wq7L/wlteoxLR9qGz8qBYnclkIhxz1vu2K67 CpyIUWhAf1ELcMo//4tlUZIBFWqmQM X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100334_028697_A36D3C3D X-CRM114-Status: GOOD ( 11.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Quite a few of the overrides in idreg-override.c have a mix of tabs and spaces in their definitions, fix these. Signed-off-by: Mark Brown --- arch/arm64/kernel/idreg-override.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index 8a2ceb591686..b797f232ebcd 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -53,7 +53,7 @@ static const struct ftr_set_desc pfr1 __initconst = { .name = "id_aa64pfr1", .override = &id_aa64pfr1_override, .fields = { - { "bt", ID_AA64PFR1_BT_SHIFT }, + { "bt", ID_AA64PFR1_BT_SHIFT }, { "mte", ID_AA64PFR1_MTE_SHIFT}, {} }, @@ -63,10 +63,10 @@ static const struct ftr_set_desc isar1 __initconst = { .name = "id_aa64isar1", .override = &id_aa64isar1_override, .fields = { - { "gpi", ID_AA64ISAR1_GPI_SHIFT }, - { "gpa", ID_AA64ISAR1_GPA_SHIFT }, - { "api", ID_AA64ISAR1_API_SHIFT }, - { "apa", ID_AA64ISAR1_APA_SHIFT }, + { "gpi", ID_AA64ISAR1_GPI_SHIFT }, + { "gpa", ID_AA64ISAR1_GPA_SHIFT }, + { "api", ID_AA64ISAR1_API_SHIFT }, + { "apa", ID_AA64ISAR1_APA_SHIFT }, {} }, }; @@ -75,8 +75,8 @@ static const struct ftr_set_desc isar2 __initconst = { .name = "id_aa64isar2", .override = &id_aa64isar2_override, .fields = { - { "gpa3", ID_AA64ISAR2_GPA3_SHIFT }, - { "apa3", ID_AA64ISAR2_APA3_SHIFT }, + { "gpa3", ID_AA64ISAR2_GPA3_SHIFT }, + { "apa3", ID_AA64ISAR2_APA3_SHIFT }, {} }, }; From patchwork Mon Jul 4 17:02:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74EAEC433EF for ; Mon, 4 Jul 2022 17:04:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; 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Mon, 04 Jul 2022 17:03:33 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 53FF3614F8; Mon, 4 Jul 2022 17:03:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52089C341CE; Mon, 4 Jul 2022 17:03:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954210; bh=2ArsSZmKdMsL2Z2QckgwDodtq0Ac8Oi0E83OF81ANUM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sKA+S4HFa1Hp344gQz+jGnl770ZgXUZtPHpegYgKfqdio7g3WDVthe6HCDu8sr4Tm uW+lxGrfzwzKoktibuFqYyF14Yv/fMbfYdJxlvAycEnZtgwbtaLgmHX4FJL7IjFWOC cet/cI4Wm1XuCPnHe0yl93VT9pSWDU41LnMS9VRyf/hHa5PE3CfItI4dU30aasu9Sw VIXJxCESQzrYLkdzSB86TTR1t7X/UJgY/hYnMd+ybRe+JiAf7ZtHzO1F4BZYVTNSEz MPsnP3L+aRVrgmxCnvyR8+CSFZXCp70dOJOSHEQUtJfLYImB0BtRjgeRmicqn7DZx9 fzR433ClYWbMw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 03/28] arm64/sysreg: Allow leading blanks on comments in sysreg file Date: Mon, 4 Jul 2022 18:02:37 +0100 Message-Id: <20220704170302.2609529-4-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/tools/gen-sysreg.awk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk index 5c55509eb43f..db461921d256 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -88,7 +88,7 @@ END { # skip blank lines and comment lines /^$/ { next } -/^#/ { next } +/^[\t ]*#/ { next } /^SysregFields/ { change_block("SysregFields", "None", "SysregFields") From patchwork Mon Jul 4 17:02:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D245AC43334 for ; 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Mon, 04 Jul 2022 17:04:03 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PTx-00A9Hb-JO for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 17:03:34 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 380B961506; Mon, 4 Jul 2022 17:03:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 341F0C341CD; Mon, 4 Jul 2022 17:03:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954212; bh=UdVQ6xUYiefhCG/BeUWlW7OhkNqbxHeaeCnSgCKaT5g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KcKN0sOCM8g+nbWnk0levbH7BexDy70giXMM3txEfwKoTb9CabH/vatWHvktgSR/H dWaow0Yi/aYHkvPzdj+29Nx5GgTjQPuiu0IEaKRASZpVkxHBd0Bf63eoADfzjyq27k Xsg/YMhKufN7YDzcsadmO+z0FHQcAZNygA3jH1m0FES1snJS6TbZWBiPkRRzs5ww7/ hg3SOhsN7FNTFMTP2s46phSMMcIoWaUBzFMaPAUc0jmaoB+8tGrwVNv8L6vmPTQM0n eU51KJr5YbUMfiTkKAWuFCo5ImvIlO9yxKVjdbwhBeLHtcWtAe2LDphpsSpBVW7yq/ CT9HlUXc6wjfw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 04/28] arm64/sysreg: Add SYS_FIELD_GET() helper Date: Mon, 4 Jul 2022 18:02:38 +0100 Message-Id: <20220704170302.2609529-5-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=776; h=from:subject; bh=UdVQ6xUYiefhCG/BeUWlW7OhkNqbxHeaeCnSgCKaT5g=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx0xu5cKguQn7Dx4oiW0PELkooDdowLWewfb41mM PvDkHT+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdMQAKCRAk1otyXVSH0MofB/ 9yicAf9OfKSq0nh89tr3h0WTbJfwBEaVrjs3K64nThYVsoZ/JMGc1xpBTTEV3Un9ncfIaxcaBJyv+0 hGDrduFiYqs7gX8s9pfWubPaxTVpjdASvJ11rhtQWNbH1t7qlDjcYuRxHbnl0JDIJwiozj8GYLwc9H bXHDHH5w2PYzFLb5Q60MpyQDRhwVfU76xqql98Tj+rBzLpKlrxX7EfBbiA6Nb3hBgg/0xbrxE1nWFu VsNnATan13a5APEstrJvkgUbbQWZvNaBLWTxJKWZvnWm+Ji5vuTlGCpYdPaNgaQKsBm/CzrupqmyyG LIt7eru3HzuwThN+/vMtB7x10vcRMl X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100333_709420_CEFAC679 X-CRM114-Status: GOOD ( 11.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a SYS_FIELD_GET() helper to match SYS_FIELD_PREP(), providing a simplified interface to FIELD_GET() when using the generated defines with standardized naming. Signed-off-by: Mark Brown Acked-by: Mark Rutland --- arch/arm64/include/asm/sysreg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 42ff95dba6da..58286c83d592 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1324,6 +1324,9 @@ #endif +#define SYS_FIELD_GET(reg, field, val) \ + FIELD_GET(reg##_##field##_MASK, val) + #define SYS_FIELD_PREP(reg, field, val) \ FIELD_PREP(reg##_##field##_MASK, val) From patchwork Mon Jul 4 17:02:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905692 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5EDEC433EF for ; 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Mon, 04 Jul 2022 17:04:34 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PU1-00A9Ih-55 for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 17:03:38 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C32BAB810C6; Mon, 4 Jul 2022 17:03:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 14B95C341CE; Mon, 4 Jul 2022 17:03:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954214; bh=3YVk7h+Yf0S/OtlwO6RBp5I8QuG+cXwKXZrwe19u9hw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KD5q0vzpYRZuUGAlW8Mu5zlIPPDI1Ik04+kNI41dlG6aRk6W4olxcrRebJAXkeXUW k94Ts3lMYqrHJj9DV4fa51LU6R8UWJ33wBHgb3q/UuwJ9pGEP9DUjD7iuivDADX4hD M39s+isFX+0yqPsBCJ8W7QLBdHKccfFgCm4joWNNZsYywY5OxGiPegUhGGMdL1KOku gYoicFAiNmkh1XgMNcpB6oO4rvDKgFYL8wLzHsfaJtzYIxhuF0c7smm5MWeG2FDnoY AKAywAio1DYLib+0sCMubGACFeks5Ut4PvbMna7QADoxBfVAuvrmF8LhRtvvgcX5wl yK4iCLy8x7PhA== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 05/28] arm64/cache: Restrict which headers are included in __ASSEMBLY__ Date: Mon, 4 Jul 2022 18:02:39 +0100 Message-Id: <20220704170302.2609529-6-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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This will mean that headers it in turn includes that are not safe for use in such a context (eg, due to the use of assembler macros) cause build problems. Avoid these issues by moving the affected includes and associated defines to the section of the file already guarded by ifndef __ASSEMBLY__. Suggested-by: Will Deacon Signed-off-by: Mark Brown --- arch/arm64/include/asm/cache.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 0cbe75b9e4e5..da4886b1922b 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -5,9 +5,6 @@ #ifndef __ASM_CACHE_H #define __ASM_CACHE_H -#include -#include - #define CTR_L1IP_SHIFT 14 #define CTR_L1IP_MASK 3 #define CTR_DMINLINE_SHIFT 16 @@ -22,8 +19,6 @@ #define CTR_CACHE_MINLINE_MASK \ (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT) -#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) - #define ICACHE_POLICY_VPIPT 0 #define ICACHE_POLICY_VIPT 2 #define ICACHE_POLICY_PIPT 3 @@ -31,7 +26,6 @@ #define L1_CACHE_SHIFT (6) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - #define CLIDR_LOUU_SHIFT 27 #define CLIDR_LOC_SHIFT 24 #define CLIDR_LOUIS_SHIFT 21 @@ -54,6 +48,9 @@ #include #include +#include +#include + #ifdef CONFIG_KASAN_SW_TAGS #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT) #elif defined(CONFIG_KASAN_HW_TAGS) @@ -65,6 +62,8 @@ static inline unsigned int arch_slab_minalign(void) #define arch_slab_minalign() arch_slab_minalign() #endif +#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) + #define ICACHEF_ALIASING 0 #define ICACHEF_VPIPT 1 extern unsigned long __icache_flags; From patchwork Mon Jul 4 17:02:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C684EC433EF for ; Mon, 4 Jul 2022 17:05:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 4 Jul 2022 17:03:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E81AAC341CD; Mon, 4 Jul 2022 17:03:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954216; bh=pNNADdZV/+yOGcwHuL1HeG2A2PokiUbq7GquZCOyj/s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p/fpjr8G5XImhSrm4c8N7FINO5Fib9F9OIFFXxWrpHiO1pr9rQwpREjd56w26pidK KIE07tznGC19YnvWvBD/BohVEy3DqQc9g+Ux8h6Ylm5vlb7vVPIOiLkQjn4RFO7dIU Ds/qanOYH7vkLtvNmeAyEgOTMtWmf9+TttE06x1FhAv0s6mlc578pwgulO4JuwaTZo +7/V8i+YDt582KIrv10ZGF79ReWBGi9+vLRsVqYN7O5RBoPBZZMwcCHsaorkTyhvHN FKlyH5+zjrZDcGihSdxtknW7jfEhNIZV7ogIfn1IoQdIqQr/26lDK8022X31AxAZ0w 8DOxnlEGOQ2kA== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 06/28] arm64/sysreg: Standardise naming for CTR_EL0 fields Date: Mon, 4 Jul 2022 18:02:40 +0100 Message-Id: <20220704170302.2609529-7-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Update the names of the constants to reflect standardised naming and move them to sysreg.h. There is also a helper CTR_L1IP() which was open coded and has been converted to use SYS_FIELD_GET(). Signed-off-by: Mark Brown --- arch/arm64/include/asm/cache.h | 31 +++++++++---------------------- arch/arm64/include/asm/sysreg.h | 15 +++++++++++++++ arch/arm64/kernel/alternative.c | 2 +- arch/arm64/kernel/cpu_errata.c | 2 +- arch/arm64/kernel/cpufeature.c | 20 ++++++++++---------- arch/arm64/kernel/cpuinfo.c | 12 ++++++------ arch/arm64/kernel/traps.c | 6 +++--- 7 files changed, 45 insertions(+), 43 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index da4886b1922b..ca9b487112cc 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -5,24 +5,6 @@ #ifndef __ASM_CACHE_H #define __ASM_CACHE_H -#define CTR_L1IP_SHIFT 14 -#define CTR_L1IP_MASK 3 -#define CTR_DMINLINE_SHIFT 16 -#define CTR_IMINLINE_SHIFT 0 -#define CTR_IMINLINE_MASK 0xf -#define CTR_ERG_SHIFT 20 -#define CTR_CWG_SHIFT 24 -#define CTR_CWG_MASK 15 -#define CTR_IDC_SHIFT 28 -#define CTR_DIC_SHIFT 29 - -#define CTR_CACHE_MINLINE_MASK \ - (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT) - -#define ICACHE_POLICY_VPIPT 0 -#define ICACHE_POLICY_VIPT 2 -#define ICACHE_POLICY_PIPT 3 - #define L1_CACHE_SHIFT (6) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) @@ -50,6 +32,7 @@ #include #include +#include #ifdef CONFIG_KASAN_SW_TAGS #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT) @@ -62,7 +45,11 @@ static inline unsigned int arch_slab_minalign(void) #define arch_slab_minalign() arch_slab_minalign() #endif -#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) +#define CTR_CACHE_MINLINE_MASK \ + (0xf << CTR_EL0_DMINLINE_SHIFT | \ + CTR_EL0_IMINLINE_MASK << CTR_EL0_IMINLINE_SHIFT) + +#define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr) #define ICACHEF_ALIASING 0 #define ICACHEF_VPIPT 1 @@ -84,7 +71,7 @@ static __always_inline int icache_is_vpipt(void) static inline u32 cache_type_cwg(void) { - return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; + return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK; } #define __read_mostly __section(".data..read_mostly") @@ -118,12 +105,12 @@ static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void) { u32 ctr = read_cpuid_cachetype(); - if (!(ctr & BIT(CTR_IDC_SHIFT))) { + if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) { u64 clidr = read_sysreg(clidr_el1); if (CLIDR_LOC(clidr) == 0 || (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0)) - ctr |= BIT(CTR_IDC_SHIFT); + ctr |= BIT(CTR_EL0_IDC_SHIFT); } return ctr; diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 58286c83d592..c4293754954e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1084,6 +1084,21 @@ #define MVFR2_FPMISC_SHIFT 4 #define MVFR2_SIMDMISC_SHIFT 0 +#define CTR_EL0_L1Ip_VPIPT 0 +#define CTR_EL0_L1Ip_VIPT 2 +#define CTR_EL0_L1Ip_PIPT 3 + +#define CTR_EL0_L1Ip_SHIFT 14 +#define CTR_EL0_L1Ip_MASK 3 +#define CTR_EL0_DminLine_SHIFT 16 +#define CTR_EL0_IminLine_SHIFT 0 +#define CTR_EL0_IminLine_MASK 0xf +#define CTR_EL0_ERG_SHIFT 20 +#define CTR_EL0_CWG_SHIFT 24 +#define CTR_EL0_CWG_MASK 15 +#define CTR_EL0_IDC_SHIFT 28 +#define CTR_EL0_DIC_SHIFT 29 + #define DCZID_DZP_SHIFT 4 #define DCZID_BS_SHIFT 0 diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c index 7bbf5104b7b7..9bcaa5eacf16 100644 --- a/arch/arm64/kernel/alternative.c +++ b/arch/arm64/kernel/alternative.c @@ -121,7 +121,7 @@ static void clean_dcache_range_nopatch(u64 start, u64 end) ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0); d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0, - CTR_DMINLINE_SHIFT); + CTR_EL0_DminLine_SHIFT); cur = start & ~(d_size - 1); do { /* diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index c05cc3b6162e..a0dd3ea8f585 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -187,7 +187,7 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, int scope) { u32 midr = read_cpuid_id(); - bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); + bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT); const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 8d88433de81d..b7cd50eb6d8a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -396,18 +396,18 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { static const struct arm64_ftr_bits ftr_ctr[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), /* * Linux can handle differing I-cache policies. Userspace JITs will * make use of *minLine. * If we have differing I-cache policies, report it as the weakest - VIPT. */ - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -1480,7 +1480,7 @@ static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, else ctr = read_cpuid_effective_cachetype(); - return ctr & BIT(CTR_IDC_SHIFT); + return ctr & BIT(CTR_EL0_IDC_SHIFT); } static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) @@ -1491,7 +1491,7 @@ static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unu * to the CTR_EL0 on this CPU and emulate it with the real/safe * value. */ - if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) + if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); } @@ -1505,7 +1505,7 @@ static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, else ctr = read_cpuid_cachetype(); - return ctr & BIT(CTR_DIC_SHIFT); + return ctr & BIT(CTR_EL0_DIC_SHIFT); } static bool __maybe_unused diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index deaaa9438fc2..e1e727899821 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -36,11 +36,11 @@ static struct cpuinfo_arm64 boot_cpu_data; static inline const char *icache_policy_str(int l1ip) { switch (l1ip) { - case ICACHE_POLICY_VPIPT: + case CTR_EL0_L1Ip_VPIPT: return "VPIPT"; - case ICACHE_POLICY_VIPT: + case CTR_EL0_L1Ip_VIPT: return "VIPT"; - case ICACHE_POLICY_PIPT: + case CTR_EL0_L1Ip_PIPT: return "PIPT"; default: return "RESERVED/UNKNOWN"; @@ -349,12 +349,12 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) u32 l1ip = CTR_L1IP(info->reg_ctr); switch (l1ip) { - case ICACHE_POLICY_PIPT: + case CTR_EL0_L1Ip_PIPT: break; - case ICACHE_POLICY_VPIPT: + case CTR_EL0_L1Ip_VPIPT: set_bit(ICACHEF_VPIPT, &__icache_flags); break; - case ICACHE_POLICY_VIPT: + case CTR_EL0_L1Ip_VIPT: default: /* Assume aliasing */ set_bit(ICACHEF_ALIASING, &__icache_flags); diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 9ac7a81b79be..b7fed33981f7 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -579,11 +579,11 @@ static void ctr_read_handler(unsigned long esr, struct pt_regs *regs) if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { /* Hide DIC so that we can trap the unnecessary maintenance...*/ - val &= ~BIT(CTR_DIC_SHIFT); + val &= ~BIT(CTR_EL0_DIC_SHIFT); /* ... and fake IminLine to reduce the number of traps. */ - val &= ~CTR_IMINLINE_MASK; - val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK; + val &= ~CTR_EL0_IminLine_MASK; + val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK; } pt_regs_write_reg(regs, rt, val); From patchwork Mon Jul 4 17:02:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 144F0C433EF for ; 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Mon, 04 Jul 2022 17:05:06 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PU3-00A9Jf-Cs for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 17:03:40 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 036EF614FC; Mon, 4 Jul 2022 17:03:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F3838C341CB; Mon, 4 Jul 2022 17:03:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954218; bh=oImKs/Z3C2gs7J9Hq+U7SDWiSQY+itKQK1uvHqkP4LU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hl/ykCxeGFN+cxsi1pp6sz5pvTHbzZtZSY+Kl82ptfYeFq/Wxwp1Ia25QmJM+0wh5 EAXA4D9xqoVFvOfc0tOrotQ9U0aZW6dxQHUeGspgYCpZQA4Aqfd4LUqg6HicLzKppk ZkEpF1/lnxUffSek6otyeHilLyid6wAZgIZwyXW9pRtwCkDEROBmvXeo/W/HM4V16u RuGZm24yPBA3hzE91YHG0GvSHgHznHO8PfTCmxfqItkl8VnKXubfelCs24eYRe3iNq anXwo/FuYxSbzIsTiBF7WUhvVTvBtOMyU0LPe88PDoMpAFe3aYSwKE5VxoWgFAro9/ 4jG9ckOsPiMGA== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 07/28] arm64/sysreg: Standardise naming for DCZID_EL0 field names Date: Mon, 4 Jul 2022 18:02:41 +0100 Message-Id: <20220704170302.2609529-8-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1676; h=from:subject; bh=oImKs/Z3C2gs7J9Hq+U7SDWiSQY+itKQK1uvHqkP4LU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx0z/qffsiRRlhNRHpYfI7YAVkNjrylKWG1RrvoD aOR5zWeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdMwAKCRAk1otyXVSH0IS3B/ sEO/OCgkc/qJ2ykuJh93mZRg/ryjlUR8K9+m7rGZ22tO1OnRoQviuFmbtO5sDoQWW4617KaWu9wghC 5Ceqq094doDhzZRxTBD0fIt5O5UcGJwL3St3XzC73PtD3AjhzzzD/htyRcyzI9zzHTcR8TKEmhn4PY UyyuZ6gjToXGryu1YxQ9ZLVSdjQlLDdYlIv2q+pmXWhhWK9IWrfBFgk5xBtAaEFtPZ6j0NSM+VM9S2 sIs2bGaA0qWX8V7hfFfLdGgVAiqIXUQGLs+g88g9KrEyH2gPFSjfmcbBRMbWLcF9emKzuYKmGlJdGH bxOGH8g4xkvvfRVIZOhOCguKREt9Db X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100339_512336_D95C8598 X-CRM114-Status: GOOD ( 13.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The constants defining field names for DCZID_EL0 do not include the _EL0 that is included as part of our standard naming scheme. In preparation for automatic generation of the defines add the _EL0 in. No functional change. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 4 ++-- arch/arm64/kernel/cpufeature.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index c4293754954e..e62baf910249 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1099,8 +1099,8 @@ #define CTR_EL0_IDC_SHIFT 28 #define CTR_EL0_DIC_SHIFT 29 -#define DCZID_DZP_SHIFT 4 -#define DCZID_BS_SHIFT 0 +#define DCZID_EL0_DZP_SHIFT 4 +#define DCZID_EL0_BS_SHIFT 0 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b7cd50eb6d8a..b9c5b11c17c3 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -453,8 +453,8 @@ static const struct arm64_ftr_bits ftr_mvfr2[] = { }; static const struct arm64_ftr_bits ftr_dczid[] = { - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), ARM64_FTR_END, }; From patchwork Mon Jul 4 17:02:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1ABB4C433EF for ; Mon, 4 Jul 2022 17:06:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 4 Jul 2022 17:03:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D359BC341CD; Mon, 4 Jul 2022 17:03:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954220; bh=PaS2j8K/6zs60P4aeWQZf/pQXIdCQ9F2dRBgtTgd69c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Yy/A6kApaxvqtgmjf2dey2veMAULB/08CFW4WgYMqHuS+Ys5bw9mkWLg9MxKh94L7 PRR3MYhFeI4nXOONj1rLxN2AbgYN9XupCOQz7N+YN1oO2LPoE9kK9MENTzc1VhG8I6 U0khEQTlRN9AnfchTaR6yGItXu4Am+Wy+D0b8K8TJ04ztK3gflUDOfTkWJyhc+zehs Ftp+KEAz6JahEZKjNyDX4/GivyWJ35znx0nZ4WSpU6rpXiEyirOYxh0OV/bl3hQJKb SXlO6uKGDgalzLhx/ioox9rDV4zLrAvSZugz4qk9lIVlAj6/AN/s4/skHZgyIR17AQ OwKjKaC4jbE9Q== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 08/28] arm64/mte: Standardise GMID field name definitions Date: Mon, 4 Jul 2022 18:02:42 +0100 Message-Id: <20220704170302.2609529-9-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1901; h=from:subject; bh=PaS2j8K/6zs60P4aeWQZf/pQXIdCQ9F2dRBgtTgd69c=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx00tltjou//yrq4htYc97AwpigCec//FegbyICA P3HvXZuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdNAAKCRAk1otyXVSH0Dn5B/ 4ufyBP3YWlqRVocEHG4iq3fYMHdEnY9U3mOreMudJMRu5tCxv0aHDtKp37ZOfvosG3B7Rn6Pj4CyEW GFZBcYxuXs/klOcYj0BwT685zGwkb/a569ajn+gPN9xR+ZKdINmFH/uShnImarPgch0qBLfcFnbAZj 5hesIFyKDHyvHm5CPO/VXHgW8eUSQoQ48tc/064bPwELT4Q0Jl/sD4B7T1Mz6hyX5wq24LfoCNDKwH wp0z7Jet6jiuKpWPtHi1hmhqibGHtXELWIj8Hft17FPP3DJx8B6py2iwczTqF6WROOQKnmpastNF6I fubFo1POZkmed8Tye9grAzTKfPtGlz X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100343_227332_3D14ED13 X-CRM114-Status: GOOD ( 14.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Usually our defines for bitfields in system registers do not include a SYS_ prefix but those for GMID do. In preparation for automatic generation of defines remove that prefix. No functional change. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 4 ++-- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/lib/mte.S | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e62baf910249..cc6a847f8bdd 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1136,8 +1136,8 @@ #define SYS_RGSR_EL1_SEED_MASK 0xffffUL /* GMID_EL1 field definitions */ -#define SYS_GMID_EL1_BS_SHIFT 0 -#define SYS_GMID_EL1_BS_SIZE 4 +#define GMID_EL1_BS_SHIFT 0 +#define GMID_EL1_BS_SIZE 4 /* TFSR{,E0}_EL1 bit definitions */ #define SYS_TFSR_EL1_TF0_SHIFT 0 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b9c5b11c17c3..7d838b5f7e20 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -459,7 +459,7 @@ static const struct arm64_ftr_bits ftr_dczid[] = { }; static const struct arm64_ftr_bits ftr_gmid[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), ARM64_FTR_END, }; diff --git a/arch/arm64/lib/mte.S b/arch/arm64/lib/mte.S index eeb9e45bcce8..1b7c93ae7e63 100644 --- a/arch/arm64/lib/mte.S +++ b/arch/arm64/lib/mte.S @@ -18,7 +18,7 @@ */ .macro multitag_transfer_size, reg, tmp mrs_s \reg, SYS_GMID_EL1 - ubfx \reg, \reg, #SYS_GMID_EL1_BS_SHIFT, #SYS_GMID_EL1_BS_SIZE + ubfx \reg, \reg, #GMID_EL1_BS_SHIFT, #GMID_EL1_BS_SIZE mov \tmp, #4 lsl \reg, \tmp, \reg .endm From patchwork Mon Jul 4 17:02:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CEC0C433EF for ; Mon, 4 Jul 2022 17:06:52 +0000 (UTC) DKIM-Signature: v=1; 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Mon, 04 Jul 2022 17:03:44 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B88F1614B9; Mon, 4 Jul 2022 17:03:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B50F9C341CE; Mon, 4 Jul 2022 17:03:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954222; bh=DXmmpZ/Dfgv6heEOSFLoyjX7mHx3QrAjRtHrfale+J0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VrPUp6TSSQEA/TMwC7cNiLjXOevQdAgccDelcDFLGq9Cv3aAdo2kElrv4evN57ljI KyaWSHMYG2hBHw11aX9xRirehnABGDTS4KnGQt/ef3Nw8MzTpzwy6A/vRQzRXdnbkX mojkTNkP9OBhprn4PC/dXfQKRzriWtUiAfP8N9v/4zmpdfAmcRapPUpp1ofzV1f5po i+AKYzZkMnpyXoNNFTSLW26HRegi1KiwX3UK92OPL1xvrdsTSl/p0uvRrthM5T71gv qBkKDHEGw9s3/yn0Wf45J/0IoSImoxItC96gJCsQPd9qklxeFMdijxiJWHsmEXDEJv a1QkSX8zlbQEA== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 09/28] arm64/sysreg: Align pointer auth enumeration defines with architecture Date: Mon, 4 Jul 2022 18:02:43 +0100 Message-Id: <20220704170302.2609529-10-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6271; h=from:subject; bh=DXmmpZ/Dfgv6heEOSFLoyjX7mHx3QrAjRtHrfale+J0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx01ypD6fSlGHISQGT/CdkQg+f3gbJYefdGjQWes 3AdMyb2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdNQAKCRAk1otyXVSH0P9GB/ 48tAjBfNQPxOBaXdLcyESAw0PAblsvrlNOmfI/lEmEecHhkOHOR/7lt6quPpnjY7j/PxRp4mbidrl3 K/poE+Puq/sYJ13ZWRKmy7BPATTzDtoCCXHD+QJert9e3qQu4nPYxkWh8kkyglGNM2cvQilqsI3wVC mlmfpyI5RYVu7T18fsAuTu8aAPlPcY9sTpmcFywzy5CWrdnbG+erpHaKcJSLXDIWv+/ZszpjbE+wRm Q3F1SQ7J4m1pFG2HdkbzsFRY3c1w6VIQZY2IBAi5MSC3bIMIkJRF21KZNv8Lts5Fq8BlpVMm5Y7lRL fjmkbrwbL5bxO5Nbcws7+uQgvKFDBg X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100343_353941_BFEE8BE7 X-CRM114-Status: GOOD ( 14.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The defines used for the pointer authentication feature enumerations do not follow the naming convention we've decided to use where we name things after the architecture feature that introduced. Prepare for generating the defines for the ISA ID registers by updating to use the feature names. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 34 ++++++++++++++++----------------- arch/arm64/kernel/cpufeature.c | 24 +++++++++++------------ 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index cc6a847f8bdd..9f2656d2fce3 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -721,21 +721,21 @@ #define ID_AA64ISAR1_DPB_SHIFT 0 #define ID_AA64ISAR1_APA_NI 0x0 -#define ID_AA64ISAR1_APA_ARCHITECTED 0x1 +#define ID_AA64ISAR1_APA_PAuth 0x1 #define ID_AA64ISAR1_APA_ARCH_EPAC 0x2 -#define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3 -#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4 -#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5 +#define ID_AA64ISAR1_APA_Pauth2 0x3 +#define ID_AA64ISAR1_APA_FPAC 0x4 +#define ID_AA64ISAR1_APA_FPACCOMBINE 0x5 #define ID_AA64ISAR1_API_NI 0x0 -#define ID_AA64ISAR1_API_IMP_DEF 0x1 -#define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2 -#define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3 -#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4 -#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5 +#define ID_AA64ISAR1_API_PAuth 0x1 +#define ID_AA64ISAR1_API_EPAC 0x2 +#define ID_AA64ISAR1_API_PAuth2 0x3 +#define ID_AA64ISAR1_API_FPAC 0x4 +#define ID_AA64ISAR1_API_FPACCOMBINE 0x5 #define ID_AA64ISAR1_GPA_NI 0x0 -#define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 +#define ID_AA64ISAR1_GPA_IMP 0x1 #define ID_AA64ISAR1_GPI_NI 0x0 -#define ID_AA64ISAR1_GPI_IMP_DEF 0x1 +#define ID_AA64ISAR1_GPI_IMP 0x1 /* id_aa64isar2 */ #define ID_AA64ISAR2_CLEARBHB_SHIFT 28 @@ -755,14 +755,14 @@ #define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 #define ID_AA64ISAR2_APA3_NI 0x0 -#define ID_AA64ISAR2_APA3_ARCHITECTED 0x1 -#define ID_AA64ISAR2_APA3_ARCH_EPAC 0x2 -#define ID_AA64ISAR2_APA3_ARCH_EPAC2 0x3 -#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC 0x4 -#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB 0x5 +#define ID_AA64ISAR2_APA3_PAuth 0x1 +#define ID_AA64ISAR2_APA3_EPAC 0x2 +#define ID_AA64ISAR2_APA3_PAuth2 0x3 +#define ID_AA64ISAR2_APA3_FPAC 0x4 +#define ID_AA64ISAR2_APA3_FPACCOMBINE 0x5 #define ID_AA64ISAR2_GPA3_NI 0x0 -#define ID_AA64ISAR2_GPA3_ARCHITECTED 0x1 +#define ID_AA64ISAR2_GPA3_IMP 0x1 /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 7d838b5f7e20..838b3dcd8473 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2317,7 +2317,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_APA_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, + .min_field_value = ID_AA64ISAR1_APA_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2328,7 +2328,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR2_APA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED, + .min_field_value = ID_AA64ISAR2_APA3_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2339,7 +2339,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_API_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_API_IMP_DEF, + .min_field_value = ID_AA64ISAR1_API_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2355,7 +2355,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_GPA_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, + .min_field_value = ID_AA64ISAR1_GPA_IMP, .matches = has_cpuid_feature, }, { @@ -2366,7 +2366,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR2_GPA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED, + .min_field_value = ID_AA64ISAR2_GPA3_IMP, .matches = has_cpuid_feature, }, { @@ -2377,7 +2377,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_GPI_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, + .min_field_value = ID_AA64ISAR1_GPI_IMP, .matches = has_cpuid_feature, }, { @@ -2562,15 +2562,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 4, FTR_UNSIGNED, - ID_AA64ISAR1_APA_ARCHITECTED) + ID_AA64ISAR1_APA_PAuth) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED) + 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) + 4, FTR_UNSIGNED, ID_AA64ISAR1_API_PAuth) }, {}, }; @@ -2578,15 +2578,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) + 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_IMP) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED) + 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) + 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP) }, {}, }; From patchwork Mon Jul 4 17:02:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA3A3C433EF for ; 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Mon, 04 Jul 2022 17:06:07 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PU8-00A9Le-Vv for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 17:03:46 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 94096614FC; Mon, 4 Jul 2022 17:03:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 941BFC341CD; Mon, 4 Jul 2022 17:03:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954224; bh=M9K1IP/4je0NJDdGU+JfzHhZp0G/9AEcSVbv+FX+CYk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W609SzfC81hoqlIBQiluh4m63mqM0HHM/2jRSgxlByC7nEvsKU6jHnnh/r1eDvR7p x38oDbU6a8Mi8i2etyfK/pRdDB0r9vxlQcETj9zILsy1inaBOCIbSLiePn7z8moHRc cWMoi/urcgExvNC2/dulYxfpijFm/EYAfN+fJ87C26zfte4dvNPEMUnj/kxPDzO2ZY mYOl6tfr1J+TsFHgrp35UFGqpcwryNBrasJ1bZPMe0bvXjUD2k1WEhLLTsDvwuSUCe 8E+y+UKALiK1+egCq1GBy55OqzbpXF0KNYKn0CMIBPKPF36nLKwdTBVa+HxXAv7RC6 5hUD1iY/zUZHw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 10/28] arm64/sysreg: Make BHB clear feature defines match the architecture Date: Mon, 4 Jul 2022 18:02:44 +0100 Message-Id: <20220704170302.2609529-11-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2240; h=from:subject; bh=M9K1IP/4je0NJDdGU+JfzHhZp0G/9AEcSVbv+FX+CYk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx020p2ch/rszXUh2C+W61GjGITDYyeLuRALUsi3 uLOnhdGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdNgAKCRAk1otyXVSH0J/2B/ 4x3oJYp5clljOukv2QdaXkExa1bexDBuYuSLbW+FEA3RsT3PhOfWSytzAmRNjnZt5mHa+6zyN4EUBJ sSKu5+ezwMao5E8YZO95oYdH7t9mTerF0MqEdAxRgKTBdJjlJ+CNtepcLdYv60tIqpXhO8hm6ntu6O dkDj3LtA8HqHxHf3iPAAmVQLsRyO7cBgtrBl3y/bkYvVd9rjBTngQxtD/Nzx4GH7/N/lWUUL76+bRS n/+eJ2fOBCxPTSkhatax4ZsPHT8Gy/PBHcOiAbfXXFqaIGhAIdlm+I+MlItgHcSkB2TqfpEmoyGBgM ollCtDtaP6Kb+i48djg8zsneLpBAel X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100345_157513_5619E68B X-CRM114-Status: GOOD ( 15.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The architecture refers to the field identifying support for BHB clear as BC but the kernel has called it CLEARBHB. In preparation for generation of defines for ID_AA64ISAR2_EL1 rename to use the architecture's naming. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/include/asm/sysreg.h | 2 +- arch/arm64/kernel/cpufeature.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 14a8f3d93add..6472f2badc97 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope) isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); return cpuid_feature_extract_unsigned_field(isar2, - ID_AA64ISAR2_CLEARBHB_SHIFT); + ID_AA64ISAR2_BC_SHIFT); } const struct cpumask *system_32bit_el0_cpumask(void); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9f2656d2fce3..34bf421c52df 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -738,7 +738,7 @@ #define ID_AA64ISAR1_GPI_IMP 0x1 /* id_aa64isar2 */ -#define ID_AA64ISAR2_CLEARBHB_SHIFT 28 +#define ID_AA64ISAR2_BC_SHIFT 28 #define ID_AA64ISAR2_APA3_SHIFT 12 #define ID_AA64ISAR2_GPA3_SHIFT 8 #define ID_AA64ISAR2_RPRES_SHIFT 4 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 838b3dcd8473..0f9c9d8b21a2 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -231,7 +231,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_BC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), From patchwork Mon Jul 4 17:02:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F984C43334 for ; Mon, 4 Jul 2022 17:07:44 +0000 (UTC) DKIM-Signature: v=1; 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Mon, 04 Jul 2022 17:03:48 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7712361506; Mon, 4 Jul 2022 17:03:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73AC5C341CE; Mon, 4 Jul 2022 17:03:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954225; bh=chZhNiHRU1RnALCbKLWMEFE0auV05XV3+KeVNWP1l5E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PYtCo2oOl9ttJma4RAZ6RaYdrvRM1Er2MMcBwyZkE/jNgRKHcPzD/i8npRyFS0zOZ 703n8QflDvW5kkVZrlprULu0PwxTHU1OQKktu8C3uu8ytoQQpfMgDq0i9XMItwF0XN 1YtfxmGIEYJ8u2Rdo2btz9JZaSlVBCK6WE7ke7FobZzrs7xVPY3bj/Wig11C5WLopq 6ay22O7ugwGU4mgmqwf/NbXubV38sRZBtYE/YRN/2LBOgUkkpsayZFKbadm6J2Zvms cNf/cfgYJsW/6YXm2e64SmS7rYzVnfVCSLEcZ+WfoZ/3qWAPOs7GbirOH4HJJXu1bU kx1out96SUORA== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 11/28] arm64/sysreg: Standardise naming for WFxT defines Date: Mon, 4 Jul 2022 18:02:45 +0100 Message-Id: <20220704170302.2609529-12-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3995; h=from:subject; bh=chZhNiHRU1RnALCbKLWMEFE0auV05XV3+KeVNWP1l5E=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx03vlvS35hsybrqKl/DQ2t7zcoD0W+8PGA2FwYO yrDYE/uJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdNwAKCRAk1otyXVSH0NECB/ 9hATTVHfJbAUE0gDGO7y2oTtHwBcnzerv8ngY6CwzQbZir5RcJuT/LJShLIRPzdHoBSMuPh7SbVzu1 Zd9x0shh9Gbp22Bk1RmAkzx4EoAPhbiCsqXuxshJome8H+EwbFdGbxicPxK1rF25UY9vbcTiuGogqC 3TYfrDcXUuV9Wwvl4XKJzt/+144Ix1tZaihElCUk7VEJfXDTK53DPbRdCjr38FswTGSlQFev1qyiBb 5Wv/qIoUkNdzmF/gSIsKZResEcIMnLvf94e/ypvjUliPW5iM4ZCuXpVO9+Ez6dcy9OQwz1BBQl3ivh PFA8ZyztgteHgYws3vymsF3bUxPxuJ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100347_065393_3CAFACE4 X-CRM114-Status: GOOD ( 16.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The defines for WFxT refer to the feature as WFXT and use SUPPORTED rather than IMP. In preparation for automatic generation of defines update these to be more standard. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 6 +++--- arch/arm64/kernel/cpufeature.c | 8 ++++---- arch/arm64/kvm/sys_regs.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 34bf421c52df..1b1ea5bd01c0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -742,7 +742,7 @@ #define ID_AA64ISAR2_APA3_SHIFT 12 #define ID_AA64ISAR2_GPA3_SHIFT 8 #define ID_AA64ISAR2_RPRES_SHIFT 4 -#define ID_AA64ISAR2_WFXT_SHIFT 0 +#define ID_AA64ISAR2_WFxT_SHIFT 0 #define ID_AA64ISAR2_RPRES_8BIT 0x0 #define ID_AA64ISAR2_RPRES_12BIT 0x1 @@ -751,8 +751,8 @@ * reserved, but has not yet been removed from the ARM ARM * as of ARM DDI 0487G.b. */ -#define ID_AA64ISAR2_WFXT_NI 0x0 -#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 +#define ID_AA64ISAR2_WFxT_NI 0x0 +#define ID_AA64ISAR2_WFxT_IMP 0x2 #define ID_AA64ISAR2_APA3_NI 0x0 #define ID_AA64ISAR2_APA3_PAuth 0x1 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0f9c9d8b21a2..83f8e9d360ce 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -237,7 +237,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFXT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFxT_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2516,10 +2516,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_WFXT_SHIFT, + .field_pos = ID_AA64ISAR2_WFxT_SHIFT, .field_width = 4, .matches = has_cpuid_feature, - .min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED, + .min_field_value = ID_AA64ISAR2_WFxT_IMP, }, {}, }; @@ -2654,7 +2654,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), - HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFXT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFXT_SUPPORTED, CAP_HWCAP, KERNEL_HWCAP_WFXT), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), #ifdef CONFIG_ARM64_SME HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c06c0477fab5..f12c6d457677 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1146,7 +1146,7 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); if (!cpus_have_final_cap(ARM64_HAS_WFXT)) - val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFXT); + val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFxT); break; case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ From patchwork Mon Jul 4 17:02:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28F79C433EF for ; Mon, 4 Jul 2022 17:08:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 4 Jul 2022 17:03:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 535A5C341CB; Mon, 4 Jul 2022 17:03:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954227; bh=aXl1zEeonhKmSdCZLo2V94zi48bhS3FF8tFmF+zDM3E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DKBIdHegUjfJFJFIoC9xP2R74DPd+avXT7qPAgxpGjMDaNpL2ua/YNTFlc68OMVok rleqHGlOD1LeMQ7qdDdR3qCW+Y11pv+YYLmjCZEhEBNA7YsdAOkz9tAV2DhopTwazz m2Uh7ZFGM5GZu/EXvWQjbmPVlYzLOO6OavVm8dBK40DaBOdeJdCyM3RP5ontXKHMVS BsxjRUPVHr0THs1wwpHW8kgXbkJu7oxarTOLdgfgv2r6eEUnHBr8z2tLdgWPfZ+IaG PHYbdRda/T/Nz8k0BA5ndN82nSbX2qT4kfNEK96EVvB2rWiP/X4lXZFLkvPOKhKhV0 p9vM+6dBZiW6A== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 12/28] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Date: Mon, 4 Jul 2022 18:02:46 +0100 Message-Id: <20220704170302.2609529-13-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7266; h=from:subject; bh=aXl1zEeonhKmSdCZLo2V94zi48bhS3FF8tFmF+zDM3E=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx03czEwi2I1JvbsLtf/uFYthui3x+bNUuDwXXQD lVlsM8uJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdNwAKCRAk1otyXVSH0KOMB/ 9qX/M4Rw/38OZWDgyXOhxcoNHLGDAqlwBi/IWj7Oa7TLlHc8b3RDBh3WCKl2wT3ZRWbQmTARLGt4yk qTuMvUmKom/xc+/BxL18y/aHBeY0XPdPWpU/pHc2xnVys62XWYV6H4GppQCDEAesiFbhwbf0l5Sv0M Po8pte34bEuPSOkUtrOQNLrC3MFYG2MamrEFZpKJDxhEeIlXzL6D78cIuBxlwQuJmHKUJRkaysBT09 dFnahjZcUOo4j06I5kKbKfrkHL6KHfmeP0c5MPulX/8lJzfEFsJEyAwtj4LJKlX8VhRO+e4K1HIwdK gmvtRRrKjaHKGgvtnj6qYLgof2iziL X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100348_931049_521D2DB0 X-CRM114-Status: GOOD ( 14.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org We have a series of defines for enumeration values we test for in the fields in ID_AA64SMFR0_EL1 which do not follow our usual convention of including the EL1 in the name and having _IMP at the end of the basic "feature present" define. In preparation for automatic register generation bring the defines into sync with convention, no functional change. Signed-off-by: Mark Brown --- arch/arm64/include/asm/el2_setup.h | 2 +- arch/arm64/include/asm/sysreg.h | 30 ++++++++++++++-------------- arch/arm64/kernel/cpufeature.c | 32 +++++++++++++++--------------- 3 files changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 34ceff08cac4..bfd0ad64b598 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -161,7 +161,7 @@ mov x1, #0 // SMCR controls mrs_s x2, SYS_ID_AA64SMFR0_EL1 - ubfx x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM? + ubfx x2, x2, #ID_AA64SMFR0_EL1_FA64_SHIFT, #1 // Full FP in SM? cbz x2, .Lskip_sme_fa64_\@ orr x1, x1, SMCR_ELx_FA64_MASK diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1b1ea5bd01c0..3c77cf850f36 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -834,21 +834,21 @@ #define ID_AA64ZFR0_SVEVER_SVE2 0x1 /* id_aa64smfr0 */ -#define ID_AA64SMFR0_FA64_SHIFT 63 -#define ID_AA64SMFR0_I16I64_SHIFT 52 -#define ID_AA64SMFR0_F64F64_SHIFT 48 -#define ID_AA64SMFR0_I8I32_SHIFT 36 -#define ID_AA64SMFR0_F16F32_SHIFT 35 -#define ID_AA64SMFR0_B16F32_SHIFT 34 -#define ID_AA64SMFR0_F32F32_SHIFT 32 - -#define ID_AA64SMFR0_FA64 0x1 -#define ID_AA64SMFR0_I16I64 0xf -#define ID_AA64SMFR0_F64F64 0x1 -#define ID_AA64SMFR0_I8I32 0xf -#define ID_AA64SMFR0_F16F32 0x1 -#define ID_AA64SMFR0_B16F32 0x1 -#define ID_AA64SMFR0_F32F32 0x1 +#define ID_AA64SMFR0_EL1_FA64_SHIFT 63 +#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52 +#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48 +#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36 +#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35 +#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34 +#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32 + +#define ID_AA64SMFR0_EL1_FA64_IMP 0x1 +#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf +#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1 +#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf +#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1 +#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1 +#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1 /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 83f8e9d360ce..a6c224539ce4 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -298,19 +298,19 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_FA64_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I16I64_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F64F64_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I8I32_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F16F32_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_B16F32_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), - FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F32F32_SHIFT, 1, 0), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), ARM64_FTR_END, }; @@ -2503,9 +2503,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .capability = ARM64_SME_FA64, .sys_reg = SYS_ID_AA64SMFR0_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64SMFR0_FA64_SHIFT, + .field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT, .field_width = 1, - .min_field_value = ID_AA64SMFR0_FA64, + .min_field_value = ID_AA64SMFR0_EL1_FA64_IMP, .matches = has_cpuid_feature, .cpu_enable = fa64_kernel_enable, }, @@ -2657,13 +2657,13 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), #ifdef CONFIG_ARM64_SME HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I16I64, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F64F64, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I8I32, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F16F32, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_B16F32, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), - HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F32F32, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), + HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), #endif /* CONFIG_ARM64_SME */ {}, }; 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Mon, 4 Jul 2022 17:03:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32286C341CD; Mon, 4 Jul 2022 17:03:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954229; bh=hwY83Qu81a2yJ0TfSfi1PmMGmc0Q4UZUyQ+/FOThgPY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A/Zi1boOtM3kftmRPvpD6ggGrWQGFtnMCadswKkTAczRlYP3Qh542xE+MyZ0f6o7D F8sMR+pown71Hfg0OYxWb8PHIph+4kwMEW7JCztNd9lUit6bt5lrCHSGEfrW8qxAVT ha/IzFEDiqKJ/JEf+IdGe20pW7kZIvc4gzm24DdibQfp5U5/pfBjEdvDSWhSqr6PP1 u5J4qsGG+QdlT8xMFtOkH75zrXXGzksxOonvLzG5vnIfYtglEI2M0nyAgS6rYJEDN8 ZMiC6zaFibgser1BY8vv5rNBfoSR0PNNM9eRBhfxft1rIa332+XVdd27sRVxzzHZ3M P8rDq/J8FlUjw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 13/28] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Date: Mon, 4 Jul 2022 18:02:47 +0100 Message-Id: <20220704170302.2609529-14-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7866; h=from:subject; bh=hwY83Qu81a2yJ0TfSfi1PmMGmc0Q4UZUyQ+/FOThgPY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx04k5hx4nT/5niiQWwhZESoFe6RThIy/o4zCtFs AKpQR32JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdOAAKCRAk1otyXVSH0IFcB/ 9ded6Ig2tYx5MRpiCfPYL/Mspe9Odo92Ig8FlQwnEf/2h3rd+c2XD8vjCd+WIgGqXcQ1j6YpZGGp5S 67uTCrhnAeGtAaFHwE8uSkGlzlWiAVPynWtgA4j2ZLlr6Lt+ngZBMA8PUQs6B0S1IXPDK/0YmsRWBT UaZvLvHofrXCEyvG9Z7+9xT/k+3ufew4FVv5BCycB5yR6YAkzE4hhQpswdGNiC8MGxDW5YFFW/ZxzV 0yx8DGqi9CgoMhnf+6OWaL5aCdX2u/ilfPbVBkAIwZ5i0UojWdZsYVW+vwSHRGWXG93ztS5bNf7l+a EKJx2cZ5wrTY8PlykJWGVZFgPiUDwK X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100350_835474_E87BD03E X-CRM114-Status: GOOD ( 13.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The various defines for bitfields in ID_AA64ZFR0_EL1 do not follow our conventions for register field names, they omit the _EL1, they don't use specific defines for enumeration values and they don't follow the naming in the architecture in some cases. In preparation for automatic generation bring them into line with convention. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 40 ++++++++++++++++----------------- arch/arm64/kernel/cpufeature.c | 38 +++++++++++++++---------------- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 3c77cf850f36..cbc5f311c0cf 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -812,26 +812,26 @@ #define ID_AA64PFR1_MTE_ASYMM 0x3 /* id_aa64zfr0 */ -#define ID_AA64ZFR0_F64MM_SHIFT 56 -#define ID_AA64ZFR0_F32MM_SHIFT 52 -#define ID_AA64ZFR0_I8MM_SHIFT 44 -#define ID_AA64ZFR0_SM4_SHIFT 40 -#define ID_AA64ZFR0_SHA3_SHIFT 32 -#define ID_AA64ZFR0_BF16_SHIFT 20 -#define ID_AA64ZFR0_BITPERM_SHIFT 16 -#define ID_AA64ZFR0_AES_SHIFT 4 -#define ID_AA64ZFR0_SVEVER_SHIFT 0 - -#define ID_AA64ZFR0_F64MM 0x1 -#define ID_AA64ZFR0_F32MM 0x1 -#define ID_AA64ZFR0_I8MM 0x1 -#define ID_AA64ZFR0_BF16 0x1 -#define ID_AA64ZFR0_SM4 0x1 -#define ID_AA64ZFR0_SHA3 0x1 -#define ID_AA64ZFR0_BITPERM 0x1 -#define ID_AA64ZFR0_AES 0x1 -#define ID_AA64ZFR0_AES_PMULL 0x2 -#define ID_AA64ZFR0_SVEVER_SVE2 0x1 +#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56 +#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52 +#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44 +#define ID_AA64ZFR0_EL1_SM4_SHIFT 40 +#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32 +#define ID_AA64ZFR0_EL1_BF16_SHIFT 20 +#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16 +#define ID_AA64ZFR0_EL1_AES_SHIFT 4 +#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0 + +#define ID_AA64ZFR0_EL1_F64MM_IMP 0x1 +#define ID_AA64ZFR0_EL1_F32MM_IMP 0x1 +#define ID_AA64ZFR0_EL1_I8MM_IMP 0x1 +#define ID_AA64ZFR0_EL1_BF16_IMP 0x1 +#define ID_AA64ZFR0_EL1_SM4_IMP 0x1 +#define ID_AA64ZFR0_EL1_SHA3_IMP 0x1 +#define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1 +#define ID_AA64ZFR0_EL1_AES_IMP 0x1 +#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 +#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 /* id_aa64smfr0 */ #define ID_AA64SMFR0_EL1_FA64_SHIFT 63 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index a6c224539ce4..08288ad17307 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -276,23 +276,23 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2628,16 +2628,16 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), - HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), + HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), #endif HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), #ifdef CONFIG_ARM64_BTI From patchwork Mon Jul 4 17:02:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A830C43334 for ; Mon, 4 Jul 2022 17:09:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z/tYLJFDtIxEAV3HqCAdZdan4GXOTEG0n3B+LxJeH+o=; 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Mon, 4 Jul 2022 17:03:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954231; bh=3mESYXXK0PMoLYS0ZknRLsmAjjE8K4nw9L0uqOjf850=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rH3pTdCryklQ32dc5P7hd88SmBWMVSR4v5LC8ymQAPJ2PAo2tcY6dAEFIcleu/Wa7 66abPpXFN6qc/PDUB6AwN8fZNmjtXaYH4Ff5YOvedEHuGjmxfKdO5GiYS85kONnWs4 cJjvjeWNEgxrkDbWkBkMwOSIG2FF8Hl0heTlds/H92gO/3cxkZTc5/t3FkgGOU4tmd hMHrr57T0yZj7D7gHWhSZh3BMyJaLkPttJtHLOs3BG2EfRp25xvySZa++hxzGJF9TX Odo5TJrzw5LWC+ZUuo24/583kqLeTiZPnQVzQ4wT1MwEgcAOFP6zGRx7pFhc9JDpG4 uoo/qZBxGtoWg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 14/28] arm64/sysreg: Remove defines for RPRES enumeration Date: Mon, 4 Jul 2022 18:02:48 +0100 Message-Id: <20220704170302.2609529-15-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Since these defines are never used just remove them. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index cbc5f311c0cf..a2576d58d89a 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -744,8 +744,6 @@ #define ID_AA64ISAR2_RPRES_SHIFT 4 #define ID_AA64ISAR2_WFxT_SHIFT 0 -#define ID_AA64ISAR2_RPRES_8BIT 0x0 -#define ID_AA64ISAR2_RPRES_12BIT 0x1 /* * Value 0x1 has been removed from the architecture, and is * reserved, but has not yet been removed from the ARM ARM From patchwork Mon Jul 4 17:02:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE63FCCA481 for ; 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Mon, 04 Jul 2022 17:09:00 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PUI-00A9PU-Kl for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 17:03:57 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 23886614FC; Mon, 4 Jul 2022 17:03:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E875DC341CB; Mon, 4 Jul 2022 17:03:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954233; bh=4qhmQI+AIBer3HvEu2l31x8ZHfXRPzU8YILgtkPb5kI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kPEHoGiCUnAfehDpbgkQDFWjyEadeshTV+XsgLRDiAbMcdNhDjsnzX0Uao5R3q3n1 zbKiJIyd8TUXbBD9WFhej/HlhQionimxeQgEDVVoqbQXBn/vmsYpJwB8ym5F29K902 bhbS1O3GPdZzkGvSM2PxKHrUlM4Ar3lszTOu7QfN21fffFBrQD9UjTW9Lw08PLd9EO vzreEHs34oPoO6KYMYwg1/cfzG1U29OpdhybrJKnLCnQFGbxQ5OasHqc04zd3f8Lzj kiANArMZbx4F5ZY8+TD3r6XUhGxhaEAgCbvE3CUxhBICnwpm+6Vd2R0vfjz6n9Zpzc v5Y0RLU6g5kOw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 15/28] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Date: Mon, 4 Jul 2022 18:02:49 +0100 Message-Id: <20220704170302.2609529-16-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=19189; h=from:subject; bh=4qhmQI+AIBer3HvEu2l31x8ZHfXRPzU8YILgtkPb5kI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx06jLzPcxjeShPUrtF6+EqWoV55AfvsFow47Nzs oe+hSKaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdOgAKCRAk1otyXVSH0IMYB/ 0RtUU6+dqIjB97ZW3/dyfcqWKYvBPbz9FwfyMP/5rbi2izzP8IlcYFhyCNAd2mlz76Gioxdz5qmVQ6 F9rAFB8Unbb7TcKU6Ax4w/e7Y2O3+D/5UB3tUnuoULos9BfKXu1M2YILjDUylMamhlp6CJxJLFsYfs HqoIIEl3IrGcD9stp6o1Q+dqZN2iPVe/NAXpcE3BoA5TQfDurjZimXTRtHgcFjiO9NY6BlDzGMipaJ 1WZszehK8pd+3quwOxS+L80+8JL/89Pt+DbccQgH39n9dZ4Zt+2S/kJ4Oeex6EV7ed2VkuEjrLmhTk K+T9CTegNUPiFKeQAzOOno1E3NCpCt X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100354_824088_20E9801F X-CRM114-Status: GOOD ( 16.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Normally we include the full register name in the defines for fields within registers but this has not been followed for ID registers. In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR1_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/asm_pointer_auth.h | 2 +- arch/arm64/include/asm/sysreg.h | 62 ++++++------- arch/arm64/kernel/cpufeature.c | 90 +++++++++---------- arch/arm64/kernel/idreg-override.c | 8 +- .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 28 +++--- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 8 +- arch/arm64/kvm/sys_regs.c | 8 +- 7 files changed, 103 insertions(+), 103 deletions(-) diff --git a/arch/arm64/include/asm/asm_pointer_auth.h b/arch/arm64/include/asm/asm_pointer_auth.h index ead62f7dd269..3b192e04a5dd 100644 --- a/arch/arm64/include/asm/asm_pointer_auth.h +++ b/arch/arm64/include/asm/asm_pointer_auth.h @@ -59,7 +59,7 @@ alternative_else_nop_endif .macro __ptrauth_keys_init_cpu tsk, tmp1, tmp2, tmp3 mrs \tmp1, id_aa64isar1_el1 - ubfx \tmp1, \tmp1, #ID_AA64ISAR1_APA_SHIFT, #8 + ubfx \tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8 mrs_s \tmp2, SYS_ID_AA64ISAR2_EL1 ubfx \tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4 orr \tmp1, \tmp1, \tmp2 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index a2576d58d89a..495f37015677 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -705,37 +705,37 @@ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) /* id_aa64isar1 */ -#define ID_AA64ISAR1_I8MM_SHIFT 52 -#define ID_AA64ISAR1_DGH_SHIFT 48 -#define ID_AA64ISAR1_BF16_SHIFT 44 -#define ID_AA64ISAR1_SPECRES_SHIFT 40 -#define ID_AA64ISAR1_SB_SHIFT 36 -#define ID_AA64ISAR1_FRINTTS_SHIFT 32 -#define ID_AA64ISAR1_GPI_SHIFT 28 -#define ID_AA64ISAR1_GPA_SHIFT 24 -#define ID_AA64ISAR1_LRCPC_SHIFT 20 -#define ID_AA64ISAR1_FCMA_SHIFT 16 -#define ID_AA64ISAR1_JSCVT_SHIFT 12 -#define ID_AA64ISAR1_API_SHIFT 8 -#define ID_AA64ISAR1_APA_SHIFT 4 -#define ID_AA64ISAR1_DPB_SHIFT 0 - -#define ID_AA64ISAR1_APA_NI 0x0 -#define ID_AA64ISAR1_APA_PAuth 0x1 -#define ID_AA64ISAR1_APA_ARCH_EPAC 0x2 -#define ID_AA64ISAR1_APA_Pauth2 0x3 -#define ID_AA64ISAR1_APA_FPAC 0x4 -#define ID_AA64ISAR1_APA_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_API_NI 0x0 -#define ID_AA64ISAR1_API_PAuth 0x1 -#define ID_AA64ISAR1_API_EPAC 0x2 -#define ID_AA64ISAR1_API_PAuth2 0x3 -#define ID_AA64ISAR1_API_FPAC 0x4 -#define ID_AA64ISAR1_API_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_GPA_NI 0x0 -#define ID_AA64ISAR1_GPA_IMP 0x1 -#define ID_AA64ISAR1_GPI_NI 0x0 -#define ID_AA64ISAR1_GPI_IMP 0x1 +#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52 +#define ID_AA64ISAR1_EL1_DGH_SHIFT 48 +#define ID_AA64ISAR1_EL1_BF16_SHIFT 44 +#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 +#define ID_AA64ISAR1_EL1_SB_SHIFT 36 +#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 +#define ID_AA64ISAR1_EL1_GPI_SHIFT 28 +#define ID_AA64ISAR1_EL1_GPA_SHIFT 24 +#define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20 +#define ID_AA64ISAR1_EL1_FCMA_SHIFT 16 +#define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12 +#define ID_AA64ISAR1_EL1_API_SHIFT 8 +#define ID_AA64ISAR1_EL1_APA_SHIFT 5 +#define ID_AA64ISAR1_EL1_DPB_SHIFT 0 + +#define ID_AA64ISAR1_EL1_APA_NI 0x0 +#define ID_AA64ISAR1_EL1_APA_PAuth 0x1 +#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC 0x2 +#define ID_AA64ISAR1_EL1_APA_Pauth2 0x3 +#define ID_AA64ISAR1_EL1_APA_FPAC 0x4 +#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE 0x5 +#define ID_AA64ISAR1_EL1_API_NI 0x0 +#define ID_AA64ISAR1_EL1_API_PAuth 0x1 +#define ID_AA64ISAR1_EL1_API_EPAC 0x2 +#define ID_AA64ISAR1_EL1_API_PAuth2 0x3 +#define ID_AA64ISAR1_EL1_API_FPAC 0x4 +#define ID_AA64ISAR1_EL1_API_FPACCOMBINE 0x5 +#define ID_AA64ISAR1_EL1_GPA_NI 0x0 +#define ID_AA64ISAR1_EL1_GPA_IMP 0x1 +#define ID_AA64ISAR1_EL1_GPI_NI 0x0 +#define ID_AA64ISAR1_EL1_GPI_IMP 0x1 /* id_aa64isar2 */ #define ID_AA64ISAR2_BC_SHIFT 28 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 08288ad17307..0d4f0120c516 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -209,24 +209,24 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2132,7 +2132,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR1_EL1, - .field_pos = ID_AA64ISAR1_DPB_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, .field_width = 4, .min_field_value = 1, }, @@ -2143,7 +2143,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_DPB_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT, .field_width = 4, .min_field_value = 2, }, @@ -2303,7 +2303,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR1_EL1, - .field_pos = ID_AA64ISAR1_SB_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_SB_SHIFT, .field_width = 4, .sign = FTR_UNSIGNED, .min_field_value = 1, @@ -2315,9 +2315,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_APA_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_APA_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_APA_PAuth, + .min_field_value = ID_AA64ISAR1_EL1_APA_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2337,9 +2337,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_API_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_API_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_API_PAuth, + .min_field_value = ID_AA64ISAR1_EL1_API_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2353,9 +2353,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_GPA_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_GPA_IMP, + .min_field_value = ID_AA64ISAR1_EL1_GPA_IMP, .matches = has_cpuid_feature, }, { @@ -2375,9 +2375,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_GPI_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR1_GPI_IMP, + .min_field_value = ID_AA64ISAR1_EL1_GPI_IMP, .matches = has_cpuid_feature, }, { @@ -2478,7 +2478,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, + .field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT, .field_width = 4, .matches = has_cpuid_feature, .min_field_value = 1, @@ -2560,33 +2560,33 @@ static const struct arm64_cpu_capabilities arm64_features[] = { #ifdef CONFIG_ARM64_PTR_AUTH static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT, 4, FTR_UNSIGNED, - ID_AA64ISAR1_APA_PAuth) + ID_AA64ISAR1_EL1_APA_PAuth) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_API_PAuth) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth) }, {}, }; static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_IMP) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP) }, {}, }; @@ -2614,17 +2614,17 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), - HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index b797f232ebcd..1a4ebaa315eb 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -63,10 +63,10 @@ static const struct ftr_set_desc isar1 __initconst = { .name = "id_aa64isar1", .override = &id_aa64isar1_override, .fields = { - { "gpi", ID_AA64ISAR1_GPI_SHIFT }, - { "gpa", ID_AA64ISAR1_GPA_SHIFT }, - { "api", ID_AA64ISAR1_API_SHIFT }, - { "apa", ID_AA64ISAR1_APA_SHIFT }, + { "gpi", ID_AA64ISAR1_EL1_GPI_SHIFT }, + { "gpa", ID_AA64ISAR1_EL1_GPA_SHIFT }, + { "api", ID_AA64ISAR1_EL1_API_SHIFT }, + { "apa", ID_AA64ISAR1_EL1_APA_SHIFT }, {} }, }; diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index fd55014b3497..46cf9dec21ba 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -176,20 +176,20 @@ ) #define PVM_ID_AA64ISAR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR1_DPB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_JSCVT) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_FCMA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_LRCPC) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_FRINTTS) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_SB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_SPECRES) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_BF16) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_DGH) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_I8MM) \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \ ) #define PVM_ID_AA64ISAR2_ALLOW (\ diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 35a4331ba5f3..5b77bc1cca0c 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -173,10 +173,10 @@ static u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR1_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI)); + allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); return id_aa64isar1_el1_sys_val & allow_mask; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f12c6d457677..ccd973dc346a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1136,10 +1136,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, break; case SYS_ID_AA64ISAR1_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI)); + val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | + ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); 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Mon, 4 Jul 2022 17:03:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 006B4C341C7; Mon, 4 Jul 2022 17:03:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954235; bh=p5GN9KfYWgNvt7Me3VR5J6OnpWb5z8bG0SGOHukRiAo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QnSHDWXx630aG2x06zsfLePWwBR15p7KwHB/yNetFMvYrx4HKE/Dje3W12dep2MMB U6v7UkO79l4rm7Q7pR5HgVBnKV187ky2w1jv43NQNAH7jQkQBAZDjHR0oqViEFM1Ir m8Yv6vcRcwfcL67r088BOmWOnAfBpd7fGgkoSez2ZR1twhmVt1rQJ+5/rKMJBhcD1k eNhx3hXABtZF3iOwrQwFnSckWtG039gbL7BfwHf2I+O59ArMgtJlukyu+jCNvIm4II e/aKc5MtodjkouYgSHihN+ya2Y8o0yextR2gT0ldZOVNpueKPWlG12b4f4TfaKhccO CUlyRPU/aGqdw== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 16/28] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names Date: Mon, 4 Jul 2022 18:02:50 +0100 Message-Id: <20220704170302.2609529-17-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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In preparation for automatic generation of defines add the _EL1s into the defines for ID_AA64ISAR2_EL1 to follow the convention. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/asm_pointer_auth.h | 2 +- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/include/asm/sysreg.h | 34 +++++++++---------- arch/arm64/kernel/cpufeature.c | 34 +++++++++---------- arch/arm64/kernel/idreg-override.c | 4 +-- .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 4 +-- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 4 +-- arch/arm64/kvm/sys_regs.c | 6 ++-- 8 files changed, 45 insertions(+), 45 deletions(-) diff --git a/arch/arm64/include/asm/asm_pointer_auth.h b/arch/arm64/include/asm/asm_pointer_auth.h index 3b192e04a5dd..13ecc79854ee 100644 --- a/arch/arm64/include/asm/asm_pointer_auth.h +++ b/arch/arm64/include/asm/asm_pointer_auth.h @@ -61,7 +61,7 @@ alternative_else_nop_endif mrs \tmp1, id_aa64isar1_el1 ubfx \tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8 mrs_s \tmp2, SYS_ID_AA64ISAR2_EL1 - ubfx \tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4 + ubfx \tmp2, \tmp2, #ID_AA64ISAR2_EL1_APA3_SHIFT, #4 orr \tmp1, \tmp1, \tmp2 cbz \tmp1, .Lno_addr_auth\@ mov_q \tmp1, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \ diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 6472f2badc97..fe59035bdc22 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope) isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); return cpuid_feature_extract_unsigned_field(isar2, - ID_AA64ISAR2_BC_SHIFT); + ID_AA64ISAR2_EL1_BC_SHIFT); } const struct cpumask *system_32bit_el0_cpumask(void); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 495f37015677..0b547f181fb0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -738,29 +738,29 @@ #define ID_AA64ISAR1_EL1_GPI_IMP 0x1 /* id_aa64isar2 */ -#define ID_AA64ISAR2_BC_SHIFT 28 -#define ID_AA64ISAR2_APA3_SHIFT 12 -#define ID_AA64ISAR2_GPA3_SHIFT 8 -#define ID_AA64ISAR2_RPRES_SHIFT 4 -#define ID_AA64ISAR2_WFxT_SHIFT 0 +#define ID_AA64ISAR2_EL1_BC_SHIFT 28 +#define ID_AA64ISAR2_EL1_APA3_SHIFT 12 +#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 +#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 +#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 /* * Value 0x1 has been removed from the architecture, and is * reserved, but has not yet been removed from the ARM ARM * as of ARM DDI 0487G.b. */ -#define ID_AA64ISAR2_WFxT_NI 0x0 -#define ID_AA64ISAR2_WFxT_IMP 0x2 - -#define ID_AA64ISAR2_APA3_NI 0x0 -#define ID_AA64ISAR2_APA3_PAuth 0x1 -#define ID_AA64ISAR2_APA3_EPAC 0x2 -#define ID_AA64ISAR2_APA3_PAuth2 0x3 -#define ID_AA64ISAR2_APA3_FPAC 0x4 -#define ID_AA64ISAR2_APA3_FPACCOMBINE 0x5 - -#define ID_AA64ISAR2_GPA3_NI 0x0 -#define ID_AA64ISAR2_GPA3_IMP 0x1 +#define ID_AA64ISAR2_EL1_WFxT_NI 0x0 +#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2 + +#define ID_AA64ISAR2_EL1_APA3_NI 0x0 +#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1 +#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2 +#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3 +#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4 +#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5 + +#define ID_AA64ISAR2_EL1_GPA3_NI 0x0 +#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1 /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0d4f0120c516..be20100a7d4c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -231,13 +231,13 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_BC_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0), + FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFxT_SHIFT, 4, 0), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2326,9 +2326,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_APA3_SHIFT, + .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_APA3_PAuth, + .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth, .matches = has_address_auth_cpucap, }, { @@ -2364,9 +2364,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_GPA3_SHIFT, + .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT, .field_width = 4, - .min_field_value = ID_AA64ISAR2_GPA3_IMP, + .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP, .matches = has_cpuid_feature, }, { @@ -2516,10 +2516,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .type = ARM64_CPUCAP_SYSTEM_FEATURE, .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, - .field_pos = ID_AA64ISAR2_WFxT_SHIFT, + .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT, .field_width = 4, .matches = has_cpuid_feature, - .min_field_value = ID_AA64ISAR2_WFxT_IMP, + .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP, }, {}, }; @@ -2565,8 +2565,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { ID_AA64ISAR1_EL1_APA_PAuth) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT, @@ -2581,8 +2581,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP) }, { - HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT, - 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP) + HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT, + 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP) }, { HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT, @@ -2653,8 +2653,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #endif /* CONFIG_ARM64_MTE */ HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP), - HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), - HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES), + HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), #ifdef CONFIG_ARM64_SME HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index 1a4ebaa315eb..21b3d03089ca 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -75,8 +75,8 @@ static const struct ftr_set_desc isar2 __initconst = { .name = "id_aa64isar2", .override = &id_aa64isar2_override, .fields = { - { "gpa3", ID_AA64ISAR2_GPA3_SHIFT }, - { "apa3", ID_AA64ISAR2_APA3_SHIFT }, + { "gpa3", ID_AA64ISAR2_EL1_GPA3_SHIFT }, + { "apa3", ID_AA64ISAR2_EL1_APA3_SHIFT }, {} }, }; diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index 46cf9dec21ba..fa6e466ed57f 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -193,8 +193,8 @@ ) #define PVM_ID_AA64ISAR2_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) \ + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \ ) u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id); diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 5b77bc1cca0c..6b94c3e6ff26 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -186,8 +186,8 @@ static u64 get_pvm_id_aa64isar2(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR2_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); + allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); return id_aa64isar2_el1_sys_val & allow_mask; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index ccd973dc346a..c4fb3874b5e2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1143,10 +1143,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, break; case SYS_ID_AA64ISAR2_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); + val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | + ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); if (!cpus_have_final_cap(ARM64_HAS_WFXT)) - val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFxT); + val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); break; case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ From patchwork Mon Jul 4 17:02:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905704 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFE71C433EF for ; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 16 ---------------- arch/arm64/tools/sysreg | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 0b547f181fb0..234f9a3844de 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -461,7 +461,6 @@ #define SMIDR_EL1_SMPS_SHIFT 15 #define SMIDR_EL1_AFFINITY_SHIFT 0 -#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) @@ -1082,21 +1081,6 @@ #define MVFR2_FPMISC_SHIFT 4 #define MVFR2_SIMDMISC_SHIFT 0 -#define CTR_EL0_L1Ip_VPIPT 0 -#define CTR_EL0_L1Ip_VIPT 2 -#define CTR_EL0_L1Ip_PIPT 3 - -#define CTR_EL0_L1Ip_SHIFT 14 -#define CTR_EL0_L1Ip_MASK 3 -#define CTR_EL0_DminLine_SHIFT 16 -#define CTR_EL0_IminLine_SHIFT 0 -#define CTR_EL0_IminLine_MASK 0xf -#define CTR_EL0_ERG_SHIFT 20 -#define CTR_EL0_CWG_SHIFT 24 -#define CTR_EL0_CWG_MASK 15 -#define CTR_EL0_IDC_SHIFT 28 -#define CTR_EL0_DIC_SHIFT 29 - #define DCZID_EL0_DZP_SHIFT 4 #define DCZID_EL0_BS_SHIFT 0 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ff5e552f7420..a9f4c157c4be 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -273,6 +273,27 @@ Field 3:1 Level Field 0 InD EndSysreg +Sysreg CTR_EL0 3 3 0 0 1 +Res0 63:38 +Field 37:32 TminLine +Res1 31 +Res0 30 +Field 29 DIC +Field 28 IDC +Field 27:24 CWG +Field 23:20 ERG +Field 19:16 DminLine +Enum 15:14 L1Ip + 0b00 VPIPT + # This is named as AIVIVT in the ARM but documented as reserved + 0b01 RESERVED + 0b10 VIPT + 0b11 PIPT +EndEnum +Res0 13:4 +Field 3:0 IminLine +EndSysreg + Sysreg SVCR 3 3 4 2 2 Res0 63:2 Field 1 ZA From patchwork Mon Jul 4 17:02:52 2022 Content-Type: text/plain; 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Mon, 4 Jul 2022 17:03:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954239; bh=cdagZIIzLuaTt9Ly5Wf/O4o9jvkrXC/jW8pG8OgZs+E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rObYT8O6hxEpEoyFiDHZHlh44Xjec2lurXSMoDHOSwsNvCm7e2V2OYnlZlLtZjwca mQvXdIUPBBiwB3U/TjCf8UCxSj1E218ERgmMxV+pdkWDU1P29uw3RqLgGt79yxP4E2 8mjtgGKGrHOtKu3HTmRu74c22QS8eLC7rSj5zvgQ0gvrFOH40zab/CiSiSmZnc+iAj o7/fl8/SzZ+NFxshK48uh6kyQc3Dl22+MU5cSq/EcBteqcUQclk8ynjf8/x7YFwAcf vHaIWCVXwmguY038VSGAGTP4Irz5RXxASf2ZMU67MISIO2r0ZXJNEET1PACxJAjGVd sJYpS6s6RR45g== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 18/28] arm64/sysreg: Convert DCZID_EL0 to automatic generation Date: Mon, 4 Jul 2022 18:02:52 +0100 Message-Id: <20220704170302.2609529-19-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 5 ----- arch/arm64/tools/sysreg | 6 ++++++ 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 234f9a3844de..1a6a04b96dfa 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -461,8 +461,6 @@ #define SMIDR_EL1_SMPS_SHIFT 15 #define SMIDR_EL1_AFFINITY_SHIFT 0 -#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) - #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) @@ -1081,9 +1079,6 @@ #define MVFR2_FPMISC_SHIFT 4 #define MVFR2_SIMDMISC_SHIFT 0 -#define DCZID_EL0_DZP_SHIFT 4 -#define DCZID_EL0_BS_SHIFT 0 - #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a9f4c157c4be..c286b62958ea 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -294,6 +294,12 @@ Res0 13:4 Field 3:0 IminLine EndSysreg +Sysreg DCZID_EL0 3 3 0 0 7 +Res0 63:5 +Field 4 DZP +Field 3:0 BS +EndSysreg + Sysreg SVCR 3 3 4 2 2 Res0 63:2 Field 1 ZA From patchwork Mon Jul 4 17:02:53 2022 Content-Type: text/plain; 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Mon, 4 Jul 2022 17:03:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954241; bh=XrFUJZHSXzlqJ/kZ7tvy+jlKwQpeNfKPeK8HHkXLPgY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FdQc9FtzDPU6o7Rnp+PRG5NmG//CqNblDBCCUPLQEM8vPXJ5JVwq8gxML3h2sRM6C zu7HGpRqcqmQJ1lK6RUjR/7yJKyysx6Cw6oia0ixzXNKozjodvsmQJxpdNlJLSKSp9 WYhbUZFe6TsUhEwSYN48xvLFTFxqqiEoH81jpwP+pJypD7ZcsbLw5FasnzQIzs6Wg9 i3N+AYvMaiS4DM8183aRn66rbqtgZ/Yih9ftBySz+ASBy9culm3L792krSPjPytv7h YBd4sUrVbBBi1Q0JHSS/ixQPHm3dw2Xux844AFxWjDS6gZvLO0OPszcCVokGuPDB/g q61K2PP8GhDPg== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 19/28] arm64/sysreg: Convert GMID to automatic generation Date: Mon, 4 Jul 2022 18:02:53 +0100 Message-Id: <20220704170302.2609529-20-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1a6a04b96dfa..1b92bea9299a 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -454,7 +454,6 @@ #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) -#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4) #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) #define SMIDR_EL1_IMPLEMENTER_SHIFT 24 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c286b62958ea..ea3520a347b1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -257,6 +257,11 @@ Field 5:3 Ctype2 Field 2:0 Ctype1 EndSysreg +Sysreg GMID_EL1 3 1 0 0 4 +Res0 63:4 +Field 3:0 BS +EndSysreg + Sysreg SMIDR_EL1 3 1 0 0 6 Res0 63:32 Field 31:24 IMPLEMENTER From patchwork Mon Jul 4 17:02:54 2022 Content-Type: text/plain; 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Mon, 4 Jul 2022 17:04:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954242; bh=lgo7JHdlD/jye/JhPv7FGuvRn4k/AquPXtK/6mLBEPM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ePEl0AQmaOvKQvSV7+rFbz71tYhYG0dANLyHD9VKHDTWcAhhTTRr5J7a1B3QvYQX2 uGsoLIauDSR2fvKV8yYjcGY9YlFnHN9pGwxZ56JURFzW2iJ7LOHQiw+QpOlgQFJxAZ /XIBzye3YklfEf67eIy0XiJBzOut23Zll9nJVZT6GpATPCcTUYPVZ2VKa2dtK68KQY 1GqaeQJjsYUu5o243lExKA1zQXIOADluoHqUxcXPrbMZG5fKenkODwYXgYntRgCWU2 Pad3cX9oroO6wgRKLbr6gO7KVI0ZW4d4rCovCld4ZPgk4NUUav/WLasYn42Dly++zw JL4cMd1cb4gZA== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 20/28] arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation Date: Mon, 4 Jul 2022 18:02:54 +0100 Message-Id: <20220704170302.2609529-21-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 34 -------------- arch/arm64/tools/sysreg | 83 +++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+), 34 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1b92bea9299a..7f87690e74b3 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -201,7 +201,6 @@ #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) -#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) #define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) @@ -700,39 +699,6 @@ /* Position the attr at the correct index */ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) -/* id_aa64isar1 */ -#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52 -#define ID_AA64ISAR1_EL1_DGH_SHIFT 48 -#define ID_AA64ISAR1_EL1_BF16_SHIFT 44 -#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40 -#define ID_AA64ISAR1_EL1_SB_SHIFT 36 -#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32 -#define ID_AA64ISAR1_EL1_GPI_SHIFT 28 -#define ID_AA64ISAR1_EL1_GPA_SHIFT 24 -#define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20 -#define ID_AA64ISAR1_EL1_FCMA_SHIFT 16 -#define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12 -#define ID_AA64ISAR1_EL1_API_SHIFT 8 -#define ID_AA64ISAR1_EL1_APA_SHIFT 5 -#define ID_AA64ISAR1_EL1_DPB_SHIFT 0 - -#define ID_AA64ISAR1_EL1_APA_NI 0x0 -#define ID_AA64ISAR1_EL1_APA_PAuth 0x1 -#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC 0x2 -#define ID_AA64ISAR1_EL1_APA_Pauth2 0x3 -#define ID_AA64ISAR1_EL1_APA_FPAC 0x4 -#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_EL1_API_NI 0x0 -#define ID_AA64ISAR1_EL1_API_PAuth 0x1 -#define ID_AA64ISAR1_EL1_API_EPAC 0x2 -#define ID_AA64ISAR1_EL1_API_PAuth2 0x3 -#define ID_AA64ISAR1_EL1_API_FPAC 0x4 -#define ID_AA64ISAR1_EL1_API_FPACCOMBINE 0x5 -#define ID_AA64ISAR1_EL1_GPA_NI 0x0 -#define ID_AA64ISAR1_EL1_GPA_IMP 0x1 -#define ID_AA64ISAR1_EL1_GPI_NI 0x0 -#define ID_AA64ISAR1_EL1_GPI_IMP 0x1 - /* id_aa64isar2 */ #define ID_AA64ISAR2_EL1_BC_SHIFT 28 #define ID_AA64ISAR2_EL1_APA3_SHIFT 12 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ea3520a347b1..164221177079 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -114,6 +114,89 @@ EndEnum Res0 3:0 EndSysreg +Sysreg ID_AA64ISAR1_EL1 3 0 0 6 1 +Enum 63:60 LS64 + 0b0000 NI + 0b0001 LS64 + 0b0010 LS64_V + 0b0011 LS64_ACCDATA +EndEnum +Enum 59:56 XS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 55:52 I8MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 51:48 DGH + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 47:44 BF16 + 0b0000 NI + 0b0001 IMP + 0b0010 EBF16 +EndEnum +Enum 43:40 SPECRES + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 39:36 SB + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 35:32 FRINTTS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 31:28 GPI + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 27:24 GPA + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 LRCPC + 0b0000 NI + 0b0001 IMP + 0b0010 LRCPC2 +EndEnum +Enum 19:16 FCMA + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 JSCVT + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 API + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 7:4 APA + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 3:0 DPB + 0b0000 NI + 0b0001 IMP + 0b0010 DPB2 +EndEnum +EndSysreg + 0b0001 IMP +EndEnum +EndSysreg + Sysreg SCTLR_EL1 3 0 1 0 0 Field 63 TIDCP Field 62 SPINMASK From patchwork Mon Jul 4 17:02:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FBFEC433EF for ; Mon, 4 Jul 2022 17:15:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mm8ALVmm8k3GCZxWrVzSvZ+zphgrbEjEzwgF4EXpCl0=; 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Mon, 4 Jul 2022 17:04:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954244; bh=SYhxV8Xv3mc8918rY24Af16Lj77Z2AMIIax1BuqJkrk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tp2L8jgG9p4qGkD4AKFHYl8XiGgCKIJKwQZztYp/pnet+Yw7oqHcRQpWXXbBQvE9X /8p+LLaF3RmxCdiK5yqJgklVy5CSQRe/jFwbF9BFtcL4/2FJ6ec60CV3UwJ3vcDvVM Mxzl4pdGsz5Zw9Mh5CI5/6msIgKMI1tOQH0r/mUOjoRJH8w+bjM9CuypbXocoVvq3V xKUhThyP6+ecieftEm+OHGV8i8xwNCsSu/WvSJQ4EI2nI73H2vIen7DcIHOT8rCxuG eZS6Co0K0HzW0GEhtvDlcLTOSsEowyhqXrXtEhOtoVf/z+RJstYZQeOE3Xh0JW+iCg jwZyKUP5Qjm2Q== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 21/28] arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation Date: Mon, 4 Jul 2022 18:02:55 +0100 Message-Id: <20220704170302.2609529-22-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2775; h=from:subject; bh=SYhxV8Xv3mc8918rY24Af16Lj77Z2AMIIax1BuqJkrk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx0+zxV2B1VxLDKgrFoOvTsQ8/H0IRl6iZndVal+ 7aoMa4iJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdPgAKCRAk1otyXVSH0PHEB/ 9ALh+YpQX8pBgRZCUAXUcwL2qUalIOAdTalpIo/hkJwMqyYIe1bViqHbEUGEPZZO35SCwVfYFImomK AZ3y3aShbwiPMhqj8dc0gb/2pjl6+Th3l4dfYFNPJyQlQlAybyBqzasoQr60/vKqUwRWGdn7sjj43F sg4TJauQqyfXT1L/BjESbG8BPWqVz7VglTaXuF91cVzhYNv6oXH4kBi2gaHnI6omd2fyAvlBStVzZG 82Toz7xhCt1BoR8KcVCxqkMZRf2yJVnA+zDxJ8qV7RfZ1z7Dvk0/ILF108qjkSBXKMSkK6YPH0v6Xe pEdAKk49vyzepO5DhjioibvbAz55B1 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100407_823090_609CED4E X-CRM114-Status: GOOD ( 14.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions in DDI0487H.a. No functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 27 --------------------------- arch/arm64/tools/sysreg | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 27 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7f87690e74b3..cd6820f6e819 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -201,8 +201,6 @@ #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) -#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) - #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) @@ -699,31 +697,6 @@ /* Position the attr at the correct index */ #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) -/* id_aa64isar2 */ -#define ID_AA64ISAR2_EL1_BC_SHIFT 28 -#define ID_AA64ISAR2_EL1_APA3_SHIFT 12 -#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8 -#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4 -#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0 - -/* - * Value 0x1 has been removed from the architecture, and is - * reserved, but has not yet been removed from the ARM ARM - * as of ARM DDI 0487G.b. - */ -#define ID_AA64ISAR2_EL1_WFxT_NI 0x0 -#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2 - -#define ID_AA64ISAR2_EL1_APA3_NI 0x0 -#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1 -#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2 -#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3 -#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4 -#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5 - -#define ID_AA64ISAR2_EL1_GPA3_NI 0x0 -#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1 - /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 164221177079..da5e925bf624 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -193,8 +193,41 @@ Enum 3:0 DPB 0b0010 DPB2 EndEnum EndSysreg + +Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2 +Res0 63:28 +Enum 27:24 PAC_frac + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 BC + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 19:16 MOPS + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 15:12 APA3 + 0b0000 NI + 0b0001 PAuth + 0b0010 EPAC + 0b0011 PAuth2 + 0b0100 FPAC + 0b0101 FPACCOMBINE +EndEnum +Enum 11:8 GPA3 + 0b0000 NI 0b0001 IMP EndEnum +Enum 7:4 RPRES + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 WFxT + 0b0000 NI + 0b0010 IMP +EndEnum EndSysreg Sysreg SCTLR_EL1 3 0 1 0 0 From patchwork Mon Jul 4 17:02:56 2022 Content-Type: text/plain; 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Mon, 4 Jul 2022 17:04:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954246; bh=AQHN6Z2dK3kXp9W3wc+36hXQmeanVjaJN4I6rHfnwoo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K/MJueH2/b0SO28mezgZExNYPzFCmJWfUtDKOzglMC/FcN4CmF2Pr5H5QDi/bg/AS chHNpQEDSQi6bVD3Ben7SSPMokn+YETqJbartquexraCQg0jMi3tBsBP1CzgnKk1ek NQXawG7/kEo74dKQpZiXc3yS5NHv6ryf9O4Es+6ugz80jLvJQoRcl8Nm7a0Gi2TPsL yhJD18D4zj+D1aey2Ka9QSMEteEgLc5uKpReZza1Lb2DPQn3KVrqubqxZ1GxggEREO kXSkbSs5s+obUZa09axJvd4KNukLwTHdbtQxjbiBW98okJC3G5XCecA3nFgPQETDEr Jwh9aZcX51R7Q== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 22/28] arm64/sysreg: Convert LORSA_EL1 to automatic generation Date: Mon, 4 Jul 2022 18:02:56 +0100 Message-Id: <20220704170302.2609529-23-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 8 ++++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index cd6820f6e819..48a48974515b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index da5e925bf624..c1e3a9ceb049 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -515,3 +515,11 @@ EndSysreg Sysreg TTBR1_EL1 3 0 2 0 1 Fields TTBRx_EL1 EndSysreg + +Sysreg LORSA_EL1 3 0 10 4 0 +Res0 63:52 +Field 51:16 SA +Res0 15:1 +Field 0 Valid +EndSysreg + From patchwork Mon Jul 4 17:02:57 2022 Content-Type: text/plain; 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Mon, 4 Jul 2022 17:04:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954248; bh=dBg+SZyltdd1yWVOW03/km/Q5r4vbuCK8shPVk0zqnI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZN0+BQnntrrNzMLQrurn2RdGAbYPDs6pddDzKLj9UBBo+d74PVBUD6o3+wMDkoW5f 9xV1aBbcrrmmiI5en49ojRy+lDvY9aIRcrWAPPNFB53sRs/d33nsHQj2cQwktiJrrD Aw0pb9qZFqDDCZ1lgEpbNl50QksDKojxqWbaO7sx6VNN4rvIsJa7j9Vhpq0/dJ6zCf LkG7T2U3ahtB8NEckOAOcFN/nXUtt8xwzXBUj+ciqo4GVOHNk5qSjsV2kMep/UHAL4 TzdgS+fphhcecAfhQ9QRTdDlW0yvrenTc/9Sb9XZyH1D2cvFYPPn3IVVV5aRssJjVa uRxoSDhkj/krQ== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 23/28] arm64/sysreg: Convert LOREA_EL1 to automatic generation Date: Mon, 4 Jul 2022 18:02:57 +0100 Message-Id: <20220704170302.2609529-24-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 6 ++++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 48a48974515b..56989d982c81 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c1e3a9ceb049..4c23c65e53d1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -523,3 +523,9 @@ Res0 15:1 Field 0 Valid EndSysreg +Sysreg LOREA_EL1 3 0 10 4 1 +Res0 63:52 +Field 51:48 EA_51_48 +Field 47:16 EA_47_16 +Res0 15:0 +EndSysreg From patchwork Mon Jul 4 17:02:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B63EC43334 for ; Mon, 4 Jul 2022 17:19:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KtlcqwAjxXovPnHRJNSexw48zFE92AkLH13vaLQKFg0=; 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Mon, 4 Jul 2022 17:04:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954250; bh=uMgkSIlxgwYOZxnTOw7Jn6MTGQgnZ/2Irj3Q5QKSItA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jP44GL0erBKAfn3/ejXcgqH6g6GuLqgh6qjgpWGNcktmGk/cAhlt2m7IB4gqFhNRv yMd/dquat/fGgiB6dQwE/sgvy76yyfKNyjYA5tW7l7FvyGan7R01pJdVgJxHY4LcSG d1VX2HcNj1MqScBy9K6QskZrlvQCZeJCAtX5C+eEC9jIY4HP4vBEPimT8c3rAhXPlr L+l+GLYqGTMKH41DHvnv4Kec065/atZPConWovC0tQamzo7BJa+4Ld66AadX4D9ybP ZEGTFn3j36YHblhJNWW9EKSEP5HLiPocMmJKPpjqC/5f/qN5GPfmo7NcLmJU9SQwe/ r7mrvlf3tkxiQ== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 24/28] arm64/sysreg: Convert LORN_EL1 to automatic generation Date: Mon, 4 Jul 2022 18:02:58 +0100 Message-Id: <20220704170302.2609529-25-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 56989d982c81..78e61eb25eff 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4c23c65e53d1..ec84a76fe66e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -529,3 +529,8 @@ Field 51:48 EA_51_48 Field 47:16 EA_47_16 Res0 15:0 EndSysreg + +Sysreg LORN_EL1 3 0 10 4 2 +Res0 63:8 +Field 7:0 Num +EndSysreg From patchwork Mon Jul 4 17:02:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90935C43334 for ; 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Mon, 04 Jul 2022 17:19:17 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o8PUb-00A9XT-S3 for linux-arm-kernel@lists.infradead.org; Mon, 04 Jul 2022 17:04:15 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 77D02B80BEB; Mon, 4 Jul 2022 17:04:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB20FC341CF; Mon, 4 Jul 2022 17:04:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954252; bh=rju9udwleRaBDjH/0XnnKPRlWiYZK97Z5BVin/FaQx0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HqUgqPhqVVEm0VpWN59T9pDKF2bEWjAQW3ZMwW3N3HsKoh8ZZvlFQYs54di+YYMR6 meVIwoBlxz5xId6f+cJTkG+ua14ttdaxWERnst1Pjg+LOMkFRZAwJyzW29p3I+8j3z 6BlwyAzQwyoNZgkWvzyt5Rnp49OPMuo88VL8fy7jD7gxa05Ch07UcFLphBcegkQd4C LdZt1/kii1Hp3RDssYWTdiUS8WDYWRoSqggD+YeZ02c9uJQiVe/venI9XQ7CaEmRyX 4Pev+wdmTyWnUi7GHO6uME3r2+aCLhQ8bxheLNmkiGZIbHF3YGqFnXkCnLaoLr+Hia QFLzUmJAYYO6w== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 25/28] arm64/sysreg: Convert LORC_EL1 to automatic generation Date: Mon, 4 Jul 2022 18:02:59 +0100 Message-Id: <20220704170302.2609529-26-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 78e61eb25eff..261b42b88e9f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,7 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ec84a76fe66e..95fcad79b917 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -534,3 +534,10 @@ Sysreg LORN_EL1 3 0 10 4 2 Res0 63:8 Field 7:0 Num EndSysreg + +Sysreg LORC_EL1 3 0 10 4 3 +Res0 63:10 +Field 9:2 DS +Res0 1 +Field 0 EN +EndSysreg From patchwork Mon Jul 4 17:03:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1567C43334 for ; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 2 -- arch/arm64/tools/sysreg | 7 +++++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 261b42b88e9f..ee7ecba7f498 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -407,8 +407,6 @@ #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) -#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) - #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 95fcad79b917..13b8f85682af 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -541,3 +541,10 @@ Field 9:2 DS Res0 1 Field 0 EN EndSysreg + +Sysreg LORID_EL1 3 0 10 4 7 +Res0 63:24 +Field 23:16 LD +Res0 15:8 +Field 7:0 LR +EndSysreg From patchwork Mon Jul 4 17:03:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 12905726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45577C43334 for ; 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Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 18 ---------------- arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 18 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ee7ecba7f498..2e2b5811e081 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -193,7 +193,6 @@ #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) -#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) @@ -760,23 +759,6 @@ #define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 #define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 -/* id_aa64smfr0 */ -#define ID_AA64SMFR0_EL1_FA64_SHIFT 63 -#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52 -#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48 -#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36 -#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35 -#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34 -#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32 - -#define ID_AA64SMFR0_EL1_FA64_IMP 0x1 -#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf -#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1 -#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf -#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1 -#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1 -#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 #define ID_AA64MMFR0_FGT_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 13b8f85682af..b5c4251c6796 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -46,6 +46,43 @@ # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration # item ACCDATA) though it may be more taseful to do something else. +Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5 +Enum 63 FA64 + 0b0 NI + 0b1 IMP +EndEnum +Res0 62:60 +Field 59:56 SMEver +Enum 55:52 I16I64 + 0b0000 NI + 0b1111 IMP +EndEnum +Res0 51:49 +Enum 48 F64F64 + 0b0 NI + 0b1 IMP +EndEnum +Res0 47:40 +Enum 39:36 I8I32 + 0b0000 NI + 0b1111 IMP +EndEnum +Enum 35 F16F32 + 0b0 NI + 0b1 IMP +EndEnum +Enum 34 B16F32 + 0b0 NI + 0b1 IMP +EndEnum +Res0 33 +Enum 32 F32F32 + 0b0 NI + 0b1 IMP +EndEnum +Res0 31:0 +EndSysreg + Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0 Enum 63:60 RNDR 0b0000 NI From patchwork Mon Jul 4 17:03:02 2022 Content-Type: text/plain; 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Mon, 4 Jul 2022 17:04:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656954257; bh=kjy+ZCaM/Hljyp5fANCRsR61j7nqRGIjFcHy5o3bxtE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YxSfCDy2DwOxGlvYU6YeCDnXAOZ2DMV5weF4hLWhREsyeapsAFPrmAnO2BUDWeb4t rlyIscKNJFtBYl32mfUfnSgOUFIKcEDE4ica1wZR0W3P3J9TVFtMhyIwI67qy7HS7y 8eB30oSraYBRHpdCzObbOZlwl9MIfcjGkPMR3LGaljg4i167PiHTGWx6UjOOXUWvOe g2plpeTvGhy8r6pJ/u49wdUFBjlss2NkV3AQjfaazo596vgJFWSpfV/t+0oRxidSYf eKcgviUOjgGxuwNTiFy5/7oPpGdJzQMW+VvBOvze93oHHIWOchl2v7Y0ZN5WtHVkUo FqFj+VQjrLP3w== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Joey Gouly , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v7 28/28] arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation Date: Mon, 4 Jul 2022 18:03:02 +0100 Message-Id: <20220704170302.2609529-29-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220704170302.2609529-1-broonie@kernel.org> References: <20220704170302.2609529-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2877; h=from:subject; bh=kjy+ZCaM/Hljyp5fANCRsR61j7nqRGIjFcHy5o3bxtE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiwx1ElEhMpbTRFDtLX0r2Px4rmSnE6U0KXtjir8fM +8Ps//eJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYsMdRAAKCRAk1otyXVSH0Kx5B/ 0cCBFqdLt17tEIgUuXp8uTVWp8N7oInD8iZHJ27Y0p06W3SutwlpeEB/Q/hr2O+FEHbX5H8gFjV8Rx 0xREmk9Hg51+9KQzTCPbJIjLs6l7cM/5XhmvrFLZ+5yRSwDyyon1o/xbJyVNSsz8iO8VohnQUHNpTj M+DtWwrC0mClnNJW8j7pd7ghP60Uyi5hqcLAiFGxgxHm+w5DQMgMLh/9CywDQ6v1kgvI2M4oYzzMCM ohFQ8PUIZRg1+yyf49zwC9YT8BEweBdKXoWP47FlppGtj5NTMzyA7GCZUzu29X88D7+IJq3DroIAHu 4lg+RftQrXn7B3S2FG8y4pE6z4F3tP X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220704_100419_092074_2C693183 X-CRM114-Status: GOOD ( 11.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a, no functional changes. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 23 ----------------- arch/arm64/tools/sysreg | 46 +++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 23 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2e2b5811e081..d7f115368197 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -192,7 +192,6 @@ #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) -#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) @@ -737,28 +736,6 @@ #define ID_AA64PFR1_MTE 0x2 #define ID_AA64PFR1_MTE_ASYMM 0x3 -/* id_aa64zfr0 */ -#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56 -#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52 -#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44 -#define ID_AA64ZFR0_EL1_SM4_SHIFT 40 -#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32 -#define ID_AA64ZFR0_EL1_BF16_SHIFT 20 -#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16 -#define ID_AA64ZFR0_EL1_AES_SHIFT 4 -#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0 - -#define ID_AA64ZFR0_EL1_F64MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_F32MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_I8MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_BF16_IMP 0x1 -#define ID_AA64ZFR0_EL1_SM4_IMP 0x1 -#define ID_AA64ZFR0_EL1_SHA3_IMP 0x1 -#define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1 -#define ID_AA64ZFR0_EL1_AES_IMP 0x1 -#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 -#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 #define ID_AA64MMFR0_FGT_SHIFT 56 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b5c4251c6796..9ae483ec1e56 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -46,6 +46,52 @@ # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration # item ACCDATA) though it may be more taseful to do something else. +Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4 +Res0 63:60 +Enum 59:56 F64MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 55:52 F32MM + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 51:48 +Enum 47:44 I8MM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 43:40 SM4 + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 39:36 +Enum 35:32 SHA3 + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 31:24 +Enum 23:20 BF16 + 0b0000 NI + 0b0001 IMP + 0b0010 EBF16 +EndEnum +Enum 19:16 BitPerm + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 15:8 +Enum 7:4 AES + 0b0000 NI + 0b0001 IMP + 0b0010 PMULL128 +EndEnum +Enum 3:0 SVEver + 0b0000 IMP + 0b0001 SVE2 +EndEnum +EndSysreg + Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5 Enum 63 FA64 0b0 NI