From patchwork Mon Jul 4 19:51:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Delevoryas X-Patchwork-Id: 12905818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B452AC43334 for ; Mon, 4 Jul 2022 19:53:11 +0000 (UTC) Received: from localhost ([::1]:47752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o8S86-0004i4-PI for qemu-devel@archiver.kernel.org; Mon, 04 Jul 2022 15:53:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o8S6g-0002sC-Ss; Mon, 04 Jul 2022 15:51:42 -0400 Received: from new3-smtp.messagingengine.com ([66.111.4.229]:40647) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o8S6e-0000DE-Lr; Mon, 04 Jul 2022 15:51:42 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailnew.nyi.internal (Postfix) with ESMTP id 64FA65803AF; Mon, 4 Jul 2022 15:51:37 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Mon, 04 Jul 2022 15:51:37 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pjd.dev; h=cc:cc :content-transfer-encoding:date:date:from:from:in-reply-to :message-id:mime-version:reply-to:sender:subject:subject:to:to; s=fm1; t=1656964297; x=1656967897; bh=Sw6AnPb2jkpWNlAF4H6i19pM/ re/Qd9enb6AWeyfsnY=; b=qVPRIbVGUT2IRQoGGUbPESyLe9PpV6nvE6CShBpnf J+KyyMInnL9qri7qLlA/0C9+NyYInz2xf0WSsI6d+iLTem7kv7OoC4Tk7pE17966 tj8CzZlXu7nmp4OU8PGRDZkEaWg3A7ZS7VWCwJSFzDGys77bqSlFQJOsNWA+qzHI ejFw7Wsm3bkM7ifZJRI4/n+cKnFK/e89UxswpLXJSxfJh4wAefS6joImkiFwWuqQ d8UYc9PI0gfQLWVm7uPCZ4HvT/Zgd81AO0qnmOlwN3iDEiP37Mj3xr06ieUDTbMC BPvTnmxTerhyABiAmfmn5WCv6lGilApt4SiC24T6V5rpA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:message-id :mime-version:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=i9e814621.fm2; t=1656964297; x=1656967897; bh=Sw6AnPb2jkpWNlAF4H6i19pM/re/Qd9e nb6AWeyfsnY=; b=NwY4BSf/sFr8Nue7JjBTT20/KZZWKCQ4VxlG/bmAZ1tjuGY3 OQ4ChEfRgBz8rEOBdtLMsXLnId+lSb5v5vOCU9997tmrw/Wb0BxkPEjp2c17932a YozK2OCklGqJ+nAC0znwkjtzp6e7VVhdv5EgyRZomPf3YsxTeVjDdHqDVEPbfsng OhrGqgPSMH+zjA/bivZeDJnIP8OIAMsmhyfUywUwQZx+FM8/ViXDFHA6+UQFe8h/ iz9cjZNXmfhBdo/ufFMre1W+R3oGnZ07TA/DWvJD9PUv1zdcMs2gKr/RjtmOfBWT bd9HMI2qa6oYSNdXM8tihuvBoiZeTYfK+PDB9g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrudehledgudegfecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvfevufffkffoggfgsedtkeertdertddtnecuhfhrohhmpefrvghtvghr ucffvghlvghvohhrhigrshcuoehpvghtvghrsehpjhgurdguvghvqeenucggtffrrghtth gvrhhnpedvjeeghfekjeejiedtuddtvdeugeehheefleetffeugeejuddttefgvdegveei geenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehpvg htvghrsehpjhgurdguvghv X-ME-Proxy: Feedback-ID: i9e814621:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 4 Jul 2022 15:51:36 -0400 (EDT) From: Peter Delevoryas To: clg@kaod.org Cc: Peter Delevoryas , Peter Maydell , Andrew Jeffery , Joel Stanley , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/i2c/aspeed: Allow machines to set I2CBus Date: Mon, 4 Jul 2022 12:51:34 -0700 Message-Id: <20220704195135.10348-1-peter@pjd.dev> X-Mailer: git-send-email 2.37.0 MIME-Version: 1.0 Received-SPF: pass client-ip=66.111.4.229; envelope-from=peter@pjd.dev; helo=new3-smtp.messagingengine.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_FMBLA_NEWDOM=1.498, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" In a multi-SoC board, we want to allow machines to construct shared I2CBus's, so that we can have two SoC I2C controllers attached to a single I2CBus. We already expose read-only access, this just adds a method for setting and using an external I2CBus in the Aspeed I2C bus controller. One issue is that in order to use these methods, the machine needs to reach into the SoC and call these methods on the I2C controller, and we would prefer to keep the abstraction at the SoC level. If we create a set of "aspeed_soc_i2c_get_bus/set_bus" methods though, they will just be one-liners that don't do anything interesting. I would prefer to avoid that if possible, because that doesn't seem scalable if we need to do the same thing for all of the peripherals later. In addition, we are already reaching into the Aspeed SoC to access the flash controller to determine the boot rom size, so there is a precedent that we need to reach into SoC peripherals for data sometimes. Signed-off-by: Peter Delevoryas --- hw/i2c/aspeed_i2c.c | 16 +++++++++++++++- include/hw/i2c/aspeed_i2c.h | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 42c6d69b82..00bf58c7a3 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -1236,7 +1236,12 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - s->bus = i2c_init_bus(dev, name); + /* + * If a bus hasn't been provided to the controller, create one from scratch. + */ + if (!s->bus) { + s->bus = i2c_init_bus(dev, name); + } s->slave = i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE, 0xff); @@ -1420,3 +1425,12 @@ I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr) return bus; } + +void aspeed_i2c_set_bus(AspeedI2CState *s, int busnr, I2CBus *bus) +{ + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); + + if (busnr >= 0 && busnr < aic->num_busses) { + s->busses[busnr].bus = bus; + } +} diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 300a89b343..c60f8b291d 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -376,5 +376,6 @@ static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) } I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr); +void aspeed_i2c_set_bus(AspeedI2CState *s, int busnr, I2CBus *bus); #endif /* ASPEED_I2C_H */ From patchwork Mon Jul 4 19:51:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Delevoryas X-Patchwork-Id: 12905817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DEEFC433EF for ; Mon, 4 Jul 2022 19:53:11 +0000 (UTC) Received: from localhost ([::1]:47772 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o8S85-0004iZ-H8 for qemu-devel@archiver.kernel.org; Mon, 04 Jul 2022 15:53:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45374) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o8S6g-0002sJ-V8; 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Mon, 4 Jul 2022 15:51:38 -0400 (EDT) From: Peter Delevoryas To: clg@kaod.org Cc: Peter Delevoryas , Peter Maydell , Andrew Jeffery , Joel Stanley , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] fby35: Connect BMC to slot 0 BIC over I2C Date: Mon, 4 Jul 2022 12:51:35 -0700 Message-Id: <20220704195135.10348-2-peter@pjd.dev> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220704195135.10348-1-peter@pjd.dev> References: <20220704195135.10348-1-peter@pjd.dev> MIME-Version: 1.0 Received-SPF: pass client-ip=66.111.4.229; envelope-from=peter@pjd.dev; helo=new3-smtp.messagingengine.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_FMBLA_NEWDOM=1.498, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Peter Delevoryas --- hw/arm/fby35.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index 1972948318..88923d88eb 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -15,6 +15,7 @@ #include "hw/arm/aspeed_soc.h" #include "hw/arm/boot.h" #include "hw/arm/fby35.h" +#include "hw/i2c/i2c.h" #include "hw/i2c/i2c_mux_pca954x.h" #define TYPE_FBY35 MACHINE_TYPE_NAME("fby35") @@ -83,7 +84,6 @@ static void fby35_bmc_init(Fby35State *s) memory_region_init_ram(&s->bmc_dram, OBJECT(s), "bmc-dram", FBY35_BMC_RAM_SIZE, &error_abort); - object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3"); object_property_set_int(OBJECT(&s->bmc), "ram-size", FBY35_BMC_RAM_SIZE, &error_abort); object_property_set_link(OBJECT(&s->bmc), "memory", OBJECT(&s->bmc_memory), @@ -129,7 +129,6 @@ static void fby35_bic_init(Fby35State *s) memory_region_init(&s->bic_memory, OBJECT(s), "bic-memory", UINT64_MAX); - object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1"); qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk); object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory), &error_abort); @@ -167,20 +166,27 @@ void fby35_cl_bic_i2c_init(AspeedSoCState *s) for (int i = 0; i < 8; i++) { i2c_slave_create_simple(ssd[i], "tmp105", 0x6a); } - - /* - * FIXME: This should actually be the BMC, but both the ME and the BMC - * are IPMB endpoints, and the current ME implementation is generic - * enough to respond normally to some things. - */ - i2c_slave_create_simple(i2c[6], "intel-me", 0x10); } static void fby35_init(MachineState *machine) { Fby35State *s = FBY35(machine); + I2CBus *slot_i2c[4]; + + object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3"); + object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1"); fby35_bmc_init(s); + + for (int i = 0; i < ARRAY_SIZE(slot_i2c); i++) { + slot_i2c[i] = aspeed_i2c_get_bus(&s->bmc.i2c, i); + } + + /* + * There are 4 server board slots in fby35, and the first 4 I2C buses of the + * BMC are routed to each server board's BIC. + */ + aspeed_i2c_set_bus(&s->bic.i2c, 6, slot_i2c[0]); fby35_bic_init(s); }