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Wed, 6 Jul 2022 03:13:18 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Tue, 5 Jul 2022 20:13:18 -0700 Received: from buildserver-hdc-comms.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Tue, 5 Jul 2022 20:13:14 -0700 From: Bhadram Varka To: , , CC: , , , , , , , , , , Thierry Reding , Bhadram Varka Subject: [PATCH net-next v2 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Date: Wed, 6 Jul 2022 08:42:51 +0530 Message-ID: <20220706031259.53746-2-vbhadram@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220706031259.53746-1-vbhadram@nvidia.com> References: <20220706031259.53746-1-vbhadram@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6c2b7375-392d-4a92-bf41-08da5efd79fc X-MS-TrafficTypeDiagnostic: MWHPR12MB1773:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2022 03:13:19.1440 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c2b7375-392d-4a92-bf41-08da5efd79fc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1773 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Thierry Reding Add power domain IDs for the four MGBE power partitions found on Tegra234. Signed-off-by: Thierry Reding Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski --- include/dt-bindings/power/tegra234-powergate.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index f610eee9bce8..df1d4dd8dcf3 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -18,5 +18,6 @@ #define TEGRA234_POWER_DOMAIN_MGBEA 17U #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U +#define TEGRA234_POWER_DOMAIN_MGBED 20U #endif From patchwork Wed Jul 6 03:12:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 12907267 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74637CCA473 for ; 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Tue, 5 Jul 2022 20:13:18 -0700 From: Bhadram Varka To: , , CC: , , , , , , , , , , Thierry Reding , Bhadram Varka Subject: [PATCH net-next v2 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Date: Wed, 6 Jul 2022 08:42:52 +0530 Message-ID: <20220706031259.53746-3-vbhadram@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220706031259.53746-1-vbhadram@nvidia.com> References: <20220706031259.53746-1-vbhadram@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 34b7bf90-b70b-4c14-e853-08da5efd7c64 X-MS-TrafficTypeDiagnostic: MN2PR12MB2944:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +PpWpdO1uUIn96nztHBCqJw/2kGPxhHQzRNm1DmtA5BmXm0LxDRBFJFGW/zfn9qljuWhvHKwE77C9tdJD16xIUjm28pSBetWyAXryg3HHZIhWf/BTbS2KKgzyvskTaWvh5KgHpTgIz+JvMYi6plP6JtqMbXyGZyC4Z6BkeSjgrqnQeqQxDRFK3ciVK7/0CRqiW12b/tvdadp8GMdIbo62AEYQB80OCV7NG31X7/rNNqpYWhnBjJCM8GBzMizOcCZakBPcYcptMUyaPMKBx52G+hR5Ftgsl0kK5ok7OCe7NZAMsNCgu5Vzyqf0gzTD9aD7pUZC8J3q7d4f8bZMSKe9nbjOruUwcgb+bakRs+OM7kGFjYllLViiLf3W68fhWoCiIbbRQj9ABmy0jVrIruUSoLVUjM0AFuEa4UM18knMAh7HcaFIWz2YNUiEOs+YsJXZOw+po8N7ZeYisSYyG+FonV4YkdaF2oLpRr0G+nz1rf1TVd6T/gkmUZ9tXFyLMjjlwW1LwRRTtgPHRjps13+4EG0smB5nWR25KKtSQ8insH/lMRJK+teX2+IXoOGAAGqDqeEauYpimSDuR/158MC97RbnrK8YBniTjn7i7uqynZepfa2jpny3hrxLKf2tgu6J6Gir/BqekqKJ7H0cBIlPjzMzF6WFqFqeL79Docv0xQ8vAdDgzVn/u8398m30CjzXTiKMgSFcqL2UMe/FXYmY4nFWDdt69anmJD72CnsQ3iAG5ztpvv9HPakGcDw9X6WsT09hvnNJG2nTwaD8O5SlxZ6kXjF0Zge4YzZdL4tk3xoSScSgvpe9L06rBg9jJ6F+W0ZsnnOotNc/pCDBl3LDCZsMOJyWeNzApnlxDZFwaA= X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(396003)(136003)(376002)(346002)(39860400002)(36840700001)(46966006)(40470700004)(47076005)(26005)(336012)(426003)(70206006)(70586007)(83380400001)(41300700001)(2906002)(8676002)(4326008)(5660300002)(107886003)(7416002)(1076003)(8936002)(2616005)(478600001)(40460700003)(186003)(36860700001)(110136005)(54906003)(36756003)(356005)(81166007)(7696005)(40480700001)(316002)(6666004)(82310400005)(82740400003)(86362001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2022 03:13:23.1821 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34b7bf90-b70b-4c14-e853-08da5efd7c64 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB2944 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Thierry Reding Add the clocks and resets used by the MGBE Ethernet hardware found on Tegra234 SoCs. Signed-off-by: Thierry Reding Signed-off-by: Bhadram Varka --- include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++ 2 files changed, 109 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index bd4c3086a2da..bab85d9ba8cd 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -164,10 +164,111 @@ #define TEGRA234_CLK_PEX1_C5_CORE 225U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ #define TEGRA234_CLK_PLLC4 237U +/** @brief RX clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_INPUT 248U +/** @brief RX clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_INPUT 249U +/** @brief RX clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_INPUT 250U +/** @brief RX clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_INPUT 251U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief Monitored branch of MBGE0 RX input clock */ +#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U +/** @brief Monitored branch of MBGE1 RX input clock */ +#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U +/** @brief Monitored branch of MBGE2 RX input clock */ +#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U +/** @brief Monitored branch of MBGE3 RX input clock */ +#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U +/** @brief Monitored branch of MGBE0 RX PCS mux output */ +#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U +/** @brief Monitored branch of MGBE1 RX PCS mux output */ +#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U +/** @brief Monitored branch of MGBE2 RX PCS mux output */ +#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U +/** @brief Monitored branch of MGBE3 RX PCS mux output */ +#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U +/** @brief RX PCS clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U +/** @brief RX PCS clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U +/** @brief RX PCS clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U +/** @brief RX PCS clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U +/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE0_RX_PCS 373U +/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX 374U +/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX_PCS 375U +/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U +/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MAC 377U +/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MACSEC 378U +/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE0_EEE_PCS 379U +/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE0_APP 380U +/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_PTP_REF 381U +/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE1_RX_PCS 382U +/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX 383U +/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX_PCS 384U +/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U +/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE1_MAC 386U +/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE1_EEE_PCS 388U +/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE1_APP 389U +/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_PTP_REF 390U +/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE2_RX_PCS 391U +/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX 392U +/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX_PCS 393U +/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U +/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE2_MAC 395U +/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE2_EEE_PCS 397U +/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE2_APP 398U +/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_PTP_REF 399U +/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE3_RX_PCS 400U +/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX 401U +/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX_PCS 402U +/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U +/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MAC 404U +/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MACSEC 405U +/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE3_EEE_PCS 406U +/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE3_APP 407U +/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_PTP_REF 408U /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ #define TEGRA234_CLK_AZA_2XBIT 457U /** @brief aza_2xbitclk / 2 (aza_bitclk) */ #define TEGRA234_CLK_AZA_BIT 458U + #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 547ca3b60caa..55e397823a38 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -29,6 +29,12 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_MGBE0_PCS 45U +#define TEGRA234_RESET_MGBE0_MAC 46U +#define TEGRA234_RESET_MGBE1_PCS 49U +#define TEGRA234_RESET_MGBE1_MAC 50U +#define TEGRA234_RESET_MGBE2_PCS 53U +#define TEGRA234_RESET_MGBE2_MAC 54U #define TEGRA234_RESET_PEX2_CORE_10 56U #define TEGRA234_RESET_PEX2_CORE_10_APB 57U #define TEGRA234_RESET_PEX2_COMMON_APB 58U @@ -43,6 +49,8 @@ #define TEGRA234_RESET_QSPI0 76U #define TEGRA234_RESET_QSPI1 77U #define TEGRA234_RESET_SDMMC4 85U +#define TEGRA234_RESET_MGBE3_PCS 87U +#define TEGRA234_RESET_MGBE3_MAC 88U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U From patchwork Wed Jul 6 03:12:53 2022 Content-Type: text/plain; charset="utf-8" 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X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1709 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Thierry Reding Add the memory client and stream ID definitions for the MGBE hardware found on Tegra234 SoCs. Signed-off-by: Thierry Reding Signed-off-by: Bhadram Varka --- include/dt-bindings/memory/tegra234-mc.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index e3b0e9da295d..8b0ddcb715ff 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -11,11 +11,16 @@ /* NISO0 stream IDs */ #define TEGRA234_SID_APE 0x02 #define TEGRA234_SID_HDA 0x03 +#define TEGRA234_SID_GPCDMA 0x04 +#define TEGRA234_SID_MGBE 0x06 #define TEGRA234_SID_PCIE0 0x12 #define TEGRA234_SID_PCIE4 0x13 #define TEGRA234_SID_PCIE5 0x14 #define TEGRA234_SID_PCIE6 0x15 #define TEGRA234_SID_PCIE9 0x1f +#define TEGRA234_SID_MGBE_VF1 0x49 +#define TEGRA234_SID_MGBE_VF2 0x4a +#define TEGRA234_SID_MGBE_VF3 0x4b /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 @@ -61,8 +66,24 @@ #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 /* PCIE7r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 +/* MGBE0 read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 +/* MGBEB read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 +/* MGBEC read client */ +#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a +/* MGBED read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b +/* MGBE0 write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c +/* MGBEB write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f +/* MGBEC write client */ +#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* MGBED write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 /* sdmmcd memory write client */ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 /* BPMP read client */ From patchwork Wed Jul 6 03:12:54 2022 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2022 03:13:31.7505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f3ad275-6d1a-442d-f77a-08da5efd817d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5790 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Thierry Reding Tegra234 has multiple network interfaces with each their own memory clients and stream IDs to allow for proper isolation. Signed-off-by: Thierry Reding Signed-off-by: Bhadram Varka --- drivers/memory/tegra/tegra234.c | 80 +++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index e23ebd421f17..a9e8fd99730f 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -11,6 +11,76 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { { + .id = TEGRA234_MEMORY_CLIENT_MGBEARD, + .name = "mgbeard", + .sid = TEGRA234_SID_MGBE, + .regs = { + .sid = { + .override = 0x2c0, + .security = 0x2c4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEBRD, + .name = "mgbebrd", + .sid = TEGRA234_SID_MGBE_VF1, + .regs = { + .sid = { + .override = 0x2c8, + .security = 0x2cc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBECRD, + .name = "mgbecrd", + .sid = TEGRA234_SID_MGBE_VF2, + .regs = { + .sid = { + .override = 0x2d0, + .security = 0x2d4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEDRD, + .name = "mgbedrd", + .sid = TEGRA234_SID_MGBE_VF3, + .regs = { + .sid = { + .override = 0x2d8, + .security = 0x2dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEAWR, + .name = "mgbeawr", + .sid = TEGRA234_SID_MGBE, + .regs = { + .sid = { + .override = 0x2e0, + .security = 0x2e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEBWR, + .name = "mgbebwr", + .sid = TEGRA234_SID_MGBE_VF1, + .regs = { + .sid = { + .override = 0x2f8, + .security = 0x2fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBECWR, + .name = "mgbecwr", + .sid = TEGRA234_SID_MGBE_VF2, + .regs = { + .sid = { + .override = 0x308, + .security = 0x30c, + }, + }, + }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB, .name = "sdmmcrab", .sid = TEGRA234_SID_SDMMC4, @@ -20,6 +90,16 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x31c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEDWR, + .name = "mgbedwr", + .sid = TEGRA234_SID_MGBE_VF3, + .regs = { + .sid = { + .override = 0x328, + .security = 0x32c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB, .name = "sdmmcwab", From patchwork Wed Jul 6 03:12:55 2022 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2022 03:13:35.7147 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 072f0760-7c02-4a49-da3b-08da5efd83da X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2739 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add device-tree binding documentation for the Tegra234 MGBE ethernet controller. Signed-off-by: Jon Hunter Signed-off-by: Bhadram Varka --- .../bindings/net/nvidia,tegra234-mgbe.yaml | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml new file mode 100644 index 000000000000..1a45cd374b19 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra234 MGBE Device Tree Bindings + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + + compatible: + const: nvidia,tegra234-mgbe + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: hypervisor + - const: mac + - const: xpcs + + interrupts: + minItems: 1 + + interrupt-names: + items: + - const: common + + clocks: + minItems: 12 + maxItems: 12 + + clock-names: + minItems: 12 + maxItems: 12 + contains: + enum: + - mgbe + - mac + - mac-divider + - ptp-ref + - rx-input-m + - rx-input + - tx + - eee-pcs + - rx-pcs-input + - rx-pcs-m + - rx-pcs + - tx-pcs + + resets: + minItems: 2 + maxItems: 2 + + reset-names: + contains: + enum: + - mac + - pcs + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + power-domains: + items: + - description: MGBE power-domain + + phy-handle: true + + phy-mode: + contains: + enum: + - uxgmii + - 10gbase-kr + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + description: + Creates and registers an MDIO bus. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - phy-handle + - phy-mode + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + ethernet@6800000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06800000 0x10000>, + <0x06810000 0x10000>, + <0x068a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, + <&bpmp TEGRA234_CLK_MGBE0_MAC>, + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_TX>, + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, + <&bpmp TEGRA234_RESET_MGBE0_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; + + phy-handle = <&mgbe0_phy>; + phy-mode = "usxgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mgbe0_phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + + #phy-cells = <0>; + }; + }; + }; From patchwork Wed Jul 6 03:12:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 12907271 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35A03CCA47F for ; Wed, 6 Jul 2022 03:14:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230362AbiGFDOD (ORCPT ); Tue, 5 Jul 2022 23:14:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231705AbiGFDNs (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2022 03:13:39.8981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 807451ca-c598-484d-2dd0-08da5efd8659 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5066 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Thierry Reding Add MGBE IP DT nodes in SOC DT files. Signed-off-by: Thierry Reding Signed-off-by: Bhadram Varka --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 136 +++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index cb3af539e477..b77b55e80223 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -791,6 +791,142 @@ #mbox-cells = <2>; }; + ethernet@6800000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06800000 0x10000>, + <0x06810000 0x10000>, + <0x068a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, + <&bpmp TEGRA234_CLK_MGBE0_MAC>, + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_TX>, + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, + <&bpmp TEGRA234_RESET_MGBE0_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; + status = "disabled"; + }; + + ethernet@6900000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06900000 0x10000>, + <0x06910000 0x10000>, + <0x069a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, + <&bpmp TEGRA234_CLK_MGBE1_MAC>, + <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE1_TX>, + <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, + <&bpmp TEGRA234_RESET_MGBE1_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; + status = "disabled"; + }; + + ethernet@6a00000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06a00000 0x10000>, + <0x06a10000 0x10000>, + <0x06aa0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, + <&bpmp TEGRA234_CLK_MGBE2_MAC>, + <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE2_TX>, + <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, + <&bpmp TEGRA234_RESET_MGBE2_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; + status = "disabled"; + }; + + ethernet@6b00000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06b00000 0x10000>, + <0x06b10000 0x10000>, + <0x06ba0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, + <&bpmp TEGRA234_CLK_MGBE3_MAC>, + <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE3_TX>, + <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, + <&bpmp TEGRA234_RESET_MGBE3_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; + status = "disabled"; + }; + smmu_niso1: iommu@8000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; reg = <0x8000000 0x1000000>, From patchwork Wed Jul 6 03:12:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 12907272 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BF3AC43334 for ; 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Tue, 5 Jul 2022 20:13:39 -0700 From: Bhadram Varka To: , , CC: , , , , , , , , , , Thierry Reding , Bhadram Varka Subject: [PATCH net-next v2 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit Date: Wed, 6 Jul 2022 08:42:57 +0530 Message-ID: <20220706031259.53746-8-vbhadram@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220706031259.53746-1-vbhadram@nvidia.com> References: <20220706031259.53746-1-vbhadram@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b1ba74fa-3f17-491a-e8b1-08da5efd88e0 X-MS-TrafficTypeDiagnostic: BY5PR12MB3793:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FdRpOwgoxBFQj5qyzL/pAA9Jlue37RubMfSK4+xMSBo44BRJTl3edLGU7xuGGlaXlOcZNrrQdecusvbmyHLSGlk7PTV8Z1OGxuIGNudjcWPmpwzKDTdRUkkNboFZbibdJdZwaocrVQrI+y3grvhp9SNHnyDDdC4VDABYe061fVYAlTnKEDuecaalpPJrn7bjQOA1RLb+ZM6R5Fy3T9031qhQ1EyhIMto2pLg3/CBve1R86X0pQ3yj5KmLAedv5E4sUiXrVjvvrh/mxfXcdagsWT8jaAAt5mAuehZFaKS6T3TKBpHRC4H7NToxw/iQyCT0rJPbLP6iwq6A0qZlHI1VmXfXZDtsOcC0jFu8STTP/78YD6rmsVT+a+6bgko5Kw/3GON4erPZJVr9941pO0+nmo7NIB3fADdLO4deQCLWY3gNod/OtL2fqjdMZkvlMoah91lqEvrznpTpESYtT5M7JR2o6czRfv0oSloT62mmQGGKzf1r3cGUhxcUoSMf5F4s1B3ocCBsOrPbEF5pGbFNGPgx6iPYy/UsB8q17JmX6bJDWhuDZGTD4L3oFwlBNFD6hdmMWkzpkQnBsifdGOGsMAkQ4X8JOvZh2f1fhBxfpj4Xu6ftKxYTCCQ3J0gVSKG2bZhW9ZMU+8Qzx1JeDPeejnFUnObewu2xLym39m8M6eCBGnF64rfrfauBQ6om31nGyKBD1iAMVsHSr0eB/YqTewkJ5Jpeib2Lxk4QAccTuzzvVik3pH8OobZDL5/GcX+2PqY5k24Ih9AIuzVYm9+p7YjCIRXRBrwcKs+ubynsWgIEgaaoeVzFNydwl4Gdeese6oRbybU413wXw+871AcqjgySWLyCeIHR9yEyApsI5w= X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(136003)(346002)(396003)(376002)(39860400002)(40470700004)(46966006)(36840700001)(70586007)(70206006)(82740400003)(81166007)(41300700001)(6666004)(8676002)(7696005)(82310400005)(356005)(4326008)(36860700001)(186003)(107886003)(86362001)(1076003)(8936002)(36756003)(47076005)(426003)(336012)(40460700003)(5660300002)(2616005)(7416002)(316002)(2906002)(40480700001)(478600001)(26005)(110136005)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2022 03:13:44.1430 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1ba74fa-3f17-491a-e8b1-08da5efd88e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3793 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Thierry Reding Change enables MGBE on Jetson AGX Orin Developer Kit Signed-off-by: Thierry Reding Signed-off-by: Bhadram Varka --- .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index eaf1994abb04..8e2618a902ab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -1976,6 +1976,27 @@ stdout-path = "serial0:115200n8"; }; + bus@0 { + ethernet@6800000 { + status = "okay"; + + phy-handle = <&mgbe0_phy>; + phy-mode = "usxgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mgbe0_phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + + #phy-cells = <0>; + }; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; status = "okay"; From patchwork Wed Jul 6 03:12:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 12907273 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C0A2CCA483 for ; Wed, 6 Jul 2022 03:14:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231681AbiGFDOG (ORCPT ); Tue, 5 Jul 2022 23:14:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231688AbiGFDOB (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2022 03:13:47.9245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e26b6022-130e-42b8-eac2-08da5efd8b21 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0114 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Enable Tegra MGBE driver which found on T234 SoC's. Signed-off-by: Bhadram Varka --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7d1105343bc2..f80142abd9c6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -359,6 +359,7 @@ CONFIG_SMSC911X=y CONFIG_SNI_AVE=y CONFIG_SNI_NETSEC=y CONFIG_STMMAC_ETH=m +CONFIG_DWMAC_TEGRA=m CONFIG_TI_K3_AM65_CPSW_NUSS=y CONFIG_QCOM_IPA=m CONFIG_MESON_GXL_PHY=m From patchwork Wed Jul 6 03:12:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhadram Varka X-Patchwork-Id: 12907274 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47CC5C433EF for ; Wed, 6 Jul 2022 03:14:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231727AbiGFDOK (ORCPT ); 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Wed, 6 Jul 2022 03:13:51 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Tue, 5 Jul 2022 20:13:51 -0700 Received: from buildserver-hdc-comms.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.26 via Frontend Transport; Tue, 5 Jul 2022 20:13:47 -0700 From: Bhadram Varka To: , , CC: , , , , , , , , , , Bhadram Varka , Thierry Reding Subject: [PATCH net-next v2 9/9] stmmac: tegra: Add MGBE support Date: Wed, 6 Jul 2022 08:42:59 +0530 Message-ID: <20220706031259.53746-10-vbhadram@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220706031259.53746-1-vbhadram@nvidia.com> References: <20220706031259.53746-1-vbhadram@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6c26cec1-d5f4-42f5-0f6f-08da5efd8db6 X-MS-TrafficTypeDiagnostic: BN8PR12MB3444:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2022 03:13:52.2196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c26cec1-d5f4-42f5-0f6f-08da5efd8db6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3444 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add MGBE/XPCS IP support which founds on Tegra234 SoCs. Signed-off-by: Thierry Reding Signed-off-by: Bhadram Varka --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 6 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../net/ethernet/stmicro/stmmac/dwmac-tegra.c | 294 ++++++++++++++++++ 3 files changed, 301 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 31ff35174034..e9f61bdaf7c4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -235,6 +235,12 @@ config DWMAC_INTEL_PLAT the stmmac device driver. This driver is used for the Intel Keem Bay SoC. +config DWMAC_TEGRA + tristate "NVIDIA Tegra MGBE support" + depends on ARCH_TEGRA || COMPILE_TEST + help + Support for the MGBE controller found on Tegra SoCs. + config DWMAC_VISCONTI tristate "Toshiba Visconti DWMAC support" default ARCH_VISCONTI diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index d4e12e9ace4f..057e4bab5c08 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o +obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o stmmac-platform-objs:= stmmac_platform.o dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c new file mode 100644 index 000000000000..641b8773428a --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +static const char *const mgbe_clks[] = { + "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac" +}; + +struct tegra_mgbe { + struct device *dev; + + struct clk_bulk_data *clks; + + struct reset_control *rst_mac; + struct reset_control *rst_pcs; + + void __iomem *hv; + void __iomem *regs; + void __iomem *xpcs; + + struct mii_bus *mii; +}; + + +#define XPCS_WRAP_UPHY_RX_CONTROL 0x801c +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6)) +#define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0) +#define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020 +#define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0) +#define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2) +#define XPCS_WRAP_UPHY_STATUS 0x8044 +#define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0) +#define XPCS_WRAP_IRQ_STATUS 0x8050 +#define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6) + +#define XPCS_REG_ADDR_SHIFT 10 +#define XPCS_REG_ADDR_MASK 0x1fff +#define XPCS_ADDR 0x3fc + +#define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704 +#define MAC_SBD_INTR BIT(2) +#define MGBE_WRAP_AXI_ASID0_CTRL 0x8400 +#define MGBE_SID 0x6 + +static void mgbe_uphy_lane_bringup(struct tegra_mgbe *mgbe) +{ + unsigned int retry = 300; + u32 value; + int err; + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); + if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) { + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); + value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); + } + + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value, + (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0, + 500, 500 * 2000); + if (err < 0) { + dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n"); + } + + usleep_range(10000, 20000); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value, + (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0, + 1000, 1000 * 2000); + if (err < 0) { + dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n"); + } + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + while (--retry) { + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value, + value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS, + 500, 500 * 2000); + if (err < 0) { + dev_err(mgbe->dev, "timeout waiting for link to become ready\n"); + usleep_range(10000, 20000); + continue; + } + break; + } + + /* clear status */ + writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS); +} + +static int tegra_mgbe_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat; + struct stmmac_resources res; + struct tegra_mgbe *mgbe; + int irq, err, i; + + mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL); + if (!mgbe) + return -ENOMEM; + + mgbe->dev = &pdev->dev; + + memset(&res, 0, sizeof(res)); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor"); + if (IS_ERR(mgbe->hv)) + return PTR_ERR(mgbe->hv); + + mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac"); + if (IS_ERR(mgbe->regs)) + return PTR_ERR(mgbe->regs); + + mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs"); + if (IS_ERR(mgbe->xpcs)) + return PTR_ERR(mgbe->xpcs); + + res.addr = mgbe->regs; + res.irq = irq; + + mgbe->clks = devm_kzalloc(&pdev->dev, sizeof(*mgbe->clks), GFP_KERNEL); + if (!mgbe->clks) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(mgbe_clks); i++) + mgbe->clks[i].id = mgbe_clks[i]; + + err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks); + if (err < 0) + return err; + + err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); + if (err < 0) + return err; + + /* Perform MAC reset */ + mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac"); + if (IS_ERR(mgbe->rst_mac)) + return PTR_ERR(mgbe->rst_mac); + + err = reset_control_assert(mgbe->rst_mac); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + err = reset_control_deassert(mgbe->rst_mac); + if (err < 0) + return err; + + /* Perform PCS reset */ + mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs"); + if (IS_ERR(mgbe->rst_pcs)) + return PTR_ERR(mgbe->rst_pcs); + + err = reset_control_assert(mgbe->rst_pcs); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + err = reset_control_deassert(mgbe->rst_pcs); + if (err < 0) + return err; + + plat = stmmac_probe_config_dt(pdev, res.mac); + if (IS_ERR(plat)) + return PTR_ERR(plat); + + plat->has_xgmac = 1; + plat->tso_en = 1; + plat->pmt = 1; + plat->bsp_priv = mgbe; + + if (!plat->mdio_node) { + plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio"); + } + + if (!plat->mdio_bus_data) { + plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data), + GFP_KERNEL); + if (!plat->mdio_bus_data) { + err = -ENOMEM; + goto remove; + } + } + + plat->mdio_bus_data->needs_reset = true; + + mgbe_uphy_lane_bringup(mgbe); + + /* Tx FIFO Size - 128KB */ + plat->tx_fifo_size = 131072; + /* Rx FIFO Size - 192KB */ + plat->rx_fifo_size = 196608; + + /* Enable common interrupt at wrapper level */ + writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); + + /* Program SID */ + writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); + + err = stmmac_dvr_probe(&pdev->dev, plat, &res); + if (err < 0) + goto remove; + + return 0; + +remove: + stmmac_remove_config_dt(pdev, plat); + return err; +} + +static int tegra_mgbe_remove(struct platform_device *pdev) +{ + struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev); + + clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); + + stmmac_pltfr_remove(pdev); + + return 0; +} + +static const struct of_device_id tegra_mgbe_match[] = { + { .compatible = "nvidia,tegra234-mgbe", }, + { } +}; +MODULE_DEVICE_TABLE(of, tegra_mgbe_match); + +static struct platform_driver tegra_mgbe_driver = { + .probe = tegra_mgbe_probe, + .remove = tegra_mgbe_remove, + .driver = { + .name = "tegra-mgbe", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = tegra_mgbe_match, + }, +}; +module_platform_driver(tegra_mgbe_driver); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver"); +MODULE_LICENSE("GPL");