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[2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id bd16-20020a05600c1f1000b003a18ecfcd8csm18092287wmb.19.2022.07.06.14.33.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:02 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Date: Wed, 6 Jul 2022 23:32:47 +0200 Message-Id: <20220706213255.1473069-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Add power domain IDs for the four Multi-Gigabit Ethernet (MGBE) power partitions found on NVIDIA Tegra234. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/power/tegra234-powergate.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index f610eee9bce8..df1d4dd8dcf3 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -18,5 +18,6 @@ #define TEGRA234_POWER_DOMAIN_MGBEA 17U #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U +#define TEGRA234_POWER_DOMAIN_MGBED 20U #endif From patchwork Wed Jul 6 21:32:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12908660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0C43CCA481 for ; Wed, 6 Jul 2022 21:33:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234274AbiGFVdL (ORCPT ); Wed, 6 Jul 2022 17:33:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234229AbiGFVdI (ORCPT ); Wed, 6 Jul 2022 17:33:08 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75C6D27145; Wed, 6 Jul 2022 14:33:06 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id q9so23753828wrd.8; Wed, 06 Jul 2022 14:33:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hsb46ZR+iAjqJM/8jf9bwePKdQ+/VlInmNQnXhNixRE=; b=Wa3nZRhLF9IHRHbwDFrn1FWmzoVxEe86/4eIaRBlZPnYa5XrWxF/wPux8zCxjedEgX zH1luibjn/6XoZOXRkl5XC0whSxrvaFZo+JuwIICukmnAwDQZMfRlvkbc5doIjsm1ama 7h4KJmSIRyZSa9W9N7Xnbd2CNfrAHpxp6oNcSfEcxFv8p/lsX52mjKaMg/8jr/gtfbZN UF+j43kPXekINVTaVB/PdDGC19QKOMxxvT1gPSgcbGanJh4Ig+l1p1hm5YiwCfNWggO4 ZQOk+HJN9M1+QhScQ8xgJJJgjLia/EpxdF/7UG2PlrgNRUSlVB0TzmY0SL9mNNHdUB8f rGJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hsb46ZR+iAjqJM/8jf9bwePKdQ+/VlInmNQnXhNixRE=; b=qdB3Kx/V/blknejwRb405pNCJ0iIbDUS3DeLPstAm/vWoBzrapJtmS5PpW1wL5zqcR wO9cjQg/ddg+AK/qyy6YER/2uJsjfxlTDbtnvRRW7QTXH883tnfrdrPrzrBZHieGyg1v ChIt7VJAKqbJSSFIhpvsroWeKmrqaKQQuE2vD4Bqi7BHxOFQtQLMIvTdoGZaFIu6CTjs HfURNjjpCWCH9KXoKoEBl7zMjj1EOJMatlkhS6nPGiB+7VVv0F6rMN8127n7bgc2791I uN/wI8E59Rdf5cXUgTuAoTkxFlqeS/UNpFf24F9wWa+AJsm/nMTatsm+pv2TxDLDDmlE 3phA== X-Gm-Message-State: AJIora/FUStG3x28kxcQGgqo1qa3CWqdD7Jfg4g+Kdd7XX1fiYjK5e2K FtK4Io3Nyj+IrIHIgLtX64A= X-Google-Smtp-Source: AGRyM1vyW79xSHqhJZ9b3VpkkIdExBoC880cCzeYt+jyEemqyowpVRmIY5gtv1pfkD4tsrPnjWxvNw== X-Received: by 2002:adf:fcc6:0:b0:21d:8093:1b5c with SMTP id f6-20020adffcc6000000b0021d80931b5cmr2875478wrs.41.1657143184999; Wed, 06 Jul 2022 14:33:04 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id i30-20020a1c541e000000b003a032c88877sm23140851wmb.15.2022.07.06.14.33.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:03 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Date: Wed, 6 Jul 2022 23:32:48 +0200 Message-Id: <20220706213255.1473069-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Add the clocks and resets used by the Multi-Gigabit Ethernet (MGBE) hardware found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++ 2 files changed, 109 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 6fbe66063066..b8c64e0f120c 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -174,10 +174,111 @@ #define TEGRA234_CLK_PEX1_C5_CORE 225U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ #define TEGRA234_CLK_PLLC4 237U +/** @brief RX clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_INPUT 248U +/** @brief RX clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_INPUT 249U +/** @brief RX clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_INPUT 250U +/** @brief RX clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_INPUT 251U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief Monitored branch of MBGE0 RX input clock */ +#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U +/** @brief Monitored branch of MBGE1 RX input clock */ +#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U +/** @brief Monitored branch of MBGE2 RX input clock */ +#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U +/** @brief Monitored branch of MBGE3 RX input clock */ +#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U +/** @brief Monitored branch of MGBE0 RX PCS mux output */ +#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U +/** @brief Monitored branch of MGBE1 RX PCS mux output */ +#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U +/** @brief Monitored branch of MGBE2 RX PCS mux output */ +#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U +/** @brief Monitored branch of MGBE3 RX PCS mux output */ +#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U +/** @brief RX PCS clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U +/** @brief RX PCS clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U +/** @brief RX PCS clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U +/** @brief RX PCS clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U +/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE0_RX_PCS 373U +/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX 374U +/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX_PCS 375U +/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U +/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MAC 377U +/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MACSEC 378U +/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE0_EEE_PCS 379U +/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE0_APP 380U +/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_PTP_REF 381U +/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE1_RX_PCS 382U +/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX 383U +/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX_PCS 384U +/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U +/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE1_MAC 386U +/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE1_EEE_PCS 388U +/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE1_APP 389U +/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_PTP_REF 390U +/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE2_RX_PCS 391U +/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX 392U +/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX_PCS 393U +/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U +/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE2_MAC 395U +/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE2_EEE_PCS 397U +/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE2_APP 398U +/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_PTP_REF 399U +/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE3_RX_PCS 400U +/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX 401U +/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX_PCS 402U +/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U +/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MAC 404U +/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MACSEC 405U +/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE3_EEE_PCS 406U +/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE3_APP 407U +/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_PTP_REF 408U /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ #define TEGRA234_CLK_AZA_2XBIT 457U /** @brief aza_2xbitclk / 2 (aza_bitclk) */ #define TEGRA234_CLK_AZA_BIT 458U + #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 4f72ed1c2320..92c94ee1f13d 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -31,6 +31,12 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_MGBE0_PCS 45U +#define TEGRA234_RESET_MGBE0_MAC 46U +#define TEGRA234_RESET_MGBE1_PCS 49U +#define TEGRA234_RESET_MGBE1_MAC 50U +#define TEGRA234_RESET_MGBE2_PCS 53U +#define TEGRA234_RESET_MGBE2_MAC 54U #define TEGRA234_RESET_PEX2_CORE_10 56U #define TEGRA234_RESET_PEX2_CORE_10_APB 57U #define TEGRA234_RESET_PEX2_COMMON_APB 58U @@ -45,6 +51,8 @@ #define TEGRA234_RESET_QSPI0 76U #define TEGRA234_RESET_QSPI1 77U #define TEGRA234_RESET_SDMMC4 85U +#define TEGRA234_RESET_MGBE3_PCS 87U +#define TEGRA234_RESET_MGBE3_MAC 88U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U From patchwork Wed Jul 6 21:32:49 2022 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[2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id f190-20020a1c38c7000000b0039c5328ad92sm23605784wma.41.2022.07.06.14.33.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:05 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Date: Wed, 6 Jul 2022 23:32:49 +0200 Message-Id: <20220706213255.1473069-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Add the memory client and stream ID definitions for the Multi-Gigabit Ethernet (MGBE) hardware found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/memory/tegra234-mc.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 35491bacbc86..8c785c1937f2 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -12,11 +12,15 @@ #define TEGRA234_SID_APE 0x02 #define TEGRA234_SID_HDA 0x03 #define TEGRA234_SID_GPCDMA 0x04 +#define TEGRA234_SID_MGBE 0x06 #define TEGRA234_SID_PCIE0 0x12 #define TEGRA234_SID_PCIE4 0x13 #define TEGRA234_SID_PCIE5 0x14 #define TEGRA234_SID_PCIE6 0x15 #define TEGRA234_SID_PCIE9 0x1f +#define TEGRA234_SID_MGBE_VF1 0x49 +#define TEGRA234_SID_MGBE_VF2 0x4a +#define TEGRA234_SID_MGBE_VF3 0x4b /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 @@ -63,8 +67,24 @@ #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 /* PCIE7r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 +/* MGBE0 read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 +/* MGBEB read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 +/* MGBEC read client */ +#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a +/* MGBED read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b +/* MGBE0 write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c +/* MGBEB write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f +/* MGBEC write client */ +#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* MGBED write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 /* sdmmcd memory write client */ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 /* EQOS read client */ From patchwork Wed Jul 6 21:32:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12908662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 855A4C43334 for ; Wed, 6 Jul 2022 21:33:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234599AbiGFVdM (ORCPT ); Wed, 6 Jul 2022 17:33:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234582AbiGFVdL (ORCPT ); Wed, 6 Jul 2022 17:33:11 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BC7F2A955; Wed, 6 Jul 2022 14:33:10 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id v16so12315846wrd.13; Wed, 06 Jul 2022 14:33:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qksiefyWfPEtdDN03SulVwHSuSdTMWDrDcF6sRt+8P4=; b=RqlLDdLC93LTRiXfFHQbhDbjFT/UxkW4XCzvtb6YUDIbkKNLbXpYgYcF7QaHEMWPFB uE4rwaCgMtOaohoDN2ZyvISafWSVnilJT1nn9YUwGOnRR1ZEjWryC1g3MSZUcu+HAFUY fzRqzwEcF5sgaQ8z1WIarOcoFmWTeQ6bK7Uv+VzONtOM8K9os3mZ1EFwZmUw6mZS47mb JCIzSuAM7kaVLK4CVctKU/xoMR5K5I7bORTs3/Jv297bJ3z53fBFb2CYn1dBlX5btdN/ Yo+rLqIVObShwY+JBVEXneLi9OanD+MIr8PBzL0Y9//E9cevwB6JQoqsmrWbUv3Ct7CZ yKPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qksiefyWfPEtdDN03SulVwHSuSdTMWDrDcF6sRt+8P4=; b=HFNU11XnBjQzN/IirDCD2y3JkPC8tiv8XjJaW9DBSBPdGqyAQ9no2drDPdsyAXSeEE Dv3WppikjTTdWWD6AzHTMshdtxTT7tb5DzoTRxFMqCBbhBLCsoqL8BnKpxHZbFnrzmWD +LwXLxUueJ6crLcV5Hi/k6px54+hkOxQtgZ6w7xlgZhRHeBoleTcZK8Avw82qOD5fwVZ ra0XGS4cNObtGlVNTDqCmLCb+YEGCjml4uRzMoQDSZEJLKlteSsY7BFQoG5a6FMR4N5P +y9Q+0EtxGe+INvhZUiYtpmVbBMAKHMNtYnsXIfi2zrnIH1hHrKT6o4zRRUSYdvnrut9 ekeg== X-Gm-Message-State: AJIora+NsbfwcAzmaeDAdD1tTpfi5QlluIJgYUj4YzUwtGYwFxICy90j IaIvt2aNhseBYGXFwqeGS7o= X-Google-Smtp-Source: AGRyM1s6fbdaehrJ71MyjsBSmSmbm4MN9IXvDpm8OLuI5yQ9210DMQ0DXoTrc8chF5uUY28nEo+V7g== X-Received: by 2002:a5d:4d46:0:b0:21d:8196:6181 with SMTP id a6-20020a5d4d46000000b0021d81966181mr2190490wru.459.1657143188936; Wed, 06 Jul 2022 14:33:08 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id m17-20020adfe0d1000000b0021b866397a7sm37429688wri.1.2022.07.06.14.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:07 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 4/9] memory: tegra: Add MGBE memory clients for Tegra234 Date: Wed, 6 Jul 2022 23:32:50 +0200 Message-Id: <20220706213255.1473069-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding The NVIDIA Tegra234 SoC has multiple network interfaces with each their own memory clients and stream IDs to allow for proper isolation. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra234.c | 80 +++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 5244b3c560b0..c1018a50431e 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -11,6 +11,76 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { { + .id = TEGRA234_MEMORY_CLIENT_MGBEARD, + .name = "mgbeard", + .sid = TEGRA234_SID_MGBE, + .regs = { + .sid = { + .override = 0x2c0, + .security = 0x2c4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEBRD, + .name = "mgbebrd", + .sid = TEGRA234_SID_MGBE_VF1, + .regs = { + .sid = { + .override = 0x2c8, + .security = 0x2cc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBECRD, + .name = "mgbecrd", + .sid = TEGRA234_SID_MGBE_VF2, + .regs = { + .sid = { + .override = 0x2d0, + .security = 0x2d4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEDRD, + .name = "mgbedrd", + .sid = TEGRA234_SID_MGBE_VF3, + .regs = { + .sid = { + .override = 0x2d8, + .security = 0x2dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEAWR, + .name = "mgbeawr", + .sid = TEGRA234_SID_MGBE, + .regs = { + .sid = { + .override = 0x2e0, + .security = 0x2e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEBWR, + .name = "mgbebwr", + .sid = TEGRA234_SID_MGBE_VF1, + .regs = { + .sid = { + .override = 0x2f8, + .security = 0x2fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBECWR, + .name = "mgbecwr", + .sid = TEGRA234_SID_MGBE_VF2, + .regs = { + .sid = { + .override = 0x308, + .security = 0x30c, + }, + }, + }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB, .name = "sdmmcrab", .sid = TEGRA234_SID_SDMMC4, @@ -20,6 +90,16 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x31c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEDWR, + .name = "mgbedwr", + .sid = TEGRA234_SID_MGBE_VF3, + .regs = { + .sid = { + .override = 0x328, + .security = 0x32c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB, .name = "sdmmcwab", From patchwork Wed Jul 6 21:32:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12908684 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A574CCA482 for ; Wed, 6 Jul 2022 21:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234610AbiGFVdO (ORCPT ); Wed, 6 Jul 2022 17:33:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234240AbiGFVdM (ORCPT ); Wed, 6 Jul 2022 17:33:12 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E25E27145; Wed, 6 Jul 2022 14:33:10 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id q9so23754028wrd.8; Wed, 06 Jul 2022 14:33:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HVZSEC+VenCeIo/8yTgKOXSfNE5opDjFHGiQ9pUUIZQ=; b=I4pmdpKoYpzTo0R0cK3zBQTv7GMk/4JjvJX/Bb7G70Pe55svcXBfQZq0IdjGCiskV+ P0vZwx5cPexjitW+Q/8VvWOU5bhjJr45veMEq6CKbJEfePqNrDgTV4nArcAwQ/e50HU/ JkgzzQ3H+DmLFLbxpg3WIP4ZXMkB2YPswlb5tGJAnJHD3C2fKVx8YDR8uvTDy4G8e5lJ 3Df1EbJ9Luqo4LL/9q+aaHU8SDImw+drJ1Zt+KcZ8czRWWe5KTH+9oqhiMtSSM3J6+CO X6jWftEf3Mi2N7ni+hju2Ju1/lJYkSh7xcazJbarF6HP3ZJMzmAEl2Mv8qdqk2z9bBGT CjPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HVZSEC+VenCeIo/8yTgKOXSfNE5opDjFHGiQ9pUUIZQ=; b=Ytllck8HuLi2kXiHLxuVCwHZdN55jlMXUrc4WFfAHmTUrROZ4la0pw0JhrjSwJDJ86 CBnpoOMjD98NvgWk4+Cev6Kqy+nE6pVzVeA6dDV+s5dY6wF/KLBoAyVp3Hhbm9LD62VD wjg7+gSh7Ruba8JBK1V/Q2PKGQKs35t85RG3CpYzTmdgqqwhh8EH1bQjFEXHghvm7tzD TZeVcx/rPr49akFy/8KPXi7trGsDdxOnEVZX1BDEuj4t9QFbHuYTJPTqL27470zN/5BJ IWtQBFgl/A7nhynHk4czSSUMfO3hyDxjkrFbb5hyjsQq8qfu4xa9eCke7VEEvjC9gyUK Uudg== X-Gm-Message-State: AJIora/4T5QPksCSLyYUw1WCkRkOosYUeaHKcL+lIlQbJolZD1k9RXRk H/iOzMKHxuoY2akYwIvGiuo= X-Google-Smtp-Source: AGRyM1vubie3i/VEfKiH+iR/HW2Dc7ZjSUlOMm50+gV42c6qtc1hWOltqsrSGwR6eWjVTiJj8LklRQ== X-Received: by 2002:a05:6000:1152:b0:21d:7646:a976 with SMTP id d18-20020a056000115200b0021d7646a976mr9219831wrx.416.1657143190468; Wed, 06 Jul 2022 14:33:10 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id j18-20020a05600c191200b003973ea7e725sm30611255wmq.0.2022.07.06.14.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:09 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski Cc: Thierry Reding , Jon Hunter , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v3 5/9] dt-bindings: net: Add Tegra234 MGBE Date: Wed, 6 Jul 2022 23:32:51 +0200 Message-Id: <20220706213255.1473069-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Bhadram Varka Add device-tree binding documentation for the Multi-Gigabit Ethernet (MGBE) controller found on NVIDIA Tegra234 SoCs. Signed-off-by: Jon Hunter Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding --- Changes in v3: - add macsec and macsec-ns interrupt names - improve mdio bus node description - drop power-domains description - improve bindings title Changes in v2: - add supported PHY modes - change to dual license .../bindings/net/nvidia,tegra234-mgbe.yaml | 169 ++++++++++++++++++ 1 file changed, 169 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml new file mode 100644 index 000000000000..3d242ef1ca57 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra234 MGBE Multi-Gigabit Ethernet Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + + compatible: + const: nvidia,tegra234-mgbe + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: hypervisor + - const: mac + - const: xpcs + + interrupts: + minItems: 1 + + interrupt-names: + minItems: 1 + items: + - const: common + - const: macsec-ns + - const: macsec + + clocks: + minItems: 12 + maxItems: 12 + + clock-names: + minItems: 12 + maxItems: 12 + contains: + enum: + - mgbe + - mac + - mac-divider + - ptp-ref + - rx-input-m + - rx-input + - tx + - eee-pcs + - rx-pcs-input + - rx-pcs-m + - rx-pcs + - tx-pcs + + resets: + minItems: 2 + maxItems: 2 + + reset-names: + contains: + enum: + - mac + - pcs + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + phy-handle: true + + phy-mode: + contains: + enum: + - usxgmii + - 10gbase-kr + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + description: + Optional node for embedded MDIO controller. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - phy-handle + - phy-mode + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + ethernet@6800000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06800000 0x10000>, + <0x06810000 0x10000>, + <0x068a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, + <&bpmp TEGRA234_CLK_MGBE0_MAC>, + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_TX>, + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, + <&bpmp TEGRA234_RESET_MGBE0_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; + + phy-handle = <&mgbe0_phy>; + phy-mode = "usxgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mgbe0_phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + + #phy-cells = <0>; + }; + }; + }; From patchwork Wed Jul 6 21:32:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12908685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3900ACCA47C for ; Wed, 6 Jul 2022 21:33:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233304AbiGFVd0 (ORCPT ); Wed, 6 Jul 2022 17:33:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234621AbiGFVdQ (ORCPT ); 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[2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id z9-20020adff1c9000000b0021a34023ca3sm8801822wro.62.2022.07.06.14.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:11 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v3 6/9] arm64: tegra: Add MGBE nodes on Tegra234 Date: Wed, 6 Jul 2022 23:32:52 +0200 Message-Id: <20220706213255.1473069-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Add device tree nodes for the four instances of the Multi-Gigabit Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 136 +++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 5c1b74526645..c3c74ec67c94 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -884,6 +884,142 @@ hsp_top0: hsp@3c00000 { #mbox-cells = <2>; }; + ethernet@6800000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06800000 0x10000>, + <0x06810000 0x10000>, + <0x068a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, + <&bpmp TEGRA234_CLK_MGBE0_MAC>, + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_TX>, + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, + <&bpmp TEGRA234_RESET_MGBE0_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; + status = "disabled"; + }; + + ethernet@6900000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06900000 0x10000>, + <0x06910000 0x10000>, + <0x069a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, + <&bpmp TEGRA234_CLK_MGBE1_MAC>, + <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE1_TX>, + <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, + <&bpmp TEGRA234_RESET_MGBE1_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; + status = "disabled"; + }; + + ethernet@6a00000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06a00000 0x10000>, + <0x06a10000 0x10000>, + <0x06aa0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, + <&bpmp TEGRA234_CLK_MGBE2_MAC>, + <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE2_TX>, + <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, + <&bpmp TEGRA234_RESET_MGBE2_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; + status = "disabled"; + }; + + ethernet@6b00000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06b00000 0x10000>, + <0x06b10000 0x10000>, + <0x06ba0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, + <&bpmp TEGRA234_CLK_MGBE3_MAC>, + <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE3_TX>, + <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, + <&bpmp TEGRA234_RESET_MGBE3_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; + status = "disabled"; + }; + smmu_niso1: iommu@8000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; reg = <0x8000000 0x1000000>, From patchwork Wed Jul 6 21:32:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12908686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 463E9CCA480 for ; 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[2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id b10-20020a5d4d8a000000b0021d4aca9d1esm19192334wru.99.2022.07.06.14.33.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:13 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v3 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit Date: Wed, 6 Jul 2022 23:32:53 +0200 Message-Id: <20220706213255.1473069-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding A Multi-Gigabit Ethernet (MGBE) instance drives the primary Ethernet port on the Jetson AGX Orin Developer Kit. Enable it. Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding --- .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 02a10bb38562..d5e7c29837e6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2017,6 +2017,27 @@ chosen { stdout-path = "serial0:115200n8"; }; + bus@0 { + ethernet@6800000 { + status = "okay"; + + phy-handle = <&mgbe0_phy>; + phy-mode = "usxgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mgbe0_phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + + #phy-cells = <0>; + }; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; status = "okay"; From patchwork Wed Jul 6 21:32:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12908687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F7CDCCA481 for ; Wed, 6 Jul 2022 21:33:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234684AbiGFVdb (ORCPT ); Wed, 6 Jul 2022 17:33:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234651AbiGFVdZ (ORCPT ); Wed, 6 Jul 2022 17:33:25 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D88CC2AC49; Wed, 6 Jul 2022 14:33:18 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id l40-20020a05600c1d2800b003a18adff308so10045693wms.5; Wed, 06 Jul 2022 14:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=elqrnMpvZf1KqnOFoz03ru0nzodV+71XVzlmPZhkxsw=; b=FqDZqTpsyq/NGkm/qE3FD1nFhYTK3fltw8ZEYjotV+zeuMSMui65F7HgOCkyGZpdS5 OeMI4MWqqJPUci8LsbmtDsWtawFPTF6QnQI/MlZtJLoEhcpR+SG2uQVVx3BS+lkBanz0 UDA3pqIP8JedyC/VMolnRMpIQUTooN8NLZwWGpvFQ6tDSkKow5Tcg5TvLAaatNxZW1fq F91DEcdlsnQh3EvEfCgWsPcBAUSZ7Yk8UucgsB6PIGi0ja+BmW2kauKr1F1rrJf3DJyt JDa4AbT21v++aEShuNljFUdF/6zT429TgDgUUlsQus+w+HbTn8xRQ+/NYfnn+LwhiX0G r96A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=elqrnMpvZf1KqnOFoz03ru0nzodV+71XVzlmPZhkxsw=; b=BY6TOpEml4ooNKQopDruHT9Wiyn7mmkvNy/Mmd2Xu6xl8Jb1Ettv5NCYClPwJ4RYt8 wMqvQE32uuJL+XykwE0JUv1WZ7/BWle9AOBxpnsBlwjETluFXBFL/S5uyzonh+4Q9xh+ Wm5rNl07EVWgwzGQawU3RGXQDm3C7U2/HSJ1tCjW77JNIF7cRtgJjJG6rEGBsX1C4+eR uxEu/z0LyeS23BJiXbCwviawXSd7+PfKi9HrHZnBp7O5iyBdFcaSppZZ69Av5kzJGM9G oBxsDvVnrRpiWlZjwCSJrKTpXgtpC9SL9jsXMT93hXqFwW37BVykOMdb8GeziroDwdW1 uUHA== X-Gm-Message-State: AJIora+JkTnFFl7eVaiZEoMVNcjUNlC7WUVirvHLZHoxHCDVNpBDIf7R 2xbfpD3Z8YVviM/hFNLIHOk= X-Google-Smtp-Source: AGRyM1v8HTdFGDus7b4DUbF1Wa/G+H7c9/ZHh+9tYhqVlwe4JBlfhvB2lTxKuZDAOrZjPRL0W0stdA== X-Received: by 2002:a05:600c:1d95:b0:3a0:3cf1:5eb4 with SMTP id p21-20020a05600c1d9500b003a03cf15eb4mr659292wms.50.1657143198392; Wed, 06 Jul 2022 14:33:18 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id 22-20020a05600c029600b003a2b8461ddbsm6921788wmk.41.2022.07.06.14.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:17 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v3 8/9] arm64: defconfig: Enable Tegra MGBE driver Date: Wed, 6 Jul 2022 23:32:54 +0200 Message-Id: <20220706213255.1473069-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bhadram Varka Enable the driver for the Multi-Gigabit Ethernet (MGBE) controller which can be found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d2615b37d857..07e567f73076 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -360,6 +360,7 @@ CONFIG_SMSC911X=y CONFIG_SNI_AVE=y CONFIG_SNI_NETSEC=y CONFIG_STMMAC_ETH=m +CONFIG_DWMAC_TEGRA=m CONFIG_TI_K3_AM65_CPSW_NUSS=y CONFIG_QCOM_IPA=m CONFIG_MESON_GXL_PHY=m From patchwork Wed Jul 6 21:32:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12908688 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 244E6CCA480 for ; Wed, 6 Jul 2022 21:33:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234703AbiGFVdl (ORCPT ); Wed, 6 Jul 2022 17:33:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234670AbiGFVd0 (ORCPT ); Wed, 6 Jul 2022 17:33:26 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFEB62AE0E; Wed, 6 Jul 2022 14:33:20 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id j7so9550282wmp.2; Wed, 06 Jul 2022 14:33:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qKcHwD7mAVe9vw148b10Hk52k7+B0j3FvXtghoey17U=; b=aNjAub4g2oDQn9sBDND85pNJ8asLKlZJBeNtyLG61p1Gt9rgKqu43pEqHNWHWUfo8l DBRwuFFm/PAVG0spzRGuwJLABx+HTJoObi0JYhv0D8JMdhoS3VU4pOmR2xy4oAd68nah dZCkkj8fpYTBimAEIBFu2GiqMqRbB844uszFKhsahIttw8tNXzvwID4kYKjpb5cWUqAX l+uwr8B8kFdjqPr2ZtVIZARETFAuo415T6iCK5P/UGk3v3pSVNiYzp+GyLSSNVSURfyD rRQhJ4IGI7Hd14jv7hh5D40uzOtDLc3LOvn+2ub+GLxqIZK/16B8JOc2TWIbxnU73TeX LXxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qKcHwD7mAVe9vw148b10Hk52k7+B0j3FvXtghoey17U=; b=ANkKKT8l4qUrnGqlFt1oH5j7nTktPhCVGCN2TyYiuR//ufdY1MyH+9/CzTM63wd6jn 3y6jdefpwiVLh2XNVEmkq1x6XCw/e06BV8wbUhABuf5H6LbcwJBN3Aiah8i5c/WTGEjd osfL7BmEgAIhTyvuFr35nN6a9fldg86TBPcsdX7AMv3z5WuysHo15WVoFSiaJi9xbgQr Ya+4xmSebw2FO984dpZKfWDnGMCFgx2rAjcLYC41TP+sF1PJOj1hmK3iFHvcOdnu+EHm fsfv95+gMfnXKvD7oMXRzfayKzztHbcnzTcOaDGDKeae+WHbrhVicrkKceGLZk1H3z3j wHbA== X-Gm-Message-State: AJIora934rilMRUZ9JiqgbgYoDOO4gYbFvBHfDQKAMeugHvs7BsgcZ2x wp1zQL7LBY1CZx2SxuERPxw= X-Google-Smtp-Source: AGRyM1sPJ75icTuopJlekyV60dTNFcAK+qngl5FpdqhBL4KPs/HxD3Qjk/8a3pqz8AWgbN7gRIyQpQ== X-Received: by 2002:a05:600c:3593:b0:3a1:8909:b5b2 with SMTP id p19-20020a05600c359300b003a18909b5b2mr643800wmq.77.1657143199989; Wed, 06 Jul 2022 14:33:19 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id g14-20020a05600c4ece00b0039c99f61e5bsm26391573wmq.5.2022.07.06.14.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 14:33:19 -0700 (PDT) From: Thierry Reding To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Thierry Reding , Jon Hunter , Rob Herring , Krzysztof Kozlowski , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v3 9/9] stmmac: tegra: Add MGBE support Date: Wed, 6 Jul 2022 23:32:55 +0200 Message-Id: <20220706213255.1473069-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220706213255.1473069-1-thierry.reding@gmail.com> References: <20220706213255.1473069-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Bhadram Varka Add support for the Multi-Gigabit Ethernet (MGBE/XPCS) IP found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 6 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../net/ethernet/stmicro/stmmac/dwmac-tegra.c | 290 ++++++++++++++++++ 3 files changed, 297 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 31ff35174034..e9f61bdaf7c4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -235,6 +235,12 @@ config DWMAC_INTEL_PLAT the stmmac device driver. This driver is used for the Intel Keem Bay SoC. +config DWMAC_TEGRA + tristate "NVIDIA Tegra MGBE support" + depends on ARCH_TEGRA || COMPILE_TEST + help + Support for the MGBE controller found on Tegra SoCs. + config DWMAC_VISCONTI tristate "Toshiba Visconti DWMAC support" default ARCH_VISCONTI diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index d4e12e9ace4f..057e4bab5c08 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o +obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o stmmac-platform-objs:= stmmac_platform.o dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c new file mode 100644 index 000000000000..bb4b540820fa --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +static const char *const mgbe_clks[] = { + "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac" +}; + +struct tegra_mgbe { + struct device *dev; + + struct clk_bulk_data *clks; + + struct reset_control *rst_mac; + struct reset_control *rst_pcs; + + void __iomem *hv; + void __iomem *regs; + void __iomem *xpcs; + + struct mii_bus *mii; +}; + +#define XPCS_WRAP_UPHY_RX_CONTROL 0x801c +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6)) +#define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0) +#define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020 +#define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0) +#define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2) +#define XPCS_WRAP_UPHY_STATUS 0x8044 +#define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0) +#define XPCS_WRAP_IRQ_STATUS 0x8050 +#define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6) + +#define XPCS_REG_ADDR_SHIFT 10 +#define XPCS_REG_ADDR_MASK 0x1fff +#define XPCS_ADDR 0x3fc + +#define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704 +#define MAC_SBD_INTR BIT(2) +#define MGBE_WRAP_AXI_ASID0_CTRL 0x8400 +#define MGBE_SID 0x6 + +static void mgbe_uphy_lane_bringup(struct tegra_mgbe *mgbe) +{ + unsigned int retry = 300; + u32 value; + int err; + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); + if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) { + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); + value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); + } + + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value, + (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0, + 500, 500 * 2000); + if (err < 0) + dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n"); + + usleep_range(10000, 20000); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value, + (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0, + 1000, 1000 * 2000); + if (err < 0) + dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n"); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + while (--retry) { + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value, + value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS, + 500, 500 * 2000); + if (err < 0) { + dev_err(mgbe->dev, "timeout waiting for link to become ready\n"); + usleep_range(10000, 20000); + continue; + } + break; + } + + /* clear status */ + writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS); +} + +static int tegra_mgbe_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat; + struct stmmac_resources res; + struct tegra_mgbe *mgbe; + int irq, err, i; + + mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL); + if (!mgbe) + return -ENOMEM; + + mgbe->dev = &pdev->dev; + + memset(&res, 0, sizeof(res)); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor"); + if (IS_ERR(mgbe->hv)) + return PTR_ERR(mgbe->hv); + + mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac"); + if (IS_ERR(mgbe->regs)) + return PTR_ERR(mgbe->regs); + + mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs"); + if (IS_ERR(mgbe->xpcs)) + return PTR_ERR(mgbe->xpcs); + + res.addr = mgbe->regs; + res.irq = irq; + + mgbe->clks = devm_kzalloc(&pdev->dev, sizeof(*mgbe->clks), GFP_KERNEL); + if (!mgbe->clks) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(mgbe_clks); i++) + mgbe->clks[i].id = mgbe_clks[i]; + + err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks); + if (err < 0) + return err; + + err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); + if (err < 0) + return err; + + /* Perform MAC reset */ + mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac"); + if (IS_ERR(mgbe->rst_mac)) + return PTR_ERR(mgbe->rst_mac); + + err = reset_control_assert(mgbe->rst_mac); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + err = reset_control_deassert(mgbe->rst_mac); + if (err < 0) + return err; + + /* Perform PCS reset */ + mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs"); + if (IS_ERR(mgbe->rst_pcs)) + return PTR_ERR(mgbe->rst_pcs); + + err = reset_control_assert(mgbe->rst_pcs); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + err = reset_control_deassert(mgbe->rst_pcs); + if (err < 0) + return err; + + plat = stmmac_probe_config_dt(pdev, res.mac); + if (IS_ERR(plat)) + return PTR_ERR(plat); + + plat->has_xgmac = 1; + plat->tso_en = 1; + plat->pmt = 1; + plat->bsp_priv = mgbe; + + if (!plat->mdio_node) + plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio"); + + if (!plat->mdio_bus_data) { + plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data), + GFP_KERNEL); + if (!plat->mdio_bus_data) { + err = -ENOMEM; + goto remove; + } + } + + plat->mdio_bus_data->needs_reset = true; + + mgbe_uphy_lane_bringup(mgbe); + + /* Tx FIFO Size - 128KB */ + plat->tx_fifo_size = 131072; + /* Rx FIFO Size - 192KB */ + plat->rx_fifo_size = 196608; + + /* Enable common interrupt at wrapper level */ + writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); + + /* Program SID */ + writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); + + err = stmmac_dvr_probe(&pdev->dev, plat, &res); + if (err < 0) + goto remove; + + return 0; + +remove: + stmmac_remove_config_dt(pdev, plat); + return err; +} + +static int tegra_mgbe_remove(struct platform_device *pdev) +{ + struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev); + + clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); + + stmmac_pltfr_remove(pdev); + + return 0; +} + +static const struct of_device_id tegra_mgbe_match[] = { + { .compatible = "nvidia,tegra234-mgbe", }, + { } +}; +MODULE_DEVICE_TABLE(of, tegra_mgbe_match); + +static struct platform_driver tegra_mgbe_driver = { + .probe = tegra_mgbe_probe, + .remove = tegra_mgbe_remove, + .driver = { + .name = "tegra-mgbe", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = tegra_mgbe_match, + }, +}; +module_platform_driver(tegra_mgbe_driver); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver"); +MODULE_LICENSE("GPL");