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[2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id q13-20020adff50d000000b0021d64a11727sm12810726wro.49.2022.07.07.00.48.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 00:48:20 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Date: Thu, 7 Jul 2022 09:48:10 +0200 Message-Id: <20220707074818.1481776-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220707074818.1481776-1-thierry.reding@gmail.com> References: <20220707074818.1481776-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Add power domain IDs for the four Multi-Gigabit Ethernet (MGBE) power partitions found on NVIDIA Tegra234. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/power/tegra234-powergate.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index f610eee9bce8..df1d4dd8dcf3 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -18,5 +18,6 @@ #define TEGRA234_POWER_DOMAIN_MGBEA 17U #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U +#define TEGRA234_POWER_DOMAIN_MGBED 20U #endif From patchwork Thu Jul 7 07:48:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12909176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 515BFC43334 for ; Thu, 7 Jul 2022 07:48:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235053AbiGGHse (ORCPT ); Thu, 7 Jul 2022 03:48:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234526AbiGGHs2 (ORCPT ); Thu, 7 Jul 2022 03:48:28 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1973CC1A; Thu, 7 Jul 2022 00:48:25 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id o19-20020a05600c4fd300b003a0489f414cso10201084wmq.4; Thu, 07 Jul 2022 00:48:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vUNYuwH7o5jxQDGNnxUu6dXKQA1yYpc1eiHPJaWHPVs=; b=Pxt6QPh6HZEzwWfmoOOrPcDuK5pGWb7Ff5ZzLmmyNeZSwtG+NkLIsUwmlS8q/DNFti uc/999zQI70VDJfUL6DJ6+opX2oteLHEVsO+MCqrGUwOpW1UHoG27OXtay6DtKm8omY/ 7LTUZYGTbPoHieCEBdwQyIB6v50KPhyR6BscLHFmPV0fraXQPtWwqjPQvc0nejcRNzu+ /UAQZB85gWIW7jXTq9hlA6s0DPaaRfgbIdAtq5xFxmJhf3LNTQUIg8BO/0BfNBekDieY 6p/8lzQI3grDG6rTOQzl29IPO05QwnjhPyzSUOwinxQL75e0ElQE1BLu5Xpok6CR6VJ2 Zhfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vUNYuwH7o5jxQDGNnxUu6dXKQA1yYpc1eiHPJaWHPVs=; b=jvYJtR6uBxewEdFtrkvg0ozJ+TrFgh/bPMU5kZvW60SCd2dyZQruUzb8IH7FZ/o6+P Qx8DNiYwy3xfrv1qKGruUpb6WK2O5924sEhxFuoDXpvTRTPOJUuew9gptrjKik9cWR/Q Fa50bXcklT+6YWm72fOhRMo8t1RYo2XnJckHVqLdKhPc5EUeB/0NO+E2XjO6JMNbCHmv 1ueLyYItcJmVRWOPAa2uhiTxbgVRWoHNjkQ/ETygB94wz9oD0DtlbdAhKNkATgdu02X0 NnnomTC1np11hRxa47ElURKuJuQCRhSe47ds/VTTSJZFX3qRlWhKWAnRaWVgdwpDS9u+ zKyg== X-Gm-Message-State: AJIora9m+Wiv1px1IDTMsmAZChN4tIH6cTKI4xtkQJsQWRAp/Nny1gcg C36JJ4JWE6WQ4LV/kRq3AU8= X-Google-Smtp-Source: AGRyM1uaQCaaIKFe4Ez/4ZeIDKh+VI+unCvT3ptEiyBE4zTz/bXJ7W3C7AhgynAei4eNWnBv88d1FA== X-Received: by 2002:a05:600c:3d8f:b0:3a1:963d:202d with SMTP id bi15-20020a05600c3d8f00b003a1963d202dmr2844122wmb.11.1657180103523; Thu, 07 Jul 2022 00:48:23 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id q7-20020a05600000c700b0021d76985929sm5799526wrx.80.2022.07.07.00.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 00:48:22 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Date: Thu, 7 Jul 2022 09:48:11 +0200 Message-Id: <20220707074818.1481776-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220707074818.1481776-1-thierry.reding@gmail.com> References: <20220707074818.1481776-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Add the clocks and resets used by the Multi-Gigabit Ethernet (MGBE) hardware found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++ 2 files changed, 109 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index bd4c3086a2da..bab85d9ba8cd 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -164,10 +164,111 @@ #define TEGRA234_CLK_PEX1_C5_CORE 225U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ #define TEGRA234_CLK_PLLC4 237U +/** @brief RX clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_INPUT 248U +/** @brief RX clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_INPUT 249U +/** @brief RX clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_INPUT 250U +/** @brief RX clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_INPUT 251U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief Monitored branch of MBGE0 RX input clock */ +#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U +/** @brief Monitored branch of MBGE1 RX input clock */ +#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U +/** @brief Monitored branch of MBGE2 RX input clock */ +#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U +/** @brief Monitored branch of MBGE3 RX input clock */ +#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U +/** @brief Monitored branch of MGBE0 RX PCS mux output */ +#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U +/** @brief Monitored branch of MGBE1 RX PCS mux output */ +#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U +/** @brief Monitored branch of MGBE2 RX PCS mux output */ +#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U +/** @brief Monitored branch of MGBE3 RX PCS mux output */ +#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U +/** @brief RX PCS clock recovered from MGBE0 lane input */ +#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U +/** @brief RX PCS clock recovered from MGBE1 lane input */ +#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U +/** @brief RX PCS clock recovered from MGBE2 lane input */ +#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U +/** @brief RX PCS clock recovered from MGBE3 lane input */ +#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U +/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE0_RX_PCS 373U +/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX 374U +/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_TX_PCS 375U +/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U +/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MAC 377U +/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE0_MACSEC 378U +/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE0_EEE_PCS 379U +/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE0_APP 380U +/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE0_PTP_REF 381U +/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE1_RX_PCS 382U +/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX 383U +/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_TX_PCS 384U +/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U +/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE1_MAC 386U +/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE1_EEE_PCS 388U +/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE1_APP 389U +/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE1_PTP_REF 390U +/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE2_RX_PCS 391U +/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX 392U +/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_TX_PCS 393U +/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U +/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE2_MAC 395U +/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE2_EEE_PCS 397U +/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE2_APP 398U +/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE2_PTP_REF 399U +/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ +#define TEGRA234_CLK_MGBE3_RX_PCS 400U +/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX 401U +/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_TX_PCS 402U +/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ +#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U +/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MAC 404U +/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ +#define TEGRA234_CLK_MGBE3_MACSEC 405U +/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ +#define TEGRA234_CLK_MGBE3_EEE_PCS 406U +/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ +#define TEGRA234_CLK_MGBE3_APP 407U +/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ +#define TEGRA234_CLK_MGBE3_PTP_REF 408U /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ #define TEGRA234_CLK_AZA_2XBIT 457U /** @brief aza_2xbitclk / 2 (aza_bitclk) */ #define TEGRA234_CLK_AZA_BIT 458U + #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 547ca3b60caa..55e397823a38 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -29,6 +29,12 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_MGBE0_PCS 45U +#define TEGRA234_RESET_MGBE0_MAC 46U +#define TEGRA234_RESET_MGBE1_PCS 49U +#define TEGRA234_RESET_MGBE1_MAC 50U +#define TEGRA234_RESET_MGBE2_PCS 53U +#define TEGRA234_RESET_MGBE2_MAC 54U #define TEGRA234_RESET_PEX2_CORE_10 56U #define TEGRA234_RESET_PEX2_CORE_10_APB 57U #define TEGRA234_RESET_PEX2_COMMON_APB 58U @@ -43,6 +49,8 @@ #define TEGRA234_RESET_QSPI0 76U #define TEGRA234_RESET_QSPI1 77U #define TEGRA234_RESET_SDMMC4 85U +#define TEGRA234_RESET_MGBE3_PCS 87U +#define TEGRA234_RESET_MGBE3_MAC 88U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U From patchwork Thu Jul 7 07:48:12 2022 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[2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id v6-20020a05600c12c600b0039c811077d3sm27138383wmd.22.2022.07.07.00.48.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 00:48:24 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Date: Thu, 7 Jul 2022 09:48:12 +0200 Message-Id: <20220707074818.1481776-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220707074818.1481776-1-thierry.reding@gmail.com> References: <20220707074818.1481776-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Add the memory client and stream ID definitions for the Multi-Gigabit Ethernet (MGBE) hardware found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/memory/tegra234-mc.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index e3b0e9da295d..c202e7642bbd 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -11,11 +11,15 @@ /* NISO0 stream IDs */ #define TEGRA234_SID_APE 0x02 #define TEGRA234_SID_HDA 0x03 +#define TEGRA234_SID_MGBE 0x06 #define TEGRA234_SID_PCIE0 0x12 #define TEGRA234_SID_PCIE4 0x13 #define TEGRA234_SID_PCIE5 0x14 #define TEGRA234_SID_PCIE6 0x15 #define TEGRA234_SID_PCIE9 0x1f +#define TEGRA234_SID_MGBE_VF1 0x49 +#define TEGRA234_SID_MGBE_VF2 0x4a +#define TEGRA234_SID_MGBE_VF3 0x4b /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 @@ -61,8 +65,24 @@ #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 /* PCIE7r1 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 +/* MGBE0 read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 +/* MGBEB read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 +/* MGBEC read client */ +#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a +/* MGBED read client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b +/* MGBE0 write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c +/* MGBEB write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f +/* MGBEC write client */ +#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* MGBED write client */ +#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 /* sdmmcd memory write client */ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 /* BPMP read client */ From patchwork Thu Jul 7 07:48:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12909178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44FE5C43334 for ; Thu, 7 Jul 2022 07:48:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235089AbiGGHsj (ORCPT ); Thu, 7 Jul 2022 03:48:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234396AbiGGHsa (ORCPT ); Thu, 7 Jul 2022 03:48:30 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DA2655B7; Thu, 7 Jul 2022 00:48:28 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id m6-20020a05600c3b0600b003a0489f412cso478899wms.1; Thu, 07 Jul 2022 00:48:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4NIkOiNcygsNIrF/pyEHDspUdUt7dpZ9CM2vTRfSAbQ=; b=dLMK60dvjcHyh9HyrCfa2Guijrm/7jGoI7iccHPjJCmhyGTNJfDKYVvKtihBTU8EVO Q0Jibmd3sXJh0FdMqUmjA5EIXpW7+p/9DRDyEQDiN8BxNztRHmvXmHb//B6PNDj4fSas EyvhG9oEO6Wu/bSEkQ0l83Yv5wMclZcKXJHPeRg9phUq9g8KeOZYoWE0x2A5EsMbwU1c oK0qjlOTuSsuanVCtDcgOVCpi++P+seE5d3cC8iut8MmWeXReX4bjKYhLo9+CBH/5LXm 6NKoE5H9aH5XlPm7nWPJ5OHjczp6r2v17AXxakV3vGgo1JLht943mpzEGNjMLjf7qLbS fpzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4NIkOiNcygsNIrF/pyEHDspUdUt7dpZ9CM2vTRfSAbQ=; b=JughoW6vwhESmBJ+4xDYIDU2xhtHl66X2iGxQobh6iXASRCe/JvvSZGEk1LzUam3M9 FP+n6uthEQUpv42R2/rv8Ep+GKdEYQYsadzpmG/L+uFfYA6/Pt/+gRBAeF9Qbfz/wpNf BAz+ATkJNgbysGZkEszzFH0XdcfMragOWtzhIu2bJpRUlCy9+eOHa/NClExb++gbqv6m NPfUMmea0cOmY+GICwKHEcNBDXaKo58Vketpxvfu3Y/D4RClW/qC+OcXY7M99V3IXvpe AO/ovHGVOCPuwIeL4Bz1phwrT/D+o2LFfkrWWC3cqYgLaDXbvWDHaWme3fZg1t/WTYpb v2bg== X-Gm-Message-State: AJIora8Y9YmOJmH3H439oFXTaNWx6xBswLW3IZ2W2l1nhDXR9RaKQ1BT p/Kjpi3+TMU8qn5td1EMo30= X-Google-Smtp-Source: AGRyM1uhtdRQ+r4IHNVsWwDSYNbKSIMbPcT+PRLqMYA9WCY5uGoZzLPbemQWeCvxSD1Cl4TyZhbJeg== X-Received: by 2002:a05:600c:4e90:b0:3a0:57d6:4458 with SMTP id f16-20020a05600c4e9000b003a057d64458mr2921012wmq.198.1657180106883; Thu, 07 Jul 2022 00:48:26 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id e29-20020a5d595d000000b0021bc663ed67sm32555416wri.56.2022.07.07.00.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 00:48:26 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 4/9] memory: tegra: Add MGBE memory clients for Tegra234 Date: Thu, 7 Jul 2022 09:48:13 +0200 Message-Id: <20220707074818.1481776-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220707074818.1481776-1-thierry.reding@gmail.com> References: <20220707074818.1481776-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding The NVIDIA Tegra234 SoC has multiple network interfaces with each their own memory clients and stream IDs to allow for proper isolation. Signed-off-by: Bhadram Varka Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra234.c | 80 +++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index e23ebd421f17..a9e8fd99730f 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -11,6 +11,76 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { { + .id = TEGRA234_MEMORY_CLIENT_MGBEARD, + .name = "mgbeard", + .sid = TEGRA234_SID_MGBE, + .regs = { + .sid = { + .override = 0x2c0, + .security = 0x2c4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEBRD, + .name = "mgbebrd", + .sid = TEGRA234_SID_MGBE_VF1, + .regs = { + .sid = { + .override = 0x2c8, + .security = 0x2cc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBECRD, + .name = "mgbecrd", + .sid = TEGRA234_SID_MGBE_VF2, + .regs = { + .sid = { + .override = 0x2d0, + .security = 0x2d4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEDRD, + .name = "mgbedrd", + .sid = TEGRA234_SID_MGBE_VF3, + .regs = { + .sid = { + .override = 0x2d8, + .security = 0x2dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEAWR, + .name = "mgbeawr", + .sid = TEGRA234_SID_MGBE, + .regs = { + .sid = { + .override = 0x2e0, + .security = 0x2e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEBWR, + .name = "mgbebwr", + .sid = TEGRA234_SID_MGBE_VF1, + .regs = { + .sid = { + .override = 0x2f8, + .security = 0x2fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBECWR, + .name = "mgbecwr", + .sid = TEGRA234_SID_MGBE_VF2, + .regs = { + .sid = { + .override = 0x308, + .security = 0x30c, + }, + }, + }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB, .name = "sdmmcrab", .sid = TEGRA234_SID_SDMMC4, @@ -20,6 +90,16 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x31c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_MGBEDWR, + .name = "mgbedwr", + .sid = TEGRA234_SID_MGBE_VF3, + .regs = { + .sid = { + .override = 0x328, + .security = 0x32c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB, .name = "sdmmcwab", From patchwork Thu Jul 7 07:48:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12909179 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F15B7CCA481 for ; Thu, 7 Jul 2022 07:48:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234954AbiGGHsm (ORCPT ); Thu, 7 Jul 2022 03:48:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234941AbiGGHsb (ORCPT ); Thu, 7 Jul 2022 03:48:31 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDFACB45; Thu, 7 Jul 2022 00:48:29 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id a5so10395878wrx.12; Thu, 07 Jul 2022 00:48:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CPihCLn8/rDeZJoQSL1EemIx5OmDQP/lB4w5aYX64BY=; b=X0s61VdsrYiS2FHMbVU+aMNvAqAnfHRttgQwkeB0j9jMwWPfgQQIYFGg5w/2dyAade fXmZ6MTsCAPWYP9lShHhVAheOTvc60bqpPb6301Aec6R1EMZEFCQ7JwiP7+tV2bDFvyj qfDwa2CkEDSA7BsBBbC8jcnUWD9SC6XF29v+XLoYGI/6osvz0KNs9pvPJgH/qUkKGyUz 1sKtahyTkJBkb8zOwPblW76uoKyx6s2SwPdLpNVaGwyjHWW5Gt+shkfv0WRTQYJMn1rp sujlKxL8xLtfdkORoBMcZXJMGg0s7HNoNtb9HObMFNFxxezOM7qxWFj3z+lt8hMVwW8O vrSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CPihCLn8/rDeZJoQSL1EemIx5OmDQP/lB4w5aYX64BY=; b=5n6oss9OKUzmU4tt6f7JPvzcHnTZxi+dyNBJEwuE+hul8DU9Wl80YCUB9bbbxVwpCD 2qbEDv1+9nDy0YgtXF40kkI15yWyPElWJGpqzHKjXtmTsbYlkHIg6L2X9UDIDsxGQDhu KzjsE87CR4RtSCbBsHW6E7chmWQKFp0nLgFb0fqO9hgCuBx6ZokPRMnFKFPlSyljFYcS E9hndSeNHhK+Fnr+V8gty7CaGHWbrvxzyYNcHMNX0ARn7MOBok0fu31C6OMx+GdoLQ7/ KYSUN8Jmy44AazQi+wbCfcogaheyuMB3+yJZ6QdTYO9ASzc2AbEioiwsXXzA5TsqW9kE Qd6w== X-Gm-Message-State: AJIora/7PMYSFKxbaRTGWnGVRNNTn8JI51K7kJ/5McIiWEWFG63oV86m 3iE5YhXuw+iPpHESY8E9AB1Bm9bhSjw= X-Google-Smtp-Source: AGRyM1tm8/xRBoGDWDTBaheP5Ue8MeTDAzM1KZtphSY53e0XvFRjEM+1q0mUnIt9/Wd6a4xeSSxwVA== X-Received: by 2002:a05:6000:1549:b0:21b:c7fb:9dd0 with SMTP id 9-20020a056000154900b0021bc7fb9dd0mr39226823wry.446.1657180108273; Thu, 07 Jul 2022 00:48:28 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id i13-20020a0560001acd00b0021d78b570dfsm6266444wry.108.2022.07.07.00.48.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 00:48:27 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski Cc: Thierry Reding , Jon Hunter , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v4 5/9] dt-bindings: net: Add Tegra234 MGBE Date: Thu, 7 Jul 2022 09:48:14 +0200 Message-Id: <20220707074818.1481776-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220707074818.1481776-1-thierry.reding@gmail.com> References: <20220707074818.1481776-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Bhadram Varka Add device-tree binding documentation for the Multi-Gigabit Ethernet (MGBE) controller found on NVIDIA Tegra234 SoCs. Signed-off-by: Jon Hunter Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- Changes in v4: - uses fixed lists of items for clock-names and reset-names - add missing maxItems to interrupts property - drop minItems where it equals maxItems - drop unnecessary blank lines - drop redundant comment Changes in v3: - add macsec and macsec-ns interrupt names - improve mdio bus node description - drop power-domains description - improve bindings title Changes in v2: - add supported PHY modes - change to dual license .../bindings/net/nvidia,tegra234-mgbe.yaml | 162 ++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml new file mode 100644 index 000000000000..2bd3efff2485 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra234 MGBE Multi-Gigabit Ethernet Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra234-mgbe + + reg: + maxItems: 3 + + reg-names: + items: + - const: hypervisor + - const: mac + - const: xpcs + + interrupts: + minItems: 1 + maxItems: 3 + + interrupt-names: + minItems: 1 + items: + - const: common + - const: macsec-ns + - const: macsec + + clocks: + maxItems: 12 + + clock-names: + items: + - const: mgbe + - const: mac + - const: mac-divider + - const: ptp-ref + - const: rx-input-m + - const: rx-input + - const: tx + - const: eee-pcs + - const: rx-pcs-input + - const: rx-pcs-m + - const: rx-pcs + - const: tx-pcs + + resets: + maxItems: 2 + + reset-names: + items: + - const: mac + - const: pcs + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem + - const: write + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + phy-handle: true + + phy-mode: + contains: + enum: + - usxgmii + - 10gbase-kr + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + description: + Optional node for embedded MDIO controller. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - phy-handle + - phy-mode + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + ethernet@6800000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06800000 0x10000>, + <0x06810000 0x10000>, + <0x068a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, + <&bpmp TEGRA234_CLK_MGBE0_MAC>, + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_TX>, + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, + <&bpmp TEGRA234_RESET_MGBE0_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; + + phy-handle = <&mgbe0_phy>; + phy-mode = "usxgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mgbe0_phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + + #phy-cells = <0>; + }; + }; + }; From patchwork Thu Jul 7 07:48:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12909180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8506C43334 for ; Thu, 7 Jul 2022 07:48:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235113AbiGGHsu (ORCPT ); Thu, 7 Jul 2022 03:48:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235029AbiGGHsc (ORCPT ); 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[2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id s12-20020a05600c384c00b003a2c7bf0497sm1872879wmr.16.2022.07.07.00.48.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 00:48:29 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v4 6/9] arm64: tegra: Add MGBE nodes on Tegra234 Date: Thu, 7 Jul 2022 09:48:15 +0200 Message-Id: <20220707074818.1481776-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220707074818.1481776-1-thierry.reding@gmail.com> References: <20220707074818.1481776-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding Add device tree nodes for the four instances of the Multi-Gigabit Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 136 +++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index cb3af539e477..b77b55e80223 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -791,6 +791,142 @@ hsp_top0: hsp@3c00000 { #mbox-cells = <2>; }; + ethernet@6800000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06800000 0x10000>, + <0x06810000 0x10000>, + <0x068a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, + <&bpmp TEGRA234_CLK_MGBE0_MAC>, + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_TX>, + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, + <&bpmp TEGRA234_RESET_MGBE0_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; + status = "disabled"; + }; + + ethernet@6900000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06900000 0x10000>, + <0x06910000 0x10000>, + <0x069a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, + <&bpmp TEGRA234_CLK_MGBE1_MAC>, + <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE1_TX>, + <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, + <&bpmp TEGRA234_RESET_MGBE1_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; + status = "disabled"; + }; + + ethernet@6a00000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06a00000 0x10000>, + <0x06a10000 0x10000>, + <0x06aa0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, + <&bpmp TEGRA234_CLK_MGBE2_MAC>, + <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE2_TX>, + <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, + <&bpmp TEGRA234_RESET_MGBE2_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; + status = "disabled"; + }; + + ethernet@6b00000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06b00000 0x10000>, + <0x06b10000 0x10000>, + <0x06ba0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = ; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, + <&bpmp TEGRA234_CLK_MGBE3_MAC>, + <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE3_TX>, + <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, + <&bpmp TEGRA234_RESET_MGBE3_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; + status = "disabled"; + }; + smmu_niso1: iommu@8000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; reg = <0x8000000 0x1000000>, From patchwork Thu Jul 7 07:48:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12909182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7177CCA481 for ; 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[2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id n27-20020a05600c3b9b00b003a04e900552sm1972536wms.1.2022.07.07.00.48.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 00:48:30 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v4 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit Date: Thu, 7 Jul 2022 09:48:16 +0200 Message-Id: <20220707074818.1481776-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220707074818.1481776-1-thierry.reding@gmail.com> References: <20220707074818.1481776-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Thierry Reding A Multi-Gigabit Ethernet (MGBE) instance drives the primary Ethernet port on the Jetson AGX Orin Developer Kit. Enable it. Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding --- .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index eaf1994abb04..8e2618a902ab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -1976,6 +1976,27 @@ chosen { stdout-path = "serial0:115200n8"; }; + bus@0 { + ethernet@6800000 { + status = "okay"; + + phy-handle = <&mgbe0_phy>; + phy-mode = "usxgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mgbe0_phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + + #phy-cells = <0>; + }; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; status = "okay"; From patchwork Thu Jul 7 07:48:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12909181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9557BCCA483 for ; Thu, 7 Jul 2022 07:48:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234925AbiGGHsy (ORCPT ); Thu, 7 Jul 2022 03:48:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235086AbiGGHsg (ORCPT ); Thu, 7 Jul 2022 03:48:36 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 959C43205E; Thu, 7 Jul 2022 00:48:34 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id h131-20020a1c2189000000b003a2cc290135so396191wmh.2; Thu, 07 Jul 2022 00:48:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UmEVPXSuMOSm98KToNOHXi0Hb6WIl7OgT+YvYE3P9Dw=; b=J/pDhOC9g92s4WAsGzzLFcoqGiEyoYkBip93jOIBuEHmidc1qQGd0t3dpERjjoXD40 LflVjbyRFExdvkMNSQebvSYLJO1a4ecxJ6ybyq0XnWpTzd2ilzz+fMNJXEiUYiHRyZMA sH6TWFlxNTpYTjAjR11DSm6GfpmV48lMclWizo+9/0BCz9wYOSdzAR5VhAmwEKFsTiw7 c9o7DEv4q2NYBToEhS/iY2kCHUOBzeHJvgKtWgvZh28t33g0NKya4nu/7CAiMvzovcoH KmqbOFkCsfdisaJ0D7k9rU0tFKqp95O00SKKqoxI1H3ltkhGG7HTSKBWBkaMa8qFwRZF LBjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UmEVPXSuMOSm98KToNOHXi0Hb6WIl7OgT+YvYE3P9Dw=; b=wrRfZ5Qc/8OpryJR5FSPhUMOK7Yc1QkWHzBuUDg5G/EuUTl3kiX3GazjCO8nMbw82n ZhzEUkH9sONXS4Ln+x0tsodOlUHbQVdAsV0C/DsWT6y+ikvARSig6A21osf5QOFBoRHt cnKCidBQdR4Er84BusZ6+kF+PxmriJFI6w2l0CU/Ana4uObcWMfE4whEUetOrop1EjNu es970GjprQLnw6g60Iw8B/LSTwUp7UCEsCiJZJf0goWkvbKH79T+MCT4c1Cwonnp4aui 7UxVwDmzgvlBw8rR9VMqLo2PxtX5dCTyesZPb1JRkdqw6mHOc5VgHf6ITD4tFemzmk8u XZBA== X-Gm-Message-State: AJIora9N9nEWsejDzW3sBEe9kcHsywKOpTW6kxuQVYbZMD3dwohTv4hQ K/BlZ50cnmmFAC6boyQbrhI= X-Google-Smtp-Source: AGRyM1vlEbAGPHiGtNwmfUPmWwFtg2P5CO+mr1mjFZwoytPnGsPJ5/9/CiAE9LDlo2LIOeShFe8boQ== X-Received: by 2002:a7b:cb8b:0:b0:3a1:98f8:abda with SMTP id m11-20020a7bcb8b000000b003a198f8abdamr2938192wmi.129.1657180113425; Thu, 07 Jul 2022 00:48:33 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id p13-20020a05600c358d00b003974a00697esm24622226wmq.38.2022.07.07.00.48.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 00:48:32 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Rob Herring , Krzysztof Kozlowski , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v4 8/9] arm64: defconfig: Enable Tegra MGBE driver Date: Thu, 7 Jul 2022 09:48:17 +0200 Message-Id: <20220707074818.1481776-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220707074818.1481776-1-thierry.reding@gmail.com> References: <20220707074818.1481776-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Bhadram Varka Enable the driver for the Multi-Gigabit Ethernet (MGBE) controller which can be found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7d1105343bc2..f80142abd9c6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -359,6 +359,7 @@ CONFIG_SMSC911X=y CONFIG_SNI_AVE=y CONFIG_SNI_NETSEC=y CONFIG_STMMAC_ETH=m +CONFIG_DWMAC_TEGRA=m CONFIG_TI_K3_AM65_CPSW_NUSS=y CONFIG_QCOM_IPA=m CONFIG_MESON_GXL_PHY=m From patchwork Thu Jul 7 07:48:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 12909183 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2D13CCA47F for ; Thu, 7 Jul 2022 07:48:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234941AbiGGHs5 (ORCPT ); Thu, 7 Jul 2022 03:48:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235099AbiGGHsl (ORCPT ); Thu, 7 Jul 2022 03:48:41 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD6DB32076; Thu, 7 Jul 2022 00:48:36 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id o4so25097382wrh.3; Thu, 07 Jul 2022 00:48:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f9nLTCidfnrhmXifqG1XQtiik+IMQK61AWbNeVnQJug=; b=COxPdk+QiA9hqXD15/35Y59dlziEZHl9Mel3By4DMFp9kA1AKLdKLEcuc0JwbADkBd DxoNwH+VmpZiHB3eTHCc7jK3eCDwhfD7SGJe5AMhVR5VfdcmmTSxaOhUbm/1daU2HMxo LG+8gS9SlS9/mNIWuLgQoyOMsIEACvzJA6axCHh6pAemRoozwT0abNGr18UHeYdMeaZT epkd60xBCwdBmKxvYD9cDuGKnxoztdWXFECWt8ZW8IS30m68XXmCpRTCvSMNVjInSWul CBSGWzhBttew5ehOCgk/5Gf0Fl5zIiU8ggoUXsmoX1fVr7Nv9S0+hhtWoZkKXWLSjae0 HnGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f9nLTCidfnrhmXifqG1XQtiik+IMQK61AWbNeVnQJug=; b=IMWwOevvWoSVl8ogrH2UAd15Rlq9lwawLSCPo1MA1ngNnAU9SzavJGI6lRUJVMVpk8 33F4n1BZVU0REBuDt6wy31he4PeFtmfVAoe4mjNqr7wYS37RPO3Z5rs0enYKm9SUpJVG mG04+3nvn2G818IIU1cH3Bup147q87HU/sromDstYRpevzcg95uw9CfKMAFlQUTTGyT8 TiDFZsWLOYBnOitlMLHnKPSpgv4GiwuGj8C/IzjQ4Gb0OjDzykl86ZFhwRGR4s0g7dFP SAcqFz5KVDTG9s85fzKVOdPjy+Qa2InLK1KST+/sH02RgZnWiIjXsHXhnu8K2Vv3lbyg l6pg== X-Gm-Message-State: AJIora+Empb964tL78dAqGOB6ORTppWKcU32dLtVpnMRL5WoQo70It9F iTtLqeaziZBE0BHVD8v0PiE= X-Google-Smtp-Source: AGRyM1umeORrvq7hOAosAYPuDdg+MWwN3qIG30DhfJC6NU5Xxf/xoytLKFkKU3ZG6wIk8Vd07u+gFA== X-Received: by 2002:a5d:5747:0:b0:21d:65e9:be07 with SMTP id q7-20020a5d5747000000b0021d65e9be07mr21879807wrw.215.1657180115009; Thu, 07 Jul 2022 00:48:35 -0700 (PDT) Received: from localhost (p200300e41f12c800f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f12:c800:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id b15-20020adff90f000000b0021b90cc66a1sm37586100wrr.2.2022.07.07.00.48.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 00:48:34 -0700 (PDT) From: Thierry Reding To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Thierry Reding , Jon Hunter , Rob Herring , Krzysztof Kozlowski , Bhadram Varka , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v4 9/9] stmmac: tegra: Add MGBE support Date: Thu, 7 Jul 2022 09:48:18 +0200 Message-Id: <20220707074818.1481776-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220707074818.1481776-1-thierry.reding@gmail.com> References: <20220707074818.1481776-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Bhadram Varka Add support for the Multi-Gigabit Ethernet (MGBE/XPCS) IP found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka Signed-off-by: Thierry Reding Acked-by: Thierry Reding Acked-by: Jon Hunter --- Note that this doesn't have any dependencies on any of the patches earlier in the series, so this can be applied independently. drivers/net/ethernet/stmicro/stmmac/Kconfig | 6 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../net/ethernet/stmicro/stmmac/dwmac-tegra.c | 290 ++++++++++++++++++ 3 files changed, 297 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 929cfc22cd0c..47af5a59ce88 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -232,6 +232,12 @@ config DWMAC_INTEL_PLAT the stmmac device driver. This driver is used for the Intel Keem Bay SoC. +config DWMAC_TEGRA + tristate "NVIDIA Tegra MGBE support" + depends on ARCH_TEGRA || COMPILE_TEST + help + Support for the MGBE controller found on Tegra SoCs. + config DWMAC_VISCONTI tristate "Toshiba Visconti DWMAC support" default ARCH_VISCONTI diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index d4e12e9ace4f..057e4bab5c08 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o +obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o stmmac-platform-objs:= stmmac_platform.o dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c new file mode 100644 index 000000000000..bb4b540820fa --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +static const char *const mgbe_clks[] = { + "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac" +}; + +struct tegra_mgbe { + struct device *dev; + + struct clk_bulk_data *clks; + + struct reset_control *rst_mac; + struct reset_control *rst_pcs; + + void __iomem *hv; + void __iomem *regs; + void __iomem *xpcs; + + struct mii_bus *mii; +}; + +#define XPCS_WRAP_UPHY_RX_CONTROL 0x801c +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6)) +#define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4) +#define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0) +#define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020 +#define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0) +#define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2) +#define XPCS_WRAP_UPHY_STATUS 0x8044 +#define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0) +#define XPCS_WRAP_IRQ_STATUS 0x8050 +#define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6) + +#define XPCS_REG_ADDR_SHIFT 10 +#define XPCS_REG_ADDR_MASK 0x1fff +#define XPCS_ADDR 0x3fc + +#define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704 +#define MAC_SBD_INTR BIT(2) +#define MGBE_WRAP_AXI_ASID0_CTRL 0x8400 +#define MGBE_SID 0x6 + +static void mgbe_uphy_lane_bringup(struct tegra_mgbe *mgbe) +{ + unsigned int retry = 300; + u32 value; + int err; + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); + if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) { + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); + value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); + } + + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value, + (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0, + 500, 500 * 2000); + if (err < 0) + dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n"); + + usleep_range(10000, 20000); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value, + (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0, + 1000, 1000 * 2000); + if (err < 0) + dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n"); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + + while (--retry) { + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value, + value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS, + 500, 500 * 2000); + if (err < 0) { + dev_err(mgbe->dev, "timeout waiting for link to become ready\n"); + usleep_range(10000, 20000); + continue; + } + break; + } + + /* clear status */ + writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS); +} + +static int tegra_mgbe_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat; + struct stmmac_resources res; + struct tegra_mgbe *mgbe; + int irq, err, i; + + mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL); + if (!mgbe) + return -ENOMEM; + + mgbe->dev = &pdev->dev; + + memset(&res, 0, sizeof(res)); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor"); + if (IS_ERR(mgbe->hv)) + return PTR_ERR(mgbe->hv); + + mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac"); + if (IS_ERR(mgbe->regs)) + return PTR_ERR(mgbe->regs); + + mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs"); + if (IS_ERR(mgbe->xpcs)) + return PTR_ERR(mgbe->xpcs); + + res.addr = mgbe->regs; + res.irq = irq; + + mgbe->clks = devm_kzalloc(&pdev->dev, sizeof(*mgbe->clks), GFP_KERNEL); + if (!mgbe->clks) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(mgbe_clks); i++) + mgbe->clks[i].id = mgbe_clks[i]; + + err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks); + if (err < 0) + return err; + + err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); + if (err < 0) + return err; + + /* Perform MAC reset */ + mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac"); + if (IS_ERR(mgbe->rst_mac)) + return PTR_ERR(mgbe->rst_mac); + + err = reset_control_assert(mgbe->rst_mac); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + err = reset_control_deassert(mgbe->rst_mac); + if (err < 0) + return err; + + /* Perform PCS reset */ + mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs"); + if (IS_ERR(mgbe->rst_pcs)) + return PTR_ERR(mgbe->rst_pcs); + + err = reset_control_assert(mgbe->rst_pcs); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + err = reset_control_deassert(mgbe->rst_pcs); + if (err < 0) + return err; + + plat = stmmac_probe_config_dt(pdev, res.mac); + if (IS_ERR(plat)) + return PTR_ERR(plat); + + plat->has_xgmac = 1; + plat->tso_en = 1; + plat->pmt = 1; + plat->bsp_priv = mgbe; + + if (!plat->mdio_node) + plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio"); + + if (!plat->mdio_bus_data) { + plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data), + GFP_KERNEL); + if (!plat->mdio_bus_data) { + err = -ENOMEM; + goto remove; + } + } + + plat->mdio_bus_data->needs_reset = true; + + mgbe_uphy_lane_bringup(mgbe); + + /* Tx FIFO Size - 128KB */ + plat->tx_fifo_size = 131072; + /* Rx FIFO Size - 192KB */ + plat->rx_fifo_size = 196608; + + /* Enable common interrupt at wrapper level */ + writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); + + /* Program SID */ + writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); + + err = stmmac_dvr_probe(&pdev->dev, plat, &res); + if (err < 0) + goto remove; + + return 0; + +remove: + stmmac_remove_config_dt(pdev, plat); + return err; +} + +static int tegra_mgbe_remove(struct platform_device *pdev) +{ + struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev); + + clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); + + stmmac_pltfr_remove(pdev); + + return 0; +} + +static const struct of_device_id tegra_mgbe_match[] = { + { .compatible = "nvidia,tegra234-mgbe", }, + { } +}; +MODULE_DEVICE_TABLE(of, tegra_mgbe_match); + +static struct platform_driver tegra_mgbe_driver = { + .probe = tegra_mgbe_probe, + .remove = tegra_mgbe_remove, + .driver = { + .name = "tegra-mgbe", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = tegra_mgbe_match, + }, +}; +module_platform_driver(tegra_mgbe_driver); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver"); +MODULE_LICENSE("GPL");