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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2022 15:46:26.7337 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ad41cf4-c2db-499e-a2b6-08da635483fb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2465 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Document the compatible string used by GPCDMA controller for Tegra234. Signed-off-by: Akhil R Reviewed-by: Jon Hunter --- .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index 9dd1476d1849..399edcd5cecf 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -26,6 +26,10 @@ properties: - const: nvidia,tegra194-gpcdma - const: nvidia,tegra186-gpcdma + - items: + - const: nvidia,tegra234-gpcdma + - const: nvidia,tegra186-gpcdma + "#dma-cells": const: 1 From patchwork Mon Jul 11 15:45:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 12913944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB436CCA480 for ; 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Mon, 11 Jul 2022 08:46:34 -0700 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v3 2/3] dmaengine: tegra: Add terminate() for Tegra234 Date: Mon, 11 Jul 2022 21:15:35 +0530 Message-ID: <20220711154536.41736-3-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220711154536.41736-1-akhilrajeev@nvidia.com> References: <20220711154536.41736-1-akhilrajeev@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7ae72d1c-ed26-483f-d318-08da63548b3c X-MS-TrafficTypeDiagnostic: DM6PR12MB3578:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HRrJWDstz2LNKMESFE2wrJjvT0KpR0kyDCKvvsxhcEcKFHyBOPplS0P9Rib+S1xAi2fOi8t0XxFPV/Vc0jIeTZ/oJIlNnaMr+EJ/l/EQfWoLY+iw+6Gcw+DhbRA5eBDMHj875BC6eG7lMCdvbglv4N2xzECwE65QipiboPyhXBshFll7WoguZtxLUD5V2d559cRkkGOWTnI2tejKsNvSJ0WDAiZCGzuhWQeqiGsNJTstUxtY30UaSvctwwmqSYdetTqBOuA1/MMzDhUpDEAJ4B34/QWFa3HxjcUVNWREoRfeboBgYEZ6aq0ADm/TR5mqedK8Smrz2LjPN5ou77WEm/8SEC2IrnydVWG+itmfXEj3NsBUVSQ8GVYua/fWipRwubKkK10cuH5YV14WfBKCpWKRJWEIT9i5/5pyRtuYxoz4bB9lP/evSyGOYJxh9XfVBfglVhL0p2rgXbDSzhdysiTDGZSvCKca1aChfvRGOvTgDR4SJI4QAHALt//7gQ3wh0upjuVBakaqUBEmV+4f1x2CcgM/GEGSeVLlpKRdfya/qpuV+FpYnxYu2HpmnW/+N/9kaXHKL+jPSjj3IcGKQJLC+YdkQbVY06dpenMdwDp27u6HxMWShrzZ/60FzbQ08Ne6eUfDCobxSpiqRXzHWCgYBdjIkYFCzQd9ORfIP4bbgblu6Yv5/Ila4Pn1I21z6y5Qi2BMp3yQE+CjHXhENwVsYJlDI7VtU/aqR1mW7aJ53/UWp4AHe2klis8I2DIMLTcFQ6zkJFiBoTbORcPJpHNimJ9fp2bpa4dj7QRR5AAI2wJ5LrVKizHSDOyjsouTYMNc0AHVIfj30eVlEtdx0QmhwI3Nt6Gcik4eUgSF+s7vUDe8IgfJj/sD/JYXJbxHsmEHXupa+DqcXp+r4zHj1yWXtwi7ZqkQBEVsOMH59cg= X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(376002)(346002)(136003)(39860400002)(396003)(36840700001)(46966006)(40470700004)(40480700001)(40460700003)(83380400001)(81166007)(7696005)(82740400003)(921005)(86362001)(36860700001)(82310400005)(356005)(5660300002)(8936002)(36756003)(316002)(2906002)(478600001)(110136005)(4326008)(186003)(47076005)(70586007)(8676002)(336012)(70206006)(2616005)(1076003)(26005)(426003)(41300700001)(107886003)(83996005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2022 15:46:38.9674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ae72d1c-ed26-483f-d318-08da63548b3c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3578 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org In certain cases where the DMA client bus gets corrupted or if the end device ceases to send/receive data, DMA can wait indefinitely for the data to be received/sent. Attempting to terminate the transfer will put the DMA in pause flush mode and it remains there. The channel is irrecoverable once this pause times out in Tegra194 and earlier chips. Whereas, from Tegra234, it can be recovered by disabling the channel and reprograming it. Hence add a new terminate() function that ignores the outcome of dma_pause() so that terminate_all() can proceed to disable the channel. Signed-off-by: Akhil R Reviewed-by: Jon Hunter --- drivers/dma/tegra186-gpc-dma.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 05cd451f541d..fa9bda4a2bc6 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -157,8 +157,8 @@ * If any burst is in flight and DMA paused then this is the time to complete * on-flight burst and update DMA status register. */ -#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20 -#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100 +#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 10 +#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 5000 /* 5 msec */ /* Channel base address offset from GPCDMA base address */ #define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x20000 @@ -432,6 +432,17 @@ static int tegra_dma_device_resume(struct dma_chan *dc) return 0; } +static inline int tegra_dma_pause_noerr(struct tegra_dma_channel *tdc) +{ + /* Return 0 irrespective of PAUSE status. + * This is useful to recover channels that can exit out of flush + * state when the channel is disabled. + */ + + tegra_dma_pause(tdc); + return 0; +} + static void tegra_dma_disable(struct tegra_dma_channel *tdc) { u32 csr, status; @@ -1292,6 +1303,14 @@ static const struct tegra_dma_chip_data tegra194_dma_chip_data = { .terminate = tegra_dma_pause, }; +static const struct tegra_dma_chip_data tegra234_dma_chip_data = { + .nr_channels = 31, + .channel_reg_size = SZ_64K, + .max_dma_count = SZ_1G, + .hw_support_pause = true, + .terminate = tegra_dma_pause_noerr, +}; + static const struct of_device_id tegra_dma_of_match[] = { { .compatible = "nvidia,tegra186-gpcdma", @@ -1299,6 +1318,9 @@ static const struct of_device_id tegra_dma_of_match[] = { }, { .compatible = "nvidia,tegra194-gpcdma", .data = &tegra194_dma_chip_data, + }, { + .compatible = "nvidia,tegra234-gpcdma", + .data = &tegra234_dma_chip_data, }, { }, }; From patchwork Mon Jul 11 15:45:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil R X-Patchwork-Id: 12913945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FB77C433EF for ; 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Mon, 11 Jul 2022 08:46:51 -0700 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v3 3/3] arm64: tegra: Update compatible for Tegra234 GPCDMA Date: Mon, 11 Jul 2022 21:15:36 +0530 Message-ID: <20220711154536.41736-4-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220711154536.41736-1-akhilrajeev@nvidia.com> References: <20220711154536.41736-1-akhilrajeev@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bbcbef47-ef11-40af-d11e-08da6354957c X-MS-TrafficTypeDiagnostic: SA1PR12MB5659:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GYcPTpLfn1ytAIZE0g1WD+CFN+ZcxAB5vSUulspYpsOBGAPIE63RpGGFNXcAzVUttMJ35y7TeqAjaBf+Zijab2yngExxA7RGqN4rbDxpiaiq5orXtefLHkk2mF8ZZcv3GvOCWIMTojishWetUS5OzrMxSxrwhH5an7CNjbHQvyZTmN8sY+SwU+tTmzY0UYy1LS9/UXF6/wKeDnB2ZF0+VR38Gk1bDehGryVTGC6Te13ReguG+Yq4CDRiuitAwrbg5iT67Ily8Frcm5CJKbeQ1HpKMma5FoPL92lR+fEudw3akdSrBCywUHiiugxZVLtOz3hzfacAHJ9ubSDyTapld03dy/khCruwvas+m7Lr7odyJj9VUHUA/KdhJCD2I99rA14gk8mPm8+b0M707fGGMR4ZHDdMMiXDEqyNrYMzvbtQL+OSZsYHGhe5ihsII+JWMabEcN8cU4xP1jfNTUrPwQ50EqkKt/3QcIj+G1FBxJE3RcJVruTSzoTNpLz/VZtmrjiuFjtAF86oiX4u8rYLfL22z13DL6PdT4jmbpLO3EL/gC3DAQC8vrzpvT8V5uOtgqOmXc70vf2B8gwVB1gsey9VQhIZ5Vcp4Vx9we7D0gWt5sJUkEPLojUsloRP1AqeeHyY6kAa43FPI4WpO919dzu63mQetyLJ6TmJE8u5iwHXRwXbMQiNt8qLG5Y7yxerkaXY4ZSmxMzeAGJ3bDSOW319tZKrRtQyjavK2PgJQpxYCYUUwkg/E2GbOrRsBzjN65Aj268yjHrmugwsYatJrfmD0XsApjfzQ9BzzXeAb9wKrZqjPVbCfEyvAgR88TqDsC+nrcMeufwoquc630iSwgTxvr0+R6dxMSo95Px/HaqVNIR+40wzrYqyguPktVJzwbRzzbWKfn8PEOK6k9NwGo+6sKiE4KC7JaMpORa4Hyk= X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230016)(4636009)(396003)(39860400002)(346002)(136003)(376002)(40470700004)(36840700001)(46966006)(4326008)(110136005)(4744005)(36756003)(316002)(6666004)(41300700001)(478600001)(426003)(336012)(2616005)(1076003)(47076005)(2906002)(186003)(26005)(107886003)(70206006)(70586007)(8676002)(921005)(40460700003)(7696005)(81166007)(82740400003)(40480700001)(83380400001)(86362001)(8936002)(82310400005)(5660300002)(356005)(36860700001)(36900700001)(83996005)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2022 15:46:56.1015 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbcbef47-ef11-40af-d11e-08da6354957c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5659 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Use the compatible specific to Tegra234 for GPCDMA to support additional features. Signed-off-by: Akhil R Reviewed-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index cf611eff7f6b..c3d2e48994d1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -22,8 +22,8 @@ ranges = <0x0 0x0 0x0 0x40000000>; gpcdma: dma-controller@2600000 { - compatible = "nvidia,tegra194-gpcdma", - "nvidia,tegra186-gpcdma"; + compatible = "nvidia,tegra234-gpcdma", + "nvidia,tegra186-gpcdma"; reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA234_RESET_GPCDMA>; reset-names = "gpcdma";