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Tue, 12 Jul 2022 14:59:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT065.mail.protection.outlook.com (10.13.177.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Tue, 12 Jul 2022 14:59:31 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 12 Jul 2022 09:59:29 -0500 From: Shyam Sundar S K To: , CC: , , "Mario Limonciello" , Shyam Sundar S K Subject: [PATCH v1 01/15] ACPI: platform_profile: Add support for notification chains Date: Tue, 12 Jul 2022 20:28:33 +0530 Message-ID: <20220712145847.3438544-2-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 330b7d97-0c78-49b8-b318-08da6417205f X-MS-TrafficTypeDiagnostic: BN6PR12MB1585:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:31.5733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 330b7d97-0c78-49b8-b318-08da6417205f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1585 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org From: Mario Limonciello Allow other drivers to react to determine current active profile and react to platform profile changes. Signed-off-by: Mario Limonciello Signed-off-by: Shyam Sundar S K --- drivers/acpi/platform_profile.c | 26 ++++++++++++++++++++++++++ include/linux/platform_profile.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/acpi/platform_profile.c b/drivers/acpi/platform_profile.c index d418462ab791..7e12a1f30f06 100644 --- a/drivers/acpi/platform_profile.c +++ b/drivers/acpi/platform_profile.c @@ -49,6 +49,32 @@ static ssize_t platform_profile_choices_show(struct device *dev, return len; } +int platform_profile_get(enum platform_profile_option *profile) +{ + int err; + + err = mutex_lock_interruptible(&profile_lock); + if (err) + return err; + + if (!cur_profile) { + mutex_unlock(&profile_lock); + return -ENODEV; + } + + err = cur_profile->profile_get(cur_profile, profile); + mutex_unlock(&profile_lock); + if (err) + return err; + + /* Check that profile is valid index */ + if (WARN_ON((*profile < 0) || (*profile >= ARRAY_SIZE(profile_names)))) + return -EIO; + + return 0; +} +EXPORT_SYMBOL_GPL(platform_profile_get); + static ssize_t platform_profile_show(struct device *dev, struct device_attribute *attr, char *buf) diff --git a/include/linux/platform_profile.h b/include/linux/platform_profile.h index e5cbb6841f3a..2395be670dfd 100644 --- a/include/linux/platform_profile.h +++ b/include/linux/platform_profile.h @@ -37,5 +37,6 @@ struct platform_profile_handler { int platform_profile_register(struct platform_profile_handler *pprof); int platform_profile_remove(void); void platform_profile_notify(void); +int platform_profile_get(enum platform_profile_option *profile); #endif /*_PLATFORM_PROFILE_H_*/ From patchwork Tue Jul 12 14:58:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29018C433EF for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:33.9293 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8150d820-f083-4f03-cfd8-08da641721c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6602 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org PMF core layer is meant to abstract the common functionalities across PMF features. This layer also does the plumbing work like setting up the mailbox channel for the communication between the PMF driver and the PMFW (Power Management Firmware) running on the SMU. Signed-off-by: Shyam Sundar S K Reviewed-by: Hans de Goede --- drivers/platform/x86/amd/Kconfig | 2 + drivers/platform/x86/amd/Makefile | 1 + drivers/platform/x86/amd/pmf/Kconfig | 16 ++ drivers/platform/x86/amd/pmf/Makefile | 8 + drivers/platform/x86/amd/pmf/core.c | 235 ++++++++++++++++++++++++++ drivers/platform/x86/amd/pmf/pmf.h | 47 ++++++ 6 files changed, 309 insertions(+) create mode 100644 drivers/platform/x86/amd/pmf/Kconfig create mode 100644 drivers/platform/x86/amd/pmf/Makefile create mode 100644 drivers/platform/x86/amd/pmf/core.c create mode 100644 drivers/platform/x86/amd/pmf/pmf.h diff --git a/drivers/platform/x86/amd/Kconfig b/drivers/platform/x86/amd/Kconfig index c0d0a3c5170c..a825af8126c8 100644 --- a/drivers/platform/x86/amd/Kconfig +++ b/drivers/platform/x86/amd/Kconfig @@ -3,6 +3,8 @@ # AMD x86 Platform Specific Drivers # +source "drivers/platform/x86/amd/pmf/Kconfig" + config AMD_PMC tristate "AMD SoC PMC driver" depends on ACPI && PCI && RTC_CLASS diff --git a/drivers/platform/x86/amd/Makefile b/drivers/platform/x86/amd/Makefile index a03fbb08e808..2c229198e24c 100644 --- a/drivers/platform/x86/amd/Makefile +++ b/drivers/platform/x86/amd/Makefile @@ -8,3 +8,4 @@ amd-pmc-y := pmc.o obj-$(CONFIG_AMD_PMC) += amd-pmc.o amd_hsmp-y := hsmp.o obj-$(CONFIG_AMD_HSMP) += amd_hsmp.o +obj-$(CONFIG_AMD_PMF) += pmf/ diff --git a/drivers/platform/x86/amd/pmf/Kconfig b/drivers/platform/x86/amd/pmf/Kconfig new file mode 100644 index 000000000000..2a5f72419515 --- /dev/null +++ b/drivers/platform/x86/amd/pmf/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# AMD PMF Driver +# + +config AMD_PMF + tristate "AMD Platform Management Framework" + depends on ACPI + help + This driver provides support for the AMD Platform Management Framework. + The goal is to enhance end user experience by making AMD PCs smarter, + quiter, power efficient by adapting to user behavior and environment. + + To compile this driver as a module, choose M here: the module will + be called amd_pmf. + diff --git a/drivers/platform/x86/amd/pmf/Makefile b/drivers/platform/x86/amd/pmf/Makefile new file mode 100644 index 000000000000..459005f659e5 --- /dev/null +++ b/drivers/platform/x86/amd/pmf/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for linux/drivers/platform/x86/amd/pmf +# AMD Platform Management Framework +# + +obj-$(CONFIG_AMD_PMF) += amd-pmf.o +amd-pmf-objs := core.o diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c new file mode 100644 index 000000000000..aef97965c181 --- /dev/null +++ b/drivers/platform/x86/amd/pmf/core.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Platform Management Framework Driver + * + * Copyright (c) 2022, Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Author: Shyam Sundar S K + */ + +#include +#include +#include +#include +#include "pmf.h" + +/* PMF-SMU communication registers */ +#define AMD_PMF_REGISTER_MESSAGE 0xA18 +#define AMD_PMF_REGISTER_RESPONSE 0xA78 +#define AMD_PMF_REGISTER_ARGUMENT 0xA58 + +/* Base address of SMU for mapping physical address to virtual address */ +#define AMD_PMF_SMU_INDEX_ADDRESS 0xB8 +#define AMD_PMF_SMU_INDEX_DATA 0xBC +#define AMD_PMF_MAPPING_SIZE 0x01000 +#define AMD_PMF_BASE_ADDR_OFFSET 0x10000 +#define AMD_PMF_BASE_ADDR_LO 0x13B102E8 +#define AMD_PMF_BASE_ADDR_HI 0x13B102EC +#define AMD_PMF_BASE_ADDR_LO_MASK GENMASK(15, 0) +#define AMD_PMF_BASE_ADDR_HI_MASK GENMASK(31, 20) + +/* SMU Response Codes */ +#define AMD_PMF_RESULT_OK 0x01 +#define AMD_PMF_RESULT_CMD_REJECT_BUSY 0xFC +#define AMD_PMF_RESULT_CMD_REJECT_PREREQ 0xFD +#define AMD_PMF_RESULT_CMD_UNKNOWN 0xFE +#define AMD_PMF_RESULT_FAILED 0xFF + +/* List of supported CPU ids */ +#define AMD_CPU_ID_PS 0x14e8 + +#define PMF_MSG_DELAY_MIN_US 50 +#define RESPONSE_REGISTER_LOOP_MAX 20000 + +#define DELAY_MIN_US 2000 +#define DELAY_MAX_US 3000 + +static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset) +{ + return ioread32(dev->regbase + reg_offset); +} + +static inline void amd_pmf_reg_write(struct amd_pmf_dev *dev, int reg_offset, u32 val) +{ + iowrite32(val, dev->regbase + reg_offset); +} + +static void __maybe_unused amd_pmf_dump_registers(struct amd_pmf_dev *dev) +{ + u32 value; + + value = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_RESPONSE); + dev_dbg(dev->dev, "AMD_PMF_REGISTER_RESPONSE:%x\n", value); + + value = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_ARGUMENT); + dev_dbg(dev->dev, "AMD_PMF_REGISTER_ARGUMENT:%d\n", value); + + value = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_MESSAGE); + dev_dbg(dev->dev, "AMD_PMF_REGISTER_MESSAGE:%x\n", value); +} + +int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data) +{ + int rc; + u32 val; + + mutex_lock(&dev->lock); + + /* Wait until we get a valid response */ + rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMF_REGISTER_RESPONSE, + val, val != 0, PMF_MSG_DELAY_MIN_US, + PMF_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); + if (rc) { + dev_err(dev->dev, "failed to talk to SMU\n"); + goto out_unlock; + } + + /* Write zero to response register */ + amd_pmf_reg_write(dev, AMD_PMF_REGISTER_RESPONSE, 0); + + /* Write argument into argument register */ + amd_pmf_reg_write(dev, AMD_PMF_REGISTER_ARGUMENT, arg); + + /* Write message ID to message ID register */ + amd_pmf_reg_write(dev, AMD_PMF_REGISTER_MESSAGE, message); + + /* Wait until we get a valid response */ + rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMF_REGISTER_RESPONSE, + val, val != 0, PMF_MSG_DELAY_MIN_US, + PMF_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); + if (rc) { + dev_err(dev->dev, "SMU response timed out\n"); + goto out_unlock; + } + + switch (val) { + case AMD_PMF_RESULT_OK: + if (get) { + /* PMFW may take longer time to return back the data */ + usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); + *data = amd_pmf_reg_read(dev, AMD_PMF_REGISTER_ARGUMENT); + } + break; + case AMD_PMF_RESULT_CMD_REJECT_BUSY: + dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val); + rc = -EBUSY; + goto out_unlock; + case AMD_PMF_RESULT_CMD_UNKNOWN: + dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val); + rc = -EINVAL; + goto out_unlock; + case AMD_PMF_RESULT_CMD_REJECT_PREREQ: + case AMD_PMF_RESULT_FAILED: + default: + dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val); + rc = -EIO; + goto out_unlock; + } + +out_unlock: + mutex_unlock(&dev->lock); + amd_pmf_dump_registers(dev); + return rc; +} + +static const struct pci_device_id pmf_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) }, + { } +}; + +static const struct acpi_device_id amd_pmf_acpi_ids[] = { + {"AMDI0102", 0}, + { } +}; +MODULE_DEVICE_TABLE(acpi, amd_pmf_acpi_ids); + +static int amd_pmf_probe(struct platform_device *pdev) +{ + struct amd_pmf_dev *dev; + struct pci_dev *rdev; + u32 base_addr_lo; + u32 base_addr_hi; + u64 base_addr; + u32 val; + int err; + + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + dev->dev = &pdev->dev; + + rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); + if (!rdev || !pci_match_id(pmf_pci_ids, rdev)) { + pci_dev_put(rdev); + return -ENODEV; + } + + dev->cpu_id = rdev->device; + err = pci_write_config_dword(rdev, AMD_PMF_SMU_INDEX_ADDRESS, AMD_PMF_BASE_ADDR_LO); + if (err) { + dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMF_SMU_INDEX_ADDRESS); + pci_dev_put(rdev); + return pcibios_err_to_errno(err); + } + + err = pci_read_config_dword(rdev, AMD_PMF_SMU_INDEX_DATA, &val); + if (err) { + pci_dev_put(rdev); + return pcibios_err_to_errno(err); + } + + base_addr_lo = val & AMD_PMF_BASE_ADDR_HI_MASK; + + err = pci_write_config_dword(rdev, AMD_PMF_SMU_INDEX_ADDRESS, AMD_PMF_BASE_ADDR_HI); + if (err) { + dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMF_SMU_INDEX_ADDRESS); + pci_dev_put(rdev); + return pcibios_err_to_errno(err); + } + + err = pci_read_config_dword(rdev, AMD_PMF_SMU_INDEX_DATA, &val); + if (err) { + pci_dev_put(rdev); + return pcibios_err_to_errno(err); + } + + base_addr_hi = val & AMD_PMF_BASE_ADDR_LO_MASK; + pci_dev_put(rdev); + base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); + + dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMF_BASE_ADDR_OFFSET, + AMD_PMF_MAPPING_SIZE); + if (!dev->regbase) + return -ENOMEM; + + platform_set_drvdata(pdev, dev); + + mutex_init(&dev->lock); + dev_info(dev->dev, "registered PMF device successfully\n"); + + return 0; +} + +static int amd_pmf_remove(struct platform_device *pdev) +{ + struct amd_pmf_dev *dev = platform_get_drvdata(pdev); + + mutex_destroy(&dev->lock); + kfree(dev->buf); + return 0; +} + +static struct platform_driver amd_pmf_driver = { + .driver = { + .name = "amd-pmf", + .acpi_match_table = amd_pmf_acpi_ids, + }, + .probe = amd_pmf_probe, + .remove = amd_pmf_remove, +}; +module_platform_driver(amd_pmf_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AMD Platform Management Framework Driver"); diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h new file mode 100644 index 000000000000..ab773aa5a6e1 --- /dev/null +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * AMD Platform Management Framework Driver + * + * Copyright (c) 2022, Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Author: Shyam Sundar S K + */ +#ifndef PMF_H +#define PMF_H + +/* Message Definitions */ +#define SET_SPL 0x03 /* SPL: Sustained Power Limit */ +#define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ +#define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ +#define GET_SPL 0x0B +#define GET_SPPT 0x0D +#define GET_FPPT 0x0F +#define SET_DRAM_ADDR_HIGH 0x14 +#define SET_DRAM_ADDR_LOW 0x15 +#define SET_TRANSFER_TABLE 0x16 +#define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ +#define SET_STT_LIMIT_APU 0x19 +#define SET_STT_LIMIT_HS2 0x1A +#define SET_SPPT_APU_ONLY 0x1D +#define GET_SPPT_APU_ONLY 0x1E +#define GET_STT_MIN_LIMIT 0x1F +#define GET_STT_LIMIT_APU 0x20 +#define GET_STT_LIMIT_HS2 0x21 + +struct amd_pmf_dev { + void __iomem *regbase; + void __iomem *smu_virt_addr; + void *buf; + u32 base_addr; + u32 cpu_id; + u32 hi; + u32 low; + struct device *dev; + struct mutex lock; /* protects the PMF interface */ +}; + +/* Core Layer */ +int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); + +#endif /* PMF_H */ From patchwork Tue Jul 12 14:58:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38CFFCCA483 for ; Tue, 12 Jul 2022 15:03:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233430AbiGLPDH (ORCPT ); Tue, 12 Jul 2022 11:03:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233872AbiGLPBz (ORCPT ); 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Tue, 12 Jul 2022 09:59:33 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH v1 03/15] platform/x86/amd/pmf: Add support for PMF APCI layer Date: Tue, 12 Jul 2022 20:28:35 +0530 Message-ID: <20220712145847.3438544-4-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fc00b1fa-1327-446d-8fcc-08da641722f1 X-MS-TrafficTypeDiagnostic: DM8PR12MB5397:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /rNKVSkBUKV7TdZUCQqZB/nJ9klUp0Z+fLxxtxwm3nGbECYeGswRkn8XL628QdGFVs36eDQDS/R5nRfWefKC7KeZFORQ9tQxhtkQL5GSg6RiXcuPkCZK7zhEqqbT0sYT0fUINnUDKLLOTOr3etfmxyMwIb98duu+RI+xqI6Xp617qbt7Wz9mxKOyhoysNkv+eKK9wupqbVMeHrVRKpZbuh+WqCU27VPfgwpR6+PiQvouAqnoe/5p0f1ItOIdxCT+cKh2kFY5kLYiyZ79XWOh21pFLAHUG9+36WVfWzHjePOnQW1MjwvN7FJqiHu8ghuddTyNU7kIjlU+Zk7t7zakXsEJlUax76cRaaroL9CdgoJEZK6TheH8pwFPCNvJDVg0z12pFotnhoU6AavTQZSu1j4Vw0q7gGHKFWybw7rR7o47jhGQio1WtvxkmtTrC1uJ3scY6Zbu6ZEXFbXpMSkE9lRhY5M30HYb84f10bxbHnRvHHVhwmHUwvCEOx3HA315Z4SQFW7DkaGiO97UWjA4vSHrsUdwlAwuTd1YP4wmDhyVZ0PVv/SAGKfOkw/IP61NO83nZg4QBf0mA7RFslar9ARTP8tInwYUhMYvytnO870+9fZWQex6lHavrLY5Uy96+aOEacFxSBjdX/Fnf+TML0c/fx1iiXpb+0A1txlrnh56my3XLsn7NgKVX9nc4WZ3cpQUK/8C8q59QfIpHYx/OvrdH/Ol/I8a63q6phBjVsXr9k+oX9dzK37xe+9Fq2qLz2761gGUiKqZNserSxPnpjoyv8U/+Ep5AbMhSl5+jgiiSbkpeGdBvFuPQYuRrV+qI1EGorsFCG5ZiyYAO35RX/KrxRRB7vuNG2st/iKpRgg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(136003)(39860400002)(346002)(376002)(396003)(40470700004)(36840700001)(46966006)(186003)(2616005)(26005)(47076005)(70206006)(426003)(40460700003)(1076003)(16526019)(81166007)(7696005)(336012)(82740400003)(356005)(86362001)(40480700001)(82310400005)(36860700001)(478600001)(70586007)(5660300002)(83380400001)(54906003)(8936002)(110136005)(36756003)(41300700001)(2906002)(4326008)(8676002)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:35.8847 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc00b1fa-1327-446d-8fcc-08da641722f1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5397 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org PMF driver implements the ACPI methods as defined by AMD for PMF Support. The ACPI layer acts as a glue that helps in providing the infrastructure for OEMs customization. OEMs can refer to PMF support documentation to decide on the list of functions to be supported on their specific platform model. AMD mandates that PMF ACPI fn0 and fn1 to be implemented which provides the set of functions, params and the notifications that would be sent to PMF driver so that PMF driver can adapt and react. Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmf/Makefile | 2 +- drivers/platform/x86/amd/pmf/acpi.c | 188 ++++++++++++++++++++++++++ drivers/platform/x86/amd/pmf/core.c | 1 + drivers/platform/x86/amd/pmf/pmf.h | 32 +++++ 4 files changed, 222 insertions(+), 1 deletion(-) create mode 100644 drivers/platform/x86/amd/pmf/acpi.c diff --git a/drivers/platform/x86/amd/pmf/Makefile b/drivers/platform/x86/amd/pmf/Makefile index 459005f659e5..2617eba773ce 100644 --- a/drivers/platform/x86/amd/pmf/Makefile +++ b/drivers/platform/x86/amd/pmf/Makefile @@ -5,4 +5,4 @@ # obj-$(CONFIG_AMD_PMF) += amd-pmf.o -amd-pmf-objs := core.o +amd-pmf-objs := core.o acpi.o diff --git a/drivers/platform/x86/amd/pmf/acpi.c b/drivers/platform/x86/amd/pmf/acpi.c new file mode 100644 index 000000000000..addcaae5675c --- /dev/null +++ b/drivers/platform/x86/amd/pmf/acpi.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Platform Management Framework Driver + * + * Copyright (c) 2022, Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Author: Shyam Sundar S K + */ + +#include +#include "pmf.h" + +#define APMF_METHOD "\\_SB_.PMF_.APMF" + +static unsigned long supported_func; + +static void apmf_if_parse_functions(struct apmf_if_functions *func, u32 mask); + +static union acpi_object *apmf_if_call(struct apmf_if *apmf_if, int func, struct acpi_buffer *param) +{ + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + struct acpi_object_list apmf_if_arg_list; + union acpi_object apmf_if_args[2]; + acpi_status status; + + apmf_if_arg_list.count = 2; + apmf_if_arg_list.pointer = &apmf_if_args[0]; + + apmf_if_args[0].type = ACPI_TYPE_INTEGER; + apmf_if_args[0].integer.value = func; + + if (param) { + apmf_if_args[1].type = ACPI_TYPE_BUFFER; + apmf_if_args[1].buffer.length = param->length; + apmf_if_args[1].buffer.pointer = param->pointer; + } else { + apmf_if_args[1].type = ACPI_TYPE_INTEGER; + apmf_if_args[1].integer.value = 0; + } + + status = acpi_evaluate_object(apmf_if->handle, NULL, &apmf_if_arg_list, &buffer); + if (ACPI_FAILURE(status)) { + pr_err("PMF: APMF method call failed\n"); + if (status != AE_NOT_FOUND) + kfree(buffer.pointer); + + return NULL; + } + + return buffer.pointer; +} + +static void apmf_if_parse_functions(struct apmf_if_functions *func, u32 mask) +{ + func->system_params = mask & APMF_FUNC_GET_SYS_PARAMS; +} + +static int apmf_if_verify_interface(struct amd_pmf_dev *pdev, struct apmf_if *ampf_if) +{ + struct apmf_verify_interface output; + union acpi_object *info; + size_t size; + int err = 0; + + info = apmf_if_call(ampf_if, APMF_FUNC_VERIFY_INTERFACE, NULL); + if (!info) + return -EIO; + + size = *(u16 *)info->buffer.pointer; + + if (size < sizeof(output)) { + dev_err(pdev->dev, "buffer too small %zu\n", size); + err = -EINVAL; + goto out; + } + + size = min(sizeof(output), size); + memset(&output, 0, sizeof(output)); + memcpy(&output, info->buffer.pointer, size); + apmf_if_parse_functions(&f_if->func, output.supported_functions); + supported_func = output.supported_functions; + dev_dbg(pdev->dev, "supported functions:0x%x notifications:0x%x\n", + output.supported_functions, output.notification_mask); + +out: + kfree(info); + return err; +} + +int is_apmf_func_supported(unsigned long index) +{ + /* If bit-n is set, that indicates function n+1 is supported */ + return ((supported_func & (1 << (index - 1))) != 0); +} + +static int apmf_get_system_params(struct apmf_if *ampf_if) +{ + struct apmf_system_params params; + union acpi_object *info; + size_t size; + int err = 0; + + info = apmf_if_call(ampf_if, APMF_FUNC_GET_SYS_PARAMS, NULL); + if (!info) { + err = -EIO; + goto out; + } + + size = *(u16 *)info->buffer.pointer; + + if (size < sizeof(params)) { + pr_err("PMF: buffer too small %zu\n", size); + err = -EINVAL; + goto out; + } + + size = min(sizeof(params), size); + memset(¶ms, 0, sizeof(params)); + memcpy(¶ms, info->buffer.pointer, size); + + pr_debug("PMF: system params mask:0x%x flags:0x%x cmd_code:0x%x\n", + params.valid_mask, + params.flags, + params.command_code); + params.flags = params.flags & params.valid_mask; + +out: + kfree(info); + return err; +} + +static acpi_handle apmf_if_probe_handle(void) +{ + acpi_handle handle = NULL; + char acpi_method_name[255] = { 0 }; + struct acpi_buffer buffer = { sizeof(acpi_method_name), acpi_method_name }; + acpi_status status; + + status = acpi_get_handle(NULL, (acpi_string) APMF_METHOD, &handle); + if (ACPI_SUCCESS(status)) + goto out; + + pr_err("PMF: APMF handle not found\n"); + return NULL; + +out: + acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer); + pr_debug("PMF: APMF handle %s found\n", acpi_method_name); + return handle; +} + +int apmf_acpi_init(struct amd_pmf_dev *pmf_dev) +{ + acpi_handle apmf_if_handle; + struct apmf_if *apmf_if; + int ret; + + apmf_if_handle = apmf_if_probe_handle(); + if (!apmf_if_handle) + goto out; + + apmf_if = kzalloc(sizeof(*apmf_if), GFP_KERNEL); + if (!apmf_if) + goto out; + + apmf_if->handle = apmf_if_handle; + + ret = apmf_if_verify_interface(pmf_dev, apmf_if); + if (ret) { + dev_err(pmf_dev->dev, "APMF verify interface failed :%d\n", ret); + kfree(apmf_if); + goto out; + } + pmf_dev->apmf_if = apmf_if; + + if (apmf_if->func.system_params) { + ret = apmf_get_system_params(apmf_if); + if (ret) { + dev_err(pmf_dev->dev, "APMF apmf_get_system_params failed :%d\n", ret); + kfree(apmf_if); + goto out; + } + } + +out: + return ret; +} diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index aef97965c181..c5002b7bb904 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -204,6 +204,7 @@ static int amd_pmf_probe(struct platform_device *pdev) if (!dev->regbase) return -ENOMEM; + apmf_acpi_init(dev); platform_set_drvdata(pdev, dev); mutex_init(&dev->lock); diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index ab773aa5a6e1..40f038eb6197 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -10,6 +10,12 @@ #ifndef PMF_H #define PMF_H +#include + +/* APMF Functions */ +#define APMF_FUNC_VERIFY_INTERFACE 0 +#define APMF_FUNC_GET_SYS_PARAMS 1 + /* Message Definitions */ #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ @@ -29,6 +35,30 @@ #define GET_STT_LIMIT_APU 0x20 #define GET_STT_LIMIT_HS2 0x21 +/* AMD PMF BIOS interfaces */ +struct apmf_if_functions { + bool system_params; +}; + +struct apmf_if { + acpi_handle handle; + struct apmf_if_functions func; +}; + +struct apmf_verify_interface { + u16 size; + u16 version; + u32 notification_mask; + u32 supported_functions; +} __packed; + +struct apmf_system_params { + u16 size; + u32 valid_mask; + u32 flags; + u8 command_code; +} __packed; + struct amd_pmf_dev { void __iomem *regbase; void __iomem *smu_virt_addr; @@ -38,10 +68,12 @@ struct amd_pmf_dev { u32 hi; u32 low; struct device *dev; + struct apmf_if *apmf_if; struct mutex lock; /* protects the PMF interface */ }; /* Core Layer */ +int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); #endif /* PMF_H */ From patchwork Tue Jul 12 14:58:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE7CEC433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT066.mail.protection.outlook.com (10.13.177.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Tue, 12 Jul 2022 14:59:38 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 12 Jul 2022 09:59:35 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH v1 04/15] platform/x86/amd/pmf: Add support SPS PMF feature Date: Tue, 12 Jul 2022 20:28:36 +0530 Message-ID: <20220712145847.3438544-5-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3bc21647-f4bb-4237-d05d-08da64172446 X-MS-TrafficTypeDiagnostic: SN6PR12MB2751:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:38.1211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bc21647-f4bb-4237-d05d-08da64172446 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2751 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org SPS (a.k.a. Static Power Slider) gives a feel of Windows performance power slider for the Linux users, where the user selects a certain mode (like "balanced", "low-power" or "performance") and the thermals associated with each selected mode gets applied from the silicon side via the mailboxes defined through PMFW. PMF driver hooks to platform_profile by reading the PMF ACPI fn9 to see if the support is being advertised by ACPI interface. If supported, the PMF driver reacts to platform_profile selection choices made by the user and adjust the system thermal behavior. Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmf/Makefile | 2 +- drivers/platform/x86/amd/pmf/acpi.c | 29 +++++ drivers/platform/x86/amd/pmf/core.c | 26 ++++ drivers/platform/x86/amd/pmf/pmf.h | 65 ++++++++++ drivers/platform/x86/amd/pmf/sps.c | 166 ++++++++++++++++++++++++++ 5 files changed, 287 insertions(+), 1 deletion(-) create mode 100644 drivers/platform/x86/amd/pmf/sps.c diff --git a/drivers/platform/x86/amd/pmf/Makefile b/drivers/platform/x86/amd/pmf/Makefile index 2617eba773ce..557521a80427 100644 --- a/drivers/platform/x86/amd/pmf/Makefile +++ b/drivers/platform/x86/amd/pmf/Makefile @@ -5,4 +5,4 @@ # obj-$(CONFIG_AMD_PMF) += amd-pmf.o -amd-pmf-objs := core.o acpi.o +amd-pmf-objs := core.o acpi.o sps.o diff --git a/drivers/platform/x86/amd/pmf/acpi.c b/drivers/platform/x86/amd/pmf/acpi.c index addcaae5675c..fd5ab7a116f0 100644 --- a/drivers/platform/x86/amd/pmf/acpi.c +++ b/drivers/platform/x86/amd/pmf/acpi.c @@ -54,6 +54,7 @@ static union acpi_object *apmf_if_call(struct apmf_if *apmf_if, int func, struct static void apmf_if_parse_functions(struct apmf_if_functions *func, u32 mask) { func->system_params = mask & APMF_FUNC_GET_SYS_PARAMS; + func->static_slider_granular = mask & APMF_FUNC_STATIC_SLIDER_GRANULAR; } static int apmf_if_verify_interface(struct amd_pmf_dev *pdev, struct apmf_if *ampf_if) @@ -130,6 +131,34 @@ static int apmf_get_system_params(struct apmf_if *ampf_if) return err; } +int apmf_get_static_slider_granular(struct apmf_if *ampf_if, + struct apmf_static_slider_granular_output *data) +{ + union acpi_object *info; + size_t size; + int err = 0; + + info = apmf_if_call(ampf_if, APMF_FUNC_STATIC_SLIDER_GRANULAR, NULL); + if (!info) + return -EIO; + + size = *(u16 *)info->buffer.pointer; + + if (size < sizeof(*data)) { + pr_err("PMF: buffer too small %zu\n", size); + err = -EINVAL; + goto out; + } + + size = min(sizeof(*data), size); + memset(data, 0, sizeof(*data)); + memcpy(data, info->buffer.pointer, size); + +out: + kfree(info); + return err; +} + static acpi_handle apmf_if_probe_handle(void) { acpi_handle handle = NULL; diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index c5002b7bb904..b6006e8ee1a1 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "pmf.h" /* PMF-SMU communication registers */ @@ -45,6 +46,14 @@ #define DELAY_MIN_US 2000 #define DELAY_MAX_US 3000 +int amd_pmf_get_power_source(void) +{ + if (power_supply_is_system_supplied() > 0) + return POWER_SOURCE_AC; + else + return POWER_SOURCE_DC; +} + static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset) { return ioread32(dev->regbase + reg_offset); @@ -138,6 +147,21 @@ static const struct pci_device_id pmf_pci_ids[] = { { } }; +static void amd_pmf_init_features(struct amd_pmf_dev *dev) +{ + /* Enable Static Slider */ + if (is_apmf_func_supported(APMF_FUNC_STATIC_SLIDER_GRANULAR)) { + amd_pmf_init_sps(dev); + dev_dbg(dev->dev, "SPS enabled and Platform Profiles registered\n"); + } +} + +static void amd_pmf_deinit_features(struct amd_pmf_dev *dev) +{ + if (is_apmf_func_supported(APMF_FUNC_STATIC_SLIDER_GRANULAR)) + amd_pmf_deinit_sps(dev); +} + static const struct acpi_device_id amd_pmf_acpi_ids[] = { {"AMDI0102", 0}, { } @@ -206,6 +230,7 @@ static int amd_pmf_probe(struct platform_device *pdev) apmf_acpi_init(dev); platform_set_drvdata(pdev, dev); + amd_pmf_init_features(dev); mutex_init(&dev->lock); dev_info(dev->dev, "registered PMF device successfully\n"); @@ -218,6 +243,7 @@ static int amd_pmf_remove(struct platform_device *pdev) struct amd_pmf_dev *dev = platform_get_drvdata(pdev); mutex_destroy(&dev->lock); + amd_pmf_deinit_features(dev); kfree(dev->buf); return 0; } diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 40f038eb6197..a405987ae653 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -7,14 +7,17 @@ * * Author: Shyam Sundar S K */ + #ifndef PMF_H #define PMF_H #include +#include /* APMF Functions */ #define APMF_FUNC_VERIFY_INTERFACE 0 #define APMF_FUNC_GET_SYS_PARAMS 1 +#define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 /* Message Definitions */ #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ @@ -35,9 +38,12 @@ #define GET_STT_LIMIT_APU 0x20 #define GET_STT_LIMIT_HS2 0x21 +#define ARG_NONE 0 + /* AMD PMF BIOS interfaces */ struct apmf_if_functions { bool system_params; + bool static_slider_granular; }; struct apmf_if { @@ -59,6 +65,30 @@ struct apmf_system_params { u8 command_code; } __packed; +enum amd_stt_skin_temp { + STT_TEMP_APU, + STT_TEMP_HS2, + STT_TEMP_COUNT, +}; + +enum amd_slider_op { + SLIDER_OP_GET, + SLIDER_OP_SET, +}; + +enum power_source { + POWER_SOURCE_AC, + POWER_SOURCE_DC, + POWER_SOURCE_MAX, +}; + +enum power_modes { + POWER_MODE_PERFORMANCE, + POWER_MODE_BALANCED_POWER, + POWER_MODE_POWER_SAVER, + POWER_MODE_MAX, +}; + struct amd_pmf_dev { void __iomem *regbase; void __iomem *smu_virt_addr; @@ -69,11 +99,46 @@ struct amd_pmf_dev { u32 low; struct device *dev; struct apmf_if *apmf_if; + enum platform_profile_option current_profile; + struct platform_profile_handler pprof; struct mutex lock; /* protects the PMF interface */ }; +struct apmf_sps_prop_granular { + u32 fppt; + u32 sppt; + u32 sppt_apu_only; + u32 spl; + u32 stt_min; + u8 stt_skin_temp[STT_TEMP_COUNT]; + u32 fan_id; +} __packed; + +/* Static Slider */ +struct apmf_static_slider_granular_output { + u16 size; + struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; +}; + +struct amd_pmf_static_slider_granular { + u16 size; + struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; +}; + /* Core Layer */ int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); +int is_apmf_func_supported(unsigned long index); int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); +int amd_pmf_get_power_source(void); + +/* SPS Layer */ +u8 amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); +void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, + struct amd_pmf_static_slider_granular *table); +int amd_pmf_init_sps(struct amd_pmf_dev *dev); +void amd_pmf_deinit_sps(struct amd_pmf_dev *dev); +int apmf_get_static_slider_granular(struct apmf_if *ampf_if, + struct apmf_static_slider_granular_output *output); +void amd_pmf_load_defaults_sps(struct amd_pmf_dev *dev); #endif /* PMF_H */ diff --git a/drivers/platform/x86/amd/pmf/sps.c b/drivers/platform/x86/amd/pmf/sps.c new file mode 100644 index 000000000000..25289cf5608c --- /dev/null +++ b/drivers/platform/x86/amd/pmf/sps.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Platform Management Framework (PMF) Driver + * + * Copyright (c) 2022, Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Author: Shyam Sundar S K + */ + +#include "pmf.h" + +static int amd_pmf_profile_get(struct platform_profile_handler *pprof, + enum platform_profile_option *profile); +static int amd_pmf_profile_set(struct platform_profile_handler *pprof, + enum platform_profile_option profile); +static struct amd_pmf_static_slider_granular config_store; + +void amd_pmf_load_defaults_sps(struct amd_pmf_dev *dev) +{ + struct apmf_static_slider_granular_output output; + int i, j, idx = 0; + + memset(&config_store, 0, sizeof(config_store)); + + if (dev->apmf_if->func.static_slider_granular) { + apmf_get_static_slider_granular(dev->apmf_if, &output); + + for (i = 0; i < POWER_SOURCE_MAX; i++) { + for (j = 0; j < POWER_MODE_MAX; j++) { + config_store.prop[i][j].spl = output.prop[idx].spl; + config_store.prop[i][j].sppt = output.prop[idx].sppt; + config_store.prop[i][j].sppt_apu_only = + output.prop[idx].sppt_apu_only; + config_store.prop[i][j].fppt = output.prop[idx].fppt; + config_store.prop[i][j].stt_min = output.prop[idx].stt_min; + config_store.prop[i][j].stt_skin_temp[STT_TEMP_APU] = + output.prop[idx].stt_skin_temp[STT_TEMP_APU]; + config_store.prop[i][j].stt_skin_temp[STT_TEMP_HS2] = + output.prop[idx].stt_skin_temp[STT_TEMP_HS2]; + config_store.prop[i][j].fan_id = output.prop[idx].fan_id; + idx++; + } + } + } +} + +void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, + struct amd_pmf_static_slider_granular *table) +{ + int src = amd_pmf_get_power_source(); + + if (op == SLIDER_OP_SET) { + amd_pmf_send_cmd(dev, SET_SPL, false, config_store.prop[src][idx].spl, NULL); + amd_pmf_send_cmd(dev, SET_FPPT, false, config_store.prop[src][idx].fppt, NULL); + amd_pmf_send_cmd(dev, SET_SPPT, false, config_store.prop[src][idx].sppt, NULL); + amd_pmf_send_cmd(dev, SET_SPPT_APU_ONLY, false, + config_store.prop[src][idx].sppt_apu_only, NULL); + amd_pmf_send_cmd(dev, SET_STT_MIN_LIMIT, false, + config_store.prop[src][idx].stt_min, NULL); + amd_pmf_send_cmd(dev, SET_STT_LIMIT_APU, false, + config_store.prop[src][idx].stt_skin_temp[STT_TEMP_APU], NULL); + amd_pmf_send_cmd(dev, SET_STT_LIMIT_HS2, false, + config_store.prop[src][idx].stt_skin_temp[STT_TEMP_HS2], NULL); + } else if (op == SLIDER_OP_GET) { + amd_pmf_send_cmd(dev, GET_SPL, true, ARG_NONE, &table->prop[src][idx].spl); + amd_pmf_send_cmd(dev, GET_FPPT, true, ARG_NONE, &table->prop[src][idx].fppt); + amd_pmf_send_cmd(dev, GET_SPPT, true, ARG_NONE, &table->prop[src][idx].sppt); + amd_pmf_send_cmd(dev, GET_SPPT_APU_ONLY, true, ARG_NONE, + &table->prop[src][idx].sppt_apu_only); + amd_pmf_send_cmd(dev, GET_STT_MIN_LIMIT, true, ARG_NONE, + &table->prop[src][idx].stt_min); + amd_pmf_send_cmd(dev, GET_STT_LIMIT_APU, true, ARG_NONE, + (u32 *)&table->prop[src][idx].stt_skin_temp[STT_TEMP_APU]); + amd_pmf_send_cmd(dev, GET_STT_LIMIT_HS2, true, ARG_NONE, + (u32 *)&table->prop[src][idx].stt_skin_temp[STT_TEMP_HS2]); + } +} + +static int amd_pmf_profile_get(struct platform_profile_handler *pprof, + enum platform_profile_option *profile) +{ + struct amd_pmf_dev *pmf = container_of(pprof, struct amd_pmf_dev, pprof); + + *profile = pmf->current_profile; + return 0; +} + +u8 amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf) +{ + u8 mode; + + switch (pmf->current_profile) { + case PLATFORM_PROFILE_PERFORMANCE: + mode = 0; + break; + case PLATFORM_PROFILE_BALANCED: + mode = 1; + break; + case PLATFORM_PROFILE_LOW_POWER: + mode = 2; + break; + default: + dev_err(pmf->dev, "Unknown Platform Profile.\n"); + break; + } + + return mode; +} + +int amd_pmf_profile_set(struct platform_profile_handler *pprof, + enum platform_profile_option profile) +{ + struct amd_pmf_dev *pmf = container_of(pprof, struct amd_pmf_dev, pprof); + u8 mode; + + pmf->current_profile = profile; + mode = amd_pmf_get_pprof_modes(pmf); + amd_pmf_update_slider(pmf, SLIDER_OP_SET, mode, NULL); + return 0; +} + +static void amd_pmf_profile_refresh(struct amd_pmf_dev *dev) +{ + enum platform_profile_option profile; + + /* Set intially to Balanced Mode */ + profile = PLATFORM_PROFILE_BALANCED; + + if (profile != dev->current_profile) { + dev->current_profile = profile; + platform_profile_notify(); + } +} + +int amd_pmf_init_sps(struct amd_pmf_dev *dev) +{ + int err = 0; + + dev->pprof.profile_get = amd_pmf_profile_get; + dev->pprof.profile_set = amd_pmf_profile_set; + + /* Setup supported modes */ + set_bit(PLATFORM_PROFILE_LOW_POWER, dev->pprof.choices); + set_bit(PLATFORM_PROFILE_BALANCED, dev->pprof.choices); + set_bit(PLATFORM_PROFILE_PERFORMANCE, dev->pprof.choices); + + /* Create platform_profile structure and register */ + err = platform_profile_register(&dev->pprof); + if (err) { + dev_err(dev->dev, "Failed to register SPS support, this is most likely an SBIOS bug: %d\n", + err); + return -EEXIST; + } + /* Ensure initial values are correct */ + amd_pmf_profile_refresh(dev); + + amd_pmf_load_defaults_sps(dev); + + return err; +} + +void amd_pmf_deinit_sps(struct amd_pmf_dev *dev) +{ + platform_profile_remove(); +} From patchwork Tue Jul 12 14:58:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02C4ECCA486 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT065.mail.protection.outlook.com (10.13.177.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Tue, 12 Jul 2022 14:59:40 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 12 Jul 2022 09:59:37 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH v1 05/15] platform/x86/amd/pmf: Add debugfs information Date: Tue, 12 Jul 2022 20:28:37 +0530 Message-ID: <20220712145847.3438544-6-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9bd58e6f-f19e-4f46-6901-08da64172575 X-MS-TrafficTypeDiagnostic: BY5PR12MB3859:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:40.1042 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9bd58e6f-f19e-4f46-6901-08da64172575 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3859 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Add debugfs support to the PMF driver so that using this interface the live counters from the PMFW can be queried to see if the power parameters are getting set properly when a certain power mode change happens. Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmf/core.c | 46 +++++++++++++++++++++++++++++ drivers/platform/x86/amd/pmf/pmf.h | 3 ++ 2 files changed, 49 insertions(+) diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index b6006e8ee1a1..3d2af6a8e5e4 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -8,6 +8,7 @@ * Author: Shyam Sundar S K */ +#include #include #include #include @@ -46,6 +47,49 @@ #define DELAY_MIN_US 2000 #define DELAY_MAX_US 3000 +#ifdef CONFIG_DEBUG_FS +static int current_power_limits_show(struct seq_file *seq, void *unused) +{ + struct amd_pmf_dev *dev = seq->private; + struct amd_pmf_static_slider_granular table; + int mode, src = 0; + + mode = amd_pmf_get_pprof_modes(dev); + src = amd_pmf_get_power_source(); + amd_pmf_update_slider(dev, SLIDER_OP_GET, mode, &table); + seq_printf(seq, "spl:%u fppt:%u sppt:%u sppt_apu_only:%u stt_min:%u stt[APU]:%u stt[HS2]: %u\n", + table.prop[src][mode].spl, + table.prop[src][mode].fppt, + table.prop[src][mode].sppt, + table.prop[src][mode].sppt_apu_only, + table.prop[src][mode].stt_min, + table.prop[src][mode].stt_skin_temp[STT_TEMP_APU], + table.prop[src][mode].stt_skin_temp[STT_TEMP_HS2]); + return 0; +} +DEFINE_SHOW_ATTRIBUTE(current_power_limits); + +static void amd_pmf_dbgfs_unregister(struct amd_pmf_dev *dev) +{ + debugfs_remove_recursive(dev->dbgfs_dir); +} + +static void amd_pmf_dbgfs_register(struct amd_pmf_dev *dev) +{ + dev->dbgfs_dir = debugfs_create_dir("amd_pmf", NULL); + debugfs_create_file("current_power_limits", 0644, dev->dbgfs_dir, dev, + ¤t_power_limits_fops); +} +#else +static inline void amd_pmf_dbgfs_register(struct amd_pmf_dev *dev) +{ +} + +static inline void amd_pmf_dbgfs_unregister(struct amd_pmf_dev *dev) +{ +} +#endif /* CONFIG_DEBUG_FS */ + int amd_pmf_get_power_source(void) { if (power_supply_is_system_supplied() > 0) @@ -231,6 +275,7 @@ static int amd_pmf_probe(struct platform_device *pdev) apmf_acpi_init(dev); platform_set_drvdata(pdev, dev); amd_pmf_init_features(dev); + amd_pmf_dbgfs_register(dev); mutex_init(&dev->lock); dev_info(dev->dev, "registered PMF device successfully\n"); @@ -244,6 +289,7 @@ static int amd_pmf_remove(struct platform_device *pdev) mutex_destroy(&dev->lock); amd_pmf_deinit_features(dev); + amd_pmf_dbgfs_unregister(dev); kfree(dev->buf); return 0; } diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index a405987ae653..77021ef4bfde 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -102,6 +102,9 @@ struct amd_pmf_dev { enum platform_profile_option current_profile; struct platform_profile_handler pprof; struct mutex lock; /* protects the PMF interface */ +#if IS_ENABLED(CONFIG_DEBUG_FS) + struct dentry *dbgfs_dir; +#endif /* CONFIG_DEBUG_FS */ }; struct apmf_sps_prop_granular { From patchwork Tue Jul 12 14:58:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915155 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BA6CCCA47C for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:42.0464 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be3092d7-903a-4039-6460-08da6417269b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3229 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org PMF driver can send periodic heartbeat signals to OEM BIOS. When BIOS does not receive the signal after a period of time, it can infer that AMDPMF has hung or failed to load. In this situation, BIOS can fallback to legacy operations. OEM can modify the time interval of the signal or completely disable signals through ACPI Method. Signed-off-by: Shyam Sundar S K Reviewed-by: Hans de Goede --- drivers/platform/x86/amd/pmf/acpi.c | 42 +++++++++++++++++++++++++++-- drivers/platform/x86/amd/pmf/core.c | 1 + drivers/platform/x86/amd/pmf/pmf.h | 10 +++++++ 3 files changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/platform/x86/amd/pmf/acpi.c b/drivers/platform/x86/amd/pmf/acpi.c index fd5ab7a116f0..60ffc9ba4adc 100644 --- a/drivers/platform/x86/amd/pmf/acpi.c +++ b/drivers/platform/x86/amd/pmf/acpi.c @@ -97,6 +97,7 @@ int is_apmf_func_supported(unsigned long index) static int apmf_get_system_params(struct apmf_if *ampf_if) { + struct apmf_notification_cfg *n = &f_if->notify_cfg; struct apmf_system_params params; union acpi_object *info; size_t size; @@ -120,11 +121,13 @@ static int apmf_get_system_params(struct apmf_if *ampf_if) memset(¶ms, 0, sizeof(params)); memcpy(¶ms, info->buffer.pointer, size); - pr_debug("PMF: system params mask:0x%x flags:0x%x cmd_code:0x%x\n", + pr_debug("PMF: system params mask:0x%x flags:0x%x cmd_code:0x%x heartbeat:%d\n", params.valid_mask, params.flags, - params.command_code); + params.command_code, + params.heartbeat_int); params.flags = params.flags & params.valid_mask; + n->hb_interval = params.heartbeat_int; out: kfree(info); @@ -159,6 +162,26 @@ int apmf_get_static_slider_granular(struct apmf_if *ampf_if, return err; } +static void apmf_sbios_heartbeat_notify(struct work_struct *work) +{ + struct amd_pmf_dev *dev = container_of(work, struct amd_pmf_dev, heart_beat.work); + struct apmf_notification_cfg *n = &dev->apmf_if->notify_cfg; + union acpi_object *info; + int err = 0; + + dev_dbg(dev->dev, "Sending heartbeat to SBIOS\n"); + info = apmf_if_call(dev->apmf_if, APMF_FUNC_SBIOS_HEARTBEAT, NULL); + if (!info) { + err = -EIO; + goto out; + } + + schedule_delayed_work(&dev->heart_beat, msecs_to_jiffies(n->hb_interval * 1000)); + +out: + kfree(info); +} + static acpi_handle apmf_if_probe_handle(void) { acpi_handle handle = NULL; @@ -179,8 +202,15 @@ static acpi_handle apmf_if_probe_handle(void) return handle; } +void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev) +{ + if (pmf_dev->apmf_if->func.sbios_heartbeat) + cancel_delayed_work_sync(&pmf_dev->heart_beat); +} + int apmf_acpi_init(struct amd_pmf_dev *pmf_dev) { + struct apmf_notification_cfg *n; acpi_handle apmf_if_handle; struct apmf_if *apmf_if; int ret; @@ -202,6 +232,7 @@ int apmf_acpi_init(struct amd_pmf_dev *pmf_dev) goto out; } pmf_dev->apmf_if = apmf_if; + n = &apmf_if->notify_cfg; if (apmf_if->func.system_params) { ret = apmf_get_system_params(apmf_if); @@ -212,6 +243,13 @@ int apmf_acpi_init(struct amd_pmf_dev *pmf_dev) } } + if (n->hb_interval) { + apmf_if->func.sbios_heartbeat = true; + /* send heartbeats only if the interval is not zero */ + INIT_DELAYED_WORK(&pmf_dev->heart_beat, apmf_sbios_heartbeat_notify); + schedule_delayed_work(&pmf_dev->heart_beat, 0); + } + out: return ret; } diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index 3d2af6a8e5e4..ff26928e6a49 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -289,6 +289,7 @@ static int amd_pmf_remove(struct platform_device *pdev) mutex_destroy(&dev->lock); amd_pmf_deinit_features(dev); + apmf_acpi_deinit(dev); amd_pmf_dbgfs_unregister(dev); kfree(dev->buf); return 0; diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 77021ef4bfde..504e1ae79706 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -17,6 +17,7 @@ /* APMF Functions */ #define APMF_FUNC_VERIFY_INTERFACE 0 #define APMF_FUNC_GET_SYS_PARAMS 1 +#define APMF_FUNC_SBIOS_HEARTBEAT 4 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 /* Message Definitions */ @@ -43,12 +44,18 @@ /* AMD PMF BIOS interfaces */ struct apmf_if_functions { bool system_params; + bool sbios_heartbeat; bool static_slider_granular; }; +struct apmf_notification_cfg { + int hb_interval; /* SBIOS heartbeat interval */ +}; + struct apmf_if { acpi_handle handle; struct apmf_if_functions func; + struct apmf_notification_cfg notify_cfg; }; struct apmf_verify_interface { @@ -63,6 +70,7 @@ struct apmf_system_params { u32 valid_mask; u32 flags; u8 command_code; + u32 heartbeat_int; } __packed; enum amd_stt_skin_temp { @@ -101,6 +109,7 @@ struct amd_pmf_dev { struct apmf_if *apmf_if; enum platform_profile_option current_profile; struct platform_profile_handler pprof; + struct delayed_work heart_beat; struct mutex lock; /* protects the PMF interface */ #if IS_ENABLED(CONFIG_DEBUG_FS) struct dentry *dbgfs_dir; @@ -130,6 +139,7 @@ struct amd_pmf_static_slider_granular { /* Core Layer */ int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); +void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); int is_apmf_func_supported(unsigned long index); int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); int amd_pmf_get_power_source(void); From patchwork Tue Jul 12 14:58:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0D95CCA47F for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT041.mail.protection.outlook.com (10.13.177.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Tue, 12 Jul 2022 14:59:45 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 12 Jul 2022 09:59:41 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH v1 07/15] platform/x86/amd/pmf: Add fan control support Date: Tue, 12 Jul 2022 20:28:39 +0530 Message-ID: <20220712145847.3438544-8-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8ba9c432-500a-414b-b761-08da641728bf X-MS-TrafficTypeDiagnostic: BN9PR12MB5178:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:45.6399 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ba9c432-500a-414b-b761-08da641728bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5178 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org PMF has a generic interface defined via PMF ACPI fn9 for influencing fan policy during mode switch. PMF ACPI fn9 will normally be invoked when AMDPMF needs to change the fan table index for the EC. When AMDPMF is loaded this function will be invoked to change fan speed. OEM can also choose to report the actual fan table index and fan RPM to PMF through OEM structure. This information will be communicated by PMF driver to customer BIOS. Signed-off-by: Shyam Sundar S K Reviewed-by: Hans de Goede --- drivers/platform/x86/amd/pmf/acpi.c | 26 ++++++++++++++++++++++++++ drivers/platform/x86/amd/pmf/pmf.h | 17 +++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/platform/x86/amd/pmf/acpi.c b/drivers/platform/x86/amd/pmf/acpi.c index 60ffc9ba4adc..e4822c6f4259 100644 --- a/drivers/platform/x86/amd/pmf/acpi.c +++ b/drivers/platform/x86/amd/pmf/acpi.c @@ -55,6 +55,7 @@ static void apmf_if_parse_functions(struct apmf_if_functions *func, u32 mask) { func->system_params = mask & APMF_FUNC_GET_SYS_PARAMS; func->static_slider_granular = mask & APMF_FUNC_STATIC_SLIDER_GRANULAR; + func->fan_table_idx = mask & APMF_FUNC_SET_FAN_IDX; } static int apmf_if_verify_interface(struct amd_pmf_dev *pdev, struct apmf_if *ampf_if) @@ -182,6 +183,31 @@ static void apmf_sbios_heartbeat_notify(struct work_struct *work) kfree(info); } +int apmf_update_fan_idx(struct apmf_if *ampf_if, bool manual, u32 idx) +{ + union acpi_object *info; + struct apmf_fan_idx args; + struct acpi_buffer params; + int err = 0; + + args.size = sizeof(args); + args.fan_ctl_mode = manual; + args.fan_ctl_idx = idx; + + params.length = sizeof(args); + params.pointer = (void *)&args; + + info = apmf_if_call(ampf_if, APMF_FUNC_SET_FAN_IDX, ¶ms); + if (!info) { + err = -EIO; + goto out; + } + +out: + kfree(info); + return err; +} + static acpi_handle apmf_if_probe_handle(void) { acpi_handle handle = NULL; diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 504e1ae79706..1e9e2e498d15 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -18,6 +18,7 @@ #define APMF_FUNC_VERIFY_INTERFACE 0 #define APMF_FUNC_GET_SYS_PARAMS 1 #define APMF_FUNC_SBIOS_HEARTBEAT 4 +#define APMF_FUNC_SET_FAN_IDX 7 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 /* Message Definitions */ @@ -39,12 +40,16 @@ #define GET_STT_LIMIT_APU 0x20 #define GET_STT_LIMIT_HS2 0x21 +/* Fan Index for Auto Mode */ +#define FAN_INDEX_AUTO 0xFFFFFFFF + #define ARG_NONE 0 /* AMD PMF BIOS interfaces */ struct apmf_if_functions { bool system_params; bool sbios_heartbeat; + bool fan_table_idx; bool static_slider_granular; }; @@ -73,6 +78,12 @@ struct apmf_system_params { u32 heartbeat_int; } __packed; +struct apmf_fan_idx { + u16 size; + u8 fan_ctl_mode; + u32 fan_ctl_idx; +} __packed; + enum amd_stt_skin_temp { STT_TEMP_APU, STT_TEMP_HS2, @@ -137,6 +148,11 @@ struct amd_pmf_static_slider_granular { struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; }; +struct fan_table_control { + bool manual; + unsigned long fan_id; +}; + /* Core Layer */ int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); @@ -154,4 +170,5 @@ int apmf_get_static_slider_granular(struct apmf_if *ampf_if, struct apmf_static_slider_granular_output *output); void amd_pmf_load_defaults_sps(struct amd_pmf_dev *dev); +int apmf_update_fan_idx(struct apmf_if *ampf_if, bool manual, u32 idx); #endif /* PMF_H */ From patchwork Tue Jul 12 14:58:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915153 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5314C433EF for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT041.mail.protection.outlook.com (10.13.177.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Tue, 12 Jul 2022 14:59:45 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 12 Jul 2022 09:59:43 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH v1 08/15] platform/x86/amd/pmf: Get performance metrics from PMFW Date: Tue, 12 Jul 2022 20:28:40 +0530 Message-ID: <20220712145847.3438544-9-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 806e13cf-098f-4c71-0334-08da641728ed X-MS-TrafficTypeDiagnostic: LV2PR12MB5751:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:45.9368 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 806e13cf-098f-4c71-0334-08da641728ed X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5751 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org PMF driver polls for metrics information from PMFW to understand the system behavior, power consumption etc. This metrics table information will be used the PMF features to tweak the thermal heuristics. The poll duration can also be changed by the user by changing the poll duration time. Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmf/core.c | 57 +++++++++++++++++++++++++++++ drivers/platform/x86/amd/pmf/pmf.h | 39 ++++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index ff26928e6a49..c6fd52c46818 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -47,6 +47,11 @@ #define DELAY_MIN_US 2000 #define DELAY_MAX_US 3000 +/* override Metrics Table sample size time (in ms) */ +static int metrics_table_loop_ms = 1000; +module_param(metrics_table_loop_ms, int, 0644); +MODULE_PARM_DESC(metrics_table_loop_ms, " Metrics Table sample size time (default = 1000ms) "); + #ifdef CONFIG_DEBUG_FS static int current_power_limits_show(struct seq_file *seq, void *unused) { @@ -98,6 +103,30 @@ int amd_pmf_get_power_source(void) return POWER_SOURCE_DC; } +static void amd_pmf_get_metrics(struct work_struct *work) +{ + struct amd_pmf_dev *dev = container_of(work, struct amd_pmf_dev, work_buffer.work); + enum platform_profile_option current_profile; + ktime_t time_elapsed_ms; + int socket_power; + + /* Get the current profile information */ + platform_profile_get(¤t_profile); + + /* Transfer table contents */ + memset(&dev->m_table, 0, sizeof(dev->m_table)); + amd_pmf_send_cmd(dev, SET_TRANSFER_TABLE, 0, 7, NULL); + memcpy(&dev->m_table, dev->buf, sizeof(dev->m_table)); + + time_elapsed_ms = ktime_to_ms(ktime_get()) - dev->start_time; + /* Calculate the avg SoC power consumption */ + socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; + + dev->start_time = ktime_to_ms(ktime_get()); + dev_dbg(dev->dev, "Metrics table sample size time:%d\n", metrics_table_loop_ms); + schedule_delayed_work(&dev->work_buffer, msecs_to_jiffies(metrics_table_loop_ms)); +} + static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset) { return ioread32(dev->regbase + reg_offset); @@ -191,6 +220,34 @@ static const struct pci_device_id pmf_pci_ids[] = { { } }; +int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev) +{ + struct smu_pmf_metrics *m_table; + u64 phys_addr; + + INIT_DELAYED_WORK(&dev->work_buffer, amd_pmf_get_metrics); + + /* + * Start collecting the metrics data after a small delay + * or else, we might end up getting stale values from PMFW. + */ + schedule_delayed_work(&dev->work_buffer, msecs_to_jiffies(metrics_table_loop_ms * 3)); + + /* Get Metrics Table Address */ + dev->buf = kzalloc(sizeof(*m_table), GFP_KERNEL); + if (!dev->buf) + return -ENOMEM; + + phys_addr = virt_to_phys(dev->buf); + dev->hi = phys_addr >> 32; + dev->low = phys_addr & GENMASK(31, 0); + + amd_pmf_send_cmd(dev, SET_DRAM_ADDR_HIGH, 0, dev->hi, NULL); + amd_pmf_send_cmd(dev, SET_DRAM_ADDR_LOW, 0, dev->low, NULL); + + return 0; +} + static void amd_pmf_init_features(struct amd_pmf_dev *dev) { /* Enable Static Slider */ diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 1e9e2e498d15..8f318ff59c2e 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -84,6 +84,41 @@ struct apmf_fan_idx { u32 fan_ctl_idx; } __packed; +struct smu_pmf_metrics { + u16 gfxclk_freq; /* in MHz */ + u16 socclk_freq; /* in MHz */ + u16 vclk_freq; /* in MHz */ + u16 dclk_freq; /* in MHz */ + u16 memclk_freq; /* in MHz */ + u16 spare; + u16 gfx_activity; /* in Centi */ + u16 uvd_activity; /* in Centi */ + u16 voltage[2]; /* in mV */ + u16 currents[2]; /* in mA */ + u16 power[2];/* in mW */ + u16 core_freq[8]; /* in MHz */ + u16 core_power[8]; /* in mW */ + u16 core_temp[8]; /* in centi-Celsius */ + u16 l3_freq; /* in MHz */ + u16 l3_temp; /* in centi-Celsius */ + u16 gfx_temp; /* in centi-Celsius */ + u16 soc_temp; /* in centi-Celsius */ + u16 throttler_status; + u16 current_socketpower; /* in mW */ + u16 stapm_orig_limit; /* in W */ + u16 stapm_cur_limit; /* in W */ + u32 apu_power; /* in mW */ + u32 dgpu_power; /* in mW */ + u16 vdd_tdc_val; /* in mA */ + u16 soc_tdc_val; /* in mA */ + u16 vdd_edc_val; /* in mA */ + u16 soc_edcv_al; /* in mA */ + u16 infra_cpu_maxfreq; /* in MHz */ + u16 infra_gfx_maxfreq; /* in MHz */ + u16 skin_temp; /* in centi-Celsius */ + u16 device_state; +}; + enum amd_stt_skin_temp { STT_TEMP_APU, STT_TEMP_HS2, @@ -120,8 +155,11 @@ struct amd_pmf_dev { struct apmf_if *apmf_if; enum platform_profile_option current_profile; struct platform_profile_handler pprof; + struct smu_pmf_metrics m_table; + struct delayed_work work_buffer; struct delayed_work heart_beat; struct mutex lock; /* protects the PMF interface */ + ktime_t start_time; #if IS_ENABLED(CONFIG_DEBUG_FS) struct dentry *dbgfs_dir; #endif /* CONFIG_DEBUG_FS */ @@ -158,6 +196,7 @@ int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); int is_apmf_func_supported(unsigned long index); int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); +int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); int amd_pmf_get_power_source(void); /* SPS Layer */ From patchwork Tue Jul 12 14:58:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AB7FCCA47C for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT032.mail.protection.outlook.com (10.13.177.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Tue, 12 Jul 2022 14:59:48 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 12 Jul 2022 09:59:45 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH v1 09/15] platform/x86/amd/pmf: Add support for CnQF Date: Tue, 12 Jul 2022 20:28:41 +0530 Message-ID: <20220712145847.3438544-10-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c72971ac-9795-4ca9-6af2-08da64172a44 X-MS-TrafficTypeDiagnostic: DM6PR12MB4651:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:48.1873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c72971ac-9795-4ca9-6af2-08da64172a44 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4651 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org CnQF (a.k.a Cool and Quiet Framework) extends the static slider concept. PMF dynamically manages system power limits and fan policy based on system power trends which is representative of workload trend. Static slider and CnQF controls are mutually exclusive for system power budget adjustments. CnQF supports configurable number of modes which can be unique for AC and DC. Every mode is representative of a system state characterized by unique steady state and boost behavior. OEMs can configure the different modes/system states and how the transition to a mode happens. Whether to have CnQF manage system power budget dynamically in AC or DC or both is also configurable. Mode changes due to CnQF donÂ’t result in slider position change. The default OEM values are obtained after evaluating the PMF ACPI function idx 11 & 12 for AC and DC respectively. Whether to turn ON/OFF by default is guided by a "flag" passed by the OEM BIOS. Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmf/Makefile | 3 +- drivers/platform/x86/amd/pmf/acpi.c | 56 +++++ drivers/platform/x86/amd/pmf/cnqf.c | 327 ++++++++++++++++++++++++++ drivers/platform/x86/amd/pmf/core.c | 14 ++ drivers/platform/x86/amd/pmf/pmf.h | 115 +++++++++ 5 files changed, 514 insertions(+), 1 deletion(-) create mode 100644 drivers/platform/x86/amd/pmf/cnqf.c diff --git a/drivers/platform/x86/amd/pmf/Makefile b/drivers/platform/x86/amd/pmf/Makefile index 557521a80427..d02a0bdc6429 100644 --- a/drivers/platform/x86/amd/pmf/Makefile +++ b/drivers/platform/x86/amd/pmf/Makefile @@ -5,4 +5,5 @@ # obj-$(CONFIG_AMD_PMF) += amd-pmf.o -amd-pmf-objs := core.o acpi.o sps.o +amd-pmf-objs := core.o acpi.o sps.o \ + cnqf.o diff --git a/drivers/platform/x86/amd/pmf/acpi.c b/drivers/platform/x86/amd/pmf/acpi.c index e4822c6f4259..a3ff91c605b5 100644 --- a/drivers/platform/x86/amd/pmf/acpi.c +++ b/drivers/platform/x86/amd/pmf/acpi.c @@ -56,6 +56,8 @@ static void apmf_if_parse_functions(struct apmf_if_functions *func, u32 mask) func->system_params = mask & APMF_FUNC_GET_SYS_PARAMS; func->static_slider_granular = mask & APMF_FUNC_STATIC_SLIDER_GRANULAR; func->fan_table_idx = mask & APMF_FUNC_SET_FAN_IDX; + func->dyn_slider_ac = mask & APMF_FUNC_DYN_SLIDER_GRANULAR_AC; + func->dyn_slider_dc = mask & APMF_FUNC_DYN_SLIDER_GRANULAR_DC; } static int apmf_if_verify_interface(struct amd_pmf_dev *pdev, struct apmf_if *ampf_if) @@ -208,6 +210,60 @@ int apmf_update_fan_idx(struct apmf_if *ampf_if, bool manual, u32 idx) return err; } +int apmf_get_dyn_slider_def_ac(struct apmf_if *ampf_if, struct apmf_dyn_slider_output *data) +{ + union acpi_object *info; + size_t size; + int err = 0; + + info = apmf_if_call(ampf_if, APMF_FUNC_DYN_SLIDER_GRANULAR_AC, NULL); + if (!info) + return -EIO; + + size = *(u16 *)info->buffer.pointer; + + if (size < sizeof(*data)) { + pr_debug("buffer too small %zu\n", size); + err = -EINVAL; + goto out; + } + + size = min(sizeof(*data), size); + memset(data, 0, sizeof(*data)); + memcpy(data, info->buffer.pointer, size); + +out: + kfree(info); + return err; +} + +int apmf_get_dyn_slider_def_dc(struct apmf_if *ampf_if, struct apmf_dyn_slider_output *data) +{ + union acpi_object *info; + size_t size; + int err = 0; + + info = apmf_if_call(ampf_if, APMF_FUNC_DYN_SLIDER_GRANULAR_DC, NULL); + if (!info) + return -EIO; + + size = *(u16 *)info->buffer.pointer; + + if (size < sizeof(*data)) { + pr_debug("buffer too small %zu\n", size); + err = -EINVAL; + goto out; + } + + size = min(sizeof(*data), size); + memset(data, 0, sizeof(*data)); + memcpy(data, info->buffer.pointer, size); + +out: + kfree(info); + return err; +} + static acpi_handle apmf_if_probe_handle(void) { acpi_handle handle = NULL; diff --git a/drivers/platform/x86/amd/pmf/cnqf.c b/drivers/platform/x86/amd/pmf/cnqf.c new file mode 100644 index 000000000000..8c6756faab25 --- /dev/null +++ b/drivers/platform/x86/amd/pmf/cnqf.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Platform Management Framework Driver + * + * Copyright (c) 2022, Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Author: Shyam Sundar S K + */ + +#include +#include "pmf.h" + +static struct cnqf_config config_store; + +static int amd_pmf_handle_cnqf(struct amd_pmf_dev *dev, bool op, int src, int idx, + struct cnqf_config *table) +{ + struct power_table_control *pc; + + if (op == SLIDER_OP_SET) { + pc = &config_store.mode_set[src][idx].power_control; + + amd_pmf_send_cmd(dev, SET_SPL, false, pc->spl, NULL); + amd_pmf_send_cmd(dev, SET_FPPT, false, pc->fppt, NULL); + amd_pmf_send_cmd(dev, SET_SPPT, false, pc->sppt, NULL); + amd_pmf_send_cmd(dev, SET_SPPT_APU_ONLY, false, pc->sppt_apu_only, NULL); + amd_pmf_send_cmd(dev, SET_STT_MIN_LIMIT, false, pc->stt_min, NULL); + amd_pmf_send_cmd(dev, SET_STT_LIMIT_APU, false, pc->stt_skin_temp[STT_TEMP_APU], + NULL); + amd_pmf_send_cmd(dev, SET_STT_LIMIT_HS2, false, pc->stt_skin_temp[STT_TEMP_HS2], + NULL); + } else if (op == SLIDER_OP_GET) { + pc = &table->mode_set[src][idx].power_control; + + amd_pmf_send_cmd(dev, GET_SPL, true, ARG_NONE, &pc->spl); + amd_pmf_send_cmd(dev, GET_FPPT, true, ARG_NONE, &pc->fppt); + amd_pmf_send_cmd(dev, GET_SPPT, true, ARG_NONE, &pc->sppt); + amd_pmf_send_cmd(dev, GET_SPPT_APU_ONLY, true, ARG_NONE, &pc->sppt_apu_only); + amd_pmf_send_cmd(dev, GET_STT_MIN_LIMIT, true, ARG_NONE, &pc->stt_min); + amd_pmf_send_cmd(dev, GET_STT_LIMIT_APU, true, ARG_NONE, + &pc->stt_skin_temp[STT_TEMP_APU]); + amd_pmf_send_cmd(dev, GET_STT_LIMIT_HS2, true, ARG_NONE, + &pc->stt_skin_temp[STT_TEMP_HS2]); + } + + if (dev->apmf_if->func.fan_table_idx) + apmf_update_fan_idx(dev->apmf_if, + config_store.mode_set[src][idx].fan_control.manual, + config_store.mode_set[src][idx].fan_control.fan_id); + + return 0; +} + +static void amd_pmf_update_power_threshold(void) +{ + struct cnqf_mode_settings *ts; + struct cnqf_tran_params *tp; + int i; + + for (i = 0; i < POWER_SOURCE_MAX; i++) { + tp = &config_store.trans_param[i][CNQF_TRANSITION_TO_QUIET]; + ts = &config_store.mode_set[i][CNQF_MODE_BALANCE]; + tp->power_threshold = ts->power_floor - tp->power_delta; + + tp = &config_store.trans_param[i][CNQF_TRANSITION_TO_TURBO]; + ts = &config_store.mode_set[i][CNQF_MODE_PERFORMANCE]; + tp->power_threshold = ts->power_floor - tp->power_delta; + + tp = &config_store.trans_param[i][CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE]; + ts = &config_store.mode_set[i][CNQF_MODE_BALANCE]; + tp->power_threshold = ts->power_floor - tp->power_delta; + + tp = &config_store.trans_param[i][CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE]; + ts = &config_store.mode_set[i][CNQF_MODE_PERFORMANCE]; + tp->power_threshold = ts->power_floor - tp->power_delta; + + tp = &config_store.trans_param[i][CNQF_TRANSITION_FROM_QUIET_TO_BALANCE]; + ts = &config_store.mode_set[i][CNQF_MODE_QUIET]; + tp->power_threshold = ts->power_floor - tp->power_delta; + + tp = &config_store.trans_param[i][CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE]; + ts = &config_store.mode_set[i][CNQF_MODE_TURBO]; + tp->power_threshold = ts->power_floor - tp->power_delta; + } +} + +static const char *state_as_str(unsigned int state) +{ + switch (state) { + case CNQF_MODE_QUIET: + return "QUIET"; + case CNQF_MODE_BALANCE: + return "BALANCED"; + case CNQF_MODE_TURBO: + return "TURBO"; + case CNQF_MODE_PERFORMANCE: + return "PERFORMANCE"; + default: + return "Unknown CnQF mode"; + } +} + +void amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms) +{ + struct cnqf_tran_params *tp; + int src, i, j, index = 0; + u32 avg_power = 0; + + src = amd_pmf_get_power_source(); + + if (!dev->cnqf_running) { + pr_debug("setting CNQF thermals\n"); + amd_pmf_handle_cnqf(dev, SLIDER_OP_SET, src, config_store.current_mode, NULL); + dev->cnqf_running = true; + return; + } + + for (i = 0; i < CNQF_TRANSITION_MAX; i++) { + config_store.trans_param[src][i].timer += time_lapsed_ms; + config_store.trans_param[src][i].total_power += socket_power; + config_store.trans_param[src][i].count++; + + tp = &config_store.trans_param[src][i]; + if (tp->timer >= tp->time_constant && tp->count) { + avg_power = tp->total_power / tp->count; + + /* Reset the indices */ + tp->timer = 0; + tp->total_power = 0; + tp->count = 0; + + if ((tp->shifting_up && avg_power >= tp->power_threshold) || + (!tp->shifting_up && avg_power <= tp->power_threshold)) { + tp->priority = true; + } else { + tp->priority = false; + } + } + } + + dev_dbg(dev->dev, "[CNQF] Avg power: %u mW socket power: %u mW mode:%s\n", + avg_power, socket_power, state_as_str(config_store.current_mode)); + + for (j = 0; j < CNQF_TRANSITION_MAX; j++) { + /* apply the highest priority */ + index = config_store.trans_prio[j]; + if (config_store.trans_param[src][index].priority) { + if (config_store.current_mode != + config_store.trans_param[src][index].target_mode) { + config_store.current_mode = + config_store.trans_param[src][index].target_mode; + dev_dbg(dev->dev, "Moving to Mode :%s\n", + state_as_str(config_store.current_mode)); + amd_pmf_handle_cnqf(dev, SLIDER_OP_SET, src, + config_store.current_mode, NULL); + } + break; + } + } +} + +static void amd_pmf_update_trans_data(int idx, struct apmf_dyn_slider_output out) +{ + struct cnqf_tran_params *tp; + + tp = &config_store.trans_param[idx][CNQF_TRANSITION_TO_QUIET]; + tp->time_constant = out.t_balanced_to_quiet; + tp->target_mode = CNQF_MODE_QUIET; + tp->shifting_up = false; + + tp = &config_store.trans_param[idx][CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE]; + tp->time_constant = out.t_balanced_to_perf; + tp->target_mode = CNQF_MODE_PERFORMANCE; + tp->shifting_up = true; + + tp = &config_store.trans_param[idx][CNQF_TRANSITION_FROM_QUIET_TO_BALANCE]; + tp->time_constant = out.t_quiet_to_balanced; + tp->target_mode = CNQF_MODE_BALANCE; + tp->shifting_up = true; + + tp = &config_store.trans_param[idx][CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE]; + tp->time_constant = out.t_perf_to_balanced; + tp->target_mode = CNQF_MODE_BALANCE; + tp->shifting_up = false; + + tp = &config_store.trans_param[idx][CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE]; + tp->time_constant = out.t_turbo_to_perf; + tp->target_mode = CNQF_MODE_PERFORMANCE; + tp->shifting_up = false; + + tp = &config_store.trans_param[idx][CNQF_TRANSITION_TO_TURBO]; + tp->time_constant = out.t_perf_to_turbo; + tp->target_mode = CNQF_MODE_TURBO; + tp->shifting_up = true; +} + +static void amd_pmf_update_mode_set(int idx, struct apmf_dyn_slider_output out) +{ + struct cnqf_mode_settings *ms; + + /* Quiet Mode */ + ms = &config_store.mode_set[idx][CNQF_MODE_QUIET]; + ms->power_floor = out.ps[APMF_CNQF_QUIET].pfloor; + ms->power_control.fppt = out.ps[APMF_CNQF_QUIET].fppt; + ms->power_control.sppt = out.ps[APMF_CNQF_QUIET].sppt; + ms->power_control.sppt_apu_only = out.ps[APMF_CNQF_QUIET].sppt_apu_only; + ms->power_control.spl = out.ps[APMF_CNQF_QUIET].spl; + ms->power_control.stt_min = out.ps[APMF_CNQF_QUIET].stt_min_limit; + ms->power_control.stt_skin_temp[STT_TEMP_APU] = + out.ps[APMF_CNQF_QUIET].stt_skintemp[STT_TEMP_APU]; + ms->power_control.stt_skin_temp[STT_TEMP_HS2] = + out.ps[APMF_CNQF_QUIET].stt_skintemp[STT_TEMP_HS2]; + ms->fan_control.fan_id = out.ps[APMF_CNQF_QUIET].fan_id; + + /* Balance Mode */ + ms = &config_store.mode_set[idx][CNQF_MODE_BALANCE]; + ms->power_floor = out.ps[APMF_CNQF_BALANCE].pfloor; + ms->power_control.fppt = out.ps[APMF_CNQF_BALANCE].fppt; + ms->power_control.sppt = out.ps[APMF_CNQF_BALANCE].sppt; + ms->power_control.sppt_apu_only = out.ps[APMF_CNQF_BALANCE].sppt_apu_only; + ms->power_control.spl = out.ps[APMF_CNQF_BALANCE].spl; + ms->power_control.stt_min = out.ps[APMF_CNQF_BALANCE].stt_min_limit; + ms->power_control.stt_skin_temp[STT_TEMP_APU] = + out.ps[APMF_CNQF_BALANCE].stt_skintemp[STT_TEMP_APU]; + ms->power_control.stt_skin_temp[STT_TEMP_HS2] = + out.ps[APMF_CNQF_BALANCE].stt_skintemp[STT_TEMP_HS2]; + ms->fan_control.fan_id = out.ps[APMF_CNQF_BALANCE].fan_id; + + /* Performance Mode */ + ms = &config_store.mode_set[idx][CNQF_MODE_PERFORMANCE]; + ms->power_floor = out.ps[APMF_CNQF_PERFORMANCE].pfloor; + ms->power_control.fppt = out.ps[APMF_CNQF_PERFORMANCE].fppt; + ms->power_control.sppt = out.ps[APMF_CNQF_PERFORMANCE].sppt; + ms->power_control.sppt_apu_only = out.ps[APMF_CNQF_PERFORMANCE].sppt_apu_only; + ms->power_control.spl = out.ps[APMF_CNQF_PERFORMANCE].spl; + ms->power_control.stt_min = out.ps[APMF_CNQF_PERFORMANCE].stt_min_limit; + ms->power_control.stt_skin_temp[STT_TEMP_APU] = + out.ps[APMF_CNQF_PERFORMANCE].stt_skintemp[STT_TEMP_APU]; + ms->power_control.stt_skin_temp[STT_TEMP_HS2] = + out.ps[APMF_CNQF_PERFORMANCE].stt_skintemp[STT_TEMP_HS2]; + ms->fan_control.fan_id = out.ps[APMF_CNQF_PERFORMANCE].fan_id; + + /* Turbo Mode */ + ms = &config_store.mode_set[idx][CNQF_MODE_TURBO]; + ms->power_floor = out.ps[APMF_CNQF_TURBO].pfloor; + ms->power_control.fppt = out.ps[APMF_CNQF_TURBO].fppt; + ms->power_control.sppt = out.ps[APMF_CNQF_TURBO].sppt; + ms->power_control.sppt_apu_only = out.ps[APMF_CNQF_TURBO].sppt_apu_only; + ms->power_control.spl = out.ps[APMF_CNQF_TURBO].spl; + ms->power_control.stt_min = out.ps[APMF_CNQF_TURBO].stt_min_limit; + ms->power_control.stt_skin_temp[STT_TEMP_APU] = + out.ps[APMF_CNQF_TURBO].stt_skintemp[STT_TEMP_APU]; + ms->power_control.stt_skin_temp[STT_TEMP_HS2] = + out.ps[APMF_CNQF_TURBO].stt_skintemp[STT_TEMP_HS2]; + ms->fan_control.fan_id = out.ps[APMF_CNQF_TURBO].fan_id; +} + +static int amd_pmf_check_flags(struct amd_pmf_dev *dev) +{ + struct apmf_dyn_slider_output out; + + if (dev->apmf_if->func.dyn_slider_ac) + apmf_get_dyn_slider_def_ac(dev->apmf_if, &out); + else if (dev->apmf_if->func.dyn_slider_dc) + apmf_get_dyn_slider_def_dc(dev->apmf_if, &out); + + return out.flags; +} + +void amd_pmf_load_defaults_cnqf(struct amd_pmf_dev *dev) +{ + struct apmf_dyn_slider_output out; + int i, j, ret; + + for (i = 0; i < POWER_SOURCE_MAX; i++) { + if (i == POWER_SOURCE_AC && dev->apmf_if->func.dyn_slider_ac) { + ret = apmf_get_dyn_slider_def_ac(dev->apmf_if, &out); + if (ret) + dev_err(dev->dev, + "APMF apmf_get_dyn_slider_def_ac failed :%d\n", ret); + } else if (i == POWER_SOURCE_DC && dev->apmf_if->func.dyn_slider_dc) { + ret = apmf_get_dyn_slider_def_dc(dev->apmf_if, &out); + if (ret) + dev_err(dev->dev, + "APMF apmf_get_dyn_slider_def_dc failed :%d\n", ret); + } + + amd_pmf_update_mode_set(i, out); + amd_pmf_update_trans_data(i, out); + + for (j = 0; j < CNQF_MODE_MAX; j++) { + if (config_store.mode_set[i][j].fan_control.fan_id == FAN_INDEX_AUTO) + config_store.mode_set[i][j].fan_control.manual = false; + else + config_store.mode_set[i][j].fan_control.manual = true; + } + } + amd_pmf_update_power_threshold(); + + for (i = 0; i < CNQF_TRANSITION_MAX; i++) + config_store.trans_prio[i] = i; +} + +void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev) +{ + cancel_delayed_work_sync(&dev->work_buffer); +} + +void amd_pmf_init_cnqf(struct amd_pmf_dev *dev) +{ + int ret, src; + + ret = amd_pmf_check_flags(dev); + if (!ret) { + dev_dbg(dev->dev, "CnQF bios default_enable flag not set\n"); + return; + } + + dev->cnqf_feat = true; + amd_pmf_load_defaults_cnqf(dev); + amd_pmf_init_metrics_table(dev); + + /* update the thermal for CnQF */ + src = amd_pmf_get_power_source(); + amd_pmf_handle_cnqf(dev, SLIDER_OP_SET, src, config_store.current_mode, NULL); +} diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index c6fd52c46818..bc267d333b76 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -122,6 +122,11 @@ static void amd_pmf_get_metrics(struct work_struct *work) /* Calculate the avg SoC power consumption */ socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; + if (dev->cnqf_feat) { + /* Apply the CnQF transition */ + amd_pmf_trans_cnqf(dev, socket_power, time_elapsed_ms); + } + dev->start_time = ktime_to_ms(ktime_get()); dev_dbg(dev->dev, "Metrics table sample size time:%d\n", metrics_table_loop_ms); schedule_delayed_work(&dev->work_buffer, msecs_to_jiffies(metrics_table_loop_ms)); @@ -255,12 +260,21 @@ static void amd_pmf_init_features(struct amd_pmf_dev *dev) amd_pmf_init_sps(dev); dev_dbg(dev->dev, "SPS enabled and Platform Profiles registered\n"); } + /* Enable Cool n Quiet Framework (CnQF) */ + if (is_apmf_func_supported(APMF_FUNC_DYN_SLIDER_GRANULAR_AC) || + is_apmf_func_supported(APMF_FUNC_DYN_SLIDER_GRANULAR_DC)) { + amd_pmf_init_cnqf(dev); + dev_dbg(dev->dev, "CnQF Init done\n"); + } } static void amd_pmf_deinit_features(struct amd_pmf_dev *dev) { if (is_apmf_func_supported(APMF_FUNC_STATIC_SLIDER_GRANULAR)) amd_pmf_deinit_sps(dev); + if (is_apmf_func_supported(APMF_FUNC_DYN_SLIDER_GRANULAR_AC) || + is_apmf_func_supported(APMF_FUNC_DYN_SLIDER_GRANULAR_DC)) + amd_pmf_deinit_cnqf(dev); } static const struct acpi_device_id amd_pmf_acpi_ids[] = { diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 8f318ff59c2e..452266809dfa 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -20,6 +20,8 @@ #define APMF_FUNC_SBIOS_HEARTBEAT 4 #define APMF_FUNC_SET_FAN_IDX 7 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 +#define APMF_FUNC_DYN_SLIDER_GRANULAR_AC 11 +#define APMF_FUNC_DYN_SLIDER_GRANULAR_DC 12 /* Message Definitions */ #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ @@ -51,6 +53,8 @@ struct apmf_if_functions { bool sbios_heartbeat; bool fan_table_idx; bool static_slider_granular; + bool dyn_slider_ac; + bool dyn_slider_dc; }; struct apmf_notification_cfg { @@ -163,6 +167,8 @@ struct amd_pmf_dev { #if IS_ENABLED(CONFIG_DEBUG_FS) struct dentry *dbgfs_dir; #endif /* CONFIG_DEBUG_FS */ + bool cnqf_feat; + bool cnqf_running; }; struct apmf_sps_prop_granular { @@ -191,6 +197,106 @@ struct fan_table_control { unsigned long fan_id; }; +struct power_table_control { + u32 spl; + u32 sppt; + u32 fppt; + u32 sppt_apu_only; + u32 stt_min; + u32 stt_skin_temp[STT_TEMP_COUNT]; + u32 reserved[16]; +}; + +/* CnQF Layer */ +enum cnqf_trans_priority { + CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ + CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ + CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ + CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ + CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ + CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ + CNQF_TRANSITION_MAX, +}; + +enum cnqf_mode { + CNQF_MODE_QUIET, + CNQF_MODE_BALANCE, + CNQF_MODE_PERFORMANCE, + CNQF_MODE_TURBO, + CNQF_MODE_MAX, +}; + +enum apmf_cnqf_pos { + APMF_CNQF_TURBO, + APMF_CNQF_PERFORMANCE, + APMF_CNQF_BALANCE, + APMF_CNQF_QUIET, + APMF_CNQF_MAX, +}; + +struct cnqf_mode_settings { + struct power_table_control power_control; + struct fan_table_control fan_control; + u32 power_floor; + bool enable; +}; + +struct cnqf_tran_params { + u32 time_constant; /* minimum time required to switch to next mode */ + u32 power_delta; /* minimum power required to switch to next mode */ + u32 power_threshold; + u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ + u32 total_power; + u32 count; + bool enable; + bool priority; + bool shifting_up; + enum cnqf_mode target_mode; +}; + +struct cnqf_power_delta { + u32 to_turbo; + u32 balance_to_perf; + u32 quiet_to_balance; + u32 to_quiet; + u32 perf_to_balance; + u32 turbo_to_perf; +}; + +struct cnqf_config { + struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; + struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; + struct power_table_control defaults; + enum cnqf_mode current_mode; + struct cnqf_power_delta power_delta[POWER_SOURCE_MAX]; + u32 power_src; + u32 avg_power; + enum cnqf_trans_priority trans_prio[CNQF_TRANSITION_MAX]; +}; + +struct apmf_cnqf_power_set { + u32 pfloor; + u32 fppt; + u32 sppt; + u32 sppt_apu_only; + u32 spl; + u32 stt_min_limit; + u8 stt_skintemp[STT_TEMP_COUNT]; + u32 fan_id; +} __packed; + +struct apmf_dyn_slider_output { + u16 size; + u16 flags; + u32 t_perf_to_turbo; + u32 t_balanced_to_perf; + u32 t_quiet_to_balanced; + u32 t_balanced_to_quiet; + u32 t_perf_to_balanced; + u32 t_turbo_to_perf; + struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; +}; + /* Core Layer */ int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); @@ -210,4 +316,13 @@ int apmf_get_static_slider_granular(struct apmf_if *ampf_if, void amd_pmf_load_defaults_sps(struct amd_pmf_dev *dev); int apmf_update_fan_idx(struct apmf_if *ampf_if, bool manual, u32 idx); + +/* CnQF Layer */ +int apmf_get_dyn_slider_def_ac(struct apmf_if *ampf_if, struct apmf_dyn_slider_output *data); +int apmf_get_dyn_slider_def_dc(struct apmf_if *ampf_if, struct apmf_dyn_slider_output *data); +void amd_pmf_init_cnqf(struct amd_pmf_dev *dev); +void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); +void amd_pmf_load_defaults_cnqf(struct amd_pmf_dev *dev); +void amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); + #endif /* PMF_H */ From patchwork Tue Jul 12 14:58:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 306C1C43334 for ; Tue, 12 Jul 2022 15:04:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233098AbiGLPER (ORCPT ); Tue, 12 Jul 2022 11:04:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233905AbiGLPDF (ORCPT ); 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Tue, 12 Jul 2022 09:59:47 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH v1 10/15] platform/x86/amd/pmf: Add sysfs to toggle CnQF Date: Tue, 12 Jul 2022 20:28:42 +0530 Message-ID: <20220712145847.3438544-11-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d1204096-2653-4df1-5925-08da64172b5b X-MS-TrafficTypeDiagnostic: MN2PR12MB4437:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6BkgZBYdo5lxqTjZ+MKhWN58CbMFGW7By/XK2b+SRJpORqzvRmZfHv08F5bROQpZorNpcV8u59iMhDHWScxAgabMpDHMNdj87RNZ6j5ZhN7aTaaLJexF/Kj1TZ2Og+fyvMGKd/wIKT0pQYSlPgMX8nojiv1JebFE6htUv2g6+p4VxLzKmG36R1AmiCHUJEsBqRmAZosrDOoE/nsvZ/38P766SM8NptuXbXRWohVtWf6Jx0ya1PazzEgrCJqN+MnPRJAAZM6RoePMO82sqnzRIT6k27353ek+UsaSyXf96feL9l/spJI4yXOwNzPYtyPt/HMe4q9hWyWyu5iet46YP1sKKjy2MxfkYjuEBf1CdIP4sOzX0Dvul8uvYiV+SJ4YsKRl9gVaWWtj1iUKKHZ8aMxZljRUG5hnyQQfwxoP80ipRnglgMzbOuEUg2E+Xr5Au/DKBqMjcu6u7md/eRsX41gi9nmHraliiHXv129oFuPeiLyzuPsXQDFN1HQF/Kc4jMJZt8NWeJI47NpRqyt1F1Ra0/Rbok60cqkRU/TZtClhzVKq9Hmf6bDg08wr1uHfThOXUibnAk/mwmkNrvUbx8QP0g649QjaSxczQxBzgy6b1mj9r4MpLezDG98rXE/hvkq+MfZT5wMXBlJfOrAUk0Dqk3+XNcXKWQJMytgCIZqGStQCG9A9mhETeezj2m0T4KcqM5iQtzCi6Oc8f2J5PN0kUscERSbyIt+x0Mk1hjFhGO9KZ6NeFNqAMq9X/SM2eEgqjnIREhZWG7UGu1Wv6QqJVNLQZwINxsjqBxiiIgbffDiKsRF17vDAhChOywAZ6YKgsXEYI7NlWc5tBIPV5vP+MiDAz2dR6nPLf4Jn0SI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(346002)(136003)(376002)(396003)(46966006)(36840700001)(40470700004)(8676002)(5660300002)(70206006)(16526019)(4326008)(70586007)(54906003)(82310400005)(40460700003)(336012)(186003)(110136005)(47076005)(426003)(8936002)(2616005)(36756003)(86362001)(478600001)(356005)(2906002)(7696005)(41300700001)(26005)(6666004)(82740400003)(1076003)(40480700001)(81166007)(316002)(36860700001)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:49.9997 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1204096-2653-4df1-5925-08da64172b5b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4437 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Whether to turn CnQF on/off by default upon driver load would be decided by a BIOS flag. Add a sysfs node to provide a way to the user whether to use static slider or CnQF . Signed-off-by: Shyam Sundar S K Reviewed-by: Hans de Goede --- drivers/platform/x86/amd/pmf/cnqf.c | 52 +++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/platform/x86/amd/pmf/cnqf.c b/drivers/platform/x86/amd/pmf/cnqf.c index 8c6756faab25..2b03ae1ad37f 100644 --- a/drivers/platform/x86/amd/pmf/cnqf.c +++ b/drivers/platform/x86/amd/pmf/cnqf.c @@ -302,9 +302,59 @@ void amd_pmf_load_defaults_cnqf(struct amd_pmf_dev *dev) config_store.trans_prio[i] = i; } +static ssize_t feat_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct amd_pmf_dev *pdev = dev_get_drvdata(dev); + int result, src; + bool enabled; + u8 mode; + + result = kstrtobool(buf, &enabled); + if (result) + return result; + + src = amd_pmf_get_power_source(); + pdev->cnqf_feat = enabled; + if (pdev->cnqf_feat) { + amd_pmf_handle_cnqf(pdev, SLIDER_OP_SET, src, config_store.current_mode, NULL); + } else { + pdev->cnqf_running = false; + mode = amd_pmf_get_pprof_modes(pdev); + amd_pmf_update_slider(pdev, SLIDER_OP_SET, mode, NULL); + } + + dev_dbg(pdev->dev, "Received CnQF %s\n", enabled ? "on" : "off"); + return count; +} + +static ssize_t feat_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct amd_pmf_dev *pdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", pdev->cnqf_feat ? "on" : "off"); +} + +static DEVICE_ATTR_RW(feat); + +static struct attribute *cnqf_feature_attrs[] = { + &dev_attr_feat.attr, + NULL +}; + +static const struct attribute_group cnqf_feature_attribute_group = { + .attrs = cnqf_feature_attrs, + .name = "cnqf" +}; + void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev) { cancel_delayed_work_sync(&dev->work_buffer); + sysfs_remove_group(&dev->dev->kobj, &cnqf_feature_attribute_group); + kobject_uevent(&dev->dev->kobj, KOBJ_CHANGE); } void amd_pmf_init_cnqf(struct amd_pmf_dev *dev) @@ -324,4 +374,6 @@ void amd_pmf_init_cnqf(struct amd_pmf_dev *dev) /* update the thermal for CnQF */ src = amd_pmf_get_power_source(); amd_pmf_handle_cnqf(dev, SLIDER_OP_SET, src, config_store.current_mode, NULL); + ret = sysfs_create_group(&dev->dev->kobj, &cnqf_feature_attribute_group); + kobject_uevent(&dev->dev->kobj, KOBJ_CHANGE); } From patchwork Tue Jul 12 14:58:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB630CCA485 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT065.mail.protection.outlook.com (10.13.177.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Tue, 12 Jul 2022 14:59:51 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 12 Jul 2022 09:59:49 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH v1 11/15] Documentation/ABI/testing/sysfs-amd-pmf: Add ABI doc for AMD PMF Date: Tue, 12 Jul 2022 20:28:43 +0530 Message-ID: <20220712145847.3438544-12-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f5fc5ee6-a37d-4f2e-5de2-08da64172c89 X-MS-TrafficTypeDiagnostic: MW4PR12MB5644:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:51.9790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5fc5ee6-a37d-4f2e-5de2-08da64172c89 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5644 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org AMD PMF driver provides the flexibility to turn "on" or "off" CnQF feature (introduced in the earlier patch). Add corresponding ABI documentation for the new sysfs node. Signed-off-by: Shyam Sundar S K Reviewed-by: Hans de Goede --- Documentation/ABI/testing/sysfs-amd-pmf | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-amd-pmf diff --git a/Documentation/ABI/testing/sysfs-amd-pmf b/Documentation/ABI/testing/sysfs-amd-pmf new file mode 100644 index 000000000000..5935dc549185 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-amd-pmf @@ -0,0 +1,11 @@ +What: /sys/devices/platform/AMDI0102\:00/cnqf/feat +Date: July 2022 +Contact: Shyam Sundar S K +Description: Reading this file tells if the AMD Platform Management(PMF) + Cool n Quiet Framework(CnQF) feature is enabled or not. + + This feature is not enabled by default and gets only turned on + if OEM BIOS passes a "flag" to PMF ACPI function (index 11 or 12) + or in case the user writes "on". + + To turn off CnQF user can write "off" to the sysfs node. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 14:59:54.1840 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80ca96d2-955b-4ec9-6e58-08da64172dd7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1820 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org The objective of this feature is to track the moving average of system power over the time period specified and switch to the subsequent mode. This feature has 3 modes: quiet, balanced, performance. In order to do this, PMF driver will get the moving average of APU power from PMFW and power threshold, time constants, system config parameters from OEM inputs. System power as read by PMF driver from PMFW is the filtered value over the sampling window. Every sampling window, moving average of system power is computed. At the end of the monitoring window, the moving average is compared against the threshold for mode switch for decision making. With AMD managing the system config limits, any mode switch within auto-mode will result in limits of fPPT/sPPT/STAPM or STT being scaled down. When "auto mode" is enabled, the static slider control remains out of the PMF driver, so the platform_profile registration would not happen in PMF driver. The transition to auto-mode only happens when the APMF fn5 is enabled in BIOS, platform_profile set to "balanced" and a AMT (Auto Mode transition) is received. Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmf/Makefile | 2 +- drivers/platform/x86/amd/pmf/acpi.c | 28 ++ drivers/platform/x86/amd/pmf/auto-mode.c | 317 +++++++++++++++++++++++ drivers/platform/x86/amd/pmf/core.c | 25 +- drivers/platform/x86/amd/pmf/pmf.h | 104 ++++++++ 5 files changed, 473 insertions(+), 3 deletions(-) create mode 100644 drivers/platform/x86/amd/pmf/auto-mode.c diff --git a/drivers/platform/x86/amd/pmf/Makefile b/drivers/platform/x86/amd/pmf/Makefile index d02a0bdc6429..2a9568bf9064 100644 --- a/drivers/platform/x86/amd/pmf/Makefile +++ b/drivers/platform/x86/amd/pmf/Makefile @@ -6,4 +6,4 @@ obj-$(CONFIG_AMD_PMF) += amd-pmf.o amd-pmf-objs := core.o acpi.o sps.o \ - cnqf.o + cnqf.o auto-mode.o diff --git a/drivers/platform/x86/amd/pmf/acpi.c b/drivers/platform/x86/amd/pmf/acpi.c index a3ff91c605b5..e9f33e61659f 100644 --- a/drivers/platform/x86/amd/pmf/acpi.c +++ b/drivers/platform/x86/amd/pmf/acpi.c @@ -55,6 +55,7 @@ static void apmf_if_parse_functions(struct apmf_if_functions *func, u32 mask) { func->system_params = mask & APMF_FUNC_GET_SYS_PARAMS; func->static_slider_granular = mask & APMF_FUNC_STATIC_SLIDER_GRANULAR; + func->auto_mode_def = mask & APMF_FUNC_AUTO_MODE; func->fan_table_idx = mask & APMF_FUNC_SET_FAN_IDX; func->dyn_slider_ac = mask & APMF_FUNC_DYN_SLIDER_GRANULAR_AC; func->dyn_slider_dc = mask & APMF_FUNC_DYN_SLIDER_GRANULAR_DC; @@ -210,6 +211,33 @@ int apmf_update_fan_idx(struct apmf_if *ampf_if, bool manual, u32 idx) return err; } +int apmf_get_auto_mode_def(struct apmf_if *ampf_if, struct apmf_auto_mode *data) +{ + union acpi_object *info; + size_t size; + int err = 0; + + info = apmf_if_call(ampf_if, APMF_FUNC_AUTO_MODE, NULL); + if (!info) + return -EIO; + + size = *(u16 *)info->buffer.pointer; + + if (size < sizeof(*data)) { + pr_debug("buffer too small %zu\n", size); + err = -EINVAL; + goto out; + } + + size = min(sizeof(*data), size); + memset(data, 0, sizeof(*data)); + memcpy(data, info->buffer.pointer, size); + +out: + kfree(info); + return err; +} + int apmf_get_dyn_slider_def_ac(struct apmf_if *ampf_if, struct apmf_dyn_slider_output *data) { union acpi_object *info; diff --git a/drivers/platform/x86/amd/pmf/auto-mode.c b/drivers/platform/x86/amd/pmf/auto-mode.c new file mode 100644 index 000000000000..954fde25e71e --- /dev/null +++ b/drivers/platform/x86/amd/pmf/auto-mode.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Platform Management Framework Driver + * + * Copyright (c) 2022, Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Author: Shyam Sundar S K + */ + +#include +#include +#include +#include "pmf.h" + +#define AVG_SAMPLE_SIZE 3 + +struct power_history { + int socket_power; + struct list_head list; + int avg; + int total; +}; + +struct list_pdata { + int total; + int avg; +}; + +static struct power_history power_list; +static struct list_pdata pdata; + +static struct auto_mode_mode_config config_store; +static const char *state_as_str(unsigned int state); + +static void amd_pmf_handle_automode(struct amd_pmf_dev *dev, bool op, int idx, + struct auto_mode_mode_config *table) +{ + if (op == SLIDER_OP_SET) { + struct power_table_control *pwr_ctrl = &config_store.mode_set[idx].power_control; + + amd_pmf_send_cmd(dev, SET_SPL, false, pwr_ctrl->spl, NULL); + amd_pmf_send_cmd(dev, SET_FPPT, false, pwr_ctrl->fppt, NULL); + amd_pmf_send_cmd(dev, SET_SPPT, false, pwr_ctrl->sppt, NULL); + amd_pmf_send_cmd(dev, SET_SPPT_APU_ONLY, false, pwr_ctrl->sppt_apu_only, NULL); + amd_pmf_send_cmd(dev, SET_STT_MIN_LIMIT, false, pwr_ctrl->stt_min, NULL); + amd_pmf_send_cmd(dev, SET_STT_LIMIT_APU, false, + pwr_ctrl->stt_skin_temp[STT_TEMP_APU], NULL); + amd_pmf_send_cmd(dev, SET_STT_LIMIT_HS2, false, + pwr_ctrl->stt_skin_temp[STT_TEMP_HS2], NULL); + } else if (op == SLIDER_OP_GET) { + amd_pmf_send_cmd(dev, GET_SPL, true, ARG_NONE, + &table->mode_set[idx].power_control.spl); + amd_pmf_send_cmd(dev, GET_FPPT, true, ARG_NONE, + &table->mode_set[idx].power_control.fppt); + amd_pmf_send_cmd(dev, GET_SPPT, true, ARG_NONE, + &table->mode_set[idx].power_control.sppt); + amd_pmf_send_cmd(dev, GET_SPPT_APU_ONLY, true, ARG_NONE, + &table->mode_set[idx].power_control.sppt_apu_only); + amd_pmf_send_cmd(dev, GET_STT_MIN_LIMIT, true, ARG_NONE, + &table->mode_set[idx].power_control.stt_min); + amd_pmf_send_cmd(dev, GET_STT_LIMIT_APU, true, ARG_NONE, + &table->mode_set[idx].power_control.stt_skin_temp[STT_TEMP_APU]); + amd_pmf_send_cmd(dev, GET_STT_LIMIT_HS2, true, ARG_NONE, + &table->mode_set[idx].power_control.stt_skin_temp[STT_TEMP_HS2]); + } + + if (dev->apmf_if->func.fan_table_idx) + apmf_update_fan_idx(dev->apmf_if, config_store.mode_set[idx].fan_control.manual, + config_store.mode_set[idx].fan_control.fan_id); +} + +static int amd_pmf_get_moving_avg(int socket_power) +{ + struct power_history *tmp; + struct list_head *pos, *q; + static int count; + + tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); + tmp->socket_power = socket_power; + list_add_tail(&tmp->list, &power_list.list); + + list_for_each_safe(pos, q, &power_list.list) { + if (count >= AVG_SAMPLE_SIZE) { + tmp = list_first_entry(pos, struct power_history, list); + list_del_init(pos); + goto next; + } + } + +next: + pdata.total = 0; + pdata.avg = 0; + + list_for_each(pos, &power_list.list) { + tmp = list_entry(pos, struct power_history, list); + pdata.total += tmp->socket_power; + pdata.avg = pdata.total / AVG_SAMPLE_SIZE; + } + + count++; + if (count >= AVG_SAMPLE_SIZE) + return pdata.avg; + + return 0; +} + +void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms) +{ + int avg_power = 0; + bool update = false; + int i, j; + + /* Get the average moving average computed by auto mode algorithm */ + avg_power = amd_pmf_get_moving_avg(socket_power); + + for (i = 0; i < AUTO_TRANSITION_MAX; i++) { + if ((config_store.transition[i].shifting_up && avg_power >= + config_store.transition[i].power_threshold) || + (!config_store.transition[i].shifting_up && avg_power <= + config_store.transition[i].power_threshold)) { + if (config_store.transition[i].timer < + config_store.transition[i].time_constant) + config_store.transition[i].timer += time_elapsed_ms; + } else { + config_store.transition[i].timer = 0; + } + + if (config_store.transition[i].timer >= + config_store.transition[i].time_constant && + !config_store.transition[i].applied) { + config_store.transition[i].applied = true; + update = true; + } else if (config_store.transition[i].timer <= + config_store.transition[i].time_constant && + config_store.transition[i].applied) { + config_store.transition[i].applied = false; + update = true; + } + } + + dev_dbg(dev->dev, "[AUTO_MODE] avg power: %u mW mode: %s\n", avg_power, + state_as_str(config_store.current_mode)); + + if (update) { + for (j = 0; j < AUTO_TRANSITION_MAX; j++) { + /* Apply the mode with highest priority indentified */ + if (config_store.transition[j].applied) { + if (config_store.current_mode != + config_store.transition[j].target_mode) { + config_store.current_mode = + config_store.transition[j].target_mode; + dev_dbg(dev->dev, "[AUTO_MODE] moving to mode:%s\n", + state_as_str(config_store.current_mode)); + amd_pmf_handle_automode(dev, SLIDER_OP_SET, + config_store.current_mode, NULL); + } + break; + } + } + } +} + +static void amd_pmf_get_power_threshold(void) +{ + config_store.transition[AUTO_TRANSITION_TO_QUIET].power_threshold = + config_store.mode_set[AUTO_BALANCE].power_floor - + config_store.transition[AUTO_TRANSITION_TO_QUIET].power_delta; + + config_store.transition[AUTO_TRANSITION_TO_PERFORMANCE].power_threshold = + config_store.mode_set[AUTO_BALANCE].power_floor - + config_store.transition[AUTO_TRANSITION_TO_PERFORMANCE].power_delta; + + config_store.transition[AUTO_TRANSITION_FROM_QUIET_TO_BALANCE].power_threshold = + config_store.mode_set[AUTO_QUIET].power_floor - + config_store.transition[AUTO_TRANSITION_FROM_QUIET_TO_BALANCE].power_delta; + + config_store.transition[AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE].power_threshold = + config_store.mode_set[AUTO_PERFORMANCE].power_floor - + config_store.transition[AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE].power_delta; +} + +static const char *state_as_str(unsigned int state) +{ + switch (state) { + case AUTO_QUIET: + return "QUIET"; + case AUTO_BALANCE: + return "BALANCED"; + case AUTO_PERFORMANCE_ON_LAP: + return "ON_LAP"; + case AUTO_PERFORMANCE: + return "PERFORMANCE"; + default: + return "Unknown Auto Mode State"; + } +} + +void amd_pmf_load_defaults_auto_mode(struct amd_pmf_dev *dev) +{ + struct apmf_auto_mode output; + struct power_table_control *pwr_ctrl; + int i; + + if (dev->apmf_if->func.auto_mode_def) { + apmf_get_auto_mode_def(dev->apmf_if, &output); + /* time constant */ + config_store.transition[AUTO_TRANSITION_TO_QUIET].time_constant = + output.balanced_to_quiet; + config_store.transition[AUTO_TRANSITION_TO_PERFORMANCE].time_constant = + output.balanced_to_perf; + config_store.transition[AUTO_TRANSITION_FROM_QUIET_TO_BALANCE].time_constant = + output.quiet_to_balanced; + config_store.transition[AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE].time_constant = + output.perf_to_balanced; + + /* power floor */ + config_store.mode_set[AUTO_QUIET].power_floor = output.pfloor_quiet; + config_store.mode_set[AUTO_BALANCE].power_floor = output.pfloor_balanced; + config_store.mode_set[AUTO_PERFORMANCE].power_floor = output.pfloor_perf; + config_store.mode_set[AUTO_PERFORMANCE_ON_LAP].power_floor = output.pfloor_perf; + + /* Power delta for mode change */ + config_store.transition[AUTO_TRANSITION_TO_QUIET].power_delta = + output.pd_balanced_to_quiet; + config_store.transition[AUTO_TRANSITION_TO_PERFORMANCE].power_delta = + output.pd_balanced_to_perf; + config_store.transition[AUTO_TRANSITION_FROM_QUIET_TO_BALANCE].power_delta = + output.pd_quiet_to_balanced; + config_store.transition[AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE].power_delta = + output.pd_perf_to_balanced; + + /* Power threshold */ + amd_pmf_get_power_threshold(); + + /* skin temperature limits */ + pwr_ctrl = &config_store.mode_set[AUTO_QUIET].power_control; + pwr_ctrl->spl = output.spl_quiet; + pwr_ctrl->sppt = output.sppt_quiet; + pwr_ctrl->fppt = output.fppt_quiet; + pwr_ctrl->sppt_apu_only = output.sppt_apu_only_quiet; + pwr_ctrl->stt_min = output.stt_min_limit_quiet; + pwr_ctrl->stt_skin_temp[STT_TEMP_APU] = output.stt_apu_quiet; + pwr_ctrl->stt_skin_temp[STT_TEMP_HS2] = output.stt_hs2_quiet; + + pwr_ctrl = &config_store.mode_set[AUTO_BALANCE].power_control; + pwr_ctrl->spl = output.spl_balanced; + pwr_ctrl->sppt = output.sppt_balanced; + pwr_ctrl->fppt = output.fppt_balanced; + pwr_ctrl->sppt_apu_only = output.sppt_apu_only_balanced; + pwr_ctrl->stt_min = output.stt_min_limit_balanced; + pwr_ctrl->stt_skin_temp[STT_TEMP_APU] = output.stt_apu_balanced; + pwr_ctrl->stt_skin_temp[STT_TEMP_HS2] = output.stt_hs2_balanced; + + pwr_ctrl = &config_store.mode_set[AUTO_PERFORMANCE].power_control; + pwr_ctrl->spl = output.spl_perf; + pwr_ctrl->sppt = output.sppt_perf; + pwr_ctrl->fppt = output.fppt_perf; + pwr_ctrl->sppt_apu_only = output.sppt_apu_only_perf; + pwr_ctrl->stt_min = output.stt_min_limit_perf; + pwr_ctrl->stt_skin_temp[STT_TEMP_APU] = output.stt_apu_perf; + pwr_ctrl->stt_skin_temp[STT_TEMP_HS2] = output.stt_hs2_perf; + + pwr_ctrl = &config_store.mode_set[AUTO_PERFORMANCE_ON_LAP].power_control; + pwr_ctrl->spl = output.spl_perf_on_lap; + pwr_ctrl->sppt = output.sppt_perf_on_lap; + pwr_ctrl->fppt = output.fppt_perf_on_lap; + pwr_ctrl->sppt_apu_only = output.sppt_apu_only_perf_on_lap; + pwr_ctrl->stt_min = output.stt_min_limit_perf_on_lap; + pwr_ctrl->stt_skin_temp[STT_TEMP_APU] = output.stt_apu_perf_on_lap; + pwr_ctrl->stt_skin_temp[STT_TEMP_HS2] = output.stt_hs2_perf_on_lap; + + /* Fan ID */ + config_store.mode_set[AUTO_QUIET].fan_control.fan_id = output.fan_id_quiet; + config_store.mode_set[AUTO_BALANCE].fan_control.fan_id = output.fan_id_balanced; + config_store.mode_set[AUTO_PERFORMANCE].fan_control.fan_id = output.fan_id_perf; + config_store.mode_set[AUTO_PERFORMANCE_ON_LAP].fan_control.fan_id = + output.fan_id_perf; + + config_store.transition[AUTO_TRANSITION_TO_QUIET].target_mode = AUTO_QUIET; + config_store.transition[AUTO_TRANSITION_TO_PERFORMANCE].target_mode = + AUTO_PERFORMANCE; + config_store.transition[AUTO_TRANSITION_FROM_QUIET_TO_BALANCE].target_mode = + AUTO_BALANCE; + config_store.transition[AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE].target_mode = + AUTO_BALANCE; + + config_store.transition[AUTO_TRANSITION_TO_QUIET].shifting_up = false; + config_store.transition[AUTO_TRANSITION_TO_PERFORMANCE].shifting_up = true; + config_store.transition[AUTO_TRANSITION_FROM_QUIET_TO_BALANCE].shifting_up = true; + config_store.transition[AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE].shifting_up = + false; + + for (i = 0 ; i < AUTO_MODE_MAX ; i++) { + if (config_store.mode_set[i].fan_control.fan_id == FAN_INDEX_AUTO) + config_store.mode_set[i].fan_control.manual = false; + else + config_store.mode_set[i].fan_control.manual = true; + } + } +} + +void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev) +{ + cancel_delayed_work_sync(&dev->work_buffer); +} + +void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev) +{ + INIT_LIST_HEAD(&power_list.list); + + amd_pmf_init_metrics_table(dev); + amd_pmf_load_defaults_auto_mode(dev); + + /* update the thermal for Automode */ + amd_pmf_handle_automode(dev, SLIDER_OP_SET, config_store.current_mode, NULL); +} diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index bc267d333b76..674ddf599135 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -122,6 +122,11 @@ static void amd_pmf_get_metrics(struct work_struct *work) /* Calculate the avg SoC power consumption */ socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; + if (current_profile == PLATFORM_PROFILE_BALANCED) { + /* Apply the Auto Mode transition */ + amd_pmf_trans_automode(dev, socket_power, time_elapsed_ms); + } + if (dev->cnqf_feat) { /* Apply the CnQF transition */ amd_pmf_trans_cnqf(dev, socket_power, time_elapsed_ms); @@ -260,9 +265,18 @@ static void amd_pmf_init_features(struct amd_pmf_dev *dev) amd_pmf_init_sps(dev); dev_dbg(dev->dev, "SPS enabled and Platform Profiles registered\n"); } - /* Enable Cool n Quiet Framework (CnQF) */ - if (is_apmf_func_supported(APMF_FUNC_DYN_SLIDER_GRANULAR_AC) || + + /* Enable Auto Mode */ + if (is_apmf_func_supported(APMF_FUNC_AUTO_MODE)) { + amd_pmf_init_auto_mode(dev); + dev_dbg(dev->dev, "Auto Mode Init done\n"); + /* + * Auto mode and CnQF cannot co-exist. If auto mode is supported it takes + * higher priority over CnQF. + */ + } else if (is_apmf_func_supported(APMF_FUNC_DYN_SLIDER_GRANULAR_AC) || is_apmf_func_supported(APMF_FUNC_DYN_SLIDER_GRANULAR_DC)) { + /* Enable Cool n Quiet Framework (CnQF) */ amd_pmf_init_cnqf(dev); dev_dbg(dev->dev, "CnQF Init done\n"); } @@ -272,6 +286,13 @@ static void amd_pmf_deinit_features(struct amd_pmf_dev *dev) { if (is_apmf_func_supported(APMF_FUNC_STATIC_SLIDER_GRANULAR)) amd_pmf_deinit_sps(dev); + + if (is_apmf_func_supported(APMF_FUNC_AUTO_MODE)) { + amd_pmf_deinit_auto_mode(dev); + /* If auto mode is supported, there is no need to proceed */ + return; + } + if (is_apmf_func_supported(APMF_FUNC_DYN_SLIDER_GRANULAR_AC) || is_apmf_func_supported(APMF_FUNC_DYN_SLIDER_GRANULAR_DC)) amd_pmf_deinit_cnqf(dev); diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 452266809dfa..0532f49e9613 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -18,6 +18,7 @@ #define APMF_FUNC_VERIFY_INTERFACE 0 #define APMF_FUNC_GET_SYS_PARAMS 1 #define APMF_FUNC_SBIOS_HEARTBEAT 4 +#define APMF_FUNC_AUTO_MODE 5 #define APMF_FUNC_SET_FAN_IDX 7 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 #define APMF_FUNC_DYN_SLIDER_GRANULAR_AC 11 @@ -51,6 +52,7 @@ struct apmf_if_functions { bool system_params; bool sbios_heartbeat; + bool auto_mode_def; bool fan_table_idx; bool static_slider_granular; bool dyn_slider_ac; @@ -197,6 +199,33 @@ struct fan_table_control { unsigned long fan_id; }; +/* Auto Mode Layer */ +enum auto_mode_transition_priority { + AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ + AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ + AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ + AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ + AUTO_TRANSITION_MAX, +}; + +enum auto_mode_mode { + AUTO_QUIET, + AUTO_BALANCE, + AUTO_PERFORMANCE_ON_LAP, + AUTO_PERFORMANCE, + AUTO_MODE_MAX, +}; + +struct auto_mode_trans_params { + u32 time_constant; /* minimum time required to switch to next mode */ + u32 power_delta; /* delta power to shift mode */ + u32 power_threshold; + u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ + u32 applied; + enum auto_mode_mode target_mode; + u32 shifting_up; +}; + struct power_table_control { u32 spl; u32 sppt; @@ -207,6 +236,74 @@ struct power_table_control { u32 reserved[16]; }; +struct auto_mode_mode_settings { + struct power_table_control power_control; + struct fan_table_control fan_control; + u32 power_floor; +}; + +struct auto_mode_mode_config { + struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; + struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; + enum auto_mode_mode current_mode; + bool on_lap; + bool better_perf; + u32 amt_enabled; /* Auto Mode Transition */ + u32 avg_power; +}; + +struct apmf_auto_mode { + u16 size; + /* time constant */ + u32 balanced_to_perf; + u32 perf_to_balanced; + u32 quiet_to_balanced; + u32 balanced_to_quiet; + /* power floor */ + u32 pfloor_perf; + u32 pfloor_balanced; + u32 pfloor_quiet; + /* Power delta for mode change */ + u32 pd_balanced_to_perf; + u32 pd_perf_to_balanced; + u32 pd_quiet_to_balanced; + u32 pd_balanced_to_quiet; + /* skin temperature limits */ + u8 stt_apu_perf_on_lap; /* CQL ON */ + u8 stt_hs2_perf_on_lap; /* CQL ON */ + u8 stt_apu_perf; + u8 stt_hs2_perf; + u8 stt_apu_balanced; + u8 stt_hs2_balanced; + u8 stt_apu_quiet; + u8 stt_hs2_quiet; + u32 stt_min_limit_perf_on_lap; /* CQL ON */ + u32 stt_min_limit_perf; + u32 stt_min_limit_balanced; + u32 stt_min_limit_quiet; + /* SPL based */ + u32 fppt_perf_on_lap; /* CQL ON */ + u32 sppt_perf_on_lap; /* CQL ON */ + u32 spl_perf_on_lap; /* CQL ON */ + u32 sppt_apu_only_perf_on_lap; /* CQL ON */ + u32 fppt_perf; + u32 sppt_perf; + u32 spl_perf; + u32 sppt_apu_only_perf; + u32 fppt_balanced; + u32 sppt_balanced; + u32 spl_balanced; + u32 sppt_apu_only_balanced; + u32 fppt_quiet; + u32 sppt_quiet; + u32 spl_quiet; + u32 sppt_apu_only_quiet; + /* Fan ID */ + u32 fan_id_perf; + u32 fan_id_balanced; + u32 fan_id_quiet; +} __packed; + /* CnQF Layer */ enum cnqf_trans_priority { CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ @@ -317,6 +414,13 @@ void amd_pmf_load_defaults_sps(struct amd_pmf_dev *dev); int apmf_update_fan_idx(struct apmf_if *ampf_if, bool manual, u32 idx); +/* Auto Mode Layer */ +void amd_pmf_load_defaults_auto_mode(struct amd_pmf_dev *dev); +int apmf_get_auto_mode_def(struct apmf_if *ampf_if, struct apmf_auto_mode *data); +void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); +void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); +void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); + /* CnQF Layer */ int apmf_get_dyn_slider_def_ac(struct apmf_if *ampf_if, struct apmf_dyn_slider_output *data); int apmf_get_dyn_slider_def_dc(struct apmf_if *ampf_if, struct apmf_dyn_slider_output *data); From patchwork Tue Jul 12 14:58:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70519CCA47C for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT055.mail.protection.outlook.com (10.13.177.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Tue, 12 Jul 2022 15:00:11 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 12 Jul 2022 09:59:53 -0500 From: Shyam Sundar S K To: , CC: , , "Shyam Sundar S K" Subject: [PATCH v1 13/15] platform/x86/amd/pmf: Handle AMT and CQL events for Auto mode Date: Tue, 12 Jul 2022 20:28:45 +0530 Message-ID: <20220712145847.3438544-14-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> References: <20220712145847.3438544-1-Shyam-sundar.S-k@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b5206451-0621-419a-d8e2-08da641738cd X-MS-TrafficTypeDiagnostic: BY5PR12MB4260:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 15:00:11.8730 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b5206451-0621-419a-d8e2-08da641738cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4260 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org The transition to auto-mode happens when the PMF driver receives AMT (Auto Mode transition) event. transition logic will reside in the PMF driver but the events would come from other supported drivers[1]. The thermal parameters would vary between when a performance "on-lap" mode is detected and versus when not. The CQL event would get triggered from other drivers, so that PMF driver would adjust the system thermal config based on the ACPI inputs. OEMs can control whether or not to enable AMT or CQL via other supported drivers[1] but the actual transition logic resides in the AMD PMF driver. When an AMT event is received the automatic mode transition RAPL algorithm will run. When a CQL event is received an performance "on-lap" mode will be enabled and thermal parameters will be adjusted accordingly. [1] Link: https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git/commit/?h=review-hans&id=755b249250df1b612d982f3b702c831b26ecdf73 Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmf/acpi.c | 90 +++++++++++++++++++++++- drivers/platform/x86/amd/pmf/auto-mode.c | 22 ++++++ drivers/platform/x86/amd/pmf/cnqf.c | 4 +- drivers/platform/x86/amd/pmf/core.c | 18 ++++- drivers/platform/x86/amd/pmf/pmf.h | 29 +++++++- 5 files changed, 156 insertions(+), 7 deletions(-) diff --git a/drivers/platform/x86/amd/pmf/acpi.c b/drivers/platform/x86/amd/pmf/acpi.c index e9f33e61659f..4bde86aeafa0 100644 --- a/drivers/platform/x86/amd/pmf/acpi.c +++ b/drivers/platform/x86/amd/pmf/acpi.c @@ -12,6 +12,8 @@ #include "pmf.h" #define APMF_METHOD "\\_SB_.PMF_.APMF" +#define APMF_CQL_NOTIFICATION 2 +#define APMF_AMT_NOTIFICATION 3 static unsigned long supported_func; @@ -55,6 +57,7 @@ static void apmf_if_parse_functions(struct apmf_if_functions *func, u32 mask) { func->system_params = mask & APMF_FUNC_GET_SYS_PARAMS; func->static_slider_granular = mask & APMF_FUNC_STATIC_SLIDER_GRANULAR; + func->sbios_requests = mask & APMF_FUNC_SBIOS_REQUESTS; func->auto_mode_def = mask & APMF_FUNC_AUTO_MODE; func->fan_table_idx = mask & APMF_FUNC_SET_FAN_IDX; func->dyn_slider_ac = mask & APMF_FUNC_DYN_SLIDER_GRANULAR_AC; @@ -292,6 +295,36 @@ int apmf_get_dyn_slider_def_dc(struct apmf_if *ampf_if, struct apmf_dyn_slider_o return err; } +int apmf_get_sbios_requests(struct apmf_if *ampf_if, struct apmf_sbios_req *req) +{ + union acpi_object *info; + size_t size; + int err = 0; + + info = apmf_if_call(ampf_if, APMF_FUNC_SBIOS_REQUESTS, NULL); + if (!info) + return -EIO; + + size = *(u16 *)info->buffer.pointer; + + if (size < sizeof(union acpi_object)) { + pr_err("PMF: buffer too small %zu\n", size); + err = -EINVAL; + goto out; + } + + size = min(sizeof(*req), size); + memset(req, 0, sizeof(*req)); + memcpy(req, info->buffer.pointer, size); + + pr_debug("PMF: %s: pending_req:%d cql:%d amt:%d\n", __func__, + req->pending_req, req->cql_event, req->amt_event); + +out: + kfree(info); + return err; +} + static acpi_handle apmf_if_probe_handle(void) { acpi_handle handle = NULL; @@ -312,18 +345,62 @@ static acpi_handle apmf_if_probe_handle(void) return handle; } +static void apmf_event_handler(acpi_handle handle, u32 event, void *data) +{ + struct amd_pmf_dev *pmf_dev = data; + struct apmf_if *apmf_if = pmf_dev->apmf_if; + int ret; + + if (apmf_if->func.sbios_requests) { + struct apmf_sbios_req req; + + ret = apmf_get_sbios_requests(apmf_if, &req); + if (ret) { + dev_err(pmf_dev->dev, "Failed to get SBIOS requests:%d\n", ret); + return; + } + if (req.pending_req & BIT(APMF_AMT_NOTIFICATION)) { + pr_debug("PMF: AMT is supported and notifications %s\n", + req.amt_event ? "Enabled" : "Disabled"); + if (req.amt_event) + pmf_dev->is_amt_event = true; + else + pmf_dev->is_amt_event = !!req.amt_event; + } + + if (req.pending_req & BIT(APMF_CQL_NOTIFICATION)) { + pr_debug("PMF: CQL is supported and notifications %s\n", + req.cql_event ? "Enabled" : "Disabled"); + if (req.cql_event) + pmf_dev->is_cql_event = true; + else + pmf_dev->is_cql_event = !!req.cql_event; + + /* update the target mode information */ + amd_pmf_update_2_cql(pmf_dev); + } + } +} + void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev) { + acpi_handle ahandle = ACPI_HANDLE(pmf_dev->dev); + if (pmf_dev->apmf_if->func.sbios_heartbeat) cancel_delayed_work_sync(&pmf_dev->heart_beat); + + if (is_apmf_func_supported(APMF_FUNC_AUTO_MODE)) + acpi_remove_notify_handler(ahandle, ACPI_ALL_NOTIFY, + apmf_event_handler); } int apmf_acpi_init(struct amd_pmf_dev *pmf_dev) { + acpi_handle ahandle = ACPI_HANDLE(pmf_dev->dev); struct apmf_notification_cfg *n; acpi_handle apmf_if_handle; struct apmf_if *apmf_if; - int ret; + int ret, status; apmf_if_handle = apmf_if_probe_handle(); if (!apmf_if_handle) @@ -360,6 +437,17 @@ int apmf_acpi_init(struct amd_pmf_dev *pmf_dev) schedule_delayed_work(&pmf_dev->heart_beat, 0); } + /* Install the APMF Notify handler */ + if (is_apmf_func_supported(APMF_FUNC_AUTO_MODE)) { + status = acpi_install_notify_handler(ahandle, + ACPI_ALL_NOTIFY, + apmf_event_handler, pmf_dev); + if (ACPI_FAILURE(status)) { + dev_err(pmf_dev->dev, "failed to install notify handler\n"); + return -ENODEV; + } + } + out: return ret; } diff --git a/drivers/platform/x86/amd/pmf/auto-mode.c b/drivers/platform/x86/amd/pmf/auto-mode.c index 954fde25e71e..a85ef4b95cdb 100644 --- a/drivers/platform/x86/amd/pmf/auto-mode.c +++ b/drivers/platform/x86/amd/pmf/auto-mode.c @@ -111,6 +111,13 @@ void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t t bool update = false; int i, j; + if (!dev->amt_running && dev->is_amt_event) { + dev_dbg(dev->dev, "setting AMT thermals\n"); + amd_pmf_handle_automode(dev, SLIDER_OP_SET, config_store.current_mode, NULL); + dev->amt_running = true; + return; + } + /* Get the average moving average computed by auto mode algorithm */ avg_power = amd_pmf_get_moving_avg(socket_power); @@ -161,6 +168,21 @@ void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t t } } +void amd_pmf_update_2_cql(struct amd_pmf_dev *dev) +{ + config_store.transition[AUTO_TRANSITION_TO_PERFORMANCE].target_mode = + dev->is_cql_event ? AUTO_PERFORMANCE_ON_LAP : AUTO_PERFORMANCE; + if ((config_store.current_mode == AUTO_PERFORMANCE || + config_store.current_mode == AUTO_PERFORMANCE_ON_LAP) && + config_store.current_mode != + config_store.transition[AUTO_TRANSITION_TO_PERFORMANCE].target_mode) { + config_store.current_mode = + config_store.transition[AUTO_TRANSITION_TO_PERFORMANCE].target_mode; + amd_pmf_handle_automode(dev, SLIDER_OP_SET, config_store.current_mode, NULL); + } + dev_dbg(dev->dev, "updated CQL thermals\n"); +} + static void amd_pmf_get_power_threshold(void) { config_store.transition[AUTO_TRANSITION_TO_QUIET].power_threshold = diff --git a/drivers/platform/x86/amd/pmf/cnqf.c b/drivers/platform/x86/amd/pmf/cnqf.c index 2b03ae1ad37f..eba8f0d79a62 100644 --- a/drivers/platform/x86/amd/pmf/cnqf.c +++ b/drivers/platform/x86/amd/pmf/cnqf.c @@ -101,7 +101,7 @@ static const char *state_as_str(unsigned int state) } } -void amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms) +void amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms) { struct cnqf_tran_params *tp; int src, i, j, index = 0; @@ -117,7 +117,7 @@ void amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_ } for (i = 0; i < CNQF_TRANSITION_MAX; i++) { - config_store.trans_param[src][i].timer += time_lapsed_ms; + config_store.trans_param[src][i].timer += time_elapsed_ms; config_store.trans_param[src][i].total_power += socket_power; config_store.trans_param[src][i].count++; diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index 674ddf599135..2a3dacfb2005 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -109,10 +109,15 @@ static void amd_pmf_get_metrics(struct work_struct *work) enum platform_profile_option current_profile; ktime_t time_elapsed_ms; int socket_power; + u8 mode; /* Get the current profile information */ platform_profile_get(¤t_profile); + if (!dev->is_amt_event) + dev_dbg(dev->dev, "%s amt event: %s\n", __func__, + dev->is_amt_event ? "Enabled" : "Disabled"); + /* Transfer table contents */ memset(&dev->m_table, 0, sizeof(dev->m_table)); amd_pmf_send_cmd(dev, SET_TRANSFER_TABLE, 0, 7, NULL); @@ -123,8 +128,17 @@ static void amd_pmf_get_metrics(struct work_struct *work) socket_power = dev->m_table.apu_power + dev->m_table.dgpu_power; if (current_profile == PLATFORM_PROFILE_BALANCED) { - /* Apply the Auto Mode transition */ - amd_pmf_trans_automode(dev, socket_power, time_elapsed_ms); + if (dev->is_amt_event) { + /* Apply the Auto Mode transition */ + amd_pmf_trans_automode(dev, socket_power, time_elapsed_ms); + } else if (!dev->is_amt_event && dev->amt_running) { + pr_debug("resetting AMT thermals\n"); + mode = amd_pmf_get_pprof_modes(dev); + amd_pmf_update_slider(dev, SLIDER_OP_SET, mode, NULL); + dev->amt_running = false; + } + } else { + dev->amt_running = false; } if (dev->cnqf_feat) { diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 0532f49e9613..9ae9812353cd 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -17,6 +17,7 @@ /* APMF Functions */ #define APMF_FUNC_VERIFY_INTERFACE 0 #define APMF_FUNC_GET_SYS_PARAMS 1 +#define APMF_FUNC_SBIOS_REQUESTS 2 #define APMF_FUNC_SBIOS_HEARTBEAT 4 #define APMF_FUNC_AUTO_MODE 5 #define APMF_FUNC_SET_FAN_IDX 7 @@ -51,6 +52,7 @@ /* AMD PMF BIOS interfaces */ struct apmf_if_functions { bool system_params; + bool sbios_requests; bool sbios_heartbeat; bool auto_mode_def; bool fan_table_idx; @@ -84,6 +86,24 @@ struct apmf_system_params { u32 heartbeat_int; } __packed; +struct apmf_sbios_req { + u16 size; + u32 pending_req; + u8 rsd; + u8 cql_event; + u8 amt_event; + u32 fppt; + u32 sppt; + u32 fppt_apu_only; + u32 spl; + u32 stt_min_limit; + u8 skin_temp_apu; + u8 skin_temp_hs2; + u8 dps_enable; + u32 custom_policy_1; + u32 custom_policy_2; +} __packed; + struct apmf_fan_idx { u16 size; u8 fan_ctl_mode; @@ -171,6 +191,9 @@ struct amd_pmf_dev { #endif /* CONFIG_DEBUG_FS */ bool cnqf_feat; bool cnqf_running; + bool is_amt_event; + bool is_cql_event; + bool amt_running; }; struct apmf_sps_prop_granular { @@ -417,9 +440,11 @@ int apmf_update_fan_idx(struct apmf_if *ampf_if, bool manual, u32 idx); /* Auto Mode Layer */ void amd_pmf_load_defaults_auto_mode(struct amd_pmf_dev *dev); int apmf_get_auto_mode_def(struct apmf_if *ampf_if, struct apmf_auto_mode *data); +int apmf_get_sbios_requests(struct apmf_if *ampf_if, struct apmf_sbios_req *req); void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); -void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); +void amd_pmf_update_2_cql(struct amd_pmf_dev *dev); +void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); /* CnQF Layer */ int apmf_get_dyn_slider_def_ac(struct apmf_if *ampf_if, struct apmf_dyn_slider_output *data); @@ -427,6 +452,6 @@ int apmf_get_dyn_slider_def_dc(struct apmf_if *ampf_if, struct apmf_dyn_slider_o void amd_pmf_init_cnqf(struct amd_pmf_dev *dev); void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); void amd_pmf_load_defaults_cnqf(struct amd_pmf_dev *dev); -void amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); +void amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); #endif /* PMF_H */ From patchwork Tue Jul 12 14:58:46 2022 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 15:00:14.3899 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 141a80e4-a6b1-4d1a-fec2-08da641739e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3635 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Some of the older platforms with _HID "AMDI0100" PMF driver can be force loaded by interested users but only for experimental purposes. Signed-off-by: Shyam Sundar S K Reviewed-by: Hans de Goede --- drivers/platform/x86/amd/pmf/core.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index 2a3dacfb2005..ef50d67f6013 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -39,6 +39,7 @@ #define AMD_PMF_RESULT_FAILED 0xFF /* List of supported CPU ids */ +#define AMD_CPU_ID_RMB 0x14b5 #define AMD_CPU_ID_PS 0x14e8 #define PMF_MSG_DELAY_MIN_US 50 @@ -52,6 +53,11 @@ static int metrics_table_loop_ms = 1000; module_param(metrics_table_loop_ms, int, 0644); MODULE_PARM_DESC(metrics_table_loop_ms, " Metrics Table sample size time (default = 1000ms) "); +/* Force load on supported older platforms */ +static bool force_load; +module_param(force_load, bool, 0444); +MODULE_PARM_DESC(force_load, " Force load this driver on supported older platforms (experimental) "); + #ifdef CONFIG_DEBUG_FS static int current_power_limits_show(struct seq_file *seq, void *unused) { @@ -240,6 +246,7 @@ int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 } static const struct pci_device_id pmf_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RMB) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) }, { } }; @@ -313,6 +320,7 @@ static void amd_pmf_deinit_features(struct amd_pmf_dev *dev) } static const struct acpi_device_id amd_pmf_acpi_ids[] = { + {"AMDI0100", 0x100}, {"AMDI0102", 0}, { } }; @@ -320,6 +328,7 @@ MODULE_DEVICE_TABLE(acpi, amd_pmf_acpi_ids); static int amd_pmf_probe(struct platform_device *pdev) { + const struct acpi_device_id *id; struct amd_pmf_dev *dev; struct pci_dev *rdev; u32 base_addr_lo; @@ -328,6 +337,13 @@ static int amd_pmf_probe(struct platform_device *pdev) u32 val; int err; + id = acpi_match_device(amd_pmf_acpi_ids, &pdev->dev); + if (!id) + return -ENODEV; + + if (id->driver_data == 0x100 && !force_load) + return -ENODEV; + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); if (!dev) return -ENOMEM; From patchwork Tue Jul 12 14:58:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Sundar S K X-Patchwork-Id: 12915160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B585ECCA47F for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 15:00:17.2022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dab0b62f-f9fe-4b0c-8024-08da64173b94 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0267 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Update the MAINTAINERS file with AMD PMF driver details. Signed-off-by: Shyam Sundar S K Reviewed-by: Hans de Goede --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e01478062c56..d3f6cabcaab2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -998,6 +998,13 @@ L: platform-driver-x86@vger.kernel.org S: Maintained F: drivers/platform/x86/amd/pmc.c +AMD PMF DRIVER +M: Shyam Sundar S K +L: platform-driver-x86@vger.kernel.org +S: Maintained +F: Documentation/ABI/testing/sysfs-amd-pmf +F: drivers/platform/x86/amd/pmf/ + AMD HSMP DRIVER M: Naveen Krishna Chatradhi R: Carlos Bilbao