From patchwork Wed Jul 13 08:17:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C145C43334 for ; Wed, 13 Jul 2022 08:28:14 +0000 (UTC) Received: from localhost ([::1]:38160 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBXjB-0006uH-3X for qemu-devel@archiver.kernel.org; Wed, 13 Jul 2022 04:28:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBXZW-0005bw-H5 for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:14 -0400 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]:33293) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oBXZU-0004nV-Nb for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:14 -0400 Received: by mail-ed1-x530.google.com with SMTP id t3so12857492edd.0 for ; Wed, 13 Jul 2022 01:18:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d5wvoUqATSvMX82nH9ks317lgXhND7qx1Yhp+Jpwjpw=; b=eKqa2AeTgAMV8L/QVttch9bOHBpXGbrdxGzHPaS2OWQGEmkPJqV8nuQKkhTMAEgmY4 8zc8mS665M7dUHd3WM0y5gMka5bUO2IhZQCu9Oz/BZpr1khEbnzgpk1WCm8WvATYkWN9 L38XfAKdjfajYyPoABrnnXECQ9RFkMF4xFOmYvNY3AVzO/t75GCgvDXUeVpeQZDLdh71 gf5p6/KsWlAchMolRsY2iuUGcpAS1J4tpWlZGj9r2PUhfi1xEXYsafXk7pkDooDw1Vtn czP02NJKTaPFLTo9nMRCMFp8/G57JDOT/G2Xg2QNcgqR0fLCijVkThFjTk+9dsHe5g7l tqfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d5wvoUqATSvMX82nH9ks317lgXhND7qx1Yhp+Jpwjpw=; b=F+b5Lh7ZZMOyP9IsfPwWeHSVoZga2x/INH8UKlgbYV7Wz01ASW5Pffitba1NPXqf+a /T1mzCum21aLbKQwB/qRTMg6ZtOdtU98JTIgGAoWmwHuVIF5a3JRVa4MiNCbRc2LXN1p /BJzz7trLp7S04VquEPweJqofim5zQLNOdk8KZaaAZY5arP3j90iDxlA7KqNitBETX7Q VRu8gjgUQIUdd1WwzgdvgCkEU089yO6hDa9GAZuQOXlWtgisO69oYA7u4z/WXhfFpU9F dJxIS72/SZiFEgREFk6Q6MdPYcpKra7oezd/CIgUbQUAAwVaHEFlsVe2yyQWcuYt2jgE ldug== X-Gm-Message-State: AJIora9HDtmL6cAtMAii/xySPqjfricEeJ/GKSAAfuEyl+ISv275KQgL yIB0TfSMUFCnFdUwmGOG6jvCPRhB6R0= X-Google-Smtp-Source: AGRyM1v011CerVcdi5lWidUDebxZzdpShPuIWn1Lt0TU7NLYKBTYaks9PGJ0kLgU4Qgk3Mtsm/Sgxg== X-Received: by 2002:a50:ce1d:0:b0:43a:742f:9db3 with SMTP id y29-20020a50ce1d000000b0043a742f9db3mr3170433edi.308.1657700290922; Wed, 13 Jul 2022 01:18:10 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-183-210-047.77.183.pool.telefonica.de. [77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:10 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 01/11] hw/i386/pc: QOM'ify DMA creation Date: Wed, 13 Jul 2022 10:17:25 +0200 Message-Id: <20220713081735.112016-2-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=shentey@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Just like in the real hardware, create the DMA in the southbridges. Signed-off-by: Bernhard Beschow --- hw/i386/pc.c | 3 --- hw/i386/pc_piix.c | 2 ++ hw/isa/lpc_ich9.c | 3 +++ hw/isa/piix3.c | 9 +++++++-- 4 files changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 774cb2bf07..c3602d166d 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -47,7 +47,6 @@ #include "multiboot.h" #include "hw/rtc/mc146818rtc.h" #include "hw/intc/i8259.h" -#include "hw/dma/i8257.h" #include "hw/timer/i8254.h" #include "hw/input/i8042.h" #include "hw/irq.h" @@ -1200,8 +1199,6 @@ void pc_basic_device_init(struct PCMachineState *pcms, pcspk_init(pcms->pcspk, isa_bus, pit); } - i8257_dma_init(isa_bus, 0); - /* Super I/O */ pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, pcms->vmport != ON_OFF_AUTO_ON); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index a234989ac3..7ad677e967 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -26,6 +26,7 @@ #include CONFIG_DEVICES #include "qemu/units.h" +#include "hw/dma/i8257.h" #include "hw/loader.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" @@ -217,6 +218,7 @@ static void pc_init1(MachineState *machine, pci_bus = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } isa_bus_irqs(isa_bus, x86ms->gsi); diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 4553b5925b..8694e58b21 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -34,6 +34,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/range.h" +#include "hw/dma/i8257.h" #include "hw/isa/isa.h" #include "migration/vmstate.h" #include "hw/irq.h" @@ -722,6 +723,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); isa_bus_irqs(isa_bus, lpc->gsi); + + i8257_dma_init(isa_bus, 0); } static bool ich9_rst_cnt_needed(void *opaque) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 48f9ab1096..44a9998752 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/range.h" #include "qapi/error.h" +#include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/isa/isa.h" @@ -295,9 +296,11 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); + ISABus *isa_bus; - if (!isa_bus_new(DEVICE(d), get_system_memory(), - pci_address_space_io(dev), errp)) { + isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), + pci_address_space_io(dev), errp); + if (!isa_bus) { return; } @@ -307,6 +310,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) PIIX_RCR_IOPORT, &d->rcr_mem, 1); qemu_register_reset(piix3_reset, d); + + i8257_dma_init(isa_bus, 0); } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) From patchwork Wed Jul 13 08:17:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5487C433EF for ; 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[77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:11 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 02/11] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 southbridge Date: Wed, 13 Jul 2022 10:17:26 +0200 Message-Id: <20220713081735.112016-3-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The next patches will need to take advantage of it. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/i386/pc_piix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7ad677e967..f129da29ac 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -209,7 +209,8 @@ static void pc_init1(MachineState *machine, pci_memory, ram_memory); pcms->bus = pci_bus; - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, type); + pci_dev = pci_new_multifunction(-1, true, type); + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; From patchwork Wed Jul 13 08:17:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916286 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1358DC43334 for ; Wed, 13 Jul 2022 08:49:16 +0000 (UTC) Received: from localhost ([::1]:43786 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBY3X-0005af-60 for qemu-devel@archiver.kernel.org; Wed, 13 Jul 2022 04:49:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBXZY-0005dY-52 for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:16 -0400 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]:44547) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oBXZW-0004nr-9y for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:15 -0400 Received: by mail-ed1-x530.google.com with SMTP id m16so13083216edb.11 for ; Wed, 13 Jul 2022 01:18:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GG5bkcTJ/ZyZ9QoHxkY/kklFd5clnYhDbXnHDz0jhbA=; b=GL5nXKnF+zB7r/fD9z3uABoOlaD1TFbva2/bhLvJXKkzOnmC/8F44P67CnJtRlt310 J2j0Q9+aVmHrMRNk2IwiIofeHd96zt593qJ5FRYmIm2J60E1e/sY2PRq+RK9rbLlWevo jkfyFMj5tm6mJge95Jz3HeLfCIvxPzPn8w6t93dKYEVPvqjqGqxXfNZoqzH+VkEHVPN4 B2/9GeSk5tBY6iG96b051/s0iwJlOiZ235ixzrPoMEiazKjb1GXOY1IcGgDlD6GPfrYV 7HT/GWdyJI5RGr5SLqDedZTyMr5etV+jZEg0xp1xNsaeE3lec97AvUmM5bMvTHCcFsNz WYBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GG5bkcTJ/ZyZ9QoHxkY/kklFd5clnYhDbXnHDz0jhbA=; b=isfa3JhtdQrv/K5WjJWOhXHdqIPnhhOXFvfbfP35Bc9BF99b46N5OKB4w3DpBR2t6j H5QGmB8bvpOFqh1i5R3R1kE046Pt7YRDTQbKI7OQq0rVUv+qQxJzXwrGXpy/VLs/u/b7 Aa+H7tz6W4uuD9dlKnRSbTWoYlzz/DOt/R5BWOT+yOBOoVWNxS+Qi5CFFcPzpiXPVTNN QfZDDHe6++USEQ81sBPQFHYzSMtY/Edh9XWOh9gIJJQbwHgChk74D5AW6xUtBhOxCrSY pPt6jCx6GG2Pomp1mu+ZKXOYMD1yG2urNxL6bgztIntzDMXbx5WwYrGuiZuJeSyj4bWH Px9Q== X-Gm-Message-State: AJIora/UfX4mDNmwtC8XSuBBSWqimSMAPZ9mwqNvUZyl64+K0GkaHEKC IbAtEPZ4e7damicMkiy6c9pE7L6E71k= X-Google-Smtp-Source: AGRyM1tyHwzCrGJsGJBZZ5+fAdYkrdu4IadgOxUZASeQ2LWgWcVAfU02ftHheOHQmFoUisY7GGyKjw== X-Received: by 2002:a05:6402:150d:b0:43a:2cac:ca24 with SMTP id f13-20020a056402150d00b0043a2cacca24mr3188761edw.110.1657700292866; Wed, 13 Jul 2022 01:18:12 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-183-210-047.77.183.pool.telefonica.de. [77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:12 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 03/11] hw/isa/piix3: QOM'ify USB controller creation Date: Wed, 13 Jul 2022 10:17:27 +0200 Message-Id: <20220713081735.112016-4-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=shentey@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The USB controller is an integral part of PIIX3 (function 2). So create it as part of the southbridge. Note that the USB function is optional in QEMU. This is why it gets unparented if it is disabled, otherwiese QEMU will abort with: src/hw/core/qdev.c:357: qdev_assert_realized_properly_cb: Assertion `dev->realized' failed Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 6 ++---- hw/isa/piix3.c | 26 ++++++++++++++++++++++++++ include/hw/southbridge/piix.h | 5 +++++ 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f129da29ac..96dc0db729 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -210,6 +210,8 @@ static void pc_init1(MachineState *machine, pcms->bus = pci_bus; pci_dev = pci_new_multifunction(-1, true, type); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; @@ -281,10 +283,6 @@ static void pc_init1(MachineState *machine, } #endif - if (pcmc->pci_enabled && machine_usb(machine)) { - pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci"); - } - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { PCIDevice *piix4_pm; diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 44a9998752..dd512cca84 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -27,6 +27,7 @@ #include "qapi/error.h" #include "hw/dma/i8257.h" #include "hw/southbridge/piix.h" +#include "hw/ide/pci.h" #include "hw/irq.h" #include "hw/isa/isa.h" #include "hw/xen/xen.h" @@ -296,6 +297,7 @@ static const MemoryRegionOps rcr_ops = { static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d = PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus = pci_get_bus(dev); ISABus *isa_bus; isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), @@ -312,6 +314,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) qemu_register_reset(piix3_reset, d); i8257_dma_init(isa_bus, 0); + + /* USB */ + if (d->has_usb) { + qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); + if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) { + return; + } + } else { + object_unparent(OBJECT(&d->uhci)); + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -327,6 +339,18 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) } } +static void pci_piix3_init(Object *obj) +{ + PIIX3State *d = PIIX3_PCI_DEVICE(obj); + + object_initialize_child(obj, "uhci", &d->uhci, "piix3-usb-uhci"); +} + +static Property pci_piix3_props[] = { + DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_piix3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -345,12 +369,14 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data) * pc_piix.c's pc_init1() */ dc->user_creatable = false; + device_class_set_props(dc, pci_piix3_props); adevc->build_dev_aml = build_pci_isa_aml; } static const TypeInfo piix3_pci_type_info = { .name = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, + .instance_init = pci_piix3_init, .instance_size = sizeof(PIIX3State), .abstract = true, .class_init = pci_piix3_class_init, diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 2693778b23..115311d932 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/usb/hcd-uhci.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 @@ -52,11 +53,15 @@ struct PIIXState { /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + UHCIState uhci; + /* Reset Control Register contents */ uint8_t rcr; /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + + bool has_usb; }; typedef struct PIIXState PIIX3State; From patchwork Wed Jul 13 08:17:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB93EC43334 for ; Wed, 13 Jul 2022 08:31:12 +0000 (UTC) Received: from localhost ([::1]:43388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBXm3-00022d-O8 for qemu-devel@archiver.kernel.org; Wed, 13 Jul 2022 04:31:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBXZZ-0005dz-8B for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:18 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:40614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oBXZX-0004o8-DX for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:16 -0400 Received: by mail-ej1-x62d.google.com with SMTP id dn9so18489971ejc.7 for ; Wed, 13 Jul 2022 01:18:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2+YBaKMq3piBlzakX+dKs1zm6noavo7c3COk08077mQ=; b=JTY6OuKboy54SmrxPcV35EzXoDeaF0INvM3zOLD6zCL1Yt7BUfmu+d+cugfmI/1ahc liZ05hv/UcfjdMhfOxLyHEHTd770f+790Zq84Bg01LIbJamtjU89j906m/BlaIR1IJAo 7/R+1xwB5+XRNMdligK4puSSQ0CeaU2M58u8vBvlmVJQvxALoc3VsQZbKBMXznV0K7lL 9pyM5qLb3gSTcI2O9pd3rDyKCEMA5aQAIdgBFZe5J5YBYEqZLqgGKX+dJU3zl0Gvpn2e scW1YeRcEjc+aGz5xtTLxJFWyj63ahsY/vLvBYHlTo0C8Cbdp9Zri/IBzPDC5vIEizkF bL7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2+YBaKMq3piBlzakX+dKs1zm6noavo7c3COk08077mQ=; b=gTtLAb2mjQHhI2zzAfWyeK66Rw2kkU2HWHKSQ8XFueQGZwSeHXkda/YN4IS1sOKzGe rUNFCdt7gOgDY5jQNwmRYc0MG4yoWFzHR/fb8/nf0lcEMsrZiGOWGnCV5yKhfl8obE4n pJZF26ra1+uKoV4qMZJJ/3Lh79ITr+rDTLYD0i/KdHR6u/drLN/uXyHa3NeO3Ff5s0Z/ 2Sz3L3YNh8rQOgpvzZKjuWU6oqp2tMeQvCaEbJtLOmOcWlR/2ouY5CD3GufqvBPHWezE dJPxU0f03f083YplnucPXOJDyQvGxDe7nNO6hariT25tCxOUA9dJOxMlFtMny3Iy0BPW AKtw== X-Gm-Message-State: AJIora+vxOe9rCMoatDk1gwJTA4Iojuhouc9QFvDnZZEFFQRRfUo6+9K IKAY3R/jwrNv9i+umh5kPbrd3nA/Dmk= X-Google-Smtp-Source: AGRyM1sgm5EaVhuQZ+7dXlP3ORS1FuA5vw214CIh46mapVLJuPBgiVuzIuqKQdfMiqawFwa619blbw== X-Received: by 2002:a17:907:97c2:b0:72b:9ec4:9a60 with SMTP id js2-20020a17090797c200b0072b9ec49a60mr1287809ejc.154.1657700293900; Wed, 13 Jul 2022 01:18:13 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-183-210-047.77.183.pool.telefonica.de. [77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:13 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 04/11] hw/isa/piix3: QOM'ify ACPI controller creation Date: Wed, 13 Jul 2022 10:17:28 +0200 Message-Id: <20220713081735.112016-5-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The ACPI controller is an integral part of PIIX3 (function 3). So create it as part of the southbridge. Note that the ACPI function is optional in QEMU. This is why it gets unparented if it is disabled, otherwiese QEMU will abort with: src/hw/core/qdev.c:357: qdev_assert_realized_properly_cb: Assertion `dev->realized' failed Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 22 ++++++++++++---------- hw/isa/piix3.c | 16 ++++++++++++++++ include/hw/southbridge/piix.h | 3 +++ 3 files changed, 31 insertions(+), 10 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 96dc0db729..364c73b1bc 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -44,11 +44,11 @@ #include "sysemu/kvm.h" #include "hw/kvm/clock.h" #include "hw/sysbus.h" +#include "hw/i2c/i2c.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/xen/xen-x86.h" #include "exec/memory.h" #include "hw/acpi/acpi.h" -#include "hw/acpi/piix4.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" @@ -83,6 +83,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *system_io = get_system_io(); PCIBus *pci_bus; ISABus *isa_bus; + Object *piix4_pm; int piix3_devfn = -1; qemu_irq smi_irq; GSIState *gsi_state; @@ -212,13 +213,21 @@ static void pc_init1(MachineState *machine, pci_dev = pci_new_multifunction(-1, true, type); object_property_set_bool(OBJECT(pci_dev), "has-usb", machine_usb(machine), &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-acpi", + x86_machine_is_acpi_enabled(x86ms), + &error_abort); + object_property_set_bool(OBJECT(pci_dev), "smm-enabled", + x86_machine_is_smm_enabled(x86ms), + &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); } else { pci_bus = NULL; + piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); i8257_dma_init(isa_bus, 0); @@ -283,15 +292,8 @@ static void pc_init1(MachineState *machine, } #endif - if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) { - PCIDevice *piix4_pm; - + if (piix4_pm) { smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm = pci_new(piix3_devfn + 3, TYPE_PIIX4_PM); - qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100); - qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled", - x86_machine_is_smm_enabled(x86ms)); - pci_realize_and_unref(piix4_pm, pci_bus, &error_fatal); qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); @@ -305,7 +307,7 @@ static void pc_init1(MachineState *machine, object_property_allow_set_link, OBJ_PROP_LINK_STRONG); object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, - OBJECT(piix4_pm), &error_abort); + piix4_pm, &error_abort); } if (machine->nvdimms_state->is_enabled) { diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index dd512cca84..5db0bbf7b6 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -324,6 +324,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) } else { object_unparent(OBJECT(&d->uhci)); } + + /* ACPI */ + if (d->has_acpi) { + qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3); + if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { + return; + } + } else { + object_unparent(OBJECT(&d->pm)); + } } static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope) @@ -344,9 +354,15 @@ static void pci_piix3_init(Object *obj) PIIX3State *d = PIIX3_PCI_DEVICE(obj); object_initialize_child(obj, "uhci", &d->uhci, "piix3-usb-uhci"); + + object_initialize_child(obj, "pm", &d->pm, TYPE_PIIX4_PM); + qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", 0xb100); + object_property_add_alias(obj, "smm-enabled", + OBJECT(&d->pm), "smm-enabled"); } static Property pci_piix3_props[] = { + DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 115311d932..ee847cb4f2 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" +#include "hw/acpi/piix4.h" #include "hw/usb/hcd-uhci.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ @@ -54,6 +55,7 @@ struct PIIXState { int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; UHCIState uhci; + PIIX4PMState pm; /* Reset Control Register contents */ uint8_t rcr; @@ -61,6 +63,7 @@ struct PIIXState { /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; + bool has_acpi; bool has_usb; }; typedef struct PIIXState PIIX3State; From patchwork Wed Jul 13 08:17:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE588C43334 for ; Wed, 13 Jul 2022 08:36:41 +0000 (UTC) Received: from localhost ([::1]:52170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBXrN-0008F9-0Q for qemu-devel@archiver.kernel.org; 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[77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:14 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 05/11] hw/i386/pc: QOM'ify RTC creation Date: Wed, 13 Jul 2022 10:17:29 +0200 Message-Id: <20220713081735.112016-6-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=shentey@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Just like in the real hardware, create the RTC in the southbridges. Signed-off-by: Bernhard Beschow --- hw/i386/pc.c | 12 ++++++++++-- hw/i386/pc_piix.c | 8 ++++++++ hw/i386/pc_q35.c | 1 + hw/isa/lpc_ich9.c | 8 ++++++++ hw/isa/piix3.c | 7 +++++++ include/hw/i386/ich9.h | 2 ++ include/hw/southbridge/piix.h | 2 ++ 7 files changed, 38 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index c3602d166d..eba1c98b5a 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1181,9 +1181,17 @@ void pc_basic_device_init(struct PCMachineState *pcms, pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); } - *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); - qemu_register_boot_set(pc_boot_set, *rtc_state); + if (rtc_irq) { + qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + } else { + uint32_t irq = object_property_get_uint(OBJECT(*rtc_state), + "irq", + &error_fatal); + isa_connect_gpio_out(*rtc_state, 0, irq); + } + + qemu_register_boot_set(pc_boot_set, rtc_state); if (!xen_enabled() && (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 364c73b1bc..52c550f8b8 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -32,6 +32,7 @@ #include "hw/i386/pc.h" #include "hw/i386/apic.h" #include "hw/pci-host/i440fx.h" +#include "hw/rtc/mc146818rtc.h" #include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" @@ -224,12 +225,19 @@ static void pc_init1(MachineState *machine, piix3->pic = x86ms->gsi; piix3_devfn = piix3->dev.devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), + "rtc")); piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); } else { pci_bus = NULL; piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + + rtc_state = isa_new(TYPE_MC146818_RTC); + qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); + isa_realize_and_unref(rtc_state, isa_bus, &error_fatal); + i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index f96cbd04e2..d850313180 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -230,6 +230,7 @@ static void pc_q35_init(MachineState *machine) lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, TYPE_ICH9_LPC_DEVICE); + rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc")); object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, TYPE_HOTPLUG_HANDLER, diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 8694e58b21..0051fa66ab 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -660,6 +660,8 @@ static void ich9_lpc_initfn(Object *obj) static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; + object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC); + object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, &lpc->sci_gsi, OBJ_PROP_FLAG_READ); object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, @@ -725,6 +727,12 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp) isa_bus_irqs(isa_bus, lpc->gsi); i8257_dma_init(isa_bus, 0); + + /* RTC */ + qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) { + return; + } } static bool ich9_rst_cnt_needed(void *opaque) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 5db0bbf7b6..afd36178dd 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -315,6 +315,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) i8257_dma_init(isa_bus, 0); + /* RTC */ + qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000); + if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) { + return; + } + /* USB */ if (d->has_usb) { qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); @@ -353,6 +359,7 @@ static void pci_piix3_init(Object *obj) { PIIX3State *d = PIIX3_PCI_DEVICE(obj); + object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "uhci", &d->uhci, "piix3-usb-uhci"); object_initialize_child(obj, "pm", &d->pm, TYPE_PIIX4_PM); diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index 23ee8e371b..672efc6bce 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -11,6 +11,7 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/rtc/mc146818rtc.h" #include "qom/object.h" void ich9_lpc_set_irq(void *opaque, int irq_num, int level); @@ -39,6 +40,7 @@ struct ICH9LPCState { */ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; + RTCState rtc; APMState apm; ICH9LPCPMRegs pm; uint32_t sci_level; /* track sci level */ diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index ee847cb4f2..15b05cfc93 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" /* PIRQRC[A:D]: PIRQx Route Control Registers */ @@ -54,6 +55,7 @@ struct PIIXState { /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + RTCState rtc; UHCIState uhci; PIIX4PMState pm; From patchwork Wed Jul 13 08:17:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02CD7C433EF for ; Wed, 13 Jul 2022 08:36:39 +0000 (UTC) Received: from localhost ([::1]:52036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBXrK-00089R-TQ for qemu-devel@archiver.kernel.org; Wed, 13 Jul 2022 04:36:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38234) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBXZb-0005ew-1E for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:23 -0400 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]:33289) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oBXZZ-0004of-DC for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:18 -0400 Received: by mail-ej1-x635.google.com with SMTP id va17so18573488ejb.0 for ; Wed, 13 Jul 2022 01:18:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MEInLvpkAW1LEe/0KxYlOVjh1DcOAF8NNEJb3GOJEdQ=; b=Vx+mc1tQ8fa+bcTZ0ey9SAPeiICSoqswq0f08YyrwPjYwta3yGtwqrYZc4E6VTDUAP 39HI/WPAc7S1xa811V/0oQhqaE8JOpYZ4yvVtWg2VPvdzI+2rlMqPmQZ3fZus7/ck8ko yn2oDkbnqayeCHPKcZfVyfXKc6l2BKwL1VS5wCPHpdn1wFdET9ogweFqOeC0WnEAXIsT DsAvN1s6bIbaNQ6OihG72QL2Bf9kI3xisz6aWg+vVJKthYZQJX+sNxBKBLhkvbF9oQiJ XGacy6YpTEvptnbfgkWFPdPYPv4T9kol1DiAA68cnmk09TA2CtiIRhahPUwJU7vUdj2i 6NKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MEInLvpkAW1LEe/0KxYlOVjh1DcOAF8NNEJb3GOJEdQ=; b=mUQDuWRLHHCS4YGm/y9xIT/rHP/+yWcuoukj9+8lcnwoTuQmUYafvAvVl+343Niv/6 j4rzEgTVnVSEBiFMcOh+izcShvZmYcRuKKfbCmXYBwUuweIzbllekigdgl5h1adZE8Q8 glIgoNNB8k683FNK2yL9jZ7B9yGQDqEVsJsObahpefBCje1aBn5fSWcec5Ob8iDUQyY2 7ZXhuLKu/Zk5H9TUgaZJIwKz8KhaCRCwEwKYdwnAF8WbiAMi+f7ODMQf+qor7mqS6jB/ OxXQ2Y/laL9Uemk+YOTfaXjTf4eJ9JqKiqHHZ7392Hv/YGVMSos+JiB9TAKDwiGpETuX Kkzw== X-Gm-Message-State: AJIora82Qd6Snk9UDXh3uFlnh/dxBx+4tP/NYK7nai85C5NOWtkXtZWM 6A79B0QgDgnNlYvmFN+vK3xgB+VrCpU= X-Google-Smtp-Source: AGRyM1tQq8YmfvOd/zqjsj/bxWFXbQyPMzUxjk101A+LhGnQFXOLxSH+bztewDrPnZwNzV2bwMJH+Q== X-Received: by 2002:a17:906:9b8a:b0:722:e6e0:33d with SMTP id dd10-20020a1709069b8a00b00722e6e0033dmr2167218ejc.317.1657700295855; Wed, 13 Jul 2022 01:18:15 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-183-210-047.77.183.pool.telefonica.de. [77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:15 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 06/11] hw/i386/pc: No need for rtc_state to be an out-parameter Date: Wed, 13 Jul 2022 10:17:30 +0200 Message-Id: <20220713081735.112016-7-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that the RTC is created as part of the southbridges it doesn't need to be an out-parameter any longer. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/i386/pc.c | 8 ++++---- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- include/hw/i386/pc.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index eba1c98b5a..886c6b451a 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1128,7 +1128,7 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs) { @@ -1183,12 +1183,12 @@ void pc_basic_device_init(struct PCMachineState *pcms, } if (rtc_irq) { - qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq); + qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); } else { - uint32_t irq = object_property_get_uint(OBJECT(*rtc_state), + uint32_t irq = object_property_get_uint(OBJECT(rtc_state), "irq", &error_fatal); - isa_connect_gpio_out(*rtc_state, 0, irq); + isa_connect_gpio_out(rtc_state, 0, irq); } qemu_register_boot_set(pc_boot_set, rtc_state); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 52c550f8b8..0f6cdc5bc4 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -263,7 +263,7 @@ static void pc_init1(MachineState *machine, } /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, true, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, true, 0x4); pc_nic_init(pcmc, isa_bus, pci_bus); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index d850313180..15b8b814c3 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -284,7 +284,7 @@ static void pc_q35_init(MachineState *machine) } /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy, + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, 0xff0104); /* connect pm stuff to lpc */ diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index b7735dccfc..d1fd8969a0 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -164,7 +164,7 @@ uint64_t pc_pci_hole64_start(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, - ISADevice **rtc_state, + ISADevice *rtc_state, bool create_fdctrl, uint32_t hpet_irqs); void pc_cmos_init(PCMachineState *pcms, From patchwork Wed Jul 13 08:17:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF15DC43334 for ; Wed, 13 Jul 2022 08:40:27 +0000 (UTC) Received: from localhost ([::1]:60318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBXv0-0005P6-Su for qemu-devel@archiver.kernel.org; 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[77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:16 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 07/11] hw/intc/i8259: Introduce i8259 proxy "isa-pic" Date: Wed, 13 Jul 2022 10:17:31 +0200 Message-Id: <20220713081735.112016-8-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=shentey@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Having an i8259 proxy allows for ISA PICs to be created and wired up in southbridges. This is especially interesting for PIIX3 for two reasons: First, the southbridge doesn't need to care about the virtualization technology used (KVM, TCG, Xen) due to in-IRQs (where devices get attached) and out-IRQs (which will trigger the IRQs of the respective virtzalization technology) are separated. Second, since the in-IRQs are populated with fully initialized qemu_irq's, they can already be wired up inside PIIX3. Signed-off-by: Bernhard Beschow --- hw/intc/i8259.c | 27 +++++++++++++++++++++++++++ include/hw/intc/i8259.h | 14 ++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index cc4e21ffec..531f6cca53 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -458,9 +458,36 @@ static const TypeInfo i8259_info = { .class_size = sizeof(PICClass), }; +static void isapic_set_irq(void *opaque, int irq, int level) +{ + ISAPICState *s = opaque; + + qemu_set_irq(s->out_irqs[irq], level); +} + +static void isapic_init(Object *obj) +{ + ISAPICState *s = ISA_PIC(obj); + + qdev_init_gpio_in(DEVICE(s), isapic_set_irq, ISA_NUM_IRQS); + qdev_init_gpio_out(DEVICE(s), s->out_irqs, ISA_NUM_IRQS); + + for (int i = 0; i < ISA_NUM_IRQS; ++i) { + s->in_irqs[i] = qdev_get_gpio_in(DEVICE(s), i); + } +} + +static const TypeInfo isapic_info = { + .name = TYPE_ISA_PIC, + .parent = TYPE_ISA_DEVICE, + .instance_size = sizeof(ISAPICState), + .instance_init = isapic_init, +}; + static void pic_register_types(void) { type_register_static(&i8259_info); + type_register_static(&isapic_info); } type_init(pic_register_types) diff --git a/include/hw/intc/i8259.h b/include/hw/intc/i8259.h index e2b1e8c59a..0246ab6ac6 100644 --- a/include/hw/intc/i8259.h +++ b/include/hw/intc/i8259.h @@ -1,6 +1,20 @@ #ifndef HW_I8259_H #define HW_I8259_H +#include "qom/object.h" +#include "hw/isa/isa.h" +#include "qemu/typedefs.h" + +#define TYPE_ISA_PIC "isa-pic" +OBJECT_DECLARE_SIMPLE_TYPE(ISAPICState, ISA_PIC) + +struct ISAPICState { + ISADevice parent_obj; + + qemu_irq in_irqs[ISA_NUM_IRQS]; + qemu_irq out_irqs[ISA_NUM_IRQS]; +}; + /* i8259.c */ extern DeviceState *isa_pic; From patchwork Wed Jul 13 08:17:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 066E8C43334 for ; Wed, 13 Jul 2022 08:38:50 +0000 (UTC) Received: from localhost ([::1]:57806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBXtR-0003gJ-45 for qemu-devel@archiver.kernel.org; Wed, 13 Jul 2022 04:38:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38314) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBXZg-0005fI-AC for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:26 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]:42773) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oBXZb-0004p4-I9 for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:23 -0400 Received: by mail-ej1-x629.google.com with SMTP id sz17so18503110ejc.9 for ; Wed, 13 Jul 2022 01:18:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2NPGt8xuA6Yqy8KYQ1uKmkHyOmvds1RCbXYW0GOsMr0=; b=BbyOhkofjIyw4tzwz5l6Q3QU5oBYFLujKqpzTOae2rnANG95fkvWmGGsNhw9exGY72 YcFLAr3lcaUQ9YIqeTvZUleMTX5oEtStmc2WrDYXNbg/xIAw/Ezokn9s0CJLhcqUkcI8 WKseubNxRXRWPhfR5/5So4y9v0b8+V9IMK7CJW8tARFRzaZJjLK9oOnVklFzjzlOgOKn Tj6qDJSbdQ/5UqaYqqaldAaC3hdI3pdiZXAjozhTge/0lGV4dEF5MM2uKdWP0enXGsiW a0nfDElljNgjG9QpuLFGiZjRW3d6cI65LVl49NsCpzlFJ4y2+yZiXEsVjM0iFP+xyBL6 RcVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2NPGt8xuA6Yqy8KYQ1uKmkHyOmvds1RCbXYW0GOsMr0=; b=gxJYelVAqkj3d17Ulo4tsSgU0QHu3FECjAGR/f1EP4kijOqbjqBnouCyjmUDLAbbHu TQGBSSP1BViZepYXrTAu/3RpDk60z+RM4NBJeWYxZyZ0Nsc4kecrsX8duF21xUyK22Wv tqOMwkMNf+1BmDzyCAXaN2k2+DUeSr8CLj3nLfA78QVQJLti5dYqJodg7J5t7/8+6Upq 424KwFhH8AjVOwJH4XQgg02oteuyjWDNcpsiJ66Igv3oTzXcMPgH5b8uWnjGw2iNwRx9 wFMqPJNUNT9MNLX9VZF2R3vG6e5bGyHTc7zLgmrQHTSTVi4W8wRoy/xD6qlGpVL3vhl+ CWGw== X-Gm-Message-State: AJIora/4WegtvdptYcDJVDpI4bZCTfq48T1ZRYU23hSeNzmM5QLP5oIX Fc7PIUtyg/dcNDSgu8fihIduDB4pS40= X-Google-Smtp-Source: AGRyM1sualXPIZC+hGZzpCwfIZlUnNx91rCHSoNv3uxGsy90PO0Ok8QxrqDuJa1K825xLvqJ9zSknw== X-Received: by 2002:a17:907:3f84:b0:724:2ec:b474 with SMTP id hr4-20020a1709073f8400b0072402ecb474mr2297621ejc.644.1657700297769; Wed, 13 Jul 2022 01:18:17 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-183-210-047.77.183.pool.telefonica.de. [77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:17 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 08/11] hw/isa/piix3: QOM'ify ISA PIC creation Date: Wed, 13 Jul 2022 10:17:32 +0200 Message-Id: <20220713081735.112016-9-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Use the newly introduced i8259 proxy "isa-pic" which allows for wiring up devices in the southbridge where the virtualization technology used (KVM, TCG, Xen) is not yet known. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 15 +++++++++------ hw/isa/piix3.c | 10 +++++++++- include/hw/southbridge/piix.h | 4 ++-- 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 0f6cdc5bc4..4ce215a212 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -198,10 +198,11 @@ static void pc_init1(MachineState *machine, gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); if (pcmc->pci_enabled) { - PIIX3State *piix3; + DeviceState *dev; PCIDevice *pci_dev; const char *type = xen_enabled() ? TYPE_PIIX3_XEN_DEVICE : TYPE_PIIX3_DEVICE; + int i; pci_bus = i440fx_init(host_type, pci_type, @@ -221,10 +222,12 @@ static void pc_init1(MachineState *machine, x86_machine_is_smm_enabled(x86ms), &error_abort); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - piix3->pic = x86ms->gsi; - piix3_devfn = piix3->dev.devfn; - isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "pic")); + for (i = 0; i < ISA_NUM_IRQS; ++i) { + qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); + } + piix3_devfn = pci_dev->devfn; + isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); @@ -233,6 +236,7 @@ static void pc_init1(MachineState *machine, piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + isa_bus_irqs(isa_bus, x86ms->gsi); rtc_state = isa_new(TYPE_MC146818_RTC); qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); @@ -241,7 +245,6 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } - isa_bus_irqs(isa_bus, x86ms->gsi); if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index afd36178dd..7bf3488f76 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -41,7 +41,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { - qemu_set_irq(piix3->pic[pic_irq], + qemu_set_irq(piix3->pic.in_irqs[pic_irq], !!(piix3->pic_levels & (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); @@ -306,6 +306,13 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } + /* PIC */ + if (!qdev_realize(DEVICE(&d->pic), BUS(isa_bus), errp)) { + return; + } + + isa_bus_irqs(isa_bus, d->pic.in_irqs); + memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, "piix3-reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), @@ -359,6 +366,7 @@ static void pci_piix3_init(Object *obj) { PIIX3State *d = PIIX3_PCI_DEVICE(obj); + object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "uhci", &d->uhci, "piix3-usb-uhci"); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 15b05cfc93..cfe155ce07 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -50,11 +51,10 @@ struct PIIXState { #endif uint64_t pic_levels; - qemu_irq *pic; - /* This member isn't used. Just for save/load compatibility */ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + ISAPICState pic; RTCState rtc; UHCIState uhci; PIIX4PMState pm; From patchwork Wed Jul 13 08:17:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54F07C433EF for ; Wed, 13 Jul 2022 08:54:40 +0000 (UTC) Received: from localhost ([::1]:47934 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBY8l-0000CA-7D for qemu-devel@archiver.kernel.org; Wed, 13 Jul 2022 04:54:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBXZd-0005fD-Ro for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:24 -0400 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]:34778) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oBXZc-0004pL-6W for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:21 -0400 Received: by mail-ed1-x52a.google.com with SMTP id x91so13122390ede.1 for ; Wed, 13 Jul 2022 01:18:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aFSy1//YLeom6uMH0IcyS+rawbRfVHlZe7IVtSU18LA=; b=czc0tvDnuFyY1Cw5XzXDERHt6uDCUzzZQxP22m9cpyFatHrztum/yfUaET8t13loyn TRUfA6N8rpnQ6KbVlPALmCZ3t2qOtAgS/D/Im4fA9/efuJgry84cyoHLPXQQqkUkJael zBWQ/XboGQM7CQrujUNxgB/pCFXiHjVX0tExjiwVAiJ/rFar+WtzmvZE61JgYIYTptum KRfysE3WX7YfWH8ydYt17zTSnS3vOMPSymNwwBLtJ3z+lsLPpzyO26zUdaBAKYCyXC6z exDUmxxlNQvyHWvZvOheKeiMp0gdIqoAS1ajGw4ruWkPJROlWpkUO4NZFQ++TX/3XR23 xNNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aFSy1//YLeom6uMH0IcyS+rawbRfVHlZe7IVtSU18LA=; b=7AZMvI5uwq8gIBoPxOtGD21Y7Hy1XOI5z4pakF6Njp8K/6tayLUJBVMoKzMKJ2eiuD KYZmB9/7UnwXMs67B8LZJtwYN4cX8VpGPylGj/9h62b1ECyG6YgbEQwG48Ldx1r6TNMx UdWPIn7ITqgps9mQZtgnjE1DnZv0Y6bZ7KUomTXyi4eMazqXF9Hcyy8kZSrkfhyDrABO zAYf5SeHQX/zx9tRX8jIdQdh2Qfzl8YIN1dMZQc6crwqxV2Hp7TaL2rgchpFYtYmRXjD aX7yi7pdQZrReICeXj/ib42M6nSCDVc43Oc9vv2RODUDQr69AAKRwBuyaOT8SlGSTjel n4pA== X-Gm-Message-State: AJIora8X2Y4ImD158BcB+Oa8MTEvOODRPvDi8IXEqiteyr1bNZoVrPIA MNF2wtwYPU2c44vTy0zhZQZqZVfKYOg= X-Google-Smtp-Source: AGRyM1uGVyrrSxi8+Q9B78TECwq1EJ98E1yicNMhWQBys9Ypw2H+IDeA4SwEjdphaiMU2j2jcNVGaQ== X-Received: by 2002:a05:6402:84f:b0:437:6293:d264 with SMTP id b15-20020a056402084f00b004376293d264mr3072976edz.317.1657700298722; Wed, 13 Jul 2022 01:18:18 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-183-210-047.77.183.pool.telefonica.de. [77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:18 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 09/11] hw/isa/piix3: QOM'ify IDE controller creation Date: Wed, 13 Jul 2022 10:17:33 +0200 Message-Id: <20220713081735.112016-10-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that PIIX3 contains the new isa-pic, it is possible to instantiate PIIX3 IDE in the PIIX3 southbridge. PIIX3 IDE wires up its interrupts to the ISA bus in its realize method which requires the interrupt controller to provide fully populated qemu_irqs. This is the case for isa-pic even though the virtualization technology not known yet. Signed-off-by: Bernhard Beschow --- hw/i386/Kconfig | 1 - hw/i386/pc_piix.c | 13 +++++-------- hw/isa/Kconfig | 1 + hw/isa/piix3.c | 8 ++++++++ include/hw/southbridge/piix.h | 2 ++ 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d22ac4a4b9..dd247f215c 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -74,7 +74,6 @@ config I440FX select ACPI_SMBUS select PCI_I440FX select PIIX3 - select IDE_PIIX select DIMM select SMBIOS select FW_CFG_DMA diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 4ce215a212..f843a73d90 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -85,7 +85,6 @@ static void pc_init1(MachineState *machine, PCIBus *pci_bus; ISABus *isa_bus; Object *piix4_pm; - int piix3_devfn = -1; qemu_irq smi_irq; GSIState *gsi_state; BusState *idebus[MAX_IDE_BUS]; @@ -226,11 +225,13 @@ static void pc_init1(MachineState *machine, for (i = 0; i < ISA_NUM_IRQS; ++i) { qdev_connect_gpio_out(dev, i, x86ms->gsi[i]); } - piix3_devfn = pci_dev->devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), "rtc")); piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); + dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); + idebus[0] = qdev_get_child_bus(dev, "ide.0"); + idebus[1] = qdev_get_child_bus(dev, "ide.1"); } else { pci_bus = NULL; piix4_pm = NULL; @@ -244,6 +245,8 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; + idebus[0] = NULL; + idebus[1] = NULL; } if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { @@ -272,12 +275,6 @@ static void pc_init1(MachineState *machine, pc_nic_init(pcmc, isa_bus, pci_bus); if (pcmc->pci_enabled) { - PCIDevice *dev; - - dev = pci_create_simple(pci_bus, piix3_devfn + 1, "piix3-ide"); - pci_ide_create_devs(dev); - idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0"); - idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1"); pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); } #ifdef CONFIG_IDE_ISA diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index d42143a991..808b9a30af 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -34,6 +34,7 @@ config PC87312 config PIIX3 bool select ISA_BUS + select IDE_PIIX config PIIX4 bool diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 7bf3488f76..fd9c8f853a 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -328,6 +328,13 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) return; } + /* IDE */ + qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1); + if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) { + return; + } + pci_ide_create_devs(PCI_DEVICE(&d->ide)); + /* USB */ if (d->has_usb) { qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2); @@ -368,6 +375,7 @@ static void pci_piix3_init(Object *obj) object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC); object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC); + object_initialize_child(obj, "ide", &d->ide, "piix3-ide"); object_initialize_child(obj, "uhci", &d->uhci, "piix3-usb-uhci"); object_initialize_child(obj, "pm", &d->pm, TYPE_PIIX4_PM); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index cfe155ce07..41983dfa6d 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -15,6 +15,7 @@ #include "hw/pci/pci.h" #include "qom/object.h" #include "hw/acpi/piix4.h" +#include "hw/ide/pci.h" #include "hw/intc/i8259.h" #include "hw/rtc/mc146818rtc.h" #include "hw/usb/hcd-uhci.h" @@ -56,6 +57,7 @@ struct PIIXState { ISAPICState pic; RTCState rtc; + PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; From patchwork Wed Jul 13 08:17:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0253C43334 for ; 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[77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:19 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 10/11] hw/isa/piix3: Wire up ACPI interrupt internally Date: Wed, 13 Jul 2022 10:17:34 +0200 Message-Id: <20220713081735.112016-11-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=shentey@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that PIIX3 has the PIC integrated, the ACPI controller can be wired up internally. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 1 - hw/isa/piix3.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f843a73d90..19c86b68bd 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -303,7 +303,6 @@ static void pc_init1(MachineState *machine, if (piix4_pm) { smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq); pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c")); /* TODO: Populate SPD eeprom data. */ diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index fd9c8f853a..56a741c192 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -351,6 +351,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) { return; } + qdev_connect_gpio_out(DEVICE(&d->pm), 0, + qdev_get_gpio_in(DEVICE(&d->pic), 9)); } else { object_unparent(OBJECT(&d->pm)); } From patchwork Wed Jul 13 08:17:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 12916287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10FE2C433EF for ; Wed, 13 Jul 2022 08:51:47 +0000 (UTC) Received: from localhost ([::1]:45870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBY5x-0007AY-V4 for qemu-devel@archiver.kernel.org; Wed, 13 Jul 2022 04:51:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBXZe-0005fF-VZ for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:24 -0400 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]:38910) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oBXZd-0004mw-Eg for qemu-devel@nongnu.org; Wed, 13 Jul 2022 04:18:22 -0400 Received: by mail-ed1-x52c.google.com with SMTP id fd6so13101247edb.5 for ; Wed, 13 Jul 2022 01:18:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CtEBZbRNGv3Mai7FOzAgJwZ0F0IikxgieiRPuuAt06E=; b=dCrbAFU0MTFdebpwFf7Qg9CIM65Sr6ww6TZTSqdz9uaaDNsZ/sHHylf6+FID1GYsZ8 G+cR9MdqVM+k28x9F0oCaIwiXkHvq3V7ZRrEmpH3fP3ZC0DtvE38NU3lclrDUApKfOpI uHAwt9bjIG+REvFnjwHVqd44oG2E9Z611f2iDbS/1ZdFUZ4fZujyWC8daCuTKUZdCQko t5MoW8f2VyD5m8g2LTu2ZjOKB6qkWm1dHpWHYwNgE1kbrI8cK5bLmv5HtEGMxEyU6DdP f8pr+rVANdmyoO1Jdg5IUXsscMZYBY3jHfGCROA5dHKQwL37IXeCS1l/Jm2/j1b5KdAu c3zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CtEBZbRNGv3Mai7FOzAgJwZ0F0IikxgieiRPuuAt06E=; b=abNCZNIQh2KjQQYLNRcYQK4eVfC0cJ99ICeUJ9JOcHijrx+j4FpCGNIU1/4swDkBq6 STfzx2bqQQ2u9OzbSyvZU8RI5/hbbNBRDZK1dyvUfCsEpM1PZwAz3GJt9ZtI/d7GTpoD 62gRBiHvP0RyE5O88LNs4sq7ImoNXimsx7y8dL0OQ314+3GH1Tyw2EFzgx+UAiKZQeR1 XmGWEJMPt3nV5NJM/0B8r3PQfTespySlUlKIdiebjbOAPhbi0jIgAEuQg0RE285wDq+D 7X+oULyycySNilHJTk0CIkb7RlExu+Tg910kBQRXUX5TQP4ty9FCYn2rgIigwPwvwo8P 4idA== X-Gm-Message-State: AJIora/qOOqN3+Cb6JD6u//D+KgiePa917eApQAYFcVIWN4hKQAX3T2S DOY27975VSyrqNnXwTb7z9fc2T7TEiw= X-Google-Smtp-Source: AGRyM1urcMIuoFLrTB3kI+8KZifwxU0xT+UkW7itnIi3cBSy0Y+QCOzvHh1e4ANWtWpOh06Fl18Kbw== X-Received: by 2002:a05:6402:2287:b0:43b:a9d:ab1 with SMTP id cw7-20020a056402228700b0043b0a9d0ab1mr3045712edb.325.1657700300682; Wed, 13 Jul 2022 01:18:20 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-183-210-047.77.183.pool.telefonica.de. [77.183.210.47]) by smtp.gmail.com with ESMTPSA id w13-20020aa7dccd000000b00435a62d35b5sm7483431edu.45.2022.07.13.01.18.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 01:18:20 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , Marcel Apfelbaum , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Bernhard Beschow Subject: [PATCH 11/11] hw/isa/piix3: Remove extra ';' outside of functions Date: Wed, 13 Jul 2022 10:17:35 +0200 Message-Id: <20220713081735.112016-12-shentey@gmail.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220713081735.112016-1-shentey@gmail.com> References: <20220713081735.112016-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Fixes the "extra-semi" clang-tidy check. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/isa/piix3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 56a741c192..3cfd6eafcd 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -442,7 +442,7 @@ static void piix3_realize(PCIDevice *dev, Error **errp) pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS); pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); -}; +} static void piix3_class_init(ObjectClass *klass, void *data) { @@ -477,7 +477,7 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp) */ pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, piix3, XEN_PIIX_NUM_PIRQS); -}; +} static void piix3_xen_class_init(ObjectClass *klass, void *data) { @@ -485,7 +485,7 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data) k->config_write = piix3_write_config_xen; k->realize = piix3_xen_realize; -}; +} static const TypeInfo piix3_xen_info = { .name = TYPE_PIIX3_XEN_DEVICE,