From patchwork Wed Jul 13 13:38:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bob Beckett X-Patchwork-Id: 12916743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1E97C43334 for ; Wed, 13 Jul 2022 13:38:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 28A8E10E39F; Wed, 13 Jul 2022 13:38:42 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9463410E418; Wed, 13 Jul 2022 13:38:40 +0000 (UTC) Received: from hermes-devbox.fritz.box (82-71-8-225.dsl.in-addr.zen.co.uk [82.71.8.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbeckett) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1F38C66019BF; Wed, 13 Jul 2022 14:38:39 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657719519; bh=CsNQhhmN7tfVGf4HN1uv8HbRGJrZrAmt/638xemnBMo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U3jpirrge5r19VPek6bsVlH82O/2qiPOBpGuh5J5wPQSiX+nV2d21Kt2IjKo9YV7f I1YkmjtkibkRJ1gv+B/bPfZUtShl8LuZJabDchWDrpK7kz84knef5yqEGpfVxl9uZg W+PfOr6V/GyyUwswgKHaLt3wRRobcJP2DUAXbQVTkxPvc0HNOP8gykzFgctAF9GAQ1 YIkihsVeJEZZxd+RtvTL++EycJd99mdtwrEqVDJFdTt01f+36EK81K/nbHSJDZoxQ2 IH+sXcN+CZeWOFcCFsW49w8buzH0zGf0pOGUzhICd+PSAzn6qdSmZZJezvxLG5Fn0x 6j03uVjDL1wIA== From: Robert Beckett To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH v4 1/8] drm/i915/ttm: dont trample cache_level overrides during ttm move Date: Wed, 13 Jul 2022 14:38:11 +0100 Message-Id: <20220713133818.3699604-2-bob.beckett@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713133818.3699604-1-bob.beckett@collabora.com> References: <20220713133818.3699604-1-bob.beckett@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Beckett , =?utf-8?q?Thomas_Hellstr?= =?utf-8?q?=C3=B6m?= , kernel@collabora.com, Matthew Auld , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Various places within the driver override the default chosen cache_level. Before ttm, these overrides were permanent until explicitly changed again or for the lifetime of the buffer. TTM movement code came along and decided that it could make that decision at that time, which is usually well after object creation, so overrode the cache_level decision and reverted it back to its default decision. Add logic to indicate whether the caching mode has been set by anything other than the move logic. If so, assume that the code that overrode the defaults knows best and keep it. Signed-off-by: Robert Beckett Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gem/i915_gem_object.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 + drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 9 ++++++--- 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index ccec4055fde3..966ac2d778d5 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -125,6 +125,7 @@ void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, struct drm_i915_private *i915 = to_i915(obj->base.dev); obj->cache_level = cache_level; + obj->ttm.cache_level_override = true; if (cache_level != I915_CACHE_NONE) obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ | diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 5cf36a130061..14937cf1daaa 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -623,6 +623,7 @@ struct drm_i915_gem_object { struct i915_gem_object_page_iter get_io_page; struct drm_i915_gem_object *backup; bool created:1; + bool cache_level_override:1; } ttm; /* diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c index 053b0022ddd0..b6c3fc25d9d1 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c @@ -1253,6 +1253,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem, i915_gem_object_init_memory_region(obj, mem); i915_ttm_adjust_domains_after_move(obj); i915_ttm_adjust_gem_after_move(obj); + obj->ttm.cache_level_override = false; i915_gem_object_unlock(obj); return 0; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c index 9a7e50534b84..042c2237e287 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c @@ -129,9 +129,12 @@ void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj) obj->mem_flags |= i915_ttm_cpu_maps_iomem(bo->resource) ? I915_BO_FLAG_IOMEM : I915_BO_FLAG_STRUCT_PAGE; - cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), bo->resource, - bo->ttm); - i915_gem_object_set_cache_coherency(obj, cache_level); + if (!obj->ttm.cache_level_override) { + cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), + bo->resource, bo->ttm); + i915_gem_object_set_cache_coherency(obj, cache_level); + obj->ttm.cache_level_override = false; + } } /** From patchwork Wed Jul 13 13:38:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bob Beckett X-Patchwork-Id: 12916742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07404CCA479 for ; Wed, 13 Jul 2022 13:38:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 22FD210EDC8; Wed, 13 Jul 2022 13:38:43 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4025F10E39F; Wed, 13 Jul 2022 13:38:41 +0000 (UTC) Received: from hermes-devbox.fritz.box (82-71-8-225.dsl.in-addr.zen.co.uk [82.71.8.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbeckett) by madras.collabora.co.uk (Postfix) with ESMTPSA id B804C66019D2; Wed, 13 Jul 2022 14:38:39 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657719520; bh=ha13NipozoxIlhmnqDQLSM1i3fj+EPxYLmpfjPykhKo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OVFmbp1+WuzLJbSMWJc+wgjgL0pr/UqwkAbI8SS85WZAbSLXvX6GF6UZTS5YWbd33 Tkvt74dPG8pxskKrjAhbk1ndSkP9O3E1hHuOQoxJvTOx5ko4MOn9muqgXBwn2zDFef ZLjZ+cU6kvsISJ/4xohMLhtPYqLrPwwu/fvaUG8dWYvwkg+ea361X1y7i81+rLuNHE xcjNsN96tRjpiYj9aKyk//6ByNFP7g5EVnYNJ4xNVyxBWmHIWBPEr2lax0iZbgnKrq H3SRWOmKjw77ePk+Yrl6KDk02HSbmiNYstSDVBw6QDgLkUifoJpmocOClU8MAeWfD2 +jR1rV5TVn0Dw== From: Robert Beckett To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH v4 2/8] drm/i915: limit ttm to dma32 for i965G[M] Date: Wed, 13 Jul 2022 14:38:12 +0100 Message-Id: <20220713133818.3699604-3-bob.beckett@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713133818.3699604-1-bob.beckett@collabora.com> References: <20220713133818.3699604-1-bob.beckett@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Beckett , =?utf-8?q?Thomas_Hellstr?= =?utf-8?q?=C3=B6m?= , kernel@collabora.com, Matthew Auld , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" i965G[M] cannot relocate objects above 4GiB. Ensure ttm uses dma32 on these systems. Signed-off-by: Robert Beckett Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/intel_region_ttm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c b/drivers/gpu/drm/i915/intel_region_ttm.c index 6873808a7015..642cd1587976 100644 --- a/drivers/gpu/drm/i915/intel_region_ttm.c +++ b/drivers/gpu/drm/i915/intel_region_ttm.c @@ -32,10 +32,15 @@ int intel_region_ttm_device_init(struct drm_i915_private *dev_priv) { struct drm_device *drm = &dev_priv->drm; + bool use_dma32 = false; + + /* i965g[m] cannot relocate objects above 4GiB. */ + if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) + use_dma32 = true; return ttm_device_init(&dev_priv->bdev, i915_ttm_driver(), drm->dev, drm->anon_inode->i_mapping, - drm->vma_offset_manager, false, false); + drm->vma_offset_manager, false, use_dma32); } /** From patchwork Wed Jul 13 13:38:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bob Beckett X-Patchwork-Id: 12916745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA5B9C433EF for ; Wed, 13 Jul 2022 13:38:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 057EB10EDDD; Wed, 13 Jul 2022 13:38:44 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by gabe.freedesktop.org (Postfix) with ESMTPS id EAA3A10EDC0; Wed, 13 Jul 2022 13:38:41 +0000 (UTC) Received: from hermes-devbox.fritz.box (82-71-8-225.dsl.in-addr.zen.co.uk [82.71.8.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbeckett) by madras.collabora.co.uk (Postfix) with ESMTPSA id 632D16601A38; Wed, 13 Jul 2022 14:38:40 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657719520; bh=MULA0VYW5/ZsE36/5dPbAjqG53dPkqcAhW75h7Y1TfQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cIJZean/Ej7PP3OF5y1A3OkXa1CRe5VjtnLF6pQpm5mvLFrIYQu5mszkEgIZSv6er kNamHq30zLceAEkU/hxDzrfjjt++aGdTh6gM2O/Yt7e1PeDVfIicAO7asFOWs1zNse 0fUdAWKJuygFhuQuWYJKUwAx3QkfarSMXpWbj4+yg5WYZLypCOIxi5ee0AqfM055jx zulxhPbt03iT/oCow4i8dLyzz+xYwry1CuiMdQRnX+KRZ7qloONn5VU+pI8D9imb/e peQ904yhs0ykcAn7mieEL/Ftqpgfmj6bPrSXuJCXmBWi2do6qpX1EnBL7pEbJVssny bpYpmNs99ZObg== From: Robert Beckett To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH v4 3/8] drm/i915/ttm: only trust snooping for dgfx when deciding default cache_level Date: Wed, 13 Jul 2022 14:38:13 +0100 Message-Id: <20220713133818.3699604-4-bob.beckett@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713133818.3699604-1-bob.beckett@collabora.com> References: <20220713133818.3699604-1-bob.beckett@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Beckett , =?utf-8?q?Thomas_Hellstr?= =?utf-8?q?=C3=B6m?= , kernel@collabora.com, Matthew Auld , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP. This is divergent from existing backends code which only considers HAS_LLC. Testing shows that trusting snooping on gen5- is unreliable and bsw via ggtt mappings, so limit DGFX for now and maintain previous behaviour. Signed-off-by: Robert Beckett Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c index 042c2237e287..a949594237d9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c @@ -52,7 +52,9 @@ static enum i915_cache_level i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res, struct ttm_tt *ttm) { - return ((HAS_LLC(i915) || HAS_SNOOP(i915)) && + bool can_snoop = HAS_SNOOP(i915) && IS_DGFX(i915); + + return ((HAS_LLC(i915) || can_snoop) && !i915_ttm_gtt_binds_lmem(res) && ttm->caching == ttm_cached) ? I915_CACHE_LLC : I915_CACHE_NONE; From patchwork Wed Jul 13 13:38:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bob Beckett X-Patchwork-Id: 12916748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0991FCCA479 for ; Wed, 13 Jul 2022 13:39:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EB28112088; Wed, 13 Jul 2022 13:38:52 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1CC8010E95B; Wed, 13 Jul 2022 13:38:43 +0000 (UTC) Received: from hermes-devbox.fritz.box (82-71-8-225.dsl.in-addr.zen.co.uk [82.71.8.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbeckett) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2532366019C5; Wed, 13 Jul 2022 14:38:41 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657719521; bh=5MPDE6PLauo4xeTXuzQqjxRuaatIiJJgaRF7Azzw0o0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fEmBV92DTmAxhUcy73wR4rSi/rg1nPCZyXUE5o2+TmN6KaxS3kIYj/e5XIFnAyBOx oHVxY/754MrEjw2nIL7q/tTM/kAeMYYJzJYms7z7gzcTBucVvH4zzOULDbG3tb/Ngr +bOKljnG97lDg+SE8kMn51Olj0rNBz0E/HXiVnecfa9W7REPoRoarOrMFNRW7//xKJ ArURia99XXqHlb41YhvOTSewyF8HPXzBblL9FcYr8nLRJcuVssiwo6jbSd6Y+DrHTp 2SDmbWfVTghCEBC3lAwk+0ya7UX0MJGQmWx7xON9KK3oReRXUrh1fWVpTSexM2fq6B 7SwKcm1H1eP/A== From: Robert Beckett To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH v4 4/8] drm/i915: add gen6 ppgtt dummy creation function Date: Wed, 13 Jul 2022 14:38:14 +0100 Message-Id: <20220713133818.3699604-5-bob.beckett@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713133818.3699604-1-bob.beckett@collabora.com> References: <20220713133818.3699604-1-bob.beckett@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Beckett , =?utf-8?q?Thomas_Hellstr?= =?utf-8?q?=C3=B6m?= , kernel@collabora.com, Matthew Auld , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Internal gem objects will soon just be volatile system memory region objects. To enable this, create a separate dummy object creation function for gen6 ppgtt. The object only exists as a fake object pointing to ggtt and gains no benefit in going via the internal backend. Instead, create a dummy gem object and avoid having to maintain a custom ops api in the internal backend, which makes later refactoring easier. Signed-off-by: Robert Beckett --- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 43 ++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index 1bb766c79dcb..f3b660cfeb7f 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -372,6 +372,45 @@ static const struct drm_i915_gem_object_ops pd_dummy_obj_ops = { .put_pages = pd_dummy_obj_put_pages, }; +static struct drm_i915_gem_object * +i915_gem_object_create_dummy(struct drm_i915_private *i915, phys_addr_t size) +{ + static struct lock_class_key lock_class; + struct drm_i915_gem_object *obj; + unsigned int cache_level; + + GEM_BUG_ON(!size); + GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE)); + + if (overflows_type(size, obj->base.size)) + return ERR_PTR(-E2BIG); + + obj = i915_gem_object_alloc(); + if (!obj) + return ERR_PTR(-ENOMEM); + + drm_gem_private_object_init(&i915->drm, &obj->base, size); + i915_gem_object_init(obj, &pd_dummy_obj_ops, &lock_class, 0); + obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE; + + /* + * Mark the object as volatile, such that the pages are marked as + * dontneed whilst they are still pinned. As soon as they are unpinned + * they are allowed to be reaped by the shrinker, and the caller is + * expected to repopulate - the contents of this object are only valid + * whilst active and pinned. + */ + i915_gem_object_set_volatile(obj); + + obj->read_domains = I915_GEM_DOMAIN_CPU; + obj->write_domain = I915_GEM_DOMAIN_CPU; + + cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); + + return obj; +} + static struct i915_page_directory * gen6_alloc_top_pd(struct gen6_ppgtt *ppgtt) { @@ -383,9 +422,7 @@ gen6_alloc_top_pd(struct gen6_ppgtt *ppgtt) if (unlikely(!pd)) return ERR_PTR(-ENOMEM); - pd->pt.base = __i915_gem_object_create_internal(ppgtt->base.vm.gt->i915, - &pd_dummy_obj_ops, - I915_PDES * SZ_4K); + pd->pt.base = i915_gem_object_create_dummy(ppgtt->base.vm.gt->i915, I915_PDES * SZ_4K); if (IS_ERR(pd->pt.base)) { err = PTR_ERR(pd->pt.base); pd->pt.base = NULL; From patchwork Wed Jul 13 13:38:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bob Beckett X-Patchwork-Id: 12916749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9AABC433EF for ; Wed, 13 Jul 2022 13:39:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7BCAE10FD84; Wed, 13 Jul 2022 13:38:52 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id 848F910EE98; Wed, 13 Jul 2022 13:38:44 +0000 (UTC) Received: from hermes-devbox.fritz.box (82-71-8-225.dsl.in-addr.zen.co.uk [82.71.8.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbeckett) by madras.collabora.co.uk (Postfix) with ESMTPSA id 730B66601A3B; Wed, 13 Jul 2022 14:38:42 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657719522; bh=wMtiwAPPFkbj5c6Y/VFgLDdO9V1ZdhLdYyD12xWGZnY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VkI6Ufhg1JdkgWJsynvx452joDHC+ZRzNriatrw3ve0kT+8VrY9RZFqB+6FmZG4kP ieNqkP2D/WcwD3R3f2obJv/4kqaA9joUTwDHFUYhsxxMrb12v5bJqIt47fQLMldRf0 Uqgz95jQoOa7tA4dRSu+Y/LTn5TVpcpRkn+0r22xRdfcU/yZgnZtSB8HNvdEeCBuE2 yKE+cSZutm5kWlfaSFyzPl5OFtf1nXQkvo4oWLEMYJzdQsvZyc4pj3gbp5hdaN9G+f fKI8pQ1mYpoKgKW1AXwyJaPDJkuIHY5u+1MQb08+/H66LiNhpK3zLKduiPEwINTyG5 BjNhzIPLw1jRQ== From: Robert Beckett To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH v4 5/8] drm/i915: setup ggtt scratch page after memory regions Date: Wed, 13 Jul 2022 14:38:15 +0100 Message-Id: <20220713133818.3699604-6-bob.beckett@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713133818.3699604-1-bob.beckett@collabora.com> References: <20220713133818.3699604-1-bob.beckett@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Beckett , =?utf-8?q?Thomas_Hellstr?= =?utf-8?q?=C3=B6m?= , kernel@collabora.com, Matthew Auld , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Reorder scratch page allocation so that memory regions are available to allocate the buffers Signed-off-by: Robert Beckett Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 20 ++++++++++++++++++-- drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + drivers/gpu/drm/i915/i915_driver.c | 16 ++++++++++------ 3 files changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 15a915bb4088..c4ad03e53236 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -866,8 +866,6 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) struct drm_i915_private *i915 = ggtt->vm.i915; struct pci_dev *pdev = to_pci_dev(i915->drm.dev); phys_addr_t phys_addr; - u32 pte_flags; - int ret; GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915)); phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915); @@ -889,6 +887,24 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) } kref_init(&ggtt->vm.resv_ref); + + return 0; +} + +/** + * i915_ggtt_setup_scratch_page - setup ggtt scratch page + * @i915: i915 device + */ +int i915_ggtt_setup_scratch_page(struct drm_i915_private *i915) +{ + struct i915_ggtt *ggtt = to_gt(i915)->ggtt; + u32 pte_flags; + int ret; + + /* gen5- scratch setup currently happens in @intel_gtt_init */ + if (GRAPHICS_VER(i915) <= 5) + return 0; + ret = setup_scratch_page(&ggtt->vm); if (ret) { drm_err(&i915->drm, "Scratch setup failed\n"); diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index e639434e97fd..4ebdf70b5273 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -579,6 +579,7 @@ void intel_ggtt_unbind_vma(struct i915_address_space *vm, struct i915_vma_resource *vma_res); int i915_ggtt_probe_hw(struct drm_i915_private *i915); +int i915_ggtt_setup_scratch_page(struct drm_i915_private *i915); int i915_ggtt_init_hw(struct drm_i915_private *i915); int i915_ggtt_enable_hw(struct drm_i915_private *i915); void i915_ggtt_enable_guc(struct i915_ggtt *ggtt); diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index deb8a8b76965..fa0956840fcc 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -69,6 +69,7 @@ #include "gem/i915_gem_mman.h" #include "gem/i915_gem_pm.h" #include "gt/intel_gt.h" +#include "gt/intel_gtt.h" #include "gt/intel_gt_pm.h" #include "gt/intel_rc6.h" @@ -609,12 +610,16 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) ret = intel_gt_tiles_init(dev_priv); if (ret) - goto err_mem_regions; + goto err_ggtt; + + ret = i915_ggtt_setup_scratch_page(dev_priv); + if (ret) + goto err_ggtt; ret = i915_ggtt_enable_hw(dev_priv); if (ret) { drm_err(&dev_priv->drm, "failed to enable GGTT\n"); - goto err_mem_regions; + goto err_ggtt; } pci_set_master(pdev); @@ -675,11 +680,10 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) err_msi: if (pdev->msi_enabled) pci_disable_msi(pdev); -err_mem_regions: - intel_memory_regions_driver_release(dev_priv); err_ggtt: i915_ggtt_driver_release(dev_priv); i915_gem_drain_freed_objects(dev_priv); + intel_memory_regions_driver_release(dev_priv); i915_ggtt_driver_late_release(dev_priv); err_perf: i915_perf_fini(dev_priv); @@ -928,9 +932,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) intel_modeset_driver_remove_nogem(i915); out_cleanup_hw: i915_driver_hw_remove(i915); - intel_memory_regions_driver_release(i915); i915_ggtt_driver_release(i915); i915_gem_drain_freed_objects(i915); + intel_memory_regions_driver_release(i915); i915_ggtt_driver_late_release(i915); out_cleanup_mmio: i915_driver_mmio_release(i915); @@ -987,9 +991,9 @@ static void i915_driver_release(struct drm_device *dev) i915_gem_driver_release(dev_priv); - intel_memory_regions_driver_release(dev_priv); i915_ggtt_driver_release(dev_priv); i915_gem_drain_freed_objects(dev_priv); + intel_memory_regions_driver_release(dev_priv); i915_ggtt_driver_late_release(dev_priv); i915_driver_mmio_release(dev_priv); From patchwork Wed Jul 13 13:38:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bob Beckett X-Patchwork-Id: 12916746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 973B4CCA479 for ; Wed, 13 Jul 2022 13:39:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 800B61121B4; Wed, 13 Jul 2022 13:38:49 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id D67B810EF2E; Wed, 13 Jul 2022 13:38:44 +0000 (UTC) Received: from hermes-devbox.fritz.box (82-71-8-225.dsl.in-addr.zen.co.uk [82.71.8.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbeckett) by madras.collabora.co.uk (Postfix) with ESMTPSA id 132556601A3F; Wed, 13 Jul 2022 14:38:43 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657719523; bh=MjcvOf0vDzQBv8L9PWE+EuweTtTAL68jhBOjMGIS5/w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NBxa3dKzpn0swOp/aq/dWp6Jm6MmA6wiKmCmGAIwRdhIwGbv3Y6OIi4grMy4i+YEs Ot66paKWdZYRIjPbryo7xwOYBT+OWWRfF5qYmFizAcYkXI4P4jEG8B9tW99FLviNAT CAlDIJ7CfDRaOxfgzkDUSs5K9AHDtJNfVazUCJ+cpsfYSMFG9A7QweMW3EfDqPOxFw zYHgskI1+3KPAdnD7Hv+UpIXz//vdPAOHeg71nL0zfeMnVoFR7OYT2hg2IgWl0GEi1 xC6ea30gY1s8itAmjAr2tZxNWAZxXjgFevBEKRdgUHYrNkO7LWxZHTian+6bl82bwW RbaMqt3LkkAyA== From: Robert Beckett To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH v4 6/8] drm/i915: allow volatile buffers to use ttm pool allocator Date: Wed, 13 Jul 2022 14:38:16 +0100 Message-Id: <20220713133818.3699604-7-bob.beckett@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713133818.3699604-1-bob.beckett@collabora.com> References: <20220713133818.3699604-1-bob.beckett@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Beckett , =?utf-8?q?Thomas_Hellstr?= =?utf-8?q?=C3=B6m?= , kernel@collabora.com, Matthew Auld , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Internal/volatile buffers should not be shmem backed. If a volatile buffer is requested, allow ttm to use the pool allocator to provide volatile pages as backing. Fix i915_ttm_shrink to handle !is_shmem volatile buffers by purging. Signed-off-by: Robert Beckett --- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c index b6c3fc25d9d1..599ed2713359 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c @@ -291,7 +291,8 @@ static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo, page_flags |= TTM_TT_FLAG_ZERO_ALLOC; caching = i915_ttm_select_tt_caching(obj); - if (i915_gem_object_is_shrinkable(obj) && caching == ttm_cached) { + if (i915_gem_object_is_shrinkable(obj) && caching == ttm_cached && + !i915_gem_object_is_volatile(obj)) { page_flags |= TTM_TT_FLAG_EXTERNAL | TTM_TT_FLAG_EXTERNAL_MAPPABLE; i915_tt->is_shmem = true; @@ -513,9 +514,9 @@ static int i915_ttm_shrink(struct drm_i915_gem_object *obj, unsigned int flags) if (!bo->ttm || bo->resource->mem_type != TTM_PL_SYSTEM) return 0; - GEM_BUG_ON(!i915_tt->is_shmem); + GEM_BUG_ON(!i915_tt->is_shmem && obj->mm.madv != I915_MADV_DONTNEED); - if (!i915_tt->filp) + if (i915_tt->is_shmem && !i915_tt->filp) return 0; ret = ttm_bo_wait_ctx(bo, &ctx); From patchwork Wed Jul 13 13:38:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bob Beckett X-Patchwork-Id: 12916747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76EDBC433EF for ; Wed, 13 Jul 2022 13:39:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6123410F02C; Wed, 13 Jul 2022 13:38:52 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9E6D810F02E; Wed, 13 Jul 2022 13:38:45 +0000 (UTC) Received: from hermes-devbox.fritz.box (82-71-8-225.dsl.in-addr.zen.co.uk [82.71.8.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbeckett) by madras.collabora.co.uk (Postfix) with ESMTPSA id B61A86601A43; Wed, 13 Jul 2022 14:38:43 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657719524; bh=pC7awPtmZC2mFd+19i2l1IB+tj4ajR5y+F+FffFXf70=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eENa0HlmOE2bYpysdWfOu0JXSA4dc4rHgxYQgeSFirIzEHhI2rQj5YMjvTK5ZRM/E aVQb0tXNjuiZDc2VI8YP+NWJVZkuYBXYv/cZzgWt5Car68qHFem2UtPMoa0B5vwZBs oFsn1amUKSJSHnmCYZUuTFedl5ykMygB8kCoV2YjQhoqQes/Wc8opghkNiH3Xh5mZc rP+F7GXh6VQAaAerlfadxcdRVCGyNqhMmLRwHF+lV7LHgBpzS6cS4RzduTN/3LVgKC 8zZzal98S/w0CyidXsNBxSpnZlOJJf0Y+P7x4mCdVziwx7JER0+ha4Fe5uGiJkYCF2 omxz5EStibk4w== From: Robert Beckett To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH v4 7/8] drm/i915/gem: further fix mman selftest Date: Wed, 13 Jul 2022 14:38:17 +0100 Message-Id: <20220713133818.3699604-8-bob.beckett@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713133818.3699604-1-bob.beckett@collabora.com> References: <20220713133818.3699604-1-bob.beckett@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Beckett , =?utf-8?q?Thomas_Hellstr?= =?utf-8?q?=C3=B6m?= , kernel@collabora.com, Matthew Auld , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In commit 450cede7f380 ("drm/i915/gem: Fix the mman selftest") we fixed up the mman selftest to allocate user buffers via smem only if we have lmem, otherwise it uses internal buffers. As the commit message asserts, we should only be using buffers that userland should be able to create. Internal buffers are not intended to be used by userland. Instead, fix the code to always create buffers from smem. In the case of integrated, this will create them from the shmem non-ttm backend, which is fine. This also fixes up the code to allow conversion of internal backend to ttm without breaking this test. Signed-off-by: Robert Beckett --- .../gpu/drm/i915/gem/selftests/i915_gem_mman.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index 3ced9948a331..e529eb8461ff 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -596,17 +596,12 @@ static enum i915_mmap_type default_mapping(struct drm_i915_private *i915) } static struct drm_i915_gem_object * -create_sys_or_internal(struct drm_i915_private *i915, - unsigned long size) +create_sys(struct drm_i915_private *i915, unsigned long size) { - if (HAS_LMEM(i915)) { - struct intel_memory_region *sys_region = - i915->mm.regions[INTEL_REGION_SMEM]; + struct intel_memory_region *sys_region = + i915->mm.regions[INTEL_REGION_SMEM]; - return __i915_gem_object_create_user(i915, size, &sys_region, 1); - } - - return i915_gem_object_create_internal(i915, size); + return __i915_gem_object_create_user(i915, size, &sys_region, 1); } static bool assert_mmap_offset(struct drm_i915_private *i915, @@ -617,7 +612,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915, u64 offset; int ret; - obj = create_sys_or_internal(i915, size); + obj = create_sys(i915, size); if (IS_ERR(obj)) return expected && expected == PTR_ERR(obj); @@ -719,7 +714,7 @@ static int igt_mmap_offset_exhaustion(void *arg) } /* Fill the hole, further allocation attempts should then fail */ - obj = create_sys_or_internal(i915, PAGE_SIZE); + obj = create_sys(i915, PAGE_SIZE); if (IS_ERR(obj)) { err = PTR_ERR(obj); pr_err("Unable to create object for reclaimed hole\n"); From patchwork Wed Jul 13 13:38:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bob Beckett X-Patchwork-Id: 12916750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89413C43334 for ; Wed, 13 Jul 2022 13:39:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5807B112B7B; Wed, 13 Jul 2022 13:38:53 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6526C10EE98; Wed, 13 Jul 2022 13:38:46 +0000 (UTC) Received: from hermes-devbox.fritz.box (82-71-8-225.dsl.in-addr.zen.co.uk [82.71.8.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbeckett) by madras.collabora.co.uk (Postfix) with ESMTPSA id D76F96601A47; Wed, 13 Jul 2022 14:38:44 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657719525; bh=Yl1XEZbrkHnzVcWcXJexMKIDImLbuTydhrPuaociHvA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oMyqZ8/P8ju3QFe1kmxWFyAFU1mYbKdTs5TFClEBFxQIZG+FYeNUaAfHdV9aFimzn 1gwcWebHZ0yw60D2suQqjJmQ97ugxzP8tTAWuPmI1vY0XP7YfxKk3aY2MHmBCjRRTr plZ2axD75UKamvUUuFlJ7B9pFhqG7vvF7dh6y2+uawBANdNu7qp2daPvd2B1kc6BIa E9ve8BEUupeUYaJVItcBv/iA/0FKOLGpNCh8wkOrDobVylijUDUVePDy7zr9cWP53k kNuMmvz41AOSAQd07JKKpy7g09P+FsiFTOriUx6ckzIXENXW39dlSALhXQHSEsZo8b a8Lwrj1tbvkpw== From: Robert Beckett To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Daniel Vetter Subject: [PATCH v4 8/8] drm/i915: internal buffers use ttm backend Date: Wed, 13 Jul 2022 14:38:18 +0100 Message-Id: <20220713133818.3699604-9-bob.beckett@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713133818.3699604-1-bob.beckett@collabora.com> References: <20220713133818.3699604-1-bob.beckett@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Beckett , =?utf-8?q?Thomas_Hellstr?= =?utf-8?q?=C3=B6m?= , kernel@collabora.com, Matthew Auld , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Create a kernel only internal memory region that uses ttm pool allocator to allocate volatile system pages. Refactor internal buffer backend to simply allocate from this new region. Signed-off-by: Robert Beckett --- drivers/gpu/drm/i915/gem/i915_gem_internal.c | 187 +----------------- drivers/gpu/drm/i915/gem/i915_gem_internal.h | 5 - drivers/gpu/drm/i915/i915_pci.c | 4 +- drivers/gpu/drm/i915/intel_memory_region.c | 8 +- drivers/gpu/drm/i915/intel_memory_region.h | 2 + .../gpu/drm/i915/selftests/mock_gem_device.c | 2 +- 6 files changed, 17 insertions(+), 191 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c b/drivers/gpu/drm/i915/gem/i915_gem_internal.c index c698f95af15f..a83751867ac7 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c @@ -4,188 +4,9 @@ * Copyright © 2014-2016 Intel Corporation */ -#include -#include -#include - +#include "gem/i915_gem_internal.h" +#include "gem/i915_gem_region.h" #include "i915_drv.h" -#include "i915_gem.h" -#include "i915_gem_internal.h" -#include "i915_gem_object.h" -#include "i915_scatterlist.h" -#include "i915_utils.h" - -#define QUIET (__GFP_NORETRY | __GFP_NOWARN) -#define MAYFAIL (__GFP_RETRY_MAYFAIL | __GFP_NOWARN) - -static void internal_free_pages(struct sg_table *st) -{ - struct scatterlist *sg; - - for (sg = st->sgl; sg; sg = __sg_next(sg)) { - if (sg_page(sg)) - __free_pages(sg_page(sg), get_order(sg->length)); - } - - sg_free_table(st); - kfree(st); -} - -static int i915_gem_object_get_pages_internal(struct drm_i915_gem_object *obj) -{ - struct drm_i915_private *i915 = to_i915(obj->base.dev); - struct sg_table *st; - struct scatterlist *sg; - unsigned int sg_page_sizes; - unsigned int npages; - int max_order; - gfp_t gfp; - - max_order = MAX_ORDER; -#ifdef CONFIG_SWIOTLB - if (is_swiotlb_active(obj->base.dev->dev)) { - unsigned int max_segment; - - max_segment = swiotlb_max_segment(); - if (max_segment) { - max_segment = max_t(unsigned int, max_segment, - PAGE_SIZE) >> PAGE_SHIFT; - max_order = min(max_order, ilog2(max_segment)); - } - } -#endif - - gfp = GFP_KERNEL | __GFP_HIGHMEM | __GFP_RECLAIMABLE; - if (IS_I965GM(i915) || IS_I965G(i915)) { - /* 965gm cannot relocate objects above 4GiB. */ - gfp &= ~__GFP_HIGHMEM; - gfp |= __GFP_DMA32; - } - -create_st: - st = kmalloc(sizeof(*st), GFP_KERNEL); - if (!st) - return -ENOMEM; - - npages = obj->base.size / PAGE_SIZE; - if (sg_alloc_table(st, npages, GFP_KERNEL)) { - kfree(st); - return -ENOMEM; - } - - sg = st->sgl; - st->nents = 0; - sg_page_sizes = 0; - - do { - int order = min(fls(npages) - 1, max_order); - struct page *page; - - do { - page = alloc_pages(gfp | (order ? QUIET : MAYFAIL), - order); - if (page) - break; - if (!order--) - goto err; - - /* Limit subsequent allocations as well */ - max_order = order; - } while (1); - - sg_set_page(sg, page, PAGE_SIZE << order, 0); - sg_page_sizes |= PAGE_SIZE << order; - st->nents++; - - npages -= 1 << order; - if (!npages) { - sg_mark_end(sg); - break; - } - - sg = __sg_next(sg); - } while (1); - - if (i915_gem_gtt_prepare_pages(obj, st)) { - /* Failed to dma-map try again with single page sg segments */ - if (get_order(st->sgl->length)) { - internal_free_pages(st); - max_order = 0; - goto create_st; - } - goto err; - } - - __i915_gem_object_set_pages(obj, st, sg_page_sizes); - - return 0; - -err: - sg_set_page(sg, NULL, 0, 0); - sg_mark_end(sg); - internal_free_pages(st); - - return -ENOMEM; -} - -static void i915_gem_object_put_pages_internal(struct drm_i915_gem_object *obj, - struct sg_table *pages) -{ - i915_gem_gtt_finish_pages(obj, pages); - internal_free_pages(pages); - - obj->mm.dirty = false; - - __start_cpu_write(obj); -} - -static const struct drm_i915_gem_object_ops i915_gem_object_internal_ops = { - .name = "i915_gem_object_internal", - .flags = I915_GEM_OBJECT_IS_SHRINKABLE, - .get_pages = i915_gem_object_get_pages_internal, - .put_pages = i915_gem_object_put_pages_internal, -}; - -struct drm_i915_gem_object * -__i915_gem_object_create_internal(struct drm_i915_private *i915, - const struct drm_i915_gem_object_ops *ops, - phys_addr_t size) -{ - static struct lock_class_key lock_class; - struct drm_i915_gem_object *obj; - unsigned int cache_level; - - GEM_BUG_ON(!size); - GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE)); - - if (overflows_type(size, obj->base.size)) - return ERR_PTR(-E2BIG); - - obj = i915_gem_object_alloc(); - if (!obj) - return ERR_PTR(-ENOMEM); - - drm_gem_private_object_init(&i915->drm, &obj->base, size); - i915_gem_object_init(obj, ops, &lock_class, 0); - obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE; - - /* - * Mark the object as volatile, such that the pages are marked as - * dontneed whilst they are still pinned. As soon as they are unpinned - * they are allowed to be reaped by the shrinker, and the caller is - * expected to repopulate - the contents of this object are only valid - * whilst active and pinned. - */ - i915_gem_object_set_volatile(obj); - - obj->read_domains = I915_GEM_DOMAIN_CPU; - obj->write_domain = I915_GEM_DOMAIN_CPU; - - cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; - i915_gem_object_set_cache_coherency(obj, cache_level); - - return obj; -} /** * i915_gem_object_create_internal: create an object with volatile pages @@ -206,5 +27,7 @@ struct drm_i915_gem_object * i915_gem_object_create_internal(struct drm_i915_private *i915, phys_addr_t size) { - return __i915_gem_object_create_internal(i915, &i915_gem_object_internal_ops, size); + return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_INTERNAL], + size, 0, I915_BO_ALLOC_VOLATILE); } + diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.h b/drivers/gpu/drm/i915/gem/i915_gem_internal.h index 6664e06112fc..524e1042b20f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_internal.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.h @@ -15,9 +15,4 @@ struct drm_i915_private; struct drm_i915_gem_object * i915_gem_object_create_internal(struct drm_i915_private *i915, phys_addr_t size); -struct drm_i915_gem_object * -__i915_gem_object_create_internal(struct drm_i915_private *i915, - const struct drm_i915_gem_object_ops *ops, - phys_addr_t size); - #endif /* __I915_GEM_INTERNAL_H__ */ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index aacc10f2e73f..48b27de8cbba 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -162,7 +162,7 @@ .page_sizes = I915_GTT_PAGE_SIZE_4K #define GEN_DEFAULT_REGIONS \ - .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM + .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM | REGION_INTERNAL #define I830_FEATURES \ GEN(2), \ @@ -908,7 +908,7 @@ static const struct intel_device_info rkl_info = { }; #define DGFX_FEATURES \ - .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ + .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM | REGION_INTERNAL, \ .has_llc = 0, \ .has_pxp = 0, \ .has_snoop = 1, \ diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c index 9a4a7fb55582..e950b0a125ad 100644 --- a/drivers/gpu/drm/i915/intel_memory_region.c +++ b/drivers/gpu/drm/i915/intel_memory_region.c @@ -31,6 +31,10 @@ static const struct { .class = INTEL_MEMORY_STOLEN_LOCAL, .instance = 0, }, + [INTEL_REGION_INTERNAL] = { + .class = INTEL_MEMORY_SYSTEM, + .instance = 1, + } }; static int __iopagetest(struct intel_memory_region *mem, @@ -321,12 +325,14 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915) instance = intel_region_map[i].instance; switch (type) { case INTEL_MEMORY_SYSTEM: - if (IS_DGFX(i915)) + if (IS_DGFX(i915) || i == INTEL_REGION_INTERNAL) mem = i915_gem_ttm_system_setup(i915, type, instance); else mem = i915_gem_shmem_setup(i915, type, instance); + if (i == INTEL_REGION_INTERNAL) + mem->private = true; break; case INTEL_MEMORY_STOLEN_LOCAL: mem = i915_gem_stolen_lmem_setup(i915, type, instance); diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h index 2953ed5c3248..d9cc1d8044b1 100644 --- a/drivers/gpu/drm/i915/intel_memory_region.h +++ b/drivers/gpu/drm/i915/intel_memory_region.h @@ -35,6 +35,7 @@ enum intel_region_id { INTEL_REGION_LMEM_3, INTEL_REGION_STOLEN_SMEM, INTEL_REGION_STOLEN_LMEM, + INTEL_REGION_INTERNAL, INTEL_REGION_UNKNOWN, /* Should be last */ }; @@ -42,6 +43,7 @@ enum intel_region_id { #define REGION_LMEM BIT(INTEL_REGION_LMEM_0) #define REGION_STOLEN_SMEM BIT(INTEL_REGION_STOLEN_SMEM) #define REGION_STOLEN_LMEM BIT(INTEL_REGION_STOLEN_LMEM) +#define REGION_INTERNAL BIT(INTEL_REGION_INTERNAL) #define I915_ALLOC_CONTIGUOUS BIT(0) diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 9c31a16f8380..eaa169effedc 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -179,7 +179,7 @@ struct drm_i915_private *mock_gem_device(void) I915_GTT_PAGE_SIZE_64K | I915_GTT_PAGE_SIZE_2M; - mkwrite_device_info(i915)->memory_regions = REGION_SMEM; + mkwrite_device_info(i915)->memory_regions = REGION_SMEM | REGION_INTERNAL; intel_memory_regions_hw_probe(i915); spin_lock_init(&i915->gpu_error.lock);