From patchwork Wed Jul 13 16:24:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 12916953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47063C433EF for ; Wed, 13 Jul 2022 16:28:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236409AbiGMQ2m (ORCPT ); Wed, 13 Jul 2022 12:28:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234823AbiGMQ2k (ORCPT ); Wed, 13 Jul 2022 12:28:40 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 661666348; Wed, 13 Jul 2022 09:28:35 -0700 (PDT) Received: from localhost (dynamic-002-247-252-243.2.247.pool.telefonica.de [2.247.252.243]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9E2F8660191C; Wed, 13 Jul 2022 17:28:33 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657729714; bh=dJh6TqCFVIUYIG8O0aBeAq5rq/VBA2Im5Q+ZRYT8lro=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a6WPp2cx+hVRx5U3ybwnmetov9HEN13GabDTk+sbunaDETcMnWuPus04kDprjCFiS ytDeZtW299OoiBns2nUWDx1Zbr4YxLxdNThwuMI1KqvnSUAA89Ld4QZUxUbbCXy5iU JEwc3ASWXqG76O9F9qbBODEJufki6ttpdiV1qR3/JtPB8IEQAqWaCtHHNery1YnwXc OGj+gF7ZWal7pk4V7SOuR/72lJqXWq0syJlc2DvkXjCEqmWjPlwXFyXpNFpUWy2lLV xxUPmpvD5ALeGGzVORXdHd1aJ8s3uD2GlxmFYOsOar64hUpuliq4AlqOWW3XCml6rL hjIeM9kxm6wMA== From: Sebastian Fricke To: linux-media@vger.kernel.org Cc: jernej.skrabec@gmail.com, knaerzche@gmail.com, kernel@collabora.com, bob.beckett@collabora.com, ezequiel@vanguardiasur.com.ar, mchehab@kernel.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, nicolas.dufresne@collabora.com, Jonas Karlman , Sebastian Fricke , Yury Norov , Andy Shevchenko , Rasmus Villemoes , Hans Verkuil , Benjamin Gaignard , Ming Qian , Sakari Ailus , Laurent Pinchart , Ricardo Ribalda , Andrzej Pietrasiewicz , Sergey Senozhatsky Subject: [PATCH 1/6] media: v4l2: Add NV15 pixel format Date: Wed, 13 Jul 2022 18:24:46 +0200 Message-Id: <20220713162449.133738-2-sebastian.fricke@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713162449.133738-1-sebastian.fricke@collabora.com> References: <20220713162449.133738-1-sebastian.fricke@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonas Karlman Add the NV15 pixel format used by the Rockchip Video Decoder for 10-bit buffers. NV15 is a packed 10-bit 4:2:0 Y/CbCr format similar to P010 and P210 but has no padding between components. Instead, luminance and chrominance samples are grouped into 4s so that each group is packed into an integer number of bytes: YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes The '15' suffix refers to the optimum effective bits per pixel which is achieved when the total number of luminance samples is a multiple of 8 for NV15. Signed-off-by: Jonas Karlman Signed-off-by: Sebastian Fricke --- .../media/v4l/pixfmt-yuv-planar.rst | 53 +++++++++++++++++++ drivers/media/v4l2-core/v4l2-common.c | 2 + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + include/uapi/linux/videodev2.h | 1 + 4 files changed, 57 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst index a900ff66911a..42ab3fe4667f 100644 --- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst +++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst @@ -79,6 +79,13 @@ All components are stored with the same number of bits per component. - Cr, Cb - Yes - Linear + * - V4L2_PIX_FMT_NV15 + - 'NV15' + - 15 + - 4:2:0 + - Cb, Cr + - Yes + - Linear * - V4L2_PIX_FMT_NV12M - 'NM12' - 8 @@ -176,6 +183,7 @@ horizontally. .. _V4L2-PIX-FMT-NV12: .. _V4L2-PIX-FMT-NV21: +.. _V4L2-PIX-FMT-NV15: .. _V4L2-PIX-FMT-NV12M: .. _V4L2-PIX-FMT-NV21M: .. _V4L2-PIX-FMT-P010: @@ -570,6 +578,51 @@ Data in the 10 high bits, zeros in the 6 low bits, arranged in little endian ord - Cb\ :sub:`11` - Cr\ :sub:`11` +.. _V4L2_PIX_FMT_NV15: + +NV15 +---- + +Like P010 but a packed 10-bit 4:2:0 semi-planar Y/CbCr format without padding between components. +Instead, luminance and chrominance samples are grouped into 4s so that each group is packed into an integer +number of bytes: +YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes + +.. flat-table:: Sample 4x4 NV15 Image + :header-rows: 0 + :stub-columns: 0 + + * - start + 0: + - Y'\ :sub:`00` + - Y'\ :sub:`01` + - Y'\ :sub:`02` + - Y'\ :sub:`03` + * - start + 8: + - Y'\ :sub:`10` + - Y'\ :sub:`11` + - Y'\ :sub:`12` + - Y'\ :sub:`13` + * - start + 16: + - Y'\ :sub:`20` + - Y'\ :sub:`21` + - Y'\ :sub:`22` + - Y'\ :sub:`23` + * - start + 24: + - Y'\ :sub:`30` + - Y'\ :sub:`31` + - Y'\ :sub:`32` + - Y'\ :sub:`33` + * - start + 32: + - Cb\ :sub:`00` + - Cr\ :sub:`00` + - Cb\ :sub:`01` + - Cr\ :sub:`01` + * - start + 40: + - Cb\ :sub:`10` + - Cr\ :sub:`10` + - Cb\ :sub:`11` + - Cr\ :sub:`11` + .. raw:: latex \endgroup diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c index 1e38ad8906a2..23a0cb02ea3a 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c @@ -262,6 +262,8 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) /* YUV planar formats */ { .format = V4L2_PIX_FMT_NV12, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 }, { .format = V4L2_PIX_FMT_NV21, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 }, + { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, + .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, { .format = V4L2_PIX_FMT_NV16, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 }, { .format = V4L2_PIX_FMT_NV61, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 }, { .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 }, diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index e2526701294e..9e5510cb255e 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1302,6 +1302,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_M420: descr = "YUV 4:2:0 (M420)"; break; case V4L2_PIX_FMT_NV12: descr = "Y/CbCr 4:2:0"; break; case V4L2_PIX_FMT_NV21: descr = "Y/CrCb 4:2:0"; break; + case V4L2_PIX_FMT_NV15: descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break; case V4L2_PIX_FMT_NV16: descr = "Y/CbCr 4:2:2"; break; case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break; case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 5a73b92ffe4d..47ff34d6b79f 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -598,6 +598,7 @@ struct v4l2_pix_format { /* two planes -- one Y, one Cr + Cb interleaved */ #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ #define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */ +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */ #define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ From patchwork Wed Jul 13 16:24:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 12916954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99451C43334 for ; Wed, 13 Jul 2022 16:29:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237213AbiGMQ3E (ORCPT ); Wed, 13 Jul 2022 12:29:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237208AbiGMQ3B (ORCPT ); Wed, 13 Jul 2022 12:29:01 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A4F812AEC; Wed, 13 Jul 2022 09:29:00 -0700 (PDT) Received: from localhost (dynamic-002-247-252-243.2.247.pool.telefonica.de [2.247.252.243]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id B56B2660191C; Wed, 13 Jul 2022 17:28:58 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657729739; bh=LVRQfIVTIi5K/igTKG49FQWCGWRcG10SSWqUlEl1A30=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aLXVbGm9zPp8AOmaiBTKwtKD+rzqutKp7ieoX6Rw5LrOL8/xdwkjEj57pRBNggZoD XNZ6jdDAKcflsD7qxqYNXTmUIrZv4nojTYgP4G+UC9BO/LaF5Dd8pd+Hmes8zt3JFJ vZ1tHcTOShe0+3QgIIMnYfaa2EUkf+RILQTQ0yXt98rr7TSnKe88El0gpfZmsJE1Te REfIzZFhQmPXyKN+4AR6oOhNEFk/SjCYTqvTK5GnE8YSwmrfdFsVYHfpu7YnseIFdg I7c3TSD/4evr/42bb8ublseYN54IhwPIDdjyDdSMZyWLIOKWmUPDXI9MmlsDihDTY+ GJwMjgHmCTVmg== From: Sebastian Fricke To: linux-media@vger.kernel.org Cc: jernej.skrabec@gmail.com, knaerzche@gmail.com, kernel@collabora.com, bob.beckett@collabora.com, ezequiel@vanguardiasur.com.ar, mchehab@kernel.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, nicolas.dufresne@collabora.com, Jonas Karlman , Yury Norov , Andy Shevchenko , Rasmus Villemoes , Hans Verkuil , Sebastian Fricke , Benjamin Gaignard Subject: [PATCH 2/6] media: v4l2-common: Add helpers to calculate bytesperline and sizeimage Date: Wed, 13 Jul 2022 18:24:48 +0200 Message-Id: <20220713162449.133738-3-sebastian.fricke@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713162449.133738-1-sebastian.fricke@collabora.com> References: <20220713162449.133738-1-sebastian.fricke@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jonas Karlman Add helper functions to calculate plane bytesperline and sizeimage, these new helpers consider block width and height when calculating plane bytesperline and sizeimage. This prepare support for new pixel formats added in next patch that make use of block width and height. Signed-off-by: Jonas Karlman --- drivers/media/v4l2-core/v4l2-common.c | 77 +++++++++++++-------------- 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c index 23a0cb02ea3a..2ed78f0af508 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c @@ -339,6 +339,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf return info->block_h[plane]; } +static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane, + unsigned int width) +{ + unsigned int hdiv = plane ? info->hdiv : 1; + unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane], + v4l2_format_block_width(info, plane) * + v4l2_format_block_height(info, plane)); + + return DIV_ROUND_UP(bytes, hdiv); +} + +static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane, + unsigned int height) +{ + unsigned int vdiv = plane ? info->vdiv : 1; + unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane)); + + return DIV_ROUND_UP(lines, vdiv); +} + +static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane, + unsigned int width, unsigned int height) +{ + return v4l2_format_plane_width(info, plane, width) * + v4l2_format_plane_height(info, plane, height); +} + void v4l2_apply_frmsize_constraints(u32 *width, u32 *height, const struct v4l2_frmsize_stepwise *frmsize) { @@ -374,37 +401,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, if (info->mem_planes == 1) { plane = &pixfmt->plane_fmt[0]; - plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0]; + plane->bytesperline = v4l2_format_plane_width(info, 0, width); plane->sizeimage = 0; - for (i = 0; i < info->comp_planes; i++) { - unsigned int hdiv = (i == 0) ? 1 : info->hdiv; - unsigned int vdiv = (i == 0) ? 1 : info->vdiv; - unsigned int aligned_width; - unsigned int aligned_height; - - aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); - aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); - - plane->sizeimage += info->bpp[i] * - DIV_ROUND_UP(aligned_width, hdiv) * - DIV_ROUND_UP(aligned_height, vdiv); - } + for (i = 0; i < info->comp_planes; i++) + plane->sizeimage += + v4l2_format_plane_size(info, i, width, height); } else { for (i = 0; i < info->comp_planes; i++) { - unsigned int hdiv = (i == 0) ? 1 : info->hdiv; - unsigned int vdiv = (i == 0) ? 1 : info->vdiv; - unsigned int aligned_width; - unsigned int aligned_height; - - aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); - aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); - plane = &pixfmt->plane_fmt[i]; plane->bytesperline = - info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv); - plane->sizeimage = - plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv); + v4l2_format_plane_width(info, i, width); + plane->sizeimage = plane->bytesperline * + v4l2_format_plane_height(info, i, height); } } return 0; @@ -428,22 +437,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, pixfmt->width = width; pixfmt->height = height; pixfmt->pixelformat = pixelformat; - pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0]; + pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width); pixfmt->sizeimage = 0; - for (i = 0; i < info->comp_planes; i++) { - unsigned int hdiv = (i == 0) ? 1 : info->hdiv; - unsigned int vdiv = (i == 0) ? 1 : info->vdiv; - unsigned int aligned_width; - unsigned int aligned_height; - - aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); - aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); - - pixfmt->sizeimage += info->bpp[i] * - DIV_ROUND_UP(aligned_width, hdiv) * - DIV_ROUND_UP(aligned_height, vdiv); - } + for (i = 0; i < info->comp_planes; i++) + pixfmt->sizeimage += + v4l2_format_plane_size(info, i, width, height); return 0; } EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt); From patchwork Wed Jul 13 16:31:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 12916955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B03C7C433EF for ; Wed, 13 Jul 2022 16:32:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237180AbiGMQcY (ORCPT ); Wed, 13 Jul 2022 12:32:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230114AbiGMQcW (ORCPT ); Wed, 13 Jul 2022 12:32:22 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D284C2B604; Wed, 13 Jul 2022 09:32:21 -0700 (PDT) Received: from localhost (dynamic-002-247-252-243.2.247.pool.telefonica.de [2.247.252.243]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4B99A660191C; Wed, 13 Jul 2022 17:32:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657729940; bh=dIzwKmgbXSEkeJxn4p/FQB/B/V+b2M0cBePpVdA5mgE=; h=From:To:Cc:Subject:Date:From; b=iku7kOjHUvAD7+D/BODOjWHZslQRXb7UfbF1HSjv41HaCqGg0CpgjSenu50rlKn1d 2db/FNN8L6TrGdl1rw5QfrLh5QN8SvdbKXlb0ZNDgN/R2qNvlAjcYwQhbWorgr2L7V ZL+LO4rmvAMh569pyL1jatslnrmQHdjfJigouTs310LHCdTrMBIdOn7m9Fj89T14r2 xb3fbgJUNLVFvxo5zGGl6CREebx30q44PXVp87jJkxwE4M7//JVQxPnPPUesQqnrgI nxHhzY7gumtvkffVS6kgM3hHF/2/U0v6eIrFnwIphbwwzIYF86WuxCtvwDxXGSU5dk JNw8+9GWDK97A== From: Sebastian Fricke To: linux-media@vger.kernel.org Cc: jernej.skrabec@gmail.com, knaerzche@gmail.com, kernel@collabora.com, bob.beckett@collabora.com, ezequiel@vanguardiasur.com.ar, mchehab@kernel.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, nicolas.dufresne@collabora.com, Sebastian Fricke , Yury Norov , Andy Shevchenko , Rasmus Villemoes Subject: [PATCH 3/6] bitops: bitmap helper to set variable length values Date: Wed, 13 Jul 2022 18:31:59 +0200 Message-Id: <20220713163201.136202-1-sebastian.fricke@collabora.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a new helper to set variable length values within a bitmap, that can overflow the borders of a single BITS_PER_LONG container. This function makes it easier to write values to hardware memory blobs that do not require alignment. Add tests to the lib/test_bitmap.c kselftest module to verify proper function. Signed-off-by: Sebastian Fricke --- include/linux/bitmap.h | 40 +++++++++++++++++++++++++++++++++++ lib/test_bitmap.c | 48 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h index 2e6cd5681040..9f8d635b70a9 100644 --- a/include/linux/bitmap.h +++ b/include/linux/bitmap.h @@ -76,6 +76,7 @@ struct device; * bitmap_to_arr64(buf, src, nbits) Copy nbits from buf to u64[] dst * bitmap_get_value8(map, start) Get 8bit value from map at start * bitmap_set_value8(map, value, start) Set 8bit value to map at start + * bitmap_set_value(map, value, start, nbits) Set a variable length value to map at start * * Note, bitmap_zero() and bitmap_fill() operate over the region of * unsigned longs, that is, bits behind bitmap till the unsigned long @@ -573,6 +574,45 @@ static inline void bitmap_set_value8(unsigned long *map, unsigned long value, map[index] |= value << offset; } +/** + * bitmap_set_value - set a variable length value within a memory region + * @map: address to the bitmap memory region + * @value: the variable length value + * @start: bit offset of the value + * @length: Length of the value + */ +static inline void bitmap_set_value(unsigned long *map, unsigned long value, + unsigned long start, unsigned char length) +{ + size_t index = BIT_WORD(start); + unsigned long offset = start % BITS_PER_LONG; + int diff_to_max = 0; + + if (!length) + return; + + + if (length < BITS_PER_LONG) + value &= (BIT(length) - 1); + + while (length > 0) { + diff_to_max = BITS_PER_LONG - offset; + map[index] &= ~((BIT(length) - 1) << offset); + if (length > diff_to_max) { + unsigned long tmp = value & (BIT(diff_to_max) - 1); + + map[index] |= tmp << offset; + value >>= diff_to_max; + length -= diff_to_max; + index += 1; + offset = 0; + } else { + map[index] |= value << offset; + length = 0; + } + } +} + #endif /* __ASSEMBLY__ */ #endif /* __LINUX_BITMAP_H */ diff --git a/lib/test_bitmap.c b/lib/test_bitmap.c index d5923a640457..509317ad2f72 100644 --- a/lib/test_bitmap.c +++ b/lib/test_bitmap.c @@ -869,6 +869,53 @@ static void __init test_bitmap_print_buf(void) } } +struct test_bitmap_set_value_sample { + unsigned long value[2]; + unsigned char length[2]; + unsigned int offset[2]; + unsigned long expected[2][2]; + int amount; +}; + +static const struct test_bitmap_set_value_sample test_set[] __initconst = { + /* Check that multiple values can be chained up */ + { {10, 20}, {4, 5}, {0, 4}, {{10, 330}}, 2 }, + /* Check that a value can be set across two BITS_PER_LONG chunks */ + { {10, 6}, {4, 3}, {0, 63}, {{10, 10}, {0, 3}}, 2 }, + /* Set a value with length shorter than the given length */ + { {3, 6}, {4, 10}, {0, 4}, {{3, 99}}, 1 }, + /* Set a value with length longer than the given length */ + { {15}, {2}, {0}, {{3}}, 1 }, + /* Check that values are properly overwritten */ + { {15, 12}, {4, 4}, {0, 2}, {{15, 51}}, 2 }, + /* Check that a set without a length doesn't change anything */ + { {10}, {0}, {0}, {{0}}, 1 }, +}; + +static void __init test_bitmap_set_value(void) +{ + int i, j, k; + int correct_tests = 0; + + for (i = 0; i < ARRAY_SIZE(test_set); i++) { + const struct test_bitmap_set_value_sample *t = &test_set[i]; + int test_correct = 1; + DECLARE_BITMAP(map, BITS_PER_LONG * 2); + + bitmap_zero(map, BITS_PER_LONG * 2); + for (j = 0; j < t->amount; j++) { + bitmap_set_value(map, t->value[j], t->offset[j], t->length[j]); + for (k = 0; k < 2; k++) { + if (expect_eq_uint(map[k], t->expected[k][j])) + test_correct = 0; + } + } + if (test_correct) + correct_tests += 1; + } + pr_err("set_value: %d/%ld tests correct\n", correct_tests, ARRAY_SIZE(test_set)); +} + static void __init selftest(void) { test_zero_clear(); @@ -884,6 +931,7 @@ static void __init selftest(void) test_for_each_set_clump8(); test_bitmap_cut(); test_bitmap_print_buf(); + test_bitmap_set_value(); } KSTM_MODULE_LOADERS(test_bitmap); From patchwork Wed Jul 13 16:32:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 12916956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C928C433EF for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657729964; bh=CtMDQU5Rl7w4k3vdufuEIThSkeTfJG6tKC5YQsVp1HE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l7X7PfDkc+hZ1f2XHto4cpy0UH89XxDdmLj0Ti7BFrkFWH7znIArv+eo2ik6wBNpW VhhxOdz3d+/YoqzFpVunEMwhiJ4O/3cYJWLKc+Z3sBGYa72C/rc6W1kRetOAPWUL8L u0JOjtV/5s2GSGuiAJR20gCc4l2KmLxeOxfqPsmeW30U2XElck3j5VtOMV3urbPUwJ hDf0Uz6VUKIXMezm5vuFfkKPBgEsHJPLKyvuK1jSwwu8PV+WRlomO0bKXUCfNVTsSK n8YgUnRFPACdDgCJun8CLB26pYKIWDWoK1ovC9eqBU0cj45A5rLOcDB68+m9t+pFxA /sfdRBCY8Y15g== From: Sebastian Fricke To: linux-media@vger.kernel.org Cc: jernej.skrabec@gmail.com, knaerzche@gmail.com, kernel@collabora.com, bob.beckett@collabora.com, ezequiel@vanguardiasur.com.ar, mchehab@kernel.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, nicolas.dufresne@collabora.com, Sebastian Fricke , Jonas Karlman , Yury Norov , Andy Shevchenko , Rasmus Villemoes Subject: [PATCH 4/6] staging: media: rkvdec: Add valid pixel format check Date: Wed, 13 Jul 2022 18:32:01 +0200 Message-Id: <20220713163201.136202-2-sebastian.fricke@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713163201.136202-1-sebastian.fricke@collabora.com> References: <20220713163201.136202-1-sebastian.fricke@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Provide a callback for codec variant drivers to indicate the correct output pixel-format after receiving the SPS of the byte-stream, on the initial s_ctrl ioctl call from user-space. Signed-off-by: Jonas Karlman Signed-off-by: Sebastian Fricke --- drivers/staging/media/rkvdec/TODO | 2 ++ drivers/staging/media/rkvdec/rkvdec.c | 45 +++++++++++++++++++++++---- drivers/staging/media/rkvdec/rkvdec.h | 2 ++ 3 files changed, 43 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO index 2c0779383276..44e1e06ee6e4 100644 --- a/drivers/staging/media/rkvdec/TODO +++ b/drivers/staging/media/rkvdec/TODO @@ -9,3 +9,5 @@ code in rkvdec_request_validate and cedrus_request_validate. The helper needs to the driver private data associated with the videobuf2 queue, from a media request. + +* Implement the valid_fmt callback for H264 and VP9 diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index 7bab7586918c..2625e0a736f4 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -27,6 +27,23 @@ #include "rkvdec.h" #include "rkvdec-regs.h" +/* + * Fetch the optimal pixel-format directly from the codec variation. If the + * valid_fmt callback is not implemented, then the context variable valid_fmt + * will be unset. + * When the `valid_fmt` variable is not set, the default pixel_format (the first + * entry of the decoded_fmts) is used and `enum_capture_fmt` will return all + * available formats for the current coded format. + */ +static int rkvdec_get_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) +{ + const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc; + + if (coded_desc->ops->valid_fmt) + return coded_desc->ops->valid_fmt(ctx, ctrl); + return 0; +} + static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); @@ -35,6 +52,9 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) if (desc->ops->try_ctrl) return desc->ops->try_ctrl(ctx, ctrl); + if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_get_valid_fmt(ctx, ctrl)) + /* Only allow the current valid format */ + return -EINVAL; return 0; } @@ -190,6 +210,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) { struct v4l2_format *f = &ctx->decoded_fmt; + ctx->valid_fmt = 0; rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, @@ -249,14 +270,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, if (WARN_ON(!coded_desc)) return -EINVAL; - for (i = 0; i < coded_desc->num_decoded_fmts; i++) { - if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) - break; + if (ctx->valid_fmt) { + pix_mp->pixelformat = ctx->valid_fmt; + } else { + for (i = 0; i < coded_desc->num_decoded_fmts; i++) { + if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) + break; + } + if (i == coded_desc->num_decoded_fmts) + pix_mp->pixelformat = coded_desc->decoded_fmts[0]; } - if (i == coded_desc->num_decoded_fmts) - pix_mp->pixelformat = coded_desc->decoded_fmts[0]; - /* Always apply the frmsize constraint of the coded end. */ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); pix_mp->height = max(pix_mp->height, ctx->coded_fmt.fmt.pix_mp.height); @@ -325,6 +349,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, return ret; ctx->decoded_fmt = *f; + ctx->valid_fmt = f->fmt.pix_mp.pixelformat; return 0; } @@ -428,6 +453,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, if (WARN_ON(!ctx->coded_fmt_desc)) return -EINVAL; + if (ctx->valid_fmt) { + if (f->index) + return -EINVAL; + + f->pixelformat = ctx->valid_fmt; + return 0; + } + if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) return -EINVAL; diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h index 633335ebb9c4..b9e219438bc9 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) struct rkvdec_coded_fmt_ops { int (*adjust_fmt)(struct rkvdec_ctx *ctx, struct v4l2_format *f); + u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); int (*start)(struct rkvdec_ctx *ctx); void (*stop)(struct rkvdec_ctx *ctx); int (*run)(struct rkvdec_ctx *ctx); @@ -101,6 +102,7 @@ struct rkvdec_ctx { struct v4l2_fh fh; struct v4l2_format coded_fmt; struct v4l2_format decoded_fmt; + u32 valid_fmt; const struct rkvdec_coded_fmt_desc *coded_fmt_desc; struct v4l2_ctrl_handler ctrl_hdl; struct rkvdec_dev *dev; From patchwork Wed Jul 13 16:32:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 12916957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EBC8C433EF for ; Wed, 13 Jul 2022 16:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237252AbiGMQdQ (ORCPT ); Wed, 13 Jul 2022 12:33:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237238AbiGMQdP (ORCPT ); Wed, 13 Jul 2022 12:33:15 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C63A2CE3D; Wed, 13 Jul 2022 09:33:13 -0700 (PDT) Received: from localhost (dynamic-002-247-252-243.2.247.pool.telefonica.de [2.247.252.243]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2C3D46601926; Wed, 13 Jul 2022 17:33:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657729992; bh=H45vKIVxYSOqYRL43Uz5XTwJe8yBD2CscZqG1frIUiY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DVP/8OabOAVdwWtbUamryVmHMiU9imIDdQD/mdYFbP8mAUCazpTc1qPjmeSrtqx8n jvq9kx5xIFzHL0H/6OXZYYq/GRnrRpR+JTL6f3ZKEoEiV4JjwFmlV1P3NpHfTP8iR4 5k4qcpDN4g4Xp5sTt4ajt8Z6i4t4ex7Iq2RqgD7wpBf5wY9Y0SzpqGDSSMuu28shk6 QgdZop99S4uetfY/+iAuSL/kt5tUpgR8Ndzfn0F/hMr5bTyz/qSRBzdk/X9cv7kkPd 54G4ehGJLgUHFJx/pNLCXkdzEBdlgWTqNUpswi11hLSwTz5kSS1XuG1OIarDAE5iAi qi1IxfylXDNcw== From: Sebastian Fricke To: linux-media@vger.kernel.org Cc: jernej.skrabec@gmail.com, knaerzche@gmail.com, kernel@collabora.com, bob.beckett@collabora.com, ezequiel@vanguardiasur.com.ar, mchehab@kernel.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, nicolas.dufresne@collabora.com, Sebastian Fricke , Jonas Karlman , Yury Norov , Andy Shevchenko , Rasmus Villemoes Subject: [PATCH 5/6] staging: media: rkvdec: Enable S_CTRL IOCTL Date: Wed, 13 Jul 2022 18:32:03 +0200 Message-Id: <20220713163201.136202-3-sebastian.fricke@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713163201.136202-1-sebastian.fricke@collabora.com> References: <20220713163201.136202-1-sebastian.fricke@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Enable user-space to set the SPS of the current byte-stream on the decoder. This action will trigger the decoder to pick the optimal pixel-format for the capture queue. Signed-off-by: Sebastian Fricke Signed-off-by: Jonas Karlman --- drivers/staging/media/rkvdec/rkvdec.c | 60 ++++++++++++++++++++------- 1 file changed, 46 insertions(+), 14 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index 2625e0a736f4..f84579f764ab 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -27,6 +27,17 @@ #include "rkvdec.h" #include "rkvdec-regs.h" +static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, + struct v4l2_pix_format_mplane *pix_mp) +{ + v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, + pix_mp->width, pix_mp->height); + pix_mp->plane_fmt[0].sizeimage += 128 * + DIV_ROUND_UP(pix_mp->width, 16) * + DIV_ROUND_UP(pix_mp->height, 16); + pix_mp->field = V4L2_FIELD_NONE; +} + /* * Fetch the optimal pixel-format directly from the codec variation. If the * valid_fmt callback is not implemented, then the context variable valid_fmt @@ -44,6 +55,27 @@ static int rkvdec_get_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) return 0; } +static int rkvdec_set_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) +{ + struct v4l2_pix_format_mplane *pix_mp; + + switch (ctrl->id) { + case V4L2_CID_STATELESS_H264_SPS: + case V4L2_CID_STATELESS_VP9_FRAME: + case V4L2_CID_STATELESS_HEVC_SPS: + ctx->valid_fmt = rkvdec_get_valid_fmt(ctx, ctrl); + + pix_mp = &ctx->decoded_fmt.fmt.pix_mp; + pix_mp->pixelformat = ctx->valid_fmt; + rkvdec_fill_decoded_pixfmt(ctx, pix_mp); + break; + default: + dev_err(ctx->dev->dev, "Unsupported stateless control ID: %x\n", ctrl->id); + return -EINVAL; + }; + return 0; +} + static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); @@ -58,8 +90,18 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) return 0; } +static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); + + if (!ctx->valid_fmt) + return rkvdec_set_valid_fmt(ctx, ctrl); + return 0; +} + static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { .try_ctrl = rkvdec_try_ctrl, + .s_ctrl = rkvdec_s_ctrl, }; static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { @@ -213,13 +255,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) ctx->valid_fmt = 0; rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; - v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, - ctx->coded_fmt_desc->decoded_fmts[0], - ctx->coded_fmt.fmt.pix_mp.width, - ctx->coded_fmt.fmt.pix_mp.height); - f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 * - DIV_ROUND_UP(f->fmt.pix_mp.width, 16) * - DIV_ROUND_UP(f->fmt.pix_mp.height, 16); + f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; + f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; + rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp); } static int rkvdec_enum_framesizes(struct file *file, void *priv, @@ -288,13 +326,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, &pix_mp->height, &coded_desc->frmsize); - v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, - pix_mp->width, pix_mp->height); - pix_mp->plane_fmt[0].sizeimage += - 128 * - DIV_ROUND_UP(pix_mp->width, 16) * - DIV_ROUND_UP(pix_mp->height, 16); - pix_mp->field = V4L2_FIELD_NONE; + rkvdec_fill_decoded_pixfmt(ctx, pix_mp); return 0; } From patchwork Wed Jul 13 16:32:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Fricke X-Patchwork-Id: 12916964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 125D3C433EF for ; Wed, 13 Jul 2022 16:33:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237238AbiGMQdx (ORCPT ); Wed, 13 Jul 2022 12:33:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236409AbiGMQdw (ORCPT ); Wed, 13 Jul 2022 12:33:52 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AB767656; Wed, 13 Jul 2022 09:33:48 -0700 (PDT) Received: from localhost (dynamic-002-247-252-243.2.247.pool.telefonica.de [2.247.252.243]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6F35B660191C; Wed, 13 Jul 2022 17:33:46 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1657730027; bh=YyECtHryURpSmgAO9YwS5r2n/7kfV/9ID8/glQwIOYU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WLNmSfDKdyEz8XdAkpEirxaGF55ptQDiSxUO2ql44ube4NWSdfhLt8iTWcUzZm9zj b4Pu4m8nFTj/05dGeeyWtHoLb2FobV0CMNeRKCXv2rgI9Z3toyBdeKaEqU5QYJEAFh +ftJiR3azfB6LvNaAikYHVDm+o+u1FpF46xKw+BWmXywGZKnS37WTQdWDrLg7KeP/Q EC/iT62k2sfEa9CZsYICW2ROxNbaso00JOv9gk7dTM3SS8LxSFir8JIGcoynt3JW5M Q/MmnkdAFlgBqYicA5NZezo9K20Ha/2B80GTzGgdmy/dJT12b+bl1kTTQM4tP3LYOK gjAFi47xkwbzg== From: Sebastian Fricke To: linux-media@vger.kernel.org Cc: jernej.skrabec@gmail.com, knaerzche@gmail.com, kernel@collabora.com, bob.beckett@collabora.com, ezequiel@vanguardiasur.com.ar, mchehab@kernel.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, nicolas.dufresne@collabora.com, Sebastian Fricke , Jonas Karlman , Yury Norov , Andy Shevchenko , Rasmus Villemoes Subject: [PATCH 6/6] staging: media: rkvdec: Add HEVC backend Date: Wed, 13 Jul 2022 18:32:05 +0200 Message-Id: <20220713163201.136202-4-sebastian.fricke@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220713163201.136202-1-sebastian.fricke@collabora.com> References: <20220713163201.136202-1-sebastian.fricke@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The Rockchip VDEC supports the HEVC codec with the Main and Main10 Profile up to Level 5.1 High Tier: 4096x2304@60 fps. Add the backend for that format to the decoder. Signed-off-by: Jonas Karlman Signed-off-by: Alex Bee Signed-off-by: Sebastian Fricke Signed-off-by: Nicolas Dufresne --- drivers/staging/media/rkvdec/Makefile | 2 +- drivers/staging/media/rkvdec/TODO | 20 +- .../staging/media/rkvdec/rkvdec-hevc-data.c | 1844 +++++++++++++++++ drivers/staging/media/rkvdec/rkvdec-hevc.c | 859 ++++++++ drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + drivers/staging/media/rkvdec/rkvdec.c | 77 + drivers/staging/media/rkvdec/rkvdec.h | 1 + 7 files changed, 2796 insertions(+), 8 deletions(-) create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile index cb86b429cfaa..a77122641d14 100644 --- a/drivers/staging/media/rkvdec/Makefile +++ b/drivers/staging/media/rkvdec/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o -rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o +rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO index 44e1e06ee6e4..39cee359f9b3 100644 --- a/drivers/staging/media/rkvdec/TODO +++ b/drivers/staging/media/rkvdec/TODO @@ -1,13 +1,19 @@ -* Support for HEVC is planned for this driver. - - Given the V4L controls for that CODEC will be part of - the uABI, it will be required to have the driver in staging. - - For this reason, we are keeping this driver in staging for now. - * Evaluate introducing a helper to consolidate duplicated code in rkvdec_request_validate and cedrus_request_validate. The helper needs to the driver private data associated with the videobuf2 queue, from a media request. * Implement the valid_fmt callback for H264 and VP9 + +* Currently the driver can only reset the valid_fmt (for example 8 || 10 bit + pixel format for HEVC) when user-space calls the S_FMT ioctl on the output + queue or when the device is opened. + The driver should be able to reset the valid_fmt on the capture queue at a + later point of the process by calling S_CTRL with a new SPS, while making + sure that the size of the buffers is sufficient for the new format. + There is currently no use-case for this feature as all the user-space tools + currently call S_FMT explicitly. But this might be relevant in the future. + +* Add support for other hardware revisions (like RK3288 etc.) + +* Fix concurrent decoding for the HEVC codec diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc-data.c b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c new file mode 100644 index 000000000000..2c093ea7d761 --- /dev/null +++ b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c @@ -0,0 +1,1844 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Video Decoder driver + * + * Copyright (C) 2022 Collabora, Ltd. + * Sebastian Fricke + */ +#include + +#define RKV_CABAC_TABLE_SIZE 27456 + +static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { + 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, + 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, + 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, + 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x27, 0x07, 0x40, + 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, 0x07, 0x27, 0x40, 0x17, + 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, 0x07, 0x27, 0x2f, + 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x17, 0x1f, + 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, 0x0f, + 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, + 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, + 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, + 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, + 0x40, 0x40, 0x40, 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, + 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, + 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c new file mode 100644 index 000000000000..68f88bfe54e1 --- /dev/null +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -0,0 +1,859 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Video Decoder HEVC backend + * + * Copyright (C) 2022 Collabora, Ltd. + * Sebastian Fricke + * + * Copyright (C) 2019 Collabora, Ltd. + * Boris Brezillon + * + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. + * Jeffy Chen + */ + +#include +#include + +#include "rkvdec.h" +#include "rkvdec-regs.h" +#include "rkvdec-hevc-data.c" + +/* Size in u8/u32 units. */ +#define RKV_SCALING_LIST_SIZE 1360 +#define SCALING_LIST_SIZE_NUM 4 +#define RKV_PPS_SIZE (80 / 4) +#define RKV_PPS_LEN 64 +#define RKV_RPS_SIZE (32 / 4) +#define RKV_RPS_LEN 600 +#define RKV_PPS_MAX_COLUMNS 20 +#define RKV_PPS_MAX_ROWS 22 +#define RKV_RPS_MAX_REFERENCES 15 +#define RKV_RPS_BITMAP_SIZE RKV_RPS_SIZE * 32 +#define RKV_MAX_DEPTH_IN_BYTES 2 + +/* + * Description of the PPS memory blob, as expected by the hardware, as a bitfield. + * mbz = must be zero, mbo = must be one, these are paddings that were copied from + * the MPP implementation. + */ +struct rkvdec_sps_pps_bit_field { + /* SPS */ + u8 video_parameter_set_id: 4; + u8 seq_parameter_set_id: 4; + u8 chroma_format_idc: 2; + u16 pic_width_in_luma_samples: 13; + u16 pic_height_in_luma_samples: 13; + /* 36 bits above - index 0 */ + u8 bit_depth_luma: 4; + u8 bit_depth_chroma: 4; + /* GCC complains for some values when the unit is u8 even though the bit + * size is smaller than 8 + */ + u16 log2_max_pic_order_cnt_lsb: 5; + u8 log2_diff_max_min_luma_coding_block_size: 2; + u8 log2_min_luma_coding_block_size: 3; + u16 log2_min_transform_block_size: 3; + u8 log2_diff_max_min_luma_transform_block_size: 2; + u8 max_transform_hierarchy_depth_inter: 3; + u16 max_transform_hierarchy_depth_intra: 3; + /* 65 bits above - index 1 */ + u8 scaling_list_enabled_flag: 1; + u8 amp_enabled_flag: 1; + u8 sample_adaptive_offset_enabled_flag: 1; + u8 pcm_enabled_flag: 1; + u16 pcm_sample_bit_depth_luma: 4; + u8 pcm_sample_bit_depth_chroma: 4; + u8 pcm_loop_filter_disabled_flag: 1; + u16 log2_diff_max_min_pcm_luma_coding_block_size: 3; + u8 log2_min_pcm_luma_coding_block_size: 3; + u16 num_short_term_ref_pic_sets: 7; + u8 long_term_ref_pics_present_flag: 1; + u16 num_long_term_ref_pics_sps: 6; + /* 100 bits above - index 2 */ + u8 sps_temporal_mvp_enabled_flag: 1; + u8 strong_intra_smoothing_enabled_flag: 1; + u16 _mbz_1: 7; + u32 _mbo_1: 21; + /* 130 bits above - index 3 */ + /* PPS */ + u8 pic_parameter_set_id: 6; + u16 pps_seq_parameter_set_id: 4; + u8 dependent_slice_segments_enabled_flag: 1; + u8 output_flag_present_flag: 1; + u16 num_extra_slice_header_bits: 13; + u8 sign_data_hiding_enabled_flag: 1; + u8 cabac_init_present_flag: 1; + u8 num_ref_idx_l0_default_active: 4; + /* 161 bits above - index 4 */ + u16 num_ref_idx_l1_default_active: 4; + u16 init_qp_minus26: 7; + u8 constrained_intra_pred_flag: 1; + u8 transform_skip_enabled_flag: 1; + u8 cu_qp_delta_enabled_flag: 1; + u8 log2_min_cu_qp_delta_size: 3; + u8 pps_cb_qp_offset: 5; + u16 pps_cr_qp_offset: 5; + u8 pps_slice_chroma_qp_offsets_present_flag: 1; + u8 weighted_pred_flag: 1; + u8 weighted_bipred_flag: 1; + u8 transquant_bypass_enabled_flag: 1; + /* 192 bits above - index 5 */ + u8 tiles_enabled_flag: 1; + u8 entropy_coding_sync_enabled_flag: 1; + u8 loop_filter_across_slices_enabled_flag: 1; + u8 loop_filter_across_tiles_enabled_flag: 1; + u8 deblocking_filter_override_enabled_flag: 1; + u8 deblocking_filter_disabled_flag: 1; + u8 pps_beta_offset_div2: 4; + u8 pps_tc_offset_div2: 4; + u8 lists_modification_present_flag: 1; + u8 log2_parallel_merge_level: 3; + u8 slice_segment_header_extension_present_flag: 1; + u8 _mbz_2: 3; + u16 num_tile_columns: 5; + u8 num_tile_rows: 5; + /* 224 bits above - index 6 */ + u8 pps_m_mode: 2; + u64 _mbo_2: 30; + /* 256 bits above - index 7 */ + u8 column_width[20]; + /* 416 bits above - indeces 9, 10, 11, 12, 13 */ + u8 row_height[22]; + /* 592 bits above - indeces 14, 15, 16, 17, 18 & first half 19 */ + u32 scaling_list_address: 32; + u16 _mbo_3: 16; + /* 640 bits above - second half of index 19 & index 20 */ +} __packed; + +struct rkvdec_sps_pps_packet { + u32 info[RKV_PPS_SIZE]; +}; + +struct rkvdec_rps_packet { + u32 info[RKV_RPS_SIZE]; +}; + +/* Data structure describing auxiliary buffer format. */ +struct rkvdec_hevc_priv_tbl { + u8 cabac_table[RKV_CABAC_TABLE_SIZE]; + u8 scaling_list[RKV_SCALING_LIST_SIZE]; + struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; + struct rkvdec_rps_packet rps[RKV_RPS_LEN]; +}; + +struct rkvdec_hevc_run { + struct rkvdec_run base; + const struct v4l2_ctrl_hevc_slice_params *slices_params; + const struct v4l2_ctrl_hevc_decode_params *decode_params; + const struct v4l2_ctrl_hevc_sps *sps; + const struct v4l2_ctrl_hevc_pps *pps; + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; + int num_slices; +}; + +struct rkvdec_hevc_ctx { + struct rkvdec_aux_buf priv_tbl; + struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; +}; + +struct scaling_factor { + u8 scalingfactor0[1248]; + u8 scalingfactor1[96]; /* 4X4 TU Rotate, total 16x4 */ + u8 scalingdc[12]; /* N1005 Vienna Meeting */ + u8 reserved[4]; /* 16 bytes padding */ +}; + +struct bit_writer { + DECLARE_BITMAP(map, RKV_RPS_BITMAP_SIZE); + int offset; +}; + +static void bit_writer_put_bits(struct bit_writer *bw, u32 value, u8 length) +{ + if (!length || (length + bw->offset >= RKV_RPS_BITMAP_SIZE)) + return; + bitmap_set_value(bw->map, value, bw->offset, length); + bw->offset += length; +} + +static void translate_pps(struct rkvdec_hevc_run *run, struct rkvdec_sps_pps_bit_field *output, + dma_addr_t dma_base_addr) +{ + const struct v4l2_ctrl_hevc_sps *sps = run->sps; + const struct v4l2_ctrl_hevc_pps *pps = run->pps; + u8 pcm_enabled = 0; + u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y, log2_min_cu_qp_delta_size; + u32 scaling_distance, width, height, max_min_cb_size, x, pic_in_cts_width; + u32 pic_in_cts_height, i; + u32 tmp_w = 0; + u32 prev_w = 0; + u32 tmp_h = 0; + u32 prev_h = 0; + dma_addr_t scaling_list_address; + u16 column_width[20] = {0}; + u16 row_height[22] = {0}; + + min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; + width = sps->pic_width_in_luma_samples; + height = sps->pic_height_in_luma_samples; + max_min_cb_size = sps->log2_diff_max_min_luma_coding_block_size; + + /* SPS data */ + output->video_parameter_set_id = sps->video_parameter_set_id; + output->seq_parameter_set_id = sps->seq_parameter_set_id; + output->chroma_format_idc = 1; + output->pic_width_in_luma_samples = sps->pic_width_in_luma_samples; + output->pic_height_in_luma_samples = sps->pic_height_in_luma_samples; + output->bit_depth_luma = sps->bit_depth_luma_minus8 + 8; + output->bit_depth_chroma = sps->bit_depth_chroma_minus8 + 8; + output->log2_max_pic_order_cnt_lsb = sps->log2_max_pic_order_cnt_lsb_minus4 + 4; + output->log2_diff_max_min_luma_coding_block_size = + sps->log2_diff_max_min_luma_coding_block_size; + output->log2_min_luma_coding_block_size = sps->log2_min_luma_coding_block_size_minus3 + 3; + output->log2_min_transform_block_size = sps->log2_min_luma_transform_block_size_minus2 + 2; + output->log2_diff_max_min_luma_transform_block_size = + sps->log2_diff_max_min_luma_transform_block_size; + output->max_transform_hierarchy_depth_inter = sps->max_transform_hierarchy_depth_inter; + output->max_transform_hierarchy_depth_intra = sps->max_transform_hierarchy_depth_intra; + output->scaling_list_enabled_flag = + !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED); + output->amp_enabled_flag = !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED); + output->sample_adaptive_offset_enabled_flag = + !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET); + pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED); + output->pcm_enabled_flag = pcm_enabled; + output->pcm_sample_bit_depth_luma = + pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0; + output->pcm_sample_bit_depth_chroma = + pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0; + output->pcm_loop_filter_disabled_flag = + !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED); + output->log2_diff_max_min_pcm_luma_coding_block_size = + sps->log2_diff_max_min_pcm_luma_coding_block_size; + output->log2_min_pcm_luma_coding_block_size = + pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0; + output->num_short_term_ref_pic_sets = sps->num_short_term_ref_pic_sets; + output->long_term_ref_pics_present_flag = + !!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT); + output->num_long_term_ref_pics_sps = sps->num_long_term_ref_pics_sps; + output->sps_temporal_mvp_enabled_flag = + !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED); + output->strong_intra_smoothing_enabled_flag = + !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED); + /* Padding */ + output->_mbz_1 = 0; + output->_mbo_1 = 0x1fffff; + + /* PPS data */ + output->pic_parameter_set_id = pps->pic_parameter_set_id; + output->seq_parameter_set_id = sps->seq_parameter_set_id; + output->dependent_slice_segments_enabled_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); + output->output_flag_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); + output->num_extra_slice_header_bits = pps->num_extra_slice_header_bits; + output->sign_data_hiding_enabled_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED); + output->cabac_init_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT); + output->num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1; + output->num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1; + output->init_qp_minus26 = pps->init_qp_minus26; + output->constrained_intra_pred_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED); + output->transform_skip_enabled_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED); + output->cu_qp_delta_enabled_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED); + + ctb_log2_size_y = min_cb_log2_size_y + + sps->log2_diff_max_min_luma_coding_block_size; + ctb_size_y = 1 << ctb_log2_size_y; + log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; + output->log2_min_cu_qp_delta_size = log2_min_cu_qp_delta_size; + output->pps_cb_qp_offset = pps->pps_cb_qp_offset; + output->pps_cr_qp_offset = pps->pps_cr_qp_offset; + output->pps_slice_chroma_qp_offsets_present_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT); + output->weighted_pred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED); + output->weighted_bipred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED); + output->transquant_bypass_enabled_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED); + output->tiles_enabled_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED); + output->entropy_coding_sync_enabled_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED); + output->loop_filter_across_slices_enabled_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED); + output->loop_filter_across_tiles_enabled_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED); + output->deblocking_filter_override_enabled_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED); + output->deblocking_filter_disabled_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER); + output->pps_beta_offset_div2 = pps->pps_beta_offset_div2; + output->pps_tc_offset_div2 = pps->pps_tc_offset_div2; + output->lists_modification_present_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT); + output->log2_parallel_merge_level = pps->log2_parallel_merge_level_minus2 + 2; + /* MPP demands that this should always be 0 ?!? */ + output->slice_segment_header_extension_present_flag = + !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT); + output->_mbz_2 = 0; + output->num_tile_columns = pps->num_tile_columns_minus1 + 1; + output->num_tile_rows = pps->num_tile_rows_minus1 + 1; + /* FIXME: Describe this hard coded value from MPP properly */ + output->pps_m_mode = 3; + output->_mbo_2 = 0x3fffffff; + + if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { + if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) { + x = 1 << (min_cb_log2_size_y + max_min_cb_size); + pic_in_cts_width = (width + x - 1) / (x); + pic_in_cts_height = (height + x - 1) / (x); + for (i = 0; i <= pps->num_tile_columns_minus1; i++) { + tmp_w = ((i + 1) * pic_in_cts_width) / + (pps->num_tile_columns_minus1 + 1); + column_width[i] = tmp_w - prev_w - 1; + prev_w = tmp_w; + } + for (i = 0; i <= pps->num_tile_rows_minus1; i++) { + tmp_h = ((i + 1) * pic_in_cts_height) / + (pps->num_tile_rows_minus1 + 1); + row_height[i] = tmp_h - prev_h - 1; + prev_h = tmp_h; + } + } else { + for (i = 0; i <= pps->num_tile_columns_minus1; i++) + column_width[i] = pps->column_width_minus1[i]; + for (i = 0; i <= pps->num_tile_rows_minus1; i++) + row_height[i] = pps->row_height_minus1[i]; + } + } else { + column_width[0] = + ((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1; + row_height[0] = + ((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1; + } + + for (i = 0; i < RKV_PPS_MAX_COLUMNS; i++) + output->column_width[i] = column_width[i]; + for (i = 0; i < RKV_PPS_MAX_ROWS; i++) + output->row_height[i] = row_height[i]; + + scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); + scaling_list_address = dma_base_addr + scaling_distance; + output->scaling_list_address = scaling_list_address; +} + +static void assemble_hw_pps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + const struct v4l2_ctrl_hevc_pps *pps = run->pps; + struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; + struct rkvdec_sps_pps_packet *hw_ps; + struct rkvdec_sps_pps_bit_field bit_field; + + /* + * The hardware finds the appropriate SPS/PPS information from the PPS packet + * by indexing it with the ID of the PPS. + * The offset from the base is calculated with PPS_id * 80 (which is the size + * per PPS packet unit). + */ + hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; + memset(hw_ps, 0, sizeof(*hw_ps)); + memset(&bit_field, 0, sizeof(struct rkvdec_sps_pps_bit_field)); + translate_pps(run, &bit_field, hevc_ctx->priv_tbl.dma); + memcpy(hw_ps->info, &bit_field, sizeof(struct rkvdec_sps_pps_bit_field)); +} + +/* + * Creation of the Reference Picture Set memory blob for the hardware. + * The layout looks like this: + * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference) + * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references + * + 4 bits of the 13th reference) + * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and + * 21 bits for L1 (4 references + first bit of 5) + * [3] 32 bits of padding with 0s + * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11) + * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references) + * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32) + * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12) + * number of references (bit 13 - 16), remaining 16 bits of padding with 0s + * [7] 32 bits of padding with 0s + * + * Thus we have to set up padding in between reference 5 of the L1 list. + */ +static void assemble_hw_rps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_sps *sps = run->sps; + const struct v4l2_ctrl_hevc_slice_params *sl_params; + const struct v4l2_hevc_dpb_entry *dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; + struct rkvdec_rps_packet *hw_ps; + struct bit_writer bw; + int i, j; + unsigned int lowdelay; + + for (j = 0; j < run->num_slices; j++) { + uint st_bit_offset = 0; + uint num_l0_refs = 0; + uint num_l1_refs = 0; + + sl_params = &run->slices_params[j]; + dpb = decode_params->dpb; + + if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { + num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; + + if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) + num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; + + lowdelay = 1; + } else { + lowdelay = 0; + } + + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); + bitmap_zero(bw.map, RKV_RPS_BITMAP_SIZE); + bw.offset = 0; + + for (i = 0; i < RKV_RPS_MAX_REFERENCES; i++) { + if (i < num_l0_refs) { + const struct v4l2_hevc_dpb_entry dpb_l0 = + dpb[sl_params->ref_idx_l0[i]]; + int is_long_term = + !!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE); + + bit_writer_put_bits(&bw, is_long_term, 1); + bit_writer_put_bits(&bw, sl_params->ref_idx_l0[i], 4); + + if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt) + lowdelay = 0; + } else { + bit_writer_put_bits(&bw, 0, 5); + } + } + + for (i = 0; i < RKV_RPS_MAX_REFERENCES; i++) { + if (i < num_l1_refs) { + const struct v4l2_hevc_dpb_entry dpb_l1 = + dpb[sl_params->ref_idx_l1[i]]; + int is_long_term = + !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE); + + bit_writer_put_bits(&bw, is_long_term, 1); + if (i == 4) + bit_writer_put_bits(&bw, 0, 32); + bit_writer_put_bits(&bw, sl_params->ref_idx_l1[i], 4); + + if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt) + lowdelay = 0; + } else { + if (i == 4) { + /* long term bit + 32 bits padding + 4 bits for the + * DPB index + */ + bit_writer_put_bits(&bw, 0, 37); + } else { + bit_writer_put_bits(&bw, 0, 5); + } + } + } + bit_writer_put_bits(&bw, lowdelay, 1); + + if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { + if (sl_params->short_term_ref_pic_set_size) + st_bit_offset = sl_params->short_term_ref_pic_set_size; + else if (sps->num_short_term_ref_pic_sets > 1) + st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); + } + + bit_writer_put_bits(&bw, st_bit_offset + sl_params->long_term_ref_pic_set_size, 10); + bit_writer_put_bits(&bw, st_bit_offset, 9); + + bit_writer_put_bits(&bw, decode_params->num_poc_st_curr_before + + decode_params->num_poc_st_curr_after + + decode_params->num_poc_lt_curr, 4); + + bitmap_to_arr32(hw_ps->info, bw.map, RKV_RPS_BITMAP_SIZE); + } +} + +/* + * Flip one or more matrices along their main diagonal and flatten them + * before writing it to the memory. + * Convert: + * ABCD AEIM + * EFGH => BFJN => AEIMBFJNCGKODHLP + * IJKL CGKO + * MNOP DHLP + */ +static void rotate_and_flatten_matrices(u8 *output, const u8 *input, int matrices, int row_length) +{ + int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; + + matrix_size = row_length * row_length; + for (i = 0; i < matrices; i++) { + row = 0; + x_offset = 0; + matrix_offset = i * matrix_size; + for (j = 0; j < matrix_size; j++) { + y_offset = j - (row * row_length); + rot_index = y_offset * row_length + x_offset; + new_value = *(input + i * matrix_size + j); + output[matrix_offset + rot_index] = *(input + i * matrix_size + j); + if ((j + 1) % row_length == 0) { + row += 1; + x_offset += 1; + } + } + } +} + +static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) +{ + int offset = 0; + + rotate_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); + offset = 6 * 16 * sizeof(u8); + rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); + offset += 6 * 64 * sizeof(u8); + rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_16x16, 6, 8); + offset += 6 * 64 * sizeof(u8); + /* Add a 128 byte padding with 0s between the two 32x32 matrices */ + rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_32x32, 1, 8); + offset += 64 * sizeof(u8); + memset(output + offset, 0, 128); + offset += 128 * sizeof(u8); + rotate_and_flatten_matrices(output + offset, + (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), + 1, 8); + offset += 64 * sizeof(u8); + memset(output + offset, 0, 128); +} + +/* + * Required layout: + * A = scaling_list_dc_coef_16x16 + * B = scaling_list_dc_coef_32x32 + * 0 = Padding + * + * A, A, A, A, A, A, B, 0, 0, B, 0, 0 + */ +static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) +{ + u8 list_32x32[6] = {0}; + + memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8)); + list_32x32[0] = input->scaling_list_dc_coef_32x32[0]; + list_32x32[3] = input->scaling_list_dc_coef_32x32[1]; + memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); +} + +static void translate_scaling_list(struct scaling_factor *output, + const struct v4l2_ctrl_hevc_scaling_matrix *input) +{ + assemble_scalingfactor0(output->scalingfactor0, input); + memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); + assemble_scalingdc(output->scalingdc, input); + memset(output->reserved, 0, 4 * sizeof(u8)); +} + +static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; + u8 *dst; + + if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling, + sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) + return; + + dst = tbl->scaling_list; + translate_scaling_list((struct scaling_factor *)dst, scaling); + + memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling, + sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); +} + +static struct vb2_buffer * +get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, unsigned int dpb_idx) +{ + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; + int buf_idx = -1; + + if (dpb_idx < decode_params->num_active_dpb_entries) + buf_idx = vb2_find_timestamp(cap_q, dpb[dpb_idx].timestamp, 0); + + /* + * If a DPB entry is unused or invalid, the address of the current destination + * buffer is returned. + */ + if (buf_idx < 0) + return &run->base.bufs.dst->vb2_buf; + + return vb2_get_buffer(cap_q, buf_idx); +} + +static void config_registers(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + struct rkvdec_dev *rkvdec = ctx->dev; + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; + const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; + const struct v4l2_pix_format_mplane *dst_fmt; + struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; + struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; + const struct v4l2_format *f; + dma_addr_t rlc_addr; + dma_addr_t refer_addr; + u32 rlc_len; + u32 hor_virstride; + u32 ver_virstride; + u32 y_virstride; + u32 uv_virstride; + u32 yuv_virstride; + u32 offset; + dma_addr_t dst_addr; + u32 reg, i; + + reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); + + f = &ctx->decoded_fmt; + dst_fmt = &f->fmt.pix_mp; + hor_virstride = dst_fmt->plane_fmt[0].bytesperline; + ver_virstride = dst_fmt->height; + y_virstride = hor_virstride * ver_virstride; + uv_virstride = y_virstride / 2; + yuv_virstride = y_virstride + uv_virstride; + + reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | + RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | + RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); + + /* config rlc base address */ + rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); + + rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); + reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); + + /* config cabac table */ + offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); + writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); + + /* config output base address */ + dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); + + reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); + + reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); + + /* config ref pic address */ + for (i = 0; i < 15; i++) { + struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); + + if (i < 4 && decode_params->num_active_dpb_entries) { + reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); + reg = (reg >> (i * 4)) & 0xf; + } else { + reg = 0; + } + + refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); + writel_relaxed(refer_addr | reg, rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); + + reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? + dpb[i].pic_order_cnt_val : 0); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); + } + + reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); + + /* config hw pps address */ + offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); + writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_PPS_BASE); + + /* config hw rps address */ + offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); + writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_RPS_BASE); + + reg = RKVDEC_AXI_DDR_RDATA(0); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); + + reg = RKVDEC_AXI_DDR_WDATA(0); + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); +} + +static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; + + fmt->num_planes = 1; + if (!fmt->plane_fmt[0].sizeimage) + fmt->plane_fmt[0].sizeimage = + fmt->width * fmt->height * RKV_MAX_DEPTH_IN_BYTES; + return 0; +} + +static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) +{ + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; + + if (sps->bit_depth_luma_minus8 == 2) + return V4L2_PIX_FMT_NV15; + else + return V4L2_PIX_FMT_NV12; +} + +static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) +{ + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; + + if (sps->chroma_format_idc > 1) + /* Only 4:0:0 and 4:2:0 are supported */ + return -EINVAL; + if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) + /* Only 8-bit and 10-bit is supported */ + return -EINVAL; + return 0; +} + +static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) +{ + struct rkvdec_dev *rkvdec = ctx->dev; + struct rkvdec_hevc_priv_tbl *priv_tbl; + struct rkvdec_hevc_ctx *hevc_ctx; + int ret; + + hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); + if (!hevc_ctx) + return -ENOMEM; + + priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), + &hevc_ctx->priv_tbl.dma, GFP_KERNEL); + if (!priv_tbl) { + ret = -ENOMEM; + goto err_free_ctx; + } + + hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); + hevc_ctx->priv_tbl.cpu = priv_tbl; + memset(priv_tbl, 0, sizeof(*priv_tbl)); + memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, sizeof(rkvdec_hevc_cabac_table)); + + ctx->priv = hevc_ctx; + return 0; + +err_free_ctx: + kfree(hevc_ctx); + return ret; +} + +static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) +{ + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + struct rkvdec_dev *rkvdec = ctx->dev; + + dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, + hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); + kfree(hevc_ctx); +} + +static int rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) +{ + struct v4l2_ctrl *ctrl; + + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); + run->decode_params = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->decode_params)) + return -EINVAL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); + run->slices_params = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->slices_params)) + return -EINVAL; + run->num_slices = ctrl->new_elems; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SPS); + run->sps = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->sps)) + return -EINVAL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_PPS); + run->pps = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->pps)) + return -EINVAL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); + run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; + if (WARN_ON(!run->scaling_matrix)) + return -EINVAL; + + rkvdec_run_preamble(ctx, &run->base); + return 0; +} + +static void start_hardware(struct rkvdec_dev *rkvdec) +{ + void __iomem *register_base_addr = rkvdec->regs; + struct delayed_work *watchdog_worker = &rkvdec->watchdog_work; + /* + * RkVDEC error detection doesn't work really well and seems racy + * and unstable. Disable it. + */ + writel_relaxed(0, register_base_addr + RKVDEC_REG_STRMD_ERR_EN); + writel_relaxed(0, register_base_addr + RKVDEC_REG_H264_ERR_E); + + schedule_delayed_work(watchdog_worker, msecs_to_jiffies(2000)); + + writel(1, register_base_addr + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); + writel(1, register_base_addr + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); + + /* Start decoding! */ + writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | + RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, + register_base_addr + RKVDEC_REG_INTERRUPT); +} + +static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) +{ + struct rkvdec_dev *rkvdec = ctx->dev; + struct rkvdec_hevc_run run; + int ret; + + ret = rkvdec_hevc_run_preamble(ctx, &run); + if (ret) { + dev_err(ctx->dev->dev, "Missing required controls for the RkVDEC HEVC decoder."); + return ret; + } + + assemble_hw_scaling_list(ctx, &run); + assemble_hw_pps(ctx, &run); + assemble_hw_rps(ctx, &run); + config_registers(ctx, &run); + rkvdec_run_postamble(ctx, &run.base); + start_hardware(rkvdec); + + return 0; +} + +const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { + .adjust_fmt = rkvdec_hevc_adjust_fmt, + .start = rkvdec_hevc_start, + .stop = rkvdec_hevc_stop, + .run = rkvdec_hevc_run, + .try_ctrl = rkvdec_hevc_try_ctrl, + .valid_fmt = rkvdec_hevc_valid_fmt, +}; diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h index 15b9bee92016..83bf790ed9b7 100644 --- a/drivers/staging/media/rkvdec/rkvdec-regs.h +++ b/drivers/staging/media/rkvdec/rkvdec-regs.h @@ -43,6 +43,7 @@ #define RKVDEC_RLC_MODE BIT(11) #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) #define RKVDEC_MODE(x) (((x) & 0x03) << 20) +#define RKVDEC_MODE_HEVC 0 #define RKVDEC_MODE_H264 1 #define RKVDEC_MODE_VP9 2 #define RKVDEC_RPS_MODE BIT(24) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index f84579f764ab..248e87241d90 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -80,10 +81,15 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; if (desc->ops->try_ctrl) return desc->ops->try_ctrl(ctx, ctrl); + if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || + sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) + return -EINVAL; + if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_get_valid_fmt(ctx, ctrl)) /* Only allow the current valid format */ return -EINVAL; @@ -145,6 +151,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { }, }; +static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + { + .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, + .cfg.name = "Slice parameters", + .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, + .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, + .cfg.dims = { 600 }, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, + .cfg.ops = &rkvdec_ctrl_ops, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, + .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, + .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + }, + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, + .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + }, + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, + }, +}; + +static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { + .ctrls = rkvdec_hevc_ctrl_descs, + .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), +}; + +static const u32 rkvdec_hevc_decoded_fmts[] = { + V4L2_PIX_FMT_NV12, + V4L2_PIX_FMT_NV15, +}; + static const struct rkvdec_ctrls rkvdec_h264_ctrls = { .ctrls = rkvdec_h264_ctrl_descs, .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), @@ -175,6 +237,21 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { }; static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_HEVC_SLICE, + .frmsize = { + .min_width = 64, + .max_width = 4096, + .step_width = 64, + .min_height = 64, + .max_height = 2304, + .step_height = 16, + }, + .ctrls = &rkvdec_hevc_ctrls, + .ops = &rkvdec_hevc_fmt_ops, + .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), + .decoded_fmts = rkvdec_hevc_decoded_fmts, + }, { .fourcc = V4L2_PIX_FMT_H264_SLICE, .frmsize = { diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h index b9e219438bc9..11bb6293315d 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -124,6 +124,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; +extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; #endif /* RKVDEC_H_ */