From patchwork Fri Jul 15 12:00:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12919143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C27D6C433EF for ; Fri, 15 Jul 2022 12:25:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233433AbiGOMZE (ORCPT ); Fri, 15 Jul 2022 08:25:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234091AbiGOMZC (ORCPT ); Fri, 15 Jul 2022 08:25:02 -0400 X-Greylist: delayed 1497 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 15 Jul 2022 05:25:01 PDT Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91C14820E6; Fri, 15 Jul 2022 05:25:01 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26FBApQx010543; Fri, 15 Jul 2022 12:00:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id; s=qcppdkim1; bh=iOyl1ZRSLD3l7RdXgKTCXz7qYTdfN8+bAFd8DLwJ2ws=; b=XL9g06Nl7BrhVvo86cin/AjhZvKCye/45JSdhr3AYJYnh+VN8FZuI9DBi10q/WNAB/Qh aVe6QZZeLqUXjtale2W7CDpOra1QoySk49QXAllNVja4R71FOLy/o1FXrOsR/cyUE2B5 FKiXQTkyEDeI+yCOtQuW7ZrI0PsVZKKxcEUS5FSzJ/zHuZtp0FWKh93vHY6JxVH6gv+B cJaoz8gzY3Yn+74XDzrz3JUZ7Tga7KetdzVJPlISZoPJSkHFumkDhBkLR7KbPnU5g8iK 5Xarkbe0noIs0mnhszVamT/vPuwr9AMBwN3qlXECG4yfCJv0M+nvWL/PlqDU+hKYw6MO pg== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3hay68sdux-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Jul 2022 12:00:32 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 26FC0Tiw008598; Fri, 15 Jul 2022 12:00:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3h72rjjfkq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 15 Jul 2022 12:00:29 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 26FC0SCA008593; Fri, 15 Jul 2022 12:00:28 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.37]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 26FC0SoH008592; Fri, 15 Jul 2022 12:00:28 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id D2C8242E3; Fri, 15 Jul 2022 17:30:27 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, Krishna chaitanya chundru , Prasad Malisetty , Bjorn Helgaas , "Saheed O. Bolarinwa" , Manivannan Sadhasivam , =?utf-8?q?Krzysztof_Wilczy=C5=84sk?= =?utf-8?q?i?= , Rajat Jain Subject: [PATCH v6] PCI/ASPM: Update LTR threshold based upon reported max latencies Date: Fri, 15 Jul 2022 17:30:12 +0530 Message-Id: <1657886421-779-1-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hy1lWfwyhxyVMDEEKJJECT3jKQFk5oxn X-Proofpoint-ORIG-GUID: hy1lWfwyhxyVMDEEKJJECT3jKQFk5oxn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-15_04,2022-07-15_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 suspectscore=0 mlxscore=0 adultscore=0 impostorscore=0 priorityscore=1501 clxscore=1011 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2207150053 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In ASPM driver, LTR threshold scale and value are updated based on tcommon_mode and t_poweron values. In kioxia NVMe L1.2 is failing due to LTR threshold scale and value are greater values than max snoop/non-snoop value. Based on PCIe r4.1, sec 5.5.1, L1.2 substate must be entered when reported snoop/no-snoop values is greather than or equal to LTR_L1.2_THRESHOLD value. Signed-off-by: Prasad Malisetty Signed-off-by: Krishna chaitanya chundru Acked-by: Manivannan Sadhasivam --- I am taking this patch forward as prasad is no more working with our org. changes since v5: - no changes, just reposting as standalone patch instead of reply to previous patch. Changes since v4: - Replaced conditional statements with min and max. changes since v3: - Changed the logic to include this condition "snoop/nosnoop latencies are not equal to zero and lower than LTR_L1.2_THRESHOLD" Changes since v2: - Replaced LTRME logic with max snoop/no-snoop latencies check. Changes since v1: - Added missing variable declaration in v1 patch --- drivers/pci/pcie/aspm.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index a96b742..676c03e 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -461,14 +461,36 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, { struct pci_dev *child = link->downstream, *parent = link->pdev; u32 val1, val2, scale1, scale2; + u32 max_val, max_scale, max_snp_scale, max_snp_val, max_nsnp_scale, max_nsnp_val; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; u32 ctl1 = 0, ctl2 = 0; u32 pctl1, pctl2, cctl1, cctl2; u32 pl1_2_enables, cl1_2_enables; + u16 ltr; + u16 max_snoop_lat, max_nosnoop_lat; if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) return; + ltr = pci_find_ext_capability(child, PCI_EXT_CAP_ID_LTR); + if (!ltr) + return; + + pci_read_config_word(child, ltr + PCI_LTR_MAX_SNOOP_LAT, &max_snoop_lat); + pci_read_config_word(child, ltr + PCI_LTR_MAX_NOSNOOP_LAT, &max_nosnoop_lat); + + max_snp_scale = (max_snoop_lat & PCI_LTR_SCALE_MASK) >> PCI_LTR_SCALE_SHIFT; + max_snp_val = max_snoop_lat & PCI_LTR_VALUE_MASK; + + max_nsnp_scale = (max_nosnoop_lat & PCI_LTR_SCALE_MASK) >> PCI_LTR_SCALE_SHIFT; + max_nsnp_val = max_nosnoop_lat & PCI_LTR_VALUE_MASK; + + /* choose the greater max scale value between snoop and no snoop value*/ + max_scale = max(max_snp_scale, max_nsnp_scale); + + /* choose the greater max value between snoop and no snoop scales */ + max_val = max(max_snp_val, max_nsnp_val); + /* Choose the greater of the two Port Common_Mode_Restore_Times */ val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; @@ -501,6 +523,14 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, */ l1_2_threshold = 2 + 4 + t_common_mode + t_power_on; encode_l12_threshold(l1_2_threshold, &scale, &value); + + /* + * Based on PCIe r4.1, sec 5.5.1, L1.2 substate must be entered when reported + * snoop/no-snoop values are greather than or equal to LTR_L1.2_THRESHOLD value. + */ + scale = min(scale, max_scale); + value = min(value, max_val); + ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; /* Some broken devices only support dword access to L1 SS */