From patchwork Fri Jul 15 13:53:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue (OSS)" X-Patchwork-Id: 12919305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89579CCA480 for ; Fri, 15 Jul 2022 13:54:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233497AbiGONx7 (ORCPT ); Fri, 15 Jul 2022 09:53:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233144AbiGONx5 (ORCPT ); Fri, 15 Jul 2022 09:53:57 -0400 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80048.outbound.protection.outlook.com [40.107.8.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23B211AF31; Fri, 15 Jul 2022 06:53:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IAwx7y1dze17iZdppYZvoR/p0b8RM2eGQ+R+/E5pIPSIInI8tUQEunVDpO9Y8Qb/IzvrP6oqeDdxVwFLBBpfpKbdYAFqRYkWNfH5ELHxsBcy7RJgbOpM5oixzn5Nahr7WKFcFvH25FlFs53Aas52N+ydEgAemVXkso5f2vc1DOpyly06Zfkt5nhcsz2qwOm8CEqjPFlnhSzxKsys7U8u5h1Cf8Iwr2XzjLb/J2a6F/5PgFIUG4Uk1kGmrAeq3Jjs30vOvy8uBlWNplEUpiUTmjuqHD0NIxduDRiaW3NmPxYJtlSkIIIGo1PUQQ9UKqRmRrXM71990NFboYsOio3KZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Qo/HmeunH1NHG1XXb0xWwHqLuUBAYsnJzAwWvlhyq0U=; b=jenGvhcnOYi38ig/t6KsfnJg177R2+Hrd3OzULrkRRHkaYJcuL8NKx7YvEuGzOUxfF9UTrqWjev9z3oADXsspBCuKrFHz0t9x6lqzrxlzeFazrA3U/uetWRo4u8oEX0wlRdTzP6SMeHZbMrR9Y1AHXOsAQKoLnF3tEduFdfA3Mb22tmArErgAaBvTZzLmV9sIc8x9H2SQOfwtQzuY2GWb7VwpAIoZGq3K/tvi9sTPaJHL/nBhDMBuyZKnZZzJOrHsHe91NzNz90hX5Dowk7FN7MTcMdnDDoXSQizIYuSvmoc+HZEyimAmStebyKh06TWR6iyf7rLXnqrNPnY3umwcg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Qo/HmeunH1NHG1XXb0xWwHqLuUBAYsnJzAwWvlhyq0U=; b=C2eAXbzTWmTVgPoFFPbuXAD3lrsRv054avv3scFfy+QPp/TPuQHD3F4u1zlQjkA8SoMylBmIuO+h8v6RbN72gLTXUZYb8XV0Mo2Avnn0t7KVnUQ+V8nOztk9NcbtNN1Ch9wOs5D76CJM0rqa3SqfifFVdHiycAGA56BtKcjS0dk= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by VE1PR04MB6640.eurprd04.prod.outlook.com (2603:10a6:803:122::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Fri, 15 Jul 2022 13:53:48 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f%5]) with mapi id 15.20.5438.012; Fri, 15 Jul 2022 13:53:48 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca, alexander.stein@ew.tq-group.com, ezequiel@vanguardiasur.com.ar Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 1/6] media: Documentation: dw100: Add user documentation for the DW100 driver Date: Fri, 15 Jul 2022 15:53:24 +0200 Message-Id: <20220715135329.975400-2-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> References: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR1P264CA0061.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:2ca::15) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5a0bd0cd-f13c-4198-6bc8-08da666970c0 X-MS-TrafficTypeDiagnostic: VE1PR04MB6640:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3F9IgbXWuWEc80QrUAt/UpcFJtIgn0ZWQHXn444tfwoPR2wuob+7FJdA/SV0cJnIWBeMmpNWft32oF18RKTa5oTycG0k7NUCJVNCF4g6HLg9F3FkU+gFwP2gUgDnP1n6QAJiNOmSlKjSofBPk66VbYHt0Wzq8t9dReu3EWySlBFFp+zvfs4OviyDtzTDxfApv9eF0qw1jgp+Xq6lJCBSeGTRHfywBEYPSaq3wojguO0Np+o6+zN0JOmtw+WOnAHyoL5o7emvDowKwnppfwartvkiHdjl6cCNPdghJYNQxv+hSU37BmEiB8p2+J8bq2Cbx1LG+n0OEI6fPaJFCSobGPh0MbzImVl5WQVw7ANiOkjRRn1lG6vp1glJKa4IvjrECmwn90GdOkMdzFaRvCC60R5eq9Mff5M5VAkuXZpGlNS2ux3qMUZmd2lqb6gk1LitMMa3QtiT0uQ6cCVhdLguGTWkyRhqnSmhQcHKsl6s3vyw58n5zOor7z3p5g2Lc3ObmP+bwINUC9dPOKG94C8vGLQP+4wF1G2lwznIS1CpMG/d73RwwkGPMex3iMNzJb/9u6+NyLDC6w3+g5hTQc2KeONX4bpKolZz7JD7BmfjhkDp6VwZrgDbJULA/AOVmbj/2qwnznLGsEOAPCIq6d+nNefpwhkpUclrUoYANQjaOZG8Z+3A2uhdiaP+pOo3wQuEvBhx8HSXdZ7ZYKBeA2jNedI8khoGwXjOJnyQzkRCRgMpu0S4a2slSXqXwBr2rReaJOkpgjb/YsaiTYrgiyGqpMmwZ1HkXHCRcBrDuAS6Pyg= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB8703.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(4636009)(366004)(346002)(376002)(396003)(136003)(39860400002)(6506007)(52116002)(6486002)(86362001)(478600001)(966005)(6512007)(66556008)(66476007)(6666004)(5660300002)(41300700001)(38100700002)(66946007)(316002)(2616005)(1076003)(83380400001)(8676002)(2906002)(8936002)(44832011)(7416002)(4326008)(186003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HBV14PU0G/Rh6PV1MO1yozsZzL6bPdkW4ZDOPyA8mY+Bf9m7ADsPNcaQ/RKbBEU6JY/HdtYLyZLHKUb5lNEzzuQCXB1sS/yAopO4q+As6H3RPK1v4bFFcIACKyXUeAf+tdO/xPBwsotnXDLmcSljcvpYQnOz7rXMsdXvLcGKsGlKVWCJsY116mQD/DjNrI654KfkJEcr6pEo2fRPnoReY/8s+MsrrMLPkCyMzcNAaKCcdaDvirICVtyxUC19wV3fEag4N5O83Puf3iLz2kyMxJbMqAYGkDUkWkJk4QXsMWg8dYgo6W1ScGhU2jP5ovvEycmvYBfQAyU/ae3SnX2x3vo+FzUdubWSPHgVIhtJMHLcB/Xv+a9z3Ilc+KCpbt+6Th4P0JM8hOAKrlX5xhDaW3jgRf8ua+j8ifAj1K3bl/jbJzv/oKuWlrOSTOkTOqFdF4yBbwr8LrUcsD76PqH4XUpFkhpryUjYDhG/j8XGX+FOwxoaDubv+EEHoY5x+HOVQ5mvPX1IQYiZ7ZTO2SqoroXb/xnc3Gp5uVTSC0P+clwWvSx/ef/TC0fslKbGkoarAHKYmUYksze8u2+ueBlLtpAdheVpqlzgIKIxB9x0xAas2BG3ZCLTSyofhTml6/EF5r9L8j0CEViii4tqnn16qRRuP8PxoCe87mFwKpZ0AojicdVqczrvxb/WYnDIBwlHLviwl0OrEw9fUHg9Ky1TVqEJR7+CRzGGFmBZy9DCjAawgigWGREIBBicIM4jOvSvIBTWTNIWlQZiWDDA1IBxDwwBbstv0oN27I3+d95DWP4/h1aOZiCBOFOQLVZc/IlfG59p8uMz4XmbY4brbc/vBPr8vXDbuYJiV8nlP+js12+HwUJq4PBy/YhQDIzQVtC58jP+0qHypI2UaLs0P0OhWKHMAlgsF3xRMpTeJIMmjUoZTVIXG5jx0bo9v/qsrYKc6oWcmGUOk0iUSYYMMe6F0O6yBA6KYiBIvIqqJSWA4GVnoGYczFQBR24G7Ri0mr0UNYmo1z/Vdh2zzQ4HiwSw6JT4ijWT7hoMKi1cdUqn0EFpMz+I3AFSWuW+YfVEMDZEKCDRdLfyapJ41FbqER8nyJuikX9d/2iL6qunUkVgyXxXnyrMJ53MIsR9bOXEbUrLGarhwOaR10rlGdg4LisAYZsKWBm7S/ewV6XN3m+6z6gsFgwiaAAf2hXJ6Yh9gvHZ1g444+jDjpFOPsG5aPxeYboSwp5q3JXpLy6gO9sr0b3Uv1VI0qOfgAxTFjPgo8JZn7BhbBsxSS5wzIZ+IJWomwr+BN8BTEV3/WzXnluif20hvIpgox6aj1sHNSgF6lLe29DPrmf74t9aU3jogi6V7h22gTNHmsezZLkgyR+JM8TqkxQ2x4M2GrtDh6t1+xPQVab19KjXQURGietQrrijBkCT2zSqEBMKQAsjkKVn4RBDeq658xlh9Sr9fVFZVdKffkOgv437DmXUkZ0kRhSLzp3PEbi03VFRPFHrn/AyMea6ykw/n/ldG7QYq/MMuw49YWwbVNtl3Oof2WpTwix1ndRvhb175XE/jsGaVIgPwpUBYUriLz0BM+ySaQTCfW9SJzcVRfsk6nrFPl2SjOcVxqT1wbRwBUZW+m63Ku2gyzhxw2JOmHxIbQAgWsYvW7MB8vMixzXWiWI8xU0tmVbMlQ== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5a0bd0cd-f13c-4198-6bc8-08da666970c0 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 13:53:47.7792 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VwUjMoaKoyiVtLNLKr/J0NHS8QPsSujXFh7+slnW1QlUCDYLO8Dq0TL2+HsXydEpUEJznbfwE+CUZD6Hmvwrrg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6640 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add user documentation for the DW100 driver. while at it, replace spaces with tab on drivers list. Signed-off-by: Xavier Roumegue Reviewed-by: Laurent Pinchart --- .../userspace-api/media/drivers/dw100.rst | 69 +++++++++++++++++++ .../userspace-api/media/drivers/index.rst | 3 +- 2 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 Documentation/userspace-api/media/drivers/dw100.rst diff --git a/Documentation/userspace-api/media/drivers/dw100.rst b/Documentation/userspace-api/media/drivers/dw100.rst new file mode 100644 index 000000000000..1ca6fa55f539 --- /dev/null +++ b/Documentation/userspace-api/media/drivers/dw100.rst @@ -0,0 +1,69 @@ +.. SPDX-License-Identifier: GPL-2.0 + +DW100 dewarp driver +=================== + +The Vivante DW100 Dewarp Processor IP core found on i.MX8MP SoC applies a +programmable geometrical transformation on the input image to correct distortion +introduced by lenses. + +The transformation function is exposed by the hardware as a grid map with 16x16 +pixel macroblocks indexed using X, Y vertex coordinates. +:: + + Image width + <---------------------------------------> + + ^ .-------.-------.-------.-------.-------. + | | 16x16 | | | | | + I | | pixel | | | | | + m | | block | | | | | + a | .-------.-------.-------.-------.-------. + g | | | | | | | + e | | | | | | | + | | | | | | | + h | .-------.-------.-------.-------.-------. + e | | | | | | | + i | | | | | | | + g | | | | | | | + h | .-------.-------.-------.-------.-------. + t | | | | | | | + | | | | | | | + | | | | | | | + v '-------'-------'-------'-------'-------' + + Grid of Image Blocks for Dewarping Map + + +Each x, y coordinate register uses 16 bits to record the coordinate address in +an unsigned 12.4 fixed point format (UQ12.4). +:: + + .----------------------.--------..----------------------.--------. + | 31~20 | 19~16 || 15~4 | 3~0 | + | (integer) | (frac) || (integer) | (frac) | + '----------------------'--------''----------------------'--------' + <-------------------------------><-------------------------------> + Y coordinate X coordinate + + Remap Register Layout + +The dewarping map is set from applications using the +V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP control. The control contains +an array of u32 values storing (x, y) destination coordinates for each +vertex of the grid. The x coordinate is stored in the 16 LSBs and the y +coordinate in the 16 MSBs. + +The number of elements in the array must match the image size: + +.. code-block:: C + + elems = (DIV_ROUND_UP(width, 16) + 1) * (DIV_ROUND_UP(height, 16) + 1); + +If the control has not been set by the application, the driver uses an identity +map. + +More details on the DW100 hardware operations can be found in +*chapter 13.15 DeWarp* of IMX8MP_ reference manual. + +.. _IMX8MP: https://www.nxp.com/webapp/Download?colCode=IMX8MPRM diff --git a/Documentation/userspace-api/media/drivers/index.rst b/Documentation/userspace-api/media/drivers/index.rst index 12e3c512d718..0c720ca1a27d 100644 --- a/Documentation/userspace-api/media/drivers/index.rst +++ b/Documentation/userspace-api/media/drivers/index.rst @@ -33,7 +33,8 @@ For more details see the file COPYING in the source distribution of Linux. ccs cx2341x-uapi - hantro + dw100 + hantro imx-uapi max2175 meye-uapi From patchwork Fri Jul 15 13:53:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue (OSS)" X-Patchwork-Id: 12919304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7191BC43334 for ; Fri, 15 Jul 2022 13:53:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233221AbiGONx6 (ORCPT ); Fri, 15 Jul 2022 09:53:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233202AbiGONxz (ORCPT ); Fri, 15 Jul 2022 09:53:55 -0400 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80048.outbound.protection.outlook.com [40.107.8.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBD401055B; Fri, 15 Jul 2022 06:53:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fUzBegl6NNk5/CsGrpnHWwFhPvhhk8jHxPb+EuvTmZ3ouvHvtEVLH0k5tD4BU/TvnHpUqduLvFai/GkEUXeKlAjLebxW3fgTgTIhSre0ODyNPBbrJqWK+k+OKKTSnJnp+mab1GK5NHPoXBGqGGykzctUmgiP9ykRYO7hMimYNkmbTLIuNq5ryQmsNk7QEY0lhk0iNXQpCW5530GgoB09A1TveZzPKphadVeNrUvD39hsXzZuWXMJbwPhFf6ltFWku2jH/JlAjVtKzSlFCcoJ/Tl6LeNX98GjNOwHp21eElo7eI74otD1LAgkCmrEmt7HOCvjpiU0jUbvQDewR0JSag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aXAAGNfrNiSMxe/ey4OTDpi0XLzQaqJVF9QrNOOgtV8=; b=fuLcxFQkwm1Ms02FCFv8NBO/C0b7BadYL3IMbX2+dxeAGUqPiyFTNnYRUHDxItEpLO96qkoCqUBX5EspXGjdfLfuN2nNxiarh2vyzDZ2Tvy9f36YefIsqos46kAVhhNRQU4mrUNsiMulx/zf4waGkC+Pi/buUQkzLA45QoAr6nNrk42M5hBtfZlwu1rB/Gj4586+uQ/13Bs1KIQSoZpWrfhBFMGq6KgvYcXccS0aCKStnC8o9C3Ylzw+agHyxO1zbTXFZTxG6VpCw8g/ZWnlt+BJql+inX3oTUjdb/L3We5ArlikVitiyphGFSwNQQ8dfc9YUZ1YCpS15SZDc0dBHg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aXAAGNfrNiSMxe/ey4OTDpi0XLzQaqJVF9QrNOOgtV8=; b=a1JOJBYRQj5vT6Joaft25KO5DMMUGYFxk5z5pdt/+UKvGsZ6+Cs6pjKZ6RRMHiQFjnGu83kCj7TwdWo57jh6lE+WDwcujyE6FsdhRH+Fl5eN2iaf0u3T7OXz/mck3ehUFOETronNp+It4EZwdWy+JP6AR9ESortftxLc989QNyw= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by VE1PR04MB6640.eurprd04.prod.outlook.com (2603:10a6:803:122::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Fri, 15 Jul 2022 13:53:49 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f%5]) with mapi id 15.20.5438.012; Fri, 15 Jul 2022 13:53:49 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca, alexander.stein@ew.tq-group.com, ezequiel@vanguardiasur.com.ar Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 2/6] media: v4l: uapi: Add user control base for DW100 controls Date: Fri, 15 Jul 2022 15:53:25 +0200 Message-Id: <20220715135329.975400-3-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> References: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR1P264CA0061.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:2ca::15) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c4675c8f-1540-4c0c-75b5-08da66697118 X-MS-TrafficTypeDiagnostic: VE1PR04MB6640:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qMCS12ARGlj9OfjQC2U/Zo/9IUfXxY6P2SaqUTWXP6GzYEeQ9BDZcz6wgGy2/IHmGNJ0Ss3g7m4KL4SlcAFhUJDPhYuu4cYyMRlvKhMi33MbYTanCuZA/dKgHnNb2kL4ZgxIzC/8fzY4VFQx5NluxWtB2INx1y1xvHtGpLknhHFPDVlOhYVZDEajJ9iiwh0JH2hQL3mgJ72kJjnY+nc10+ImmMMXGZWpdTB8KwUm2bAvgijxSl3Mml0+KTMxh9QPUSMOV9obcRYpflwbhJ07KL/5zdRQ+vwlCfMmPOF7hCQ1gNRf48e/xSRajKRwQatsMH7CX1JyM4VLE6UpTtwYOa+vYB5hGaNL3YESXzkwisK6QKq35glyK6VfMvV/fJM4NfGMvfT8XabbHOpFtlq3udouX1lK4nYIvURDdKWwNuuy8KI+touK1zshC5iAEAfTxeep9kOf7kxfRtRpKIosc+QsU3qi7U+V9RnuOFoq3OTp8sfS87e/DBV/cUe7kicDXjBLFmkkPSYAZXAZgSDCiER0OUdVEzq9R0i0N31IMhhipg/TLtD+PJU7xAZ59AmTxQRvZIF4zGBxfpGBlOWWgIfeLvHepwT5khPwG2s1XaSXA7XtNJtmkHCn5UJUF6bdds7MRiBp88JqDcrH1PtQwHDSUIw5ZwGb2W8frHR9xSrm5vvxuLzVnimLEsgAwiVroJ5zRuiZakf7PNUWdgkt4b9rO+TJCz2pBGebErzW+wr2IuGX8HfHMsDxW4JHPEvo X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB8703.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(4636009)(366004)(346002)(376002)(396003)(136003)(39860400002)(6506007)(52116002)(6486002)(86362001)(478600001)(6512007)(66556008)(66476007)(6666004)(5660300002)(41300700001)(38100700002)(66946007)(316002)(2616005)(1076003)(8676002)(2906002)(8936002)(44832011)(7416002)(4326008)(186003)(4744005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Wp4g8v2qc66OrOmxncKR7ByQ9lprf2dTEQ7I97py6j67Wr2UT/fUGymaxFp+qRSdP7MCAbkrP8no2oh+GPAhkZX0nAe7nzjjHshO0DubPWbPqiccrAHm8mh11ghX7AkNYNMPtT1Gtd5qndPTE8YBxIpyz+fo0OCnFtXyqJ5GO7mo509lPeTv6HWiFQ4JrPoOun+d5hjtnKdKU+9mvLfOUYG0n57ej17KqkfEyI622id+eakNNjyjIeaT13pqKY7CHjTZlfRiF8uCC9dh976z4Kxi0keAXUNJ39sJ17MCtQfC1OmhRa93o6+xyqju4MbbEa5+odkaBoIshVPUIbSkGVnznFuvEfQDQviiQE7Zamv49w/TIEi4RbO1Vs15aN3AKSenNzCYICFvyWE4ycGln5hF7EwjPJ7QD5/WAhRRQfgzCIMCbEnu5a7+WSWjmRV3OyLn+zfIk0gGcZksU63z54zLZMA2QLn+dSVNlKrSaPf4/pWMYbQQC3YhJF2ENSfaBMEyr8Bsf8NyV64QoG/uMvmxHXQ4p/s8+JUD0b5XbGiv8J3vwBHi0EvD2biI7NfZrdwJYic1hUFnIYEnV+pTkcTkCaLbBQvjBgwLbPZXcB+R2AJCKGq9U9lleO+GjIzeGa9qytrn1pBeQs9LBq4wJK1z5g/IFkqT0BS7XiGEWVVqoG4z5H6FOeIdQVZLK4kQ1WqjOTjI6onehGwMVlMhCU6BAEBdTIv3cyx1k/L7MDTNT9Yu4Mh0vBaiH0nNZj+Kfr2By9AAGfnMteoO8YrcOhMJ2UVfWzRf3juZsm5Sm5y+EQldP+xgqfBwcFSKkOZ8XpGimjzX334GB1QeSOHQW2dHY8FICivW0muQyxk3uao7Uo5Eld61NwWWTaD/uleMF6kYoiO1f86TV1ccSPIRkD8pPIdW5Mq+gN0gdPShAvbVxtZ42MoISMpFoBdoTSwsKRL5hAqMM1Bq7Wk2jiPOqLZFIkuEGcR1aAJxmdqshn0zsMYgc4uKBVq6X8cZwHvaYkF2HHk44DNzsli5XNqAhy8CenmiJ9CPrF7A8bAcw0VAGTqFOWW66GawADlsiG3qtk6vYIDw5DAtPnsYOZCK4IN+hru5BAzJeHsCL7jIGTExP074QUIWCfxH2zmAZtGTzLrh5HY0EjKV1ezDOi66lfyWO6zLA2Ke9SLDHJKFYKFgbrwCFjGDB2N8Xi0hgG1Ii3WGQQLjfhBP/6k33AlV+H4Vm4mdOtC3x9mEpWJbRoTZ2ExDFW530FlcGP1An2BB7NpJvMWEWqAOf6xs2X4HOHCb4uVfvB4O5D3eMt4bjI8l/DO+hlSDl+CwUHKjhhgpwytvXwiQnPY5LL2U3s7nkIKK9TVt+x+pjeKDwP+kNhG9QGATJCxWqcSRgHg7pCr8/h9CoWN9GNOkoc5gWBmq7ozxs0TQ15pt9MM9/3EvN5T7Ig7oVJuj/UzMNDxWaqrFqMW4ootCid7/z7XVqzULbSrPNqnSMUOlncbGy532MJuj4Fh8M5lmftkQIUeHCcZO0Pkq4uZqfStDb9+kT0SObRa+0Oy9Jb8r00Aks9bVyEW5dcpLmKQISiVZSuMEnxfiSiKugRX95l7HVWJ2JobhlGuBsWrxDfebJc40AcIGrpxaDXe/eftqbjCsO6RtYrEswKBQl1CltH1/HL3q93QhmQ== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c4675c8f-1540-4c0c-75b5-08da66697118 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 13:53:48.3717 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: owbPMarOCkktp4FfQgZGd1O7Fk6BpYwj1kJWu/Q0Ef1C0InTL7eoug+v2YNpUWaBZb9O0yS9w96E3Qyu2XURNw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6640 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a control base for DW100 driver controls, and reserve 16 controls. Signed-off-by: Xavier Roumegue Reviewed-by: Laurent Pinchart --- include/uapi/linux/v4l2-controls.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index dfff69ed88f7..0b26ebd6ca78 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -225,6 +225,12 @@ enum v4l2_colorfx { */ #define V4L2_CID_USER_ISL7998X_BASE (V4L2_CID_USER_BASE + 0x1180) +/* + * The base for DW100 driver controls. + * We reserve 16 controls for this driver. + */ +#define V4L2_CID_USER_DW100_BASE (V4L2_CID_USER_BASE + 0x1190) + /* MPEG-class control IDs */ /* The MPEG controls are applicable to all codec controls * and the 'MPEG' part of the define is historical */ From patchwork Fri Jul 15 13:53:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue (OSS)" X-Patchwork-Id: 12919306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77E1BC43334 for ; Fri, 15 Jul 2022 13:54:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233878AbiGONyA (ORCPT ); Fri, 15 Jul 2022 09:54:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233335AbiGONx6 (ORCPT ); Fri, 15 Jul 2022 09:53:58 -0400 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80052.outbound.protection.outlook.com [40.107.8.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23AE91ADA4; Fri, 15 Jul 2022 06:53:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UNAM2sQolzC4wSMMFKk82ZvHzhrnxqKda9ZtvlyYjxsPPY3oOyOAPO4PgOLbUS7kay2cvOz5k/5WTTwaLSMa+A7WyGVM8tdF4I7GuMKqKbJpHhBkXLTUuXPpRqJKykZCqwurLVMZXGQ/YYzO49KeMuAaURyBk4Ueueik2UvHi7FxECM9BEKVc+5CzNcS3d6BQZj4Mforue7tj07DxC/5omVYFjOEyG8Q5bRhtp6N9a9IRFdXpVIAh/UUxVPqmozLg3gxAAcSxg1S70x+vW0yVGDSedEtvsei/5rK/Jn7XF489rDJfZ3yXUrN+d9jCvnAn714tYYVDpglJ8oAR0tkOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ervFkx/u73e7LNB5CzxBael72hFEpKh5geegkyMMdeY=; b=nRcUw/XvHvxaWs+jjDMNajSENJ5Mie8ogtqVfvABQPeybGnDaJFNSfpJsg1N7fm/2AYNt6udX5Yq0D9T+OPyV308PBAAG/0Q/mIMl1zYCd9VFJYHubLSUPLBJC9fb4PpatkNaShmzJQkNQSrPkHrvz7J+iALsx4j2OtzCu5aaHVTQONvTlxGxvRmIihcOD8cZYBBfJ7nblKty8HyhKANMeTOjsPJg6XrSBwAuax+K9CKoJrsFNSMNde7tUZSp9F7TJ5otfZHveq8dHX3woxZSHiWJ7Ig4GmTcoUmY/JP4ozdonZMsrwZOCUZWgEbhI59QumFWAAdta+gAccE8L7Wjw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ervFkx/u73e7LNB5CzxBael72hFEpKh5geegkyMMdeY=; b=I0Pwmp6KYC1LkWjmYAl3Dpn7fKX4vJVAagEYCQ9izQ0xmTuLAoQ/I5aP0rMURRDfCCTrRJgoWEgNjInH2pBcQpuhoNwQBZwWKURWQmo2AfhUuqj5AQ4Qo3nV64x4iSe1ZpAOOY4l9O9xwfMAZBF1YQILB3Fa0miCfDt1DL1jGTs= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by VE1PR04MB6640.eurprd04.prod.outlook.com (2603:10a6:803:122::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Fri, 15 Jul 2022 13:53:49 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f%5]) with mapi id 15.20.5438.012; Fri, 15 Jul 2022 13:53:49 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca, alexander.stein@ew.tq-group.com, ezequiel@vanguardiasur.com.ar Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 3/6] media: uapi: Add a control for DW100 driver Date: Fri, 15 Jul 2022 15:53:26 +0200 Message-Id: <20220715135329.975400-4-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> References: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR1P264CA0061.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:2ca::15) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c8ac96ae-6e76-4bc6-9f24-08da66697175 X-MS-TrafficTypeDiagnostic: VE1PR04MB6640:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nHOqb+4DEcRy2ZfLJR4BpL6Baj1Uwz216m55rirRCWbGCeKXoNdBQ/tDR1e0Q+OGSKlfPxPN3YJWM0OpFzq6UA8x8w8iqZzwNypBTYP67/wYOp9ZcB3TbRQMdaIOey9yzEzjXzWdacXjuGPjWeGhG44cuQ7WDRmSwIf6J9zvtATt++IObm0C1n7kNUQK16P/qcunVnoU9pJx3j0lrkDePKr3UUXnQBGt78IwZvhW7o46jS+uhqaerH5UbW3iY13LvAwz3mO2f+Qkue4fzO5vfTxihNHq0icNMnUo6DjKDSsT1SP3/cZNRqxtauLj+l1pRwprMq4fOw23IHMdZGgWQqvrWHVbnEM9Azo89MmEE7X5L/nG0XjeATwM8XbYqpoO4yrRMQFR1muQcHycFb6DYqMZAQJt2ofVqUmvBOyKmTfRvDYPS+SQ97EmNm926S4dbxcNuI6CR3LayZ6p27PE2I3dqsgPxfKgHfaHy8p0BgS2OkUWsEp/Lywie8VgH6GRsTvfo89sot+WZy5C9zgFGBVugNb5nvKWnjasGi5wgtIWGQkZ/Fyoqqn9UKWa2drUCXPHH+mUKBLpdywF1MMoXOMCbVegWXjhSmrAYw9mmYTcAXAm8S8BvqN0phvXPygnnFVQ1qR5uPArO9XPVrbL2UpJAvYYdxlGaNZ+afwTGwsUF5r5BxrF0rQTRmNqXyzsfwvuaaNl4o7MjbrRCzMGLvSJBmTX0mXTqRp76htVoI4MCLWGKgU6dqmKRNhm/b5Yy45ruGmiDYh8Z8+mOzFaQHBJHzvrlhdIGIcppIOA4A0= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB8703.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(4636009)(366004)(346002)(376002)(396003)(136003)(39860400002)(6506007)(52116002)(6486002)(86362001)(478600001)(966005)(6512007)(66556008)(66476007)(6666004)(5660300002)(41300700001)(38100700002)(66946007)(316002)(2616005)(1076003)(83380400001)(8676002)(2906002)(8936002)(44832011)(7416002)(4326008)(186003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0cSz7R7mF8sE61aEjAXnnDHrNimWhOdmP+C0NcoCa/IH0o1qwZNQDXk7sK6BI5AC2eP8q827Neki5txu98T/aioGkUvlQrCVzTbOZKQyISAZ34izxu2H+Iyv3vfztNfdLSs9yu+IeT7q7BWMR7R947RWXrvLwL2OWzkFPoLdkH50U5igVsWo5hc4WdrhjcaBrxwhQV2vuKm0cidk9jfD/9s7ZFi/p3rYw4yxSAe9ADx32aT9c4gOkNCjm1XVdxjSvzLQuI+9t0XnzL6HLCTqhO/wu8aQjAC9UChKzwjl1u5CNNd9HiFU9daCxtMbw2jbEwfN9RxMJPu/kgwsoDIA8fIoD7RoXJVkXbfNAw66aKgiZJB3uZA7gMz2434lsM3bEGI9YcTDf6PudLnhQfzKPIAZ+7FUWxibdvfWPD/5+4LLPaPPQ5sjkVtNlOWq7ldds9tgJmNhLpiccqPADME8R7u8HLbM25pROKmG88RkoOTu5+RMcDCiiya9o/EJ5OngprA/tJs2M97amZRGzjDCw5zvdNCU7gjodBujyiJIxtpmVei1ak8zvq9z8qA0YHa008e8wDPzJdVFIQ3XQJkP1Og7BGQmrg2BH3pmqzG0W8RhZj9BRlR6KVbOwskBX1VsyQJHOqeQc/AWb06+P3zDuS1wldYu1gPubEjsS3CIGfkMZDgOGGyvtkVQ37tO9Nruq1rGkI82IqjHt0u03PZrkooEwm14iA9SAksEqmYKde9JELnQyP+XV4DUcYu3f3Mi4EbhOYwGbPWO7RHk3UfMsPwU2J58OenVWaU1cx0Ww0ysWavxuCjj1RekdV2avJcqMmDT+ox42O0LuOCVD9psOv70+UKS04JN900IFHclwJ7bsTvZVe37/f6gQMAO0h9Zo9htOn2YM2EhX9mmHQDOkTGaBCrvI2ZnRvjJJ6ZwKFaIuOoatfwfQa4AHV4/+X1E5l3czg76m8Ess11/N+vOtOPMX3S96azQKoTYops5tOWlS6kN/stccp+jxcXVJW5hMNvFJEXT1ZBqgpduzmIHg9g2To+YJnqwPN5y7YRm36XNw7XAz68EcFx0wV6bIbhMSTtgUk3eEACLTt3LlrX0qm6pFKL23F8SyvNr0pmsogVQByXl0ii5fVhy8mUxkrf5JD/KJ7KxR6DWCk4zoeYWDZNBiqy/SZ0qexzst3KaNyec61ITYrCuTMG49CAYiZLHgADQ0axK64N5pCnUrAIXL7wd3tkB74bBBPVQpqgag+DSjdxyGYoR+Ed8RrtObsXn7WnT93EQYE92xCd5i0laNLE7V/zPIJ6tAuDM3lMJcOATt+A+Da3ntSORRzO58QVCtEO9e0xuK8aQWDl2lkjwSPxeC7nxIGebqYHKoTj804pOrXY0VS+gqne/BW19tvJxIuIejQrZT/WM74f3fbQ7bH5AEQCt2qyhxuUKiQaa7V+jWu6IlB2WYrkUKdRjpogDaEwTqgKzL24YFLC7pILkVRcDfIirdu0bCek8JF6OlRN2NtHYV9sitoR+NuUabSYy//DxNOoK3FQgW21cZcMsTd2XNmgfq7/0f2Poj5HBXMcb31IU9GSQI70UAYTfZAUJwjtWsUwndZPzfWZCWmS7VT2rRELzboslwqInhlrg6X5cUNSE6jKDQLGnR1Ksgw9jEFlECDj12ZZMvXfRXYBWxA== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c8ac96ae-6e76-4bc6-9f24-08da66697175 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 13:53:48.8573 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: tfUYaOxyG8Qq4W7uvlkSQnXQ4/EXM0KOzg59p4uTQlXWIYziMc3mK8jVjewIMQUlNkzuUJTmBnrlAm/9D6senw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6640 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The DW100 driver gets the dewarping mapping as a binary blob from the userspace application through a custom control. The blob format is hardware specific so create a dedicated control for this purpose. Signed-off-by: Xavier Roumegue Reviewed-by: Laurent Pinchart --- .../userspace-api/media/drivers/dw100.rst | 15 +++++++++++++++ include/uapi/linux/dw100.h | 14 ++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 include/uapi/linux/dw100.h diff --git a/Documentation/userspace-api/media/drivers/dw100.rst b/Documentation/userspace-api/media/drivers/dw100.rst index 1ca6fa55f539..fceea6ece622 100644 --- a/Documentation/userspace-api/media/drivers/dw100.rst +++ b/Documentation/userspace-api/media/drivers/dw100.rst @@ -66,4 +66,19 @@ map. More details on the DW100 hardware operations can be found in *chapter 13.15 DeWarp* of IMX8MP_ reference manual. +The Vivante DW100 m2m driver implements the following driver-specific control: + +``V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP (__u32 array)`` + Specifies to DW100 driver its dewarping map (aka LUT) blob as described in + *chapter 13.15.2.3 Dewarping Remap* of IMX8MP_ reference manual as an U32 + dynamic array. The image is divided into many small 16x16 blocks. If the + width/height of the image is not divisible by 16, the size of the + rightmost/bottommost block is the remainder. The dewarping map only saves + the vertex coordinates of the block. The dewarping grid map is comprised of + vertex coordinates for x and y. Each x, y coordinate register uses 16 bits + (UQ12.4) to record the coordinate address, with the Y coordinate in the + upper bits and X in the lower bits. The driver modifies the dimensions of + this control when the sink format is changed, to reflect the new input + resolution. + .. _IMX8MP: https://www.nxp.com/webapp/Download?colCode=IMX8MPRM diff --git a/include/uapi/linux/dw100.h b/include/uapi/linux/dw100.h new file mode 100644 index 000000000000..3356496edd6b --- /dev/null +++ b/include/uapi/linux/dw100.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* Copyright 2022 NXP */ + +#ifndef __UAPI_DW100_H__ +#define __UAPI_DW100_H__ + +#include + +/* + * Check Documentation/userspace-api/media/drivers/dw100.rst for control details. + */ +#define V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP (V4L2_CID_USER_DW100_BASE + 1) + +#endif From patchwork Fri Jul 15 13:53:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue (OSS)" X-Patchwork-Id: 12919307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83AFCC433EF for ; Fri, 15 Jul 2022 13:54:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233519AbiGONyC (ORCPT ); Fri, 15 Jul 2022 09:54:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234025AbiGONyB (ORCPT ); Fri, 15 Jul 2022 09:54:01 -0400 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80052.outbound.protection.outlook.com [40.107.8.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5768C1ADA4; Fri, 15 Jul 2022 06:53:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Dx44Z44RSvgQVys4ikYqVEBBhu4SlWzjEhH8BXf3GVFtJz9j66QHVXqqoW4XxS5wGwDlPxUcbYuIsAfMLibj4x1XIzD6FXWN8Oo9UdVA8rSwNuY5JboEyQKRB7Screy05MG7Bl737hi9KgMDKUyD+SwaMRYYFJlyW7fQ8trp+7dDbkwfBjBob5oFRPLJg1oBhw9toIcvNF7nO29hWOUqcqJoWHnxQ0expmNl5gieArbENUAtTMwo1tZ49cAspPMVViDCB+VUPtKuPbHw+Ubcw+M16m5uqV62Pu98RlK3L2XyvPL00atesI9qQzdgPTlF/JbPgLTgGQn2cqh2wU0xGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sMkngJh0bpkLUQJek7tkMX0t7mASgAcmSByCfPSzdF8=; b=AzxdIBCzJw3Z9jmd3vYyUACAOTQeJ3LVVpTiuvkhAwqO0hKExl3NVQhV2VIiSUngOUm0pMOmka4sqVISzI03T20xgs3dsc5UvToc7UgmaAsRHu5J+gf8IxCtE8VC060OQTXp2h/Z6R3CwQ1KWLqTL4J+wZyvdzpoBwzgHURBREm2ZSosQDXnr+u2VMQG62K2AXNRXhrTjPunbiRpL5FQ8IvlaHQ9RkpCQ/pzI9ZtUEYyveKwnpL1lC4V7hvHiU5FKbeRFGUgvmMoZkge0OVfqvC/GwfIVhWFuausPHNpCpKUzwf1A3U/uN+EG3OG1s5pgn4C9MyK6x4NIRm/Mxj13g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sMkngJh0bpkLUQJek7tkMX0t7mASgAcmSByCfPSzdF8=; b=cgBTSjcMBNTfKunC1mqYig6aPdHQQDzJlGRcpvFoQQYua7xSK1r54rs4Ztbz9DhZFC8aIq1sWNl+UOfv7U9OHaVauR+RuENueR6f9XDSafYUw/TPYGSr6S4snaNGl7vRSpDr+uh+M89M3KrSKKnddv5409sKunCyOgoGL4A2dik= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by VE1PR04MB6640.eurprd04.prod.outlook.com (2603:10a6:803:122::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Fri, 15 Jul 2022 13:53:50 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f%5]) with mapi id 15.20.5438.012; Fri, 15 Jul 2022 13:53:50 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca, alexander.stein@ew.tq-group.com, ezequiel@vanguardiasur.com.ar Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v8 4/6] media: dt-bindings: media: Add i.MX8MP DW100 binding Date: Fri, 15 Jul 2022 15:53:27 +0200 Message-Id: <20220715135329.975400-5-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> References: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR1P264CA0061.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:2ca::15) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 59e169d7-30ff-4169-e9fb-08da666971c1 X-MS-TrafficTypeDiagnostic: VE1PR04MB6640:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LE2Q76e6WJeA/DqN51tgse7As5z2djC64LfGcrYi/kIHp7uyCLJ3tTe+fREiQPHkJmUCb6YaKx5qpsa5qkzYJvtzUdNH22yYTd+Uf7Gj0TMMcS3qxnc6Ym7j0UtXUh9ubSa+4l+Iae+Be5kPuOXFzNs3KBVuHcJoQzjhnyyxs2SYBsjTnkjBb323S+le0tO5uWznK+OPv1wfAcuKD+zIjuOFn+mp+skFX1w2SYTlIpRH3VD8hHGogh9T4Xf7N44VYTc4cPcT7hBCZpAaSmpzfnlK3Nl050w8f3cz140dkfGBi2q7xO8/IdtPk007HuEPsuNfIeC73bvGUKq4dWdNq6+UrMwhSi/zV5EK31DF+jfvQmgE4+NdXOIZBgLhQd5b0Xv97s58Fyfim2UAQ7Gq4FfsxxTxz//i4YzRME+ZmmAm/KteQAI3gaWT7u6nOrGSupygvkylQBzYNK+Bn/VIyr0uoQ3MBHV1LSBov/6chOIyNHf01OafICXEcH2cjuP6UH+UcaPFpZawDt5MGcCOC8DDPEdOQPsbvEO7m2hVI240LU8Wgfy5CSLQGrQhpa4Ujr/AFWGVO8U3C6fr2kfS7XrWFzzpNaQ1mZUKYViCibmFf7nLaZ/O68YPl64JquI7Nh13BTPEaUI9EoMEA213NaPWRpxHoARV+sum2rrAN4bbQeDkqQuMd/FhDCGY/gycWB33xBr/8eNwOSf6F35UJxnbVCTCTF2fU6qAd9hxwB4wRwVza5EdcgLYuXjUExAX5FRy/G3qiOaRvxNH0wQoigliaTmSAa0LegrwHy+CKbuXwcRyju1sLVSIQGAvc56KX61d56DGFouqtuTIezxlZw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB8703.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(4636009)(366004)(346002)(376002)(396003)(136003)(39860400002)(6506007)(52116002)(54906003)(6486002)(86362001)(478600001)(966005)(6512007)(66556008)(66476007)(6666004)(5660300002)(41300700001)(38100700002)(66946007)(316002)(2616005)(1076003)(83380400001)(8676002)(2906002)(8936002)(44832011)(7416002)(4326008)(186003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Cph35du7wMUXS0vEgAP6CSq6QXsRVfd5fJPPgteLL7QKiq1pWdop7xcaouI2w0xxx3jiqtH8jLquxKn2zlgwfF4BMHIzBKfy5utPK/NpC+z6XmnT9iOzRiAjzUwiDqa1ZRn9hykooRoz6UKywf3TRabqPfT6QLl7Rd4AWb0MTxNkEziSmpNvxlfu5W4Ir7zsRRCCalrFGr/oDfVxFXlmQrJudhir+oiPPGCBha4iXq0tuPwYgj/Dh0hbBLKZ+x1FHj+bSiSNSkhN4a47aRAkO2hLLCZqzj0ne8R1GqAYovYZ7c0e6erw6ZgQIX8tNk+qyyGLFYBhqAFPHRITdTgxKNHdT3p4uQks0RLp0Y3HjVeBxdFs6ggl9mJg6FZkfdlN0aF+rqeqJ4irK0Ej1JRgm+jU9YxdT68huLw/eIKnZiSiID/I1oLKNTnyWyJ40Rmg/8asEMKPCB1KMR6mnSS/dNjo3I+rAgeBvctKJGyt4pl35wEhhy226msEp9/8jFfCv/psDGGMJIwqUrNrDHN6Ke+LtMpZagddm9IiwjqgEyqqUq1l/4WLC4/WEwLFZIBJbkcnZA41NklxzKrUZB9uo3JKNa5iCsoRQE6MdDTnIgkgN8UE2uHogztTCe1TTel+7Ru312OH+SBlpMbYdHA79vk5SIe8mMoySCkuvvZJIGf9VVMyufTlK7NGzRkMv4ez+NuqSpsMRPeKMQh6nxGm+g8ehjr2ZkkuVzK5NkKTXwhgUnbqBkoqkI8hX0BN4adWrI5Hj9CFDbExOL2j1w9WZt8v3H+LaW27/KmSafZj6IzKkAOLhJSDTx20ZJMYGY2WvbJUS1To/C5au++SorYZURq27Avk+Xw6DUsEQYLfAJlMG8GkHqJbM104/9eY+VCon1Cc0DK+d1FPaXIAgR9SrKB6O+HhX6MEqI2Awb0FdfYf86xuPoM2lNEhWCAcwt0zt5R9g5LQjPT3dV8pfw9WsumavO8kmgb6ZQfsuoqza9toF/IIfHdoC0/fVRfNsceEo0Tpjzq+THxLOyfkP9JRxvFgCWH1OeXdiUk0HLETqK63zEnufLDhjHT09XXWdNokn4cnKo0fLR4r6Po/O4ArXkMXdG/k0o0SPzRYWY9W1rLLOnf3gRR1lEV5W4/Ph6S7e/oWc1+DxdjrZ0t2ynPjnPkgjON/onTpNdrrhLtyr8APhbOA7W/4VBo75ghBga6BOM6dkHdhOFH/hI/KuXsNIXPn5OxxYTd0XdhzlK7y8rtcbaY08+VHkitPdiaLQWKygO78lcNiIoU5yExT7Wk1Kk5LjSaf7vO5WhR59yDp5utkxejCezUXT5KSqtgi8PiJNVklfwwxlYUUynezB2pVZFsawCYQMvY7PrTvk0FZCyjAuFhLPUkdHpZP9OL3b/eyrgB3I92nNT4yS5Ye+l/S/EASB6mzDf4utoTHIOsLmXRkcUfR2TVyL9oe3G6Oo+k7+cPVL2vrauGjLvDwUCRRDBGJk6i3fEDAJnDVnQZ/6c6hh9AoJ9j9axeM4q89KBBweI2n8/Bk6KuMoroG1ZBe30x3kt3wSfQM60ydJEM8rDH2wo+1T/jzuqDQs8i6jUHba5tbH4MfdDRWw1tu/awCqrXSHOmPyWdEix+rJbxFyfIKcz0L2zvjBaMVVLi2u/sGmRovhqZtL6MDtNBffmI3sQ== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 59e169d7-30ff-4169-e9fb-08da666971c1 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 13:53:49.3415 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9trCLfVMN/VtG26afEkUSFrlhQFkameQcnnM3r9BIKmlTdSwN4Qfc52LyX+G4NoCH/LgvyvD6WDd9GM1k+kE4A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6640 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add DT binding documentation for the Vivante DW100 dewarper engine found on NXP i.MX8MP SoC Signed-off-by: Xavier Roumegue Reviewed-by: Laurent Pinchart Reviewed-by: Rob Herring --- .../devicetree/bindings/media/nxp,dw100.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,dw100.yaml diff --git a/Documentation/devicetree/bindings/media/nxp,dw100.yaml b/Documentation/devicetree/bindings/media/nxp,dw100.yaml new file mode 100644 index 000000000000..21910ff0e1c3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/nxp,dw100.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,dw100.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP DW100 Dewarper core + +maintainers: + - Xavier Roumegue + +description: |- + The Dewarp Engine provides high-performance dewarp processing for the + correction of the distortion that is introduced in images produced by fisheye + and wide angle lenses. It is implemented with a line/tile-cache based + architecture. With configurable address mapping look up tables and per tile + processing, it successfully generates a corrected output image. + The engine can be used to perform scaling, cropping and pixel format + conversion. + +properties: + compatible: + enum: + - nxp,imx8mp-dw100 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The AXI clock + - description: The AHB clock + + clock-names: + items: + - const: axi + - const: ahb + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + dewarp: dwe@32e30000 { + compatible = "nxp,imx8mp-dw100"; + reg = <0x32e30000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "ahb"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; + }; From patchwork Fri Jul 15 13:53:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue (OSS)" X-Patchwork-Id: 12919310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66479CCA486 for ; Fri, 15 Jul 2022 13:54:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234777AbiGONyH (ORCPT ); Fri, 15 Jul 2022 09:54:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234478AbiGONyF (ORCPT ); Fri, 15 Jul 2022 09:54:05 -0400 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80052.outbound.protection.outlook.com [40.107.8.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8E1F2496F; Fri, 15 Jul 2022 06:54:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Q9OaOybL5mrctmz35sIAhSFrjajGvByhjZPGL3tft8yc4fzaFOU3Mz7hdL6//Mx+CN5qeDVtRkrpJJ5RBKxM6wg8BVLGfBnTtAEfhZjmaV+yhciB6RF2sh/MfLwpSt+WPxexjCrLnqi2mqzLOaJh84hnVU8yG1tCJ16XZOQJYA5GsuUmKT/B20bR4G6/RR4wTI+Wda8/ccwopgfTwdpUoGa2vDwLJl+B0rc89EFNiMi37QiVZh06ZnIYlSf5F+j88+U1VKFRXz2EYssk6+2OJh4iD661fLYDNJuocGD7j9gbAqqWAHtFKz6v7nspX2df841zgIak6RJe+UQOyKCNPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dHW+4hXSGEN2WhlbVdnGpd/a1BsKRvBUSZRQROG2p8E=; b=K5+XLCPIGpL5aR1wvfhV5BbyK4AuJ36OahWjxnWtanHACNmmqnQqLbkG6SzUNQaCiTG7IzP8TC/KeLZxeO62pQzq4e1fxIpLIhRoOP1dY68I8b1tRc2kPep21SAySVweMH60V6GxtIPSevK257TFL6W6NWZRoa9CfsJIoA17gzO2p0PJYe3pTcmcFOYjmFEKlehp8MHsNRRB4a+tH6N1kcEYTh8iJ2a3iaLvB2ij141o77wkOCIQEbHskClzTWtpa8X8zllO0Lbzs8/0z6X4E+YfOrnDyQ4z3Fmh66EIZXRIzJFbNXWXzJVA1ZsNW9Smu3urOrmKmFPENNAR6fuA3A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dHW+4hXSGEN2WhlbVdnGpd/a1BsKRvBUSZRQROG2p8E=; b=ZZ/AqyhgzjEBW0O/y7FtmzUScR29N0etr1Yf2UEz19q0ebXCTtwN4ljJ+/U4Unujz2S3tkGMAdCnA8BXb831SlCIqmMjc1X4YBghrjagKI3zmQiLdadIyMo43Dyp8jlPqUJSgHU30Ev9FIU/U5uhYiwXC6TvJ3AWO8qqjwAYPrg= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by VE1PR04MB6640.eurprd04.prod.outlook.com (2603:10a6:803:122::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Fri, 15 Jul 2022 13:53:50 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f%5]) with mapi id 15.20.5438.012; Fri, 15 Jul 2022 13:53:50 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca, alexander.stein@ew.tq-group.com, ezequiel@vanguardiasur.com.ar Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 5/6] media: dw100: Add i.MX8MP dw100 dewarper driver Date: Fri, 15 Jul 2022 15:53:28 +0200 Message-Id: <20220715135329.975400-6-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> References: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR1P264CA0061.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:2ca::15) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f657371b-0c34-4a59-9057-08da66697210 X-MS-TrafficTypeDiagnostic: VE1PR04MB6640:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PC0AWo4SomFTYcaW2ZY43/vAT4uhV1iMReq8uLKyeVjRf2RcaYMiNZE668AUO86oZkK0HL9GUsWMvwvHMaGoQu8qxx02M8wTEsYO9TDBo2MqIW2g26TExas8C/fU993HaT5sgDUX1ThTw7Q12H3BCtZWvMRvklAsA9naKP8OCQFDgdcMl5vLe3etShQvZJrojrvD6SadaWg/HdmpkdCl6dUjJ3nDO5n0mwlHH2r9JCRW9XgbmyFFnanKnfXDUjVbe+tZ02sxufZC3m8MEg8quWJ6LdI+K1mKfdpTQFatgWBzjXOvGf+mqNPmMB34ugYjkFE6QQADyJxGGejlaHSOqaqRHLEjR9IuzoVaBm+6kXgOUv4nZMDNsE/DaF/tM1m+k/wyIeTqF36i6Y9Xtlirwh5qQ4WiC2vz8GtdW2aiQiDumMUUt/qp+9Q5d4NAf8XDoc04+IeL4QwFkZvVM6K7oEiJtYiH8XDi550utHMpwPBmfS1UsJDe+6y0mZPdOQp7/tLdhMtdNUf7zf9hakNNGVqhIaX5lnW+V06Z9Vg1womAjCvbDAavoaJlfIVB0hx/DBXqAGIWo4JM332sd2aoDXjNL3MGXR13RF3fOQWcTfIpHyckj65kTaLe5Qe2bokvY3NonuhEG5ylUxiKynknmkdjQLNlD+/Fqc/eHBuQKa845PfNje2cZq5TTgQdEUHEU4nDE/TPYGsvzuXE+Vz8sRoISnLfV3/uOQtWkpW4K5n/fpMGl3zhUUlDerleeqc/ X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB8703.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(4636009)(366004)(346002)(376002)(396003)(136003)(39860400002)(6506007)(52116002)(6486002)(86362001)(478600001)(6512007)(66556008)(66476007)(6666004)(5660300002)(41300700001)(38100700002)(66946007)(316002)(2616005)(1076003)(83380400001)(8676002)(2906002)(8936002)(44832011)(7416002)(4326008)(186003)(30864003)(579004)(559001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IFRzG0uPKEG46JrxNvbPvwrsOcA88ooUpme8dYaiGbFk/Vr6BKHGBcJwhB11w0RvQQK1neNRZDlwv5XsJe4YR7ApTQtj3omUAtbdsmx0cEhgaNu107d33DFTmSSWm/o3Ref8NgMf/TPZyFPxaYb4oovM8b3XJ/2vldDFTlE4SLplIaYF8qzPwdPyaaCvCwEI+4M+GNCD/gQ3CS5jPRiJNGcHtLCtSqm3j4ML9h7QS3af4i8JiDXva7U8T/w5PI9u8cjccrhuutnBH5Nr1GdjD1ZZZuL4YmrhL1GlgbHJftyub8JdecX7APV6hcE5UIPtUmDwIUyxE6YJUnq3gYRDAIc49KFz0MwC/G4JTngc2NFyqV3EHxlqyo5v95D8gsXO3VSK8hpYxNy6t4ZxBK8UNTVCt03kOiE0V6POk6+gyaE50HtR9nfjO55vomuUaNHvkOKQ7Digt+ZaolKlQA5jAkqTME63RGMinfboLiUmZhBObLA0NH8T6VWeNiXzT0D+li9pW4dvfr7HdDKwcVDnJXtWn4RNCCOoo4a6B9rQbmFBKS0DYxFzN1Oe2Q0gCj/P1xTfwLsWsYhcrfw7tfAfzH+86Q5dYoCBFfeYkR/iXv38A6i1529WVUEj48RpE2CytXo+GvazFSfZNYjbUYkJU7qh3y58mgh72R1qeW67tEQnAZwi0jqAdQ6U0GnsY92HArSNz97Zx6pkt6cYJUMhGwW6P22orAfysCberpexyIRN+BxFZc9ZBIU8X5ubIQB6jc8FSjSVuSH8LjIsO9CuvyMgcNYbJT0vjiMBHRD7LLn5LPCyicAC0iFi/Y1/fUiAYTcWJgM7z6BpbjkOanCUBIRmhRkBV1NRKLlobTzEwcaode8o7NEAsOVDL4MtcbcwHY6SsQzaQKiUSabNRsSuxRcNIlScNHDyGApX7Bskj5I5FeKDlvfZJOPxitD4eyJj3NyqwF/E+E2ISPZSX1oxAFCcZ7BeIg/Q7uv2EYjVQGaqbCFVGZJYeem2Y9bziS+AI/HgLOEQ0yFR75s6NDlkG0bXsi5YqR1uhw254vSiyfB/q5TiF/pzJ27I9BAlMqUI3+34QAD3b0ZCQIRC/DUtxwvdBOugd17OM6jM4s8OPQnDdY077XFvCVti/MXMBG14Ce48GJB7N1Yzq3HjW/P3jCMKxX8ZTc5ngbHQiGM9bSu/nsRUHJO3Rc5KNOC5BDBzUUwFhdMSe63C8Th8JsAw0ELogXd7+pBwInEcitQzgigNGYT9vZWzfA5DBkVHcb3Nf3pR8komZ5xj98N6ts5JtCgOW/pTQ3zdIYX6HXEXvwW00a+eV7djxXKbZAJ4CXv4hyXCEgjS6SCGB8uiNViOxAHJxqnnide4/v2oaWMBeC9inkZ+abSimX+EauXXYv0Ogy1/971yTgY8gm63lpLtbB0KLvL9NVwVpBAaXgD/VTuXWfS0xhVuEQpK1ZS1TJ7awkKIw8idVKi3OfdTy6Z0hgLC+Yo0ezTPAo5WZ0B1ycuZFVgRP2fmB3jf/6BF9Hw4nvQ5u3b3kk1ClLLlTJbiDrp13pfBGDeI5S8OKfp4d2o+ZB2pQI9y/P8uWjWty9zbf3CSAj5DvBH4cGUoSf5kjnds8qz4Fw3VQj51U4ZtWh0fj+XjU0BtNer7XUmOZBEzp7+GLvRCDz6jZeF40f5BEQ== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f657371b-0c34-4a59-9057-08da66697210 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 13:53:49.9196 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2/XvDRdsabwbPltvsFcCKCouYItb2u8uazqumW41KHNu47ONfVnJswIMxathlLH6eCSR5X+yryUpXQPAQqC3fA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6640 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a V4L2 mem-to-mem driver for the Vivante DW100 Dewarp Processor IP core found on i.MX8MP SoC. The processor core applies a programmable geometrical transformation on input images to correct distorsion introduced by lenses. The transformation function is exposed as a grid map with 16x16 pixel macroblocks indexed using X, Y vertex coordinates. The dewarping map can be set from application through a dedicated v4l2 control. If not set or invalid, the driver computes an identity map prior to starting the processing engine. The driver supports scaling, cropping and pixel format conversion. Signed-off-by: Xavier Roumegue Reviewed-by: Ezequiel Garcia Reviewed-by: Laurent Pinchart Reported-by: kernel test robot --- drivers/media/platform/nxp/Kconfig | 1 + drivers/media/platform/nxp/Makefile | 1 + drivers/media/platform/nxp/dw100/Kconfig | 17 + drivers/media/platform/nxp/dw100/Makefile | 3 + drivers/media/platform/nxp/dw100/dw100.c | 1683 +++++++++++++++++ drivers/media/platform/nxp/dw100/dw100_regs.h | 117 ++ 6 files changed, 1822 insertions(+) create mode 100644 drivers/media/platform/nxp/dw100/Kconfig create mode 100644 drivers/media/platform/nxp/dw100/Makefile create mode 100644 drivers/media/platform/nxp/dw100/dw100.c create mode 100644 drivers/media/platform/nxp/dw100/dw100_regs.h diff --git a/drivers/media/platform/nxp/Kconfig b/drivers/media/platform/nxp/Kconfig index 1ac0a6e91111..4c76656e353e 100644 --- a/drivers/media/platform/nxp/Kconfig +++ b/drivers/media/platform/nxp/Kconfig @@ -51,4 +51,5 @@ config VIDEO_MX2_EMMAPRP memory to memory. Operations include resizing and format conversion. +source "drivers/media/platform/nxp/dw100/Kconfig" source "drivers/media/platform/nxp/imx-jpeg/Kconfig" diff --git a/drivers/media/platform/nxp/Makefile b/drivers/media/platform/nxp/Makefile index efc38c6578ce..22ba28ac6d63 100644 --- a/drivers/media/platform/nxp/Makefile +++ b/drivers/media/platform/nxp/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-y += dw100/ obj-y += imx-jpeg/ obj-$(CONFIG_VIDEO_IMX_MIPI_CSIS) += imx-mipi-csis.o diff --git a/drivers/media/platform/nxp/dw100/Kconfig b/drivers/media/platform/nxp/dw100/Kconfig new file mode 100644 index 000000000000..45e01baf3b27 --- /dev/null +++ b/drivers/media/platform/nxp/dw100/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config VIDEO_DW100 + tristate "NXP i.MX DW100 dewarper" + depends on V4L_MEM2MEM_DRIVERS + depends on VIDEO_DEV + depends on ARCH_MXC || COMPILE_TEST + select MEDIA_CONTROLLER + select V4L2_MEM2MEM_DEV + select VIDEOBUF2_DMA_CONTIG + help + DW100 is a memory-to-memory engine performing geometrical + transformation on source images through a programmable dewarping map. + + To compile this driver as a module, choose M here: the module + will be called dw100. + diff --git a/drivers/media/platform/nxp/dw100/Makefile b/drivers/media/platform/nxp/dw100/Makefile new file mode 100644 index 000000000000..49db80589e9a --- /dev/null +++ b/drivers/media/platform/nxp/dw100/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_VIDEO_DW100) += dw100.o diff --git a/drivers/media/platform/nxp/dw100/dw100.c b/drivers/media/platform/nxp/dw100/dw100.c new file mode 100644 index 000000000000..986ef1c9dfe3 --- /dev/null +++ b/drivers/media/platform/nxp/dw100/dw100.c @@ -0,0 +1,1683 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DW100 Hardware dewarper + * + * Copyright 2022 NXP + * Author: Xavier Roumegue (xavier.roumegue@oss.nxp.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "dw100_regs.h" + +#define DRV_NAME "dw100" + +#define DW100_MIN_W 176u +#define DW100_MIN_H 144u +#define DW100_MAX_W 4096u +#define DW100_MAX_H 3072u +#define DW100_ALIGN_W 3 +#define DW100_ALIGN_H 3 + +#define DW100_BLOCK_SIZE 16 + +#define DW100_MAX_LUT_W (DIV_ROUND_UP(DW100_MAX_W, DW100_BLOCK_SIZE) + 1) +#define DW100_MIN_LUT_W (DIV_ROUND_UP(DW100_MIN_W, DW100_BLOCK_SIZE) + 1) +#define DW100_MAX_LUT_H (DIV_ROUND_UP(DW100_MAX_H, DW100_BLOCK_SIZE) + 1) +#define DW100_MIN_LUT_H (DIV_ROUND_UP(DW100_MIN_H, DW100_BLOCK_SIZE) + 1) +#define DW100_MAX_LUT_NELEMS (DW100_MAX_LUT_W * DW100_MAX_LUT_H) +#define DW100_MIN_LUT_NELEMS (DW100_MIN_LUT_W * DW100_MIN_LUT_H) + +/* + * 16 controls have been reserved for this driver for future extension, but + * let's limit the related driver allocation to the effective number of controls + * in use. + */ +#define DW100_MAX_CTRLS 1 +#define DW100_CTRL_DEWARPING_MAP 0 + +enum { + DW100_QUEUE_SRC = 0, + DW100_QUEUE_DST = 1, +}; + +enum { + DW100_FMT_CAPTURE = BIT(0), + DW100_FMT_OUTPUT = BIT(1), +}; + +struct dw100_device { + struct platform_device *pdev; + struct v4l2_m2m_dev *m2m_dev; + struct v4l2_device v4l2_dev; + struct video_device vfd; + struct media_device mdev; + /* Video device lock */ + struct mutex vfd_mutex; + void __iomem *mmio; + struct clk_bulk_data *clks; + int num_clks; + struct dentry *debugfs_root; +}; + +struct dw100_q_data { + struct v4l2_pix_format_mplane pix_fmt; + unsigned int sequence; + const struct dw100_fmt *fmt; + struct v4l2_rect crop; +}; + +struct dw100_ctx { + struct v4l2_fh fh; + struct dw100_device *dw_dev; + struct v4l2_ctrl_handler hdl; + struct v4l2_ctrl *ctrls[DW100_MAX_CTRLS]; + /* per context m2m queue lock */ + struct mutex vq_mutex; + + /* Look Up Table for pixel remapping */ + unsigned int *map; + dma_addr_t map_dma; + size_t map_size; + unsigned int map_width; + unsigned int map_height; + bool user_map_is_valid; + + /* Source and destination queue data */ + struct dw100_q_data q_data[2]; +}; + +static const struct v4l2_frmsize_stepwise dw100_frmsize_stepwise = { + .min_width = DW100_MIN_W, + .min_height = DW100_MIN_H, + .max_width = DW100_MAX_W, + .max_height = DW100_MAX_H, + .step_width = 1UL << DW100_ALIGN_W, + .step_height = 1UL << DW100_ALIGN_H, +}; + +static const struct dw100_fmt { + u32 fourcc; + u32 types; + u32 reg_format; + bool reg_swap_uv; +} formats[] = { + { + .fourcc = V4L2_PIX_FMT_NV16, + .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, + .reg_swap_uv = false, + }, { + .fourcc = V4L2_PIX_FMT_NV16M, + .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, + .reg_swap_uv = false, + }, { + .fourcc = V4L2_PIX_FMT_NV61, + .types = DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, + .reg_swap_uv = true, + }, { + .fourcc = V4L2_PIX_FMT_NV61M, + .types = DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_SP, + .reg_swap_uv = true, + }, { + .fourcc = V4L2_PIX_FMT_YUYV, + .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED, + .reg_swap_uv = false, + }, { + .fourcc = V4L2_PIX_FMT_UYVY, + .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED, + .reg_swap_uv = true, + }, { + .fourcc = V4L2_PIX_FMT_NV12, + .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, + .reg_swap_uv = false, + }, { + .fourcc = V4L2_PIX_FMT_NV12M, + .types = DW100_FMT_OUTPUT | DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, + .reg_swap_uv = false, + }, { + .fourcc = V4L2_PIX_FMT_NV21, + .types = DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, + .reg_swap_uv = true, + }, { + .fourcc = V4L2_PIX_FMT_NV21M, + .types = DW100_FMT_CAPTURE, + .reg_format = DW100_DEWARP_CTRL_FORMAT_YUV420_SP, + .reg_swap_uv = true, + }, +}; + +static inline int to_dw100_fmt_type(enum v4l2_buf_type type) +{ + if (V4L2_TYPE_IS_OUTPUT(type)) + return DW100_FMT_OUTPUT; + else + return DW100_FMT_CAPTURE; +} + +static const struct dw100_fmt *dw100_find_pixel_format(u32 pixel_format, + int fmt_type) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(formats); i++) { + const struct dw100_fmt *fmt = &formats[i]; + + if (fmt->fourcc == pixel_format && fmt->types & fmt_type) + return fmt; + } + + return NULL; +} + +static const struct dw100_fmt *dw100_find_format(struct v4l2_format *f) +{ + return dw100_find_pixel_format(f->fmt.pix_mp.pixelformat, + to_dw100_fmt_type(f->type)); +} + +static inline u32 dw100_read(struct dw100_device *dw_dev, u32 reg) +{ + return readl(dw_dev->mmio + reg); +} + +static inline void dw100_write(struct dw100_device *dw_dev, u32 reg, u32 val) +{ + writel(val, dw_dev->mmio + reg); +} + +static inline int dw100_dump_regs(struct seq_file *m) +{ + struct dw100_device *dw_dev = m->private; +#define __DECLARE_REG(x) { #x, x } + unsigned int i; + static const struct reg_desc { + const char * const name; + unsigned int addr; + } dw100_regs[] = { + __DECLARE_REG(DW100_DEWARP_ID), + __DECLARE_REG(DW100_DEWARP_CTRL), + __DECLARE_REG(DW100_MAP_LUT_ADDR), + __DECLARE_REG(DW100_MAP_LUT_SIZE), + __DECLARE_REG(DW100_MAP_LUT_ADDR2), + __DECLARE_REG(DW100_MAP_LUT_SIZE2), + __DECLARE_REG(DW100_SRC_IMG_Y_BASE), + __DECLARE_REG(DW100_SRC_IMG_UV_BASE), + __DECLARE_REG(DW100_SRC_IMG_SIZE), + __DECLARE_REG(DW100_SRC_IMG_STRIDE), + __DECLARE_REG(DW100_DST_IMG_Y_BASE), + __DECLARE_REG(DW100_DST_IMG_UV_BASE), + __DECLARE_REG(DW100_DST_IMG_SIZE), + __DECLARE_REG(DW100_DST_IMG_STRIDE), + __DECLARE_REG(DW100_DST_IMG_Y_SIZE1), + __DECLARE_REG(DW100_DST_IMG_UV_SIZE1), + __DECLARE_REG(DW100_SRC_IMG_Y_BASE2), + __DECLARE_REG(DW100_SRC_IMG_UV_BASE2), + __DECLARE_REG(DW100_SRC_IMG_SIZE2), + __DECLARE_REG(DW100_SRC_IMG_STRIDE2), + __DECLARE_REG(DW100_DST_IMG_Y_BASE2), + __DECLARE_REG(DW100_DST_IMG_UV_BASE2), + __DECLARE_REG(DW100_DST_IMG_SIZE2), + __DECLARE_REG(DW100_DST_IMG_STRIDE2), + __DECLARE_REG(DW100_DST_IMG_Y_SIZE2), + __DECLARE_REG(DW100_DST_IMG_UV_SIZE2), + __DECLARE_REG(DW100_SWAP_CONTROL), + __DECLARE_REG(DW100_VERTICAL_SPLIT_LINE), + __DECLARE_REG(DW100_HORIZON_SPLIT_LINE), + __DECLARE_REG(DW100_SCALE_FACTOR), + __DECLARE_REG(DW100_ROI_START), + __DECLARE_REG(DW100_BOUNDARY_PIXEL), + __DECLARE_REG(DW100_INTERRUPT_STATUS), + __DECLARE_REG(DW100_BUS_CTRL), + __DECLARE_REG(DW100_BUS_CTRL1), + __DECLARE_REG(DW100_BUS_TIME_OUT_CYCLE), + }; + + for (i = 0; i < ARRAY_SIZE(dw100_regs); i++) + seq_printf(m, "%s: %#x\n", dw100_regs[i].name, + dw100_read(dw_dev, dw100_regs[i].addr)); + + return 0; +} + +static inline struct dw100_ctx *dw100_file2ctx(struct file *file) +{ + return container_of(file->private_data, struct dw100_ctx, fh); +} + +static struct dw100_q_data *dw100_get_q_data(struct dw100_ctx *ctx, + enum v4l2_buf_type type) +{ + if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + return &ctx->q_data[DW100_QUEUE_SRC]; + else + return &ctx->q_data[DW100_QUEUE_DST]; +} + +static u32 dw100_get_n_vertices_from_length(u32 length) +{ + return DIV_ROUND_UP(length, DW100_BLOCK_SIZE) + 1; +} + +static u16 dw100_map_convert_to_uq12_4(u32 a) +{ + return (u16)((a & 0xfff) << 4); +} + +static u32 dw100_map_format_coordinates(u16 xq, u16 yq) +{ + return (u32)((yq << 16) | xq); +} + +static u32 *dw100_get_user_map(struct dw100_ctx *ctx) +{ + struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP]; + + if (!ctx->user_map_is_valid) + return NULL; + + return ctrl->p_cur.p_u32; +} + +/* + * Create the dewarp map from the V4L2 control. If the control hasn't been set + * by the application, generate an identity mapping. + * + * A 16 pixels cell size grid is mapped on the destination image. + * The last cells width/height might be lesser than 16 if the destination image + * width/height is not divisible by 16. This dewarping grid map specifies the + * source image pixel location (x, y) on each grid intersection point. + * Bilinear interpolation is used to compute inner cell points locations. + * + * The coordinates are saved in UQ12.4 fixed point format. + */ +static int dw100_create_mapping(struct dw100_ctx *ctx) +{ + u32 sw, sh, dw, dh, mw, mh, i, j; + u16 qx, qy, qdx, qdy, qsh, qsw; + bool is_user_map = false; + u32 *user_map, *map; + + sw = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.width; + dw = ctx->q_data[DW100_QUEUE_DST].pix_fmt.width; + sh = ctx->q_data[DW100_QUEUE_SRC].pix_fmt.height; + dh = ctx->q_data[DW100_QUEUE_DST].pix_fmt.height; + + mw = dw100_get_n_vertices_from_length(dw); + mh = dw100_get_n_vertices_from_length(dh); + + qsw = dw100_map_convert_to_uq12_4(sw); + qsh = dw100_map_convert_to_uq12_4(sh); + qdx = qsw / (mw - 1); + qdy = qsh / (mh - 1); + + if (ctx->map) + dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size, + ctx->map, ctx->map_dma); + + ctx->map_width = mw; + ctx->map_height = mh; + ctx->map_size = mh * mw * sizeof(u32); + + ctx->map = dma_alloc_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size, + &ctx->map_dma, GFP_KERNEL); + + if (!ctx->map) + return -ENOMEM; + + user_map = dw100_get_user_map(ctx); + if (user_map) { + is_user_map = true; + memcpy(ctx->map, user_map, ctx->map_size); + goto out; + } + + map = ctx->map; + for (i = 0, qy = 0; i < mh; i++, qy += qdy) { + if (qy > qsh) + qy = qsh; + for (j = 0, qx = 0; j < mw; j++, qx += qdx) { + if (qx > qsw) + qx = qsw; + *map++ = dw100_map_format_coordinates(qx, qy); + } + } + +out: + dev_dbg(&ctx->dw_dev->pdev->dev, + "%ux%u %s mapping created (d:%pad-c:%p) for stream %ux%u->%ux%u\n", + mw, mh, is_user_map ? "user" : "identity", + &ctx->map_dma, ctx->map, sw, sh, dw, dh); + + return 0; +} + +static void dw100_destroy_mapping(struct dw100_ctx *ctx) +{ + if (ctx->map) { + dma_free_coherent(&ctx->dw_dev->pdev->dev, ctx->map_size, + ctx->map, ctx->map_dma); + ctx->map = NULL; + } +} + +static int dw100_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct dw100_ctx *ctx = + container_of(ctrl->handler, struct dw100_ctx, hdl); + + switch (ctrl->id) { + case V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP: + ctx->user_map_is_valid = true; + break; + } + + return 0; +} + +static const struct v4l2_ctrl_ops dw100_ctrl_ops = { + .s_ctrl = dw100_s_ctrl, +}; + +static const struct v4l2_ctrl_config controls[] = { + [DW100_CTRL_DEWARPING_MAP] = { + .ops = &dw100_ctrl_ops, + .id = V4L2_CID_DW100_DEWARPING_16x16_VERTEX_MAP, + .name = "Look-Up Table", + .type = V4L2_CTRL_TYPE_U32, + .min = 0x00000000, + .max = 0xffffffff, + .step = 1, + .def = 0, + .dims = { DW100_MAX_LUT_W, DW100_MAX_LUT_H }, + }, +}; + +static int dw100_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], struct device *alloc_devs[]) +{ + struct dw100_ctx *ctx = vb2_get_drv_priv(vq); + const struct v4l2_pix_format_mplane *format; + unsigned int i; + + format = &dw100_get_q_data(ctx, vq->type)->pix_fmt; + + if (*nplanes) { + if (*nplanes != format->num_planes) + return -EINVAL; + + for (i = 0; i < *nplanes; ++i) { + if (sizes[i] < format->plane_fmt[i].sizeimage) + return -EINVAL; + } + + return 0; + } + + *nplanes = format->num_planes; + + for (i = 0; i < format->num_planes; ++i) + sizes[i] = format->plane_fmt[i].sizeimage; + + return 0; +} + +static int dw100_buf_prepare(struct vb2_buffer *vb) +{ + unsigned int i; + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + struct dw100_device *dw_dev = ctx->dw_dev; + const struct v4l2_pix_format_mplane *pix_fmt = + &dw100_get_q_data(ctx, vb->vb2_queue->type)->pix_fmt; + + if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { + if (vbuf->field != V4L2_FIELD_NONE) { + dev_dbg(&dw_dev->pdev->dev, "%x field isn't supported\n", + vbuf->field); + return -EINVAL; + } + } + + for (i = 0; i < pix_fmt->num_planes; i++) { + unsigned long size = pix_fmt->plane_fmt[i].sizeimage; + + if (vb2_plane_size(vb, i) < size) { + dev_dbg(&dw_dev->pdev->dev, + "User buffer too small (%lu < %lu)\n", + vb2_plane_size(vb, i), size); + return -EINVAL; + } + + vb2_set_plane_payload(vb, i, size); + } + + return 0; +} + +static void dw100_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct dw100_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + + v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); +} + +static int dw100_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct dw100_ctx *ctx = vb2_get_drv_priv(q); + struct dw100_q_data *q_data = dw100_get_q_data(ctx, q->type); + int ret; + + q_data->sequence = 0; + + ret = dw100_create_mapping(ctx); + if (ret) + return ret; + + return pm_runtime_resume_and_get(&ctx->dw_dev->pdev->dev); +} + +static void dw100_stop_streaming(struct vb2_queue *q) +{ + struct dw100_ctx *ctx = vb2_get_drv_priv(q); + struct vb2_v4l2_buffer *vbuf; + + for (;;) { + if (V4L2_TYPE_IS_OUTPUT(q->type)) + vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + else + vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + if (!vbuf) + break; + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); + } + + pm_runtime_put_sync(&ctx->dw_dev->pdev->dev); + + dw100_destroy_mapping(ctx); +} + +static const struct vb2_ops dw100_qops = { + .queue_setup = dw100_queue_setup, + .buf_prepare = dw100_buf_prepare, + .buf_queue = dw100_buf_queue, + .start_streaming = dw100_start_streaming, + .stop_streaming = dw100_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int dw100_m2m_queue_init(void *priv, struct vb2_queue *src_vq, + struct vb2_queue *dst_vq) +{ + struct dw100_ctx *ctx = priv; + int ret; + + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + src_vq->io_modes = VB2_MMAP | VB2_DMABUF; + src_vq->drv_priv = ctx; + src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); + src_vq->ops = &dw100_qops; + src_vq->mem_ops = &vb2_dma_contig_memops; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->lock = &ctx->vq_mutex; + src_vq->dev = ctx->dw_dev->v4l2_dev.dev; + + ret = vb2_queue_init(src_vq); + if (ret) + return ret; + + dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; + dst_vq->drv_priv = ctx; + dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); + dst_vq->ops = &dw100_qops; + dst_vq->mem_ops = &vb2_dma_contig_memops; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->lock = &ctx->vq_mutex; + dst_vq->dev = ctx->dw_dev->v4l2_dev.dev; + + return vb2_queue_init(dst_vq); +} + +static int dw100_open(struct file *file) +{ + struct dw100_device *dw_dev = video_drvdata(file); + struct dw100_ctx *ctx; + struct v4l2_ctrl_handler *hdl; + struct v4l2_pix_format_mplane *pix_fmt; + int ret, i; + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + mutex_init(&ctx->vq_mutex); + v4l2_fh_init(&ctx->fh, video_devdata(file)); + file->private_data = &ctx->fh; + ctx->dw_dev = dw_dev; + + hdl = &ctx->hdl; + v4l2_ctrl_handler_init(hdl, ARRAY_SIZE(controls)); + for (i = 0; i < ARRAY_SIZE(controls); i++) { + ctx->ctrls[i] = v4l2_ctrl_new_custom(hdl, &controls[i], NULL); + if (hdl->error) { + dev_err(&ctx->dw_dev->pdev->dev, + "Adding control (%d) failed\n", i); + ret = hdl->error; + goto err; + } + } + ctx->fh.ctrl_handler = hdl; + ctx->user_map_is_valid = false; + + ctx->q_data[DW100_QUEUE_SRC].fmt = &formats[0]; + + pix_fmt = &ctx->q_data[DW100_QUEUE_SRC].pix_fmt; + pix_fmt->field = V4L2_FIELD_NONE; + pix_fmt->colorspace = V4L2_COLORSPACE_REC709; + pix_fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix_fmt->colorspace); + pix_fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix_fmt->colorspace); + pix_fmt->quantization = + V4L2_MAP_QUANTIZATION_DEFAULT(false, pix_fmt->colorspace, + pix_fmt->ycbcr_enc); + + v4l2_fill_pixfmt_mp(pix_fmt, formats[0].fourcc, 640, 480); + + ctx->q_data[DW100_QUEUE_SRC].crop.top = 0; + ctx->q_data[DW100_QUEUE_SRC].crop.left = 0; + ctx->q_data[DW100_QUEUE_SRC].crop.width = 640; + ctx->q_data[DW100_QUEUE_SRC].crop.height = 480; + + ctx->q_data[DW100_QUEUE_DST] = ctx->q_data[DW100_QUEUE_SRC]; + + ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dw_dev->m2m_dev, + ctx, &dw100_m2m_queue_init); + + if (IS_ERR(ctx->fh.m2m_ctx)) { + ret = PTR_ERR(ctx->fh.m2m_ctx); + goto err; + } + + v4l2_fh_add(&ctx->fh); + + return 0; + +err: + v4l2_ctrl_handler_free(hdl); + v4l2_fh_exit(&ctx->fh); + mutex_destroy(&ctx->vq_mutex); + kfree(ctx); + + return ret; +} + +static int dw100_release(struct file *file) +{ + struct dw100_ctx *ctx = dw100_file2ctx(file); + + v4l2_fh_del(&ctx->fh); + v4l2_fh_exit(&ctx->fh); + v4l2_ctrl_handler_free(&ctx->hdl); + v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); + mutex_destroy(&ctx->vq_mutex); + kfree(ctx); + + return 0; +} + +static const struct v4l2_file_operations dw100_fops = { + .owner = THIS_MODULE, + .open = dw100_open, + .release = dw100_release, + .poll = v4l2_m2m_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = v4l2_m2m_fop_mmap, +}; + +static int dw100_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + strscpy(cap->driver, DRV_NAME, sizeof(cap->driver)); + strscpy(cap->card, "DW100 dewarper", sizeof(cap->card)); + + return 0; +} + +static int dw100_enum_fmt_vid(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + int i, num = 0; + + for (i = 0; i < ARRAY_SIZE(formats); i++) { + if (formats[i].types & to_dw100_fmt_type(f->type)) { + if (num == f->index) { + f->pixelformat = formats[i].fourcc; + return 0; + } + ++num; + } + } + + return -EINVAL; +} + +static int dw100_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) +{ + const struct dw100_fmt *fmt; + + if (fsize->index) + return -EINVAL; + + fmt = dw100_find_pixel_format(fsize->pixel_format, + DW100_FMT_OUTPUT | DW100_FMT_CAPTURE); + if (!fmt) + return -EINVAL; + + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; + fsize->stepwise = dw100_frmsize_stepwise; + + return 0; +} + +static int dw100_g_fmt_vid(struct file *file, void *priv, struct v4l2_format *f) +{ + struct dw100_ctx *ctx = dw100_file2ctx(file); + struct vb2_queue *vq; + struct dw100_q_data *q_data; + + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); + if (!vq) + return -EINVAL; + + q_data = dw100_get_q_data(ctx, f->type); + + f->fmt.pix_mp = q_data->pix_fmt; + + return 0; +} + +static int dw100_try_fmt(struct file *file, struct v4l2_format *f) +{ + struct dw100_ctx *ctx = dw100_file2ctx(file); + struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp; + const struct dw100_fmt *fmt; + + fmt = dw100_find_format(f); + if (!fmt) { + fmt = &formats[0]; + pix->pixelformat = fmt->fourcc; + } + + v4l2_apply_frmsize_constraints(&pix->width, &pix->height, + &dw100_frmsize_stepwise); + + v4l2_fill_pixfmt_mp(pix, fmt->fourcc, pix->width, pix->height); + + pix->field = V4L2_FIELD_NONE; + + if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + if (pix->colorspace == V4L2_COLORSPACE_DEFAULT) + pix->colorspace = V4L2_COLORSPACE_REC709; + if (pix->xfer_func == V4L2_XFER_FUNC_DEFAULT) + pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace); + if (pix->ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) + pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace); + if (pix->quantization == V4L2_QUANTIZATION_DEFAULT) + pix->quantization = + V4L2_MAP_QUANTIZATION_DEFAULT(false, + pix->colorspace, + pix->ycbcr_enc); + } else { + /* + * The DW100 can't perform colorspace conversion, the colorspace + * on the capture queue must be identical to the output queue. + */ + const struct dw100_q_data *q_data = + dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + + pix->colorspace = q_data->pix_fmt.colorspace; + pix->xfer_func = q_data->pix_fmt.xfer_func; + pix->ycbcr_enc = q_data->pix_fmt.ycbcr_enc; + pix->quantization = q_data->pix_fmt.quantization; + } + + return 0; +} + +static int dw100_s_fmt(struct dw100_ctx *ctx, struct v4l2_format *f) +{ + struct dw100_q_data *q_data; + struct vb2_queue *vq; + + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); + if (!vq) + return -EINVAL; + + q_data = dw100_get_q_data(ctx, f->type); + if (!q_data) + return -EINVAL; + + if (vb2_is_busy(vq)) { + dev_dbg(&ctx->dw_dev->pdev->dev, "%s queue busy\n", __func__); + return -EBUSY; + } + + q_data->fmt = dw100_find_format(f); + q_data->pix_fmt = f->fmt.pix_mp; + q_data->crop.top = 0; + q_data->crop.left = 0; + q_data->crop.width = f->fmt.pix_mp.width; + q_data->crop.height = f->fmt.pix_mp.height; + + /* Propagate buffers encoding */ + + if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + struct dw100_q_data *dst_q_data = + dw100_get_q_data(ctx, + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + + dst_q_data->pix_fmt.colorspace = q_data->pix_fmt.colorspace; + dst_q_data->pix_fmt.ycbcr_enc = q_data->pix_fmt.ycbcr_enc; + dst_q_data->pix_fmt.quantization = q_data->pix_fmt.quantization; + dst_q_data->pix_fmt.xfer_func = q_data->pix_fmt.xfer_func; + } + + dev_dbg(&ctx->dw_dev->pdev->dev, + "Setting format for type %u, wxh: %ux%u, fmt: %p4cc\n", + f->type, q_data->pix_fmt.width, q_data->pix_fmt.height, + &q_data->pix_fmt.pixelformat); + + if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + int ret; + u32 dims[V4L2_CTRL_MAX_DIMS] = {}; + struct v4l2_ctrl *ctrl = ctx->ctrls[DW100_CTRL_DEWARPING_MAP]; + + dims[0] = dw100_get_n_vertices_from_length(q_data->pix_fmt.width); + dims[1] = dw100_get_n_vertices_from_length(q_data->pix_fmt.height); + + v4l2_ctrl_lock(ctrl); + ctx->user_map_is_valid = false; + ret = __v4l2_ctrl_modify_dimensions(ctrl, dims); + v4l2_ctrl_unlock(ctrl); + + if (ret) { + dev_err(&ctx->dw_dev->pdev->dev, + "Modifying LUT dimensions failed with error %d\n", + ret); + return ret; + } + } + + return 0; +} + +static int dw100_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + return -EINVAL; + + return dw100_try_fmt(file, f); +} + +static int dw100_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct dw100_ctx *ctx = dw100_file2ctx(file); + int ret; + + ret = dw100_try_fmt_vid_cap(file, priv, f); + if (ret) + return ret; + + ret = dw100_s_fmt(ctx, f); + if (ret) + return ret; + + return 0; +} + +static int dw100_try_fmt_vid_out(struct file *file, void *priv, + struct v4l2_format *f) +{ + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + return -EINVAL; + + return dw100_try_fmt(file, f); +} + +static int dw100_s_fmt_vid_out(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct dw100_ctx *ctx = dw100_file2ctx(file); + int ret; + + ret = dw100_try_fmt_vid_out(file, priv, f); + if (ret) + return ret; + + ret = dw100_s_fmt(ctx, f); + if (ret) + return ret; + + return 0; +} + +static int dw100_g_selection(struct file *file, void *fh, + struct v4l2_selection *sel) +{ + struct dw100_ctx *ctx = dw100_file2ctx(file); + struct dw100_q_data *src_q_data; + + if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + + src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + + switch (sel->target) { + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + sel->r.top = 0; + sel->r.left = 0; + sel->r.width = src_q_data->pix_fmt.width; + sel->r.height = src_q_data->pix_fmt.height; + break; + case V4L2_SEL_TGT_CROP: + sel->r.top = src_q_data->crop.top; + sel->r.left = src_q_data->crop.left; + sel->r.width = src_q_data->crop.width; + sel->r.height = src_q_data->crop.height; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int dw100_s_selection(struct file *file, void *fh, + struct v4l2_selection *sel) +{ + struct dw100_ctx *ctx = dw100_file2ctx(file); + struct dw100_q_data *src_q_data; + u32 qscalex, qscaley, qscale; + int x, y, w, h; + unsigned int wframe, hframe; + + if (sel->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + + src_q_data = dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + + dev_dbg(&ctx->dw_dev->pdev->dev, + ">>> Buffer Type: %u Target: %u Rect: %ux%u@%d.%d\n", + sel->type, sel->target, + sel->r.width, sel->r.height, sel->r.left, sel->r.top); + + switch (sel->target) { + case V4L2_SEL_TGT_CROP: + wframe = src_q_data->pix_fmt.width; + hframe = src_q_data->pix_fmt.height; + + sel->r.top = clamp_t(int, sel->r.top, 0, hframe - DW100_MIN_H); + sel->r.left = clamp_t(int, sel->r.left, 0, wframe - DW100_MIN_W); + sel->r.height = + clamp(sel->r.height, DW100_MIN_H, hframe - sel->r.top); + sel->r.width = + clamp(sel->r.width, DW100_MIN_W, wframe - sel->r.left); + + /* UQ16.16 for float operations */ + qscalex = (sel->r.width << 16) / wframe; + qscaley = (sel->r.height << 16) / hframe; + y = sel->r.top; + x = sel->r.left; + if (qscalex == qscaley) { + qscale = qscalex; + } else { + switch (sel->flags) { + case 0: + qscale = (qscalex + qscaley) / 2; + break; + case V4L2_SEL_FLAG_GE: + qscale = max(qscaley, qscalex); + break; + case V4L2_SEL_FLAG_LE: + qscale = min(qscaley, qscalex); + break; + case V4L2_SEL_FLAG_LE | V4L2_SEL_FLAG_GE: + return -ERANGE; + default: + return -EINVAL; + } + } + + w = (u32)((((u64)wframe << 16) * qscale) >> 32); + h = (u32)((((u64)hframe << 16) * qscale) >> 32); + x = x + (sel->r.width - w) / 2; + y = y + (sel->r.height - h) / 2; + x = min(wframe - w, (unsigned int)max(0, x)); + y = min(hframe - h, (unsigned int)max(0, y)); + + sel->r.top = y; + sel->r.left = x; + sel->r.width = w; + sel->r.height = h; + + src_q_data->crop.top = sel->r.top; + src_q_data->crop.left = sel->r.left; + src_q_data->crop.width = sel->r.width; + src_q_data->crop.height = sel->r.height; + break; + + default: + return -EINVAL; + } + + dev_dbg(&ctx->dw_dev->pdev->dev, + "<<< Buffer Type: %u Target: %u Rect: %ux%u@%d.%d\n", + sel->type, sel->target, + sel->r.width, sel->r.height, sel->r.left, sel->r.top); + + return 0; +} + +static const struct v4l2_ioctl_ops dw100_ioctl_ops = { + .vidioc_querycap = dw100_querycap, + + .vidioc_enum_fmt_vid_cap = dw100_enum_fmt_vid, + .vidioc_enum_framesizes = dw100_enum_framesizes, + .vidioc_g_fmt_vid_cap_mplane = dw100_g_fmt_vid, + .vidioc_try_fmt_vid_cap_mplane = dw100_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap_mplane = dw100_s_fmt_vid_cap, + + .vidioc_enum_fmt_vid_out = dw100_enum_fmt_vid, + .vidioc_g_fmt_vid_out_mplane = dw100_g_fmt_vid, + .vidioc_try_fmt_vid_out_mplane = dw100_try_fmt_vid_out, + .vidioc_s_fmt_vid_out_mplane = dw100_s_fmt_vid_out, + + .vidioc_g_selection = dw100_g_selection, + .vidioc_s_selection = dw100_s_selection, + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, + + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static void dw100_job_finish(struct dw100_device *dw_dev, bool with_error) +{ + struct dw100_ctx *curr_ctx; + struct vb2_v4l2_buffer *src_vb, *dst_vb; + enum vb2_buffer_state buf_state; + + curr_ctx = v4l2_m2m_get_curr_priv(dw_dev->m2m_dev); + + if (!curr_ctx) { + dev_err(&dw_dev->pdev->dev, + "Instance released before the end of transaction\n"); + return; + } + + src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx); + dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx); + + if (likely(!with_error)) + buf_state = VB2_BUF_STATE_DONE; + else + buf_state = VB2_BUF_STATE_ERROR; + + v4l2_m2m_buf_done(src_vb, buf_state); + v4l2_m2m_buf_done(dst_vb, buf_state); + + dev_dbg(&dw_dev->pdev->dev, "Finishing transaction with%s error(s)\n", + with_error ? "" : "out"); + + v4l2_m2m_job_finish(dw_dev->m2m_dev, curr_ctx->fh.m2m_ctx); +} + +static void dw100_hw_reset(struct dw100_device *dw_dev) +{ + u32 val; + + val = dw100_read(dw_dev, DW100_DEWARP_CTRL); + val |= DW100_DEWARP_CTRL_ENABLE; + val |= DW100_DEWARP_CTRL_SOFT_RESET; + dw100_write(dw_dev, DW100_DEWARP_CTRL, val); + val &= ~DW100_DEWARP_CTRL_SOFT_RESET; + dw100_write(dw_dev, DW100_DEWARP_CTRL, val); +} + +static void _dw100_hw_set_master_bus_enable(struct dw100_device *dw_dev, + unsigned int enable) +{ + u32 val; + + dev_dbg(&dw_dev->pdev->dev, "%sable master bus\n", + enable ? "En" : "Dis"); + + val = dw100_read(dw_dev, DW100_BUS_CTRL); + + if (enable) + val |= DW100_BUS_CTRL_AXI_MASTER_ENABLE; + else + val &= ~DW100_BUS_CTRL_AXI_MASTER_ENABLE; + + dw100_write(dw_dev, DW100_BUS_CTRL, val); +} + +static void dw100_hw_master_bus_enable(struct dw100_device *dw_dev) +{ + _dw100_hw_set_master_bus_enable(dw_dev, 1); +} + +static void dw100_hw_master_bus_disable(struct dw100_device *dw_dev) +{ + _dw100_hw_set_master_bus_enable(dw_dev, 0); +} + +static void dw100_hw_dewarp_start(struct dw100_device *dw_dev) +{ + u32 val; + + val = dw100_read(dw_dev, DW100_DEWARP_CTRL); + + dev_dbg(&dw_dev->pdev->dev, "Starting Hardware CTRL:0x%08x\n", val); + dw100_write(dw_dev, DW100_DEWARP_CTRL, val | DW100_DEWARP_CTRL_START); + dw100_write(dw_dev, DW100_DEWARP_CTRL, val); +} + +static void dw100_hw_init_ctrl(struct dw100_device *dw_dev) +{ + u32 val; + /* + * Input format YUV422_SP + * Output format YUV422_SP + * No hardware handshake (SW) + * No automatic double src buffering (Single) + * No automatic double dst buffering (Single) + * No Black Line + * Prefetch image pixel traversal + */ + + val = DW100_DEWARP_CTRL_ENABLE + /* Valid only for auto prefetch mode*/ + | DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(32); + + /* + * Calculation mode required to support any scaling factor, + * but x4 slower than traversal mode. + * + * DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL + * DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION + * DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO + * + * TODO: Find heuristics requiring calculation mode + */ + val |= DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION; + + dw100_write(dw_dev, DW100_DEWARP_CTRL, val); +} + +static void dw100_hw_set_pixel_boundary(struct dw100_device *dw_dev) +{ + u32 val; + + val = DW100_BOUNDARY_PIXEL_V(128) + | DW100_BOUNDARY_PIXEL_U(128) + | DW100_BOUNDARY_PIXEL_Y(0); + + dw100_write(dw_dev, DW100_BOUNDARY_PIXEL, val); +} + +static void dw100_hw_set_scale(struct dw100_device *dw_dev, u8 scale) +{ + dev_dbg(&dw_dev->pdev->dev, "Setting scale factor to %u\n", scale); + + dw100_write(dw_dev, DW100_SCALE_FACTOR, scale); +} + +static void dw100_hw_set_roi(struct dw100_device *dw_dev, u32 x, u32 y) +{ + u32 val; + + dev_dbg(&dw_dev->pdev->dev, "Setting ROI region to %u.%u\n", x, y); + + val = DW100_ROI_START_X(x) | DW100_ROI_START_Y(y); + + dw100_write(dw_dev, DW100_ROI_START, val); +} + +static void dw100_hw_set_src_crop(struct dw100_device *dw_dev, + const struct dw100_q_data *src_q_data, + const struct dw100_q_data *dst_q_data) +{ + const struct v4l2_rect *rect = &src_q_data->crop; + u32 src_scale, qscale, left_scale, top_scale; + + /* HW Scale is UQ1.7 encoded */ + src_scale = (rect->width << 7) / src_q_data->pix_fmt.width; + dw100_hw_set_scale(dw_dev, src_scale); + + qscale = (dst_q_data->pix_fmt.width << 7) / src_q_data->pix_fmt.width; + + left_scale = ((rect->left << 7) * qscale) >> 14; + top_scale = ((rect->top << 7) * qscale) >> 14; + + dw100_hw_set_roi(dw_dev, left_scale, top_scale); +} + +static void dw100_hw_set_source(struct dw100_device *dw_dev, + const struct dw100_q_data *q_data, + struct vb2_buffer *buffer) +{ + u32 width, height, stride, fourcc, val; + const struct dw100_fmt *fmt = q_data->fmt; + dma_addr_t addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0); + dma_addr_t addr_uv; + + width = q_data->pix_fmt.width; + height = q_data->pix_fmt.height; + stride = q_data->pix_fmt.plane_fmt[0].bytesperline; + fourcc = q_data->fmt->fourcc; + + if (q_data->pix_fmt.num_planes == 2) + addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1); + else + addr_uv = addr_y + (stride * height); + + dev_dbg(&dw_dev->pdev->dev, + "Set HW source registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n", + width, height, stride, &fourcc, &addr_y); + + /* Pixel Format */ + val = dw100_read(dw_dev, DW100_DEWARP_CTRL); + + val &= ~DW100_DEWARP_CTRL_INPUT_FORMAT_MASK; + val |= DW100_DEWARP_CTRL_INPUT_FORMAT(fmt->reg_format); + + dw100_write(dw_dev, DW100_DEWARP_CTRL, val); + + /* Swap */ + val = dw100_read(dw_dev, DW100_SWAP_CONTROL); + + val &= ~DW100_SWAP_CONTROL_SRC_MASK; + /* + * Data swapping is performed only on Y plane for source image. + */ + if (fmt->reg_swap_uv && + fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED) + val |= DW100_SWAP_CONTROL_SRC(DW100_SWAP_CONTROL_Y + (DW100_SWAP_CONTROL_BYTE)); + + dw100_write(dw_dev, DW100_SWAP_CONTROL, val); + + /* Image resolution */ + dw100_write(dw_dev, DW100_SRC_IMG_SIZE, + DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height)); + + dw100_write(dw_dev, DW100_SRC_IMG_STRIDE, stride); + + /* Buffers */ + dw100_write(dw_dev, DW100_SRC_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y)); + dw100_write(dw_dev, DW100_SRC_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv)); +} + +static void dw100_hw_set_destination(struct dw100_device *dw_dev, + const struct dw100_q_data *q_data, + const struct dw100_fmt *ifmt, + struct vb2_buffer *buffer) +{ + u32 width, height, stride, fourcc, val, size_y, size_uv; + const struct dw100_fmt *fmt = q_data->fmt; + dma_addr_t addr_y, addr_uv; + + width = q_data->pix_fmt.width; + height = q_data->pix_fmt.height; + stride = q_data->pix_fmt.plane_fmt[0].bytesperline; + fourcc = fmt->fourcc; + + addr_y = vb2_dma_contig_plane_dma_addr(buffer, 0); + size_y = q_data->pix_fmt.plane_fmt[0].sizeimage; + + if (q_data->pix_fmt.num_planes == 2) { + addr_uv = vb2_dma_contig_plane_dma_addr(buffer, 1); + size_uv = q_data->pix_fmt.plane_fmt[1].sizeimage; + } else { + addr_uv = addr_y + ALIGN(stride * height, 16); + size_uv = size_y; + if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV420_SP) + size_uv /= 2; + } + + dev_dbg(&dw_dev->pdev->dev, + "Set HW source registers for %ux%u - stride %u, pixfmt: %p4cc, dma:%pad\n", + width, height, stride, &fourcc, &addr_y); + + /* Pixel Format */ + val = dw100_read(dw_dev, DW100_DEWARP_CTRL); + + val &= ~DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK; + val |= DW100_DEWARP_CTRL_OUTPUT_FORMAT(fmt->reg_format); + + dw100_write(dw_dev, DW100_DEWARP_CTRL, val); + + /* Swap */ + val = dw100_read(dw_dev, DW100_SWAP_CONTROL); + + val &= ~DW100_SWAP_CONTROL_DST_MASK; + + /* + * Avoid to swap twice + */ + if (fmt->reg_swap_uv ^ + (ifmt->reg_swap_uv && ifmt->reg_format != + DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED)) { + if (fmt->reg_format == DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED) + val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_Y + (DW100_SWAP_CONTROL_BYTE)); + else + val |= DW100_SWAP_CONTROL_DST(DW100_SWAP_CONTROL_UV + (DW100_SWAP_CONTROL_BYTE)); + } + + dw100_write(dw_dev, DW100_SWAP_CONTROL, val); + + /* Image resolution */ + dw100_write(dw_dev, DW100_DST_IMG_SIZE, + DW100_IMG_SIZE_WIDTH(width) | DW100_IMG_SIZE_HEIGHT(height)); + dw100_write(dw_dev, DW100_DST_IMG_STRIDE, stride); + dw100_write(dw_dev, DW100_DST_IMG_Y_BASE, DW100_IMG_Y_BASE(addr_y)); + dw100_write(dw_dev, DW100_DST_IMG_UV_BASE, DW100_IMG_UV_BASE(addr_uv)); + dw100_write(dw_dev, DW100_DST_IMG_Y_SIZE1, DW100_DST_IMG_Y_SIZE(size_y)); + dw100_write(dw_dev, DW100_DST_IMG_UV_SIZE1, + DW100_DST_IMG_UV_SIZE(size_uv)); +} + +static void dw100_hw_set_mapping(struct dw100_device *dw_dev, dma_addr_t addr, + u32 width, u32 height) +{ + dev_dbg(&dw_dev->pdev->dev, + "Set HW mapping registers for %ux%u addr:%pad", + width, height, &addr); + + dw100_write(dw_dev, DW100_MAP_LUT_ADDR, DW100_MAP_LUT_ADDR_ADDR(addr)); + dw100_write(dw_dev, DW100_MAP_LUT_SIZE, DW100_MAP_LUT_SIZE_WIDTH(width) + | DW100_MAP_LUT_SIZE_HEIGHT(height)); +} + +static void dw100_hw_clear_irq(struct dw100_device *dw_dev, unsigned int irq) +{ + dw100_write(dw_dev, DW100_INTERRUPT_STATUS, + DW100_INTERRUPT_STATUS_INT_CLEAR(irq)); +} + +static void dw100_hw_enable_irq(struct dw100_device *dw_dev) +{ + dw100_write(dw_dev, DW100_INTERRUPT_STATUS, + DW100_INTERRUPT_STATUS_INT_ENABLE_MASK); +} + +static void dw100_hw_disable_irq(struct dw100_device *dw_dev) +{ + dw100_write(dw_dev, DW100_INTERRUPT_STATUS, 0); +} + +static u32 dw_hw_get_pending_irqs(struct dw100_device *dw_dev) +{ + u32 val; + + val = dw100_read(dw_dev, DW100_INTERRUPT_STATUS); + + return DW100_INTERRUPT_STATUS_INT_STATUS(val); +} + +static irqreturn_t dw100_irq_handler(int irq, void *dev_id) +{ + struct dw100_device *dw_dev = dev_id; + u32 pending_irqs, err_irqs, frame_done_irq; + bool with_error = true; + + pending_irqs = dw_hw_get_pending_irqs(dw_dev); + frame_done_irq = pending_irqs & DW100_INTERRUPT_STATUS_INT_FRAME_DONE; + err_irqs = DW100_INTERRUPT_STATUS_INT_ERR_STATUS(pending_irqs); + + if (frame_done_irq) { + dev_dbg(&dw_dev->pdev->dev, "Frame done interrupt\n"); + with_error = false; + err_irqs &= ~DW100_INTERRUPT_STATUS_INT_ERR_STATUS + (DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE); + } + + if (err_irqs) + dev_err(&dw_dev->pdev->dev, "Interrupt error: %#x\n", err_irqs); + + dw100_hw_disable_irq(dw_dev); + dw100_hw_master_bus_disable(dw_dev); + dw100_hw_clear_irq(dw_dev, pending_irqs | + DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT); + + dw100_job_finish(dw_dev, with_error); + + return IRQ_HANDLED; +} + +static void dw100_start(struct dw100_ctx *ctx, struct vb2_v4l2_buffer *in_vb, + struct vb2_v4l2_buffer *out_vb) +{ + struct dw100_device *dw_dev = ctx->dw_dev; + + out_vb->sequence = + dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)->sequence++; + in_vb->sequence = + dw100_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)->sequence++; + + dev_dbg(&ctx->dw_dev->pdev->dev, + "Starting queues %p->%p, sequence %u->%u\n", + v4l2_m2m_get_vq(ctx->fh.m2m_ctx, + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE), + v4l2_m2m_get_vq(ctx->fh.m2m_ctx, + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE), + in_vb->sequence, out_vb->sequence); + + v4l2_m2m_buf_copy_metadata(in_vb, out_vb, true); + + /* Now, let's deal with hardware ... */ + dw100_hw_master_bus_disable(dw_dev); + dw100_hw_init_ctrl(dw_dev); + dw100_hw_set_pixel_boundary(dw_dev); + dw100_hw_set_src_crop(dw_dev, &ctx->q_data[DW100_QUEUE_SRC], + &ctx->q_data[DW100_QUEUE_DST]); + dw100_hw_set_source(dw_dev, &ctx->q_data[DW100_QUEUE_SRC], + &in_vb->vb2_buf); + dw100_hw_set_destination(dw_dev, &ctx->q_data[DW100_QUEUE_DST], + ctx->q_data[DW100_QUEUE_SRC].fmt, + &out_vb->vb2_buf); + dw100_hw_set_mapping(dw_dev, ctx->map_dma, + ctx->map_width, ctx->map_height); + dw100_hw_enable_irq(dw_dev); + dw100_hw_dewarp_start(dw_dev); + + /* Enable Bus */ + dw100_hw_master_bus_enable(dw_dev); +} + +static void dw100_device_run(void *priv) +{ + struct dw100_ctx *ctx = priv; + struct vb2_v4l2_buffer *src_buf, *dst_buf; + + src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + + dw100_start(ctx, src_buf, dst_buf); +} + +static const struct v4l2_m2m_ops dw100_m2m_ops = { + .device_run = dw100_device_run, +}; + +static struct video_device *dw100_init_video_device(struct dw100_device *dw_dev) +{ + struct video_device *vfd = &dw_dev->vfd; + + vfd->vfl_dir = VFL_DIR_M2M; + vfd->fops = &dw100_fops; + vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; + vfd->ioctl_ops = &dw100_ioctl_ops; + vfd->minor = -1; + vfd->release = video_device_release_empty; + vfd->v4l2_dev = &dw_dev->v4l2_dev; + vfd->lock = &dw_dev->vfd_mutex; + + strscpy(vfd->name, DRV_NAME, sizeof(vfd->name)); + mutex_init(vfd->lock); + video_set_drvdata(vfd, dw_dev); + + return vfd; +} + +static int dw100_dump_regs_show(struct seq_file *m, void *private) +{ + struct dw100_device *dw_dev = m->private; + int ret; + + ret = pm_runtime_resume_and_get(&dw_dev->pdev->dev); + if (ret < 0) + return ret; + + ret = dw100_dump_regs(m); + + pm_runtime_put_sync(&dw_dev->pdev->dev); + + return ret; +} +DEFINE_SHOW_ATTRIBUTE(dw100_dump_regs); + +static void dw100_debugfs_init(struct dw100_device *dw_dev) +{ + dw_dev->debugfs_root = + debugfs_create_dir(dev_name(&dw_dev->pdev->dev), NULL); + + debugfs_create_file("dump_regs", 0600, dw_dev->debugfs_root, dw_dev, + &dw100_dump_regs_fops); +} + +static void dw100_debugfs_exit(struct dw100_device *dw_dev) +{ + debugfs_remove_recursive(dw_dev->debugfs_root); +} + +static int dw100_probe(struct platform_device *pdev) +{ + struct dw100_device *dw_dev; + struct video_device *vfd; + struct resource *res; + int ret, irq; + + dw_dev = devm_kzalloc(&pdev->dev, sizeof(*dw_dev), GFP_KERNEL); + if (!dw_dev) + return -ENOMEM; + dw_dev->pdev = pdev; + + ret = devm_clk_bulk_get_all(&pdev->dev, &dw_dev->clks); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to get clocks: %d\n", ret); + return ret; + } + dw_dev->num_clks = ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dw_dev->mmio = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dw_dev->mmio)) + return PTR_ERR(dw_dev->mmio); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + platform_set_drvdata(pdev, dw_dev); + + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to resume the device: %d\n", ret); + goto err_pm; + } + + pm_runtime_put_sync(&pdev->dev); + + ret = devm_request_irq(&pdev->dev, irq, dw100_irq_handler, IRQF_ONESHOT, + dev_name(&pdev->dev), dw_dev); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); + return ret; + } + + ret = v4l2_device_register(&pdev->dev, &dw_dev->v4l2_dev); + if (ret) + goto err_pm; + + vfd = dw100_init_video_device(dw_dev); + + dw_dev->m2m_dev = v4l2_m2m_init(&dw100_m2m_ops); + if (IS_ERR(dw_dev->m2m_dev)) { + dev_err(&pdev->dev, "Failed to init mem2mem device\n"); + ret = PTR_ERR(dw_dev->m2m_dev); + goto err_v4l2; + } + + dw_dev->mdev.dev = &pdev->dev; + strscpy(dw_dev->mdev.model, "dw100", sizeof(dw_dev->mdev.model)); + media_device_init(&dw_dev->mdev); + dw_dev->v4l2_dev.mdev = &dw_dev->mdev; + + ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1); + if (ret) { + dev_err(&pdev->dev, "Failed to register video device\n"); + goto err_m2m; + } + + ret = v4l2_m2m_register_media_controller(dw_dev->m2m_dev, vfd, + MEDIA_ENT_F_PROC_VIDEO_SCALER); + if (ret) { + dev_err(&pdev->dev, "Failed to init mem2mem media controller\n"); + goto error_v4l2; + } + + ret = media_device_register(&dw_dev->mdev); + if (ret) { + dev_err(&pdev->dev, "Failed to register mem2mem media device\n"); + goto error_m2m_mc; + } + + dw100_debugfs_init(dw_dev); + + dev_info(&pdev->dev, + "dw100 v4l2 m2m registered as /dev/video%u\n", vfd->num); + + return 0; + +error_m2m_mc: + v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev); +error_v4l2: + video_unregister_device(vfd); +err_m2m: + v4l2_m2m_release(dw_dev->m2m_dev); +err_v4l2: + v4l2_device_unregister(&dw_dev->v4l2_dev); +err_pm: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int dw100_remove(struct platform_device *pdev) +{ + struct dw100_device *dw_dev = platform_get_drvdata(pdev); + + dw100_debugfs_exit(dw_dev); + + pm_runtime_disable(&pdev->dev); + + media_device_unregister(&dw_dev->mdev); + v4l2_m2m_unregister_media_controller(dw_dev->m2m_dev); + media_device_cleanup(&dw_dev->mdev); + + video_unregister_device(&dw_dev->vfd); + mutex_destroy(dw_dev->vfd.lock); + v4l2_m2m_release(dw_dev->m2m_dev); + v4l2_device_unregister(&dw_dev->v4l2_dev); + + return 0; +} + +static int __maybe_unused dw100_runtime_suspend(struct device *dev) +{ + struct dw100_device *dw_dev = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(dw_dev->num_clks, dw_dev->clks); + + return 0; +} + +static int __maybe_unused dw100_runtime_resume(struct device *dev) +{ + int ret; + struct dw100_device *dw_dev = dev_get_drvdata(dev); + + ret = clk_bulk_prepare_enable(dw_dev->num_clks, dw_dev->clks); + + if (ret) + return ret; + + dw100_hw_reset(dw_dev); + + return 0; +} + +static const struct dev_pm_ops dw100_pm = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(dw100_runtime_suspend, + dw100_runtime_resume, NULL) +}; + +static const struct of_device_id dw100_dt_ids[] = { + { .compatible = "nxp,imx8mp-dw100", .data = NULL }, + { }, +}; +MODULE_DEVICE_TABLE(of, dw100_dt_ids); + +static struct platform_driver dw100_driver = { + .probe = dw100_probe, + .remove = dw100_remove, + .driver = { + .name = DRV_NAME, + .pm = &dw100_pm, + .of_match_table = dw100_dt_ids, + }, +}; + +module_platform_driver(dw100_driver); + +MODULE_DESCRIPTION("DW100 Hardware dewarper"); +MODULE_AUTHOR("Xavier Roumegue "); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/nxp/dw100/dw100_regs.h b/drivers/media/platform/nxp/dw100/dw100_regs.h new file mode 100644 index 000000000000..e85dfeff9056 --- /dev/null +++ b/drivers/media/platform/nxp/dw100/dw100_regs.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * DW100 Hardware dewarper + * + * Copyright 2022 NXP + * Author: Xavier Roumegue (xavier.roumegue@oss.nxp.com) + */ + +#ifndef _DW100_REGS_H_ +#define _DW100_REGS_H_ + +/* AHB register offset */ +#define DW100_DEWARP_ID 0x00 +#define DW100_DEWARP_CTRL 0x04 +#define DW100_DEWARP_CTRL_ENABLE BIT(0) +#define DW100_DEWARP_CTRL_START BIT(1) +#define DW100_DEWARP_CTRL_SOFT_RESET BIT(2) +#define DW100_DEWARP_CTRL_FORMAT_YUV422_SP 0UL +#define DW100_DEWARP_CTRL_FORMAT_YUV422_PACKED 1UL +#define DW100_DEWARP_CTRL_FORMAT_YUV420_SP 2UL +#define DW100_DEWARP_CTRL_INPUT_FORMAT_MASK GENMASK(5, 4) +#define DW100_DEWARP_CTRL_INPUT_FORMAT(x) ((x) << 4) +#define DW100_DEWARP_CTRL_OUTPUT_FORMAT(x) ((x) << 6) +#define DW100_DEWARP_CTRL_OUTPUT_FORMAT_MASK GENMASK(7, 6) +#define DW100_DEWARP_CTRL_SRC_AUTO_SHADOW BIT(8) +#define DW100_DEWARP_CTRL_HW_HANDSHAKE BIT(9) +#define DW100_DEWARP_CTRL_DST_AUTO_SHADOW BIT(10) +#define DW100_DEWARP_CTRL_SPLIT_LINE BIT(11) +#define DW100_DEWARP_CTRL_PREFETCH_MODE_MASK GENMASK(17, 16) +#define DW100_DEWARP_CTRL_PREFETCH_MODE_TRAVERSAL (0UL << 16) +#define DW100_DEWARP_CTRL_PREFETCH_MODE_CALCULATION (1UL << 16) +#define DW100_DEWARP_CTRL_PREFETCH_MODE_AUTO (2UL << 16) +#define DW100_DEWARP_CTRL_PREFETCH_THRESHOLD_MASK GENMASK(24, 18) +#define DW100_DEWARP_CTRL_PREFETCH_THRESHOLD(x) ((x) << 18) + +#define DW100_MAP_LUT_ADDR 0x08 +#define DW100_MAP_LUT_ADDR_ADDR(addr) (((addr) >> 4) & GENMASK(29, 0)) +#define DW100_MAP_LUT_SIZE 0x0c +#define DW100_MAP_LUT_SIZE_WIDTH(w) (((w) & GENMASK(10, 0)) << 0) +#define DW100_MAP_LUT_SIZE_HEIGHT(h) (((h) & GENMASK(10, 0)) << 16) +#define DW100_SRC_IMG_Y_BASE 0x10 +#define DW100_IMG_Y_BASE(base) (((base) >> 4) & GENMASK(29, 0)) +#define DW100_SRC_IMG_UV_BASE 0x14 +#define DW100_IMG_UV_BASE(base) (((base) >> 4) & GENMASK(29, 0)) +#define DW100_SRC_IMG_SIZE 0x18 +#define DW100_IMG_SIZE_WIDTH(w) (((w) & GENMASK(12, 0)) << 0) +#define DW100_IMG_SIZE_HEIGHT(h) (((h) & GENMASK(12, 0)) << 16) + +#define DW100_SRC_IMG_STRIDE 0x1c +#define DW100_MAP_LUT_ADDR2 0x20 +#define DW100_MAP_LUT_SIZE2 0x24 +#define DW100_SRC_IMG_Y_BASE2 0x28 +#define DW100_SRC_IMG_UV_BASE2 0x2c +#define DW100_SRC_IMG_SIZE2 0x30 +#define DW100_SRC_IMG_STRIDE2 0x34 +#define DW100_DST_IMG_Y_BASE 0x38 +#define DW100_DST_IMG_UV_BASE 0x3c +#define DW100_DST_IMG_SIZE 0x40 +#define DW100_DST_IMG_STRIDE 0x44 +#define DW100_DST_IMG_Y_BASE2 0x48 +#define DW100_DST_IMG_UV_BASE2 0x4c +#define DW100_DST_IMG_SIZE2 0x50 +#define DW100_DST_IMG_STRIDE2 0x54 +#define DW100_SWAP_CONTROL 0x58 +#define DW100_SWAP_CONTROL_BYTE BIT(0) +#define DW100_SWAP_CONTROL_SHORT BIT(1) +#define DW100_SWAP_CONTROL_WORD BIT(2) +#define DW100_SWAP_CONTROL_LONG BIT(3) +#define DW100_SWAP_CONTROL_Y(x) (((x) & GENMASK(3, 0)) << 0) +#define DW100_SWAP_CONTROL_UV(x) (((x) & GENMASK(3, 0)) << 4) +#define DW100_SWAP_CONTROL_SRC(x) (((x) & GENMASK(7, 0)) << 0) +#define DW100_SWAP_CONTROL_DST(x) (((x) & GENMASK(7, 0)) << 8) +#define DW100_SWAP_CONTROL_SRC2(x) (((x) & GENMASK(7, 0)) << 16) +#define DW100_SWAP_CONTROL_DST2(x) (((x) & GENMASK(7, 0)) << 24) +#define DW100_SWAP_CONTROL_SRC_MASK GENMASK(7, 0) +#define DW100_SWAP_CONTROL_DST_MASK GENMASK(15, 8) +#define DW100_SWAP_CONTROL_SRC2_MASK GENMASK(23, 16) +#define DW100_SWAP_CONTROL_DST2_MASK GENMASK(31, 24) +#define DW100_VERTICAL_SPLIT_LINE 0x5c +#define DW100_HORIZON_SPLIT_LINE 0x60 +#define DW100_SCALE_FACTOR 0x64 +#define DW100_ROI_START 0x68 +#define DW100_ROI_START_X(x) (((x) & GENMASK(12, 0)) << 0) +#define DW100_ROI_START_Y(y) (((y) & GENMASK(12, 0)) << 16) +#define DW100_BOUNDARY_PIXEL 0x6c +#define DW100_BOUNDARY_PIXEL_V(v) (((v) & GENMASK(7, 0)) << 0) +#define DW100_BOUNDARY_PIXEL_U(u) (((u) & GENMASK(7, 0)) << 8) +#define DW100_BOUNDARY_PIXEL_Y(y) (((y) & GENMASK(7, 0)) << 16) + +#define DW100_INTERRUPT_STATUS 0x70 +#define DW100_INTERRUPT_STATUS_INT_FRAME_DONE BIT(0) +#define DW100_INTERRUPT_STATUS_INT_ERR_TIME_OUT BIT(1) +#define DW100_INTERRUPT_STATUS_INT_ERR_AXI_RESP BIT(2) +#define DW100_INTERRUPT_STATUS_INT_ERR_X BIT(3) +#define DW100_INTERRUPT_STATUS_INT_ERR_MB_FETCH BIT(4) +#define DW100_INTERRUPT_STATUS_INT_ERR_FRAME2 BIT(5) +#define DW100_INTERRUPT_STATUS_INT_ERR_FRAME3 BIT(6) +#define DW100_INTERRUPT_STATUS_INT_ERR_FRAME_DONE BIT(7) +#define DW100_INTERRUPT_STATUS_INT_ERR_STATUS(x) (((x) >> 1) & 0x7f) +#define DW100_INTERRUPT_STATUS_INT_STATUS(x) ((x) & 0xff) + +#define DW100_INTERRUPT_STATUS_INT_ENABLE_MASK GENMASK(15, 8) +#define DW100_INTERRUPT_STATUS_INT_ENABLE(x) (((x) & GENMASK(7, 0)) << 8) +#define DW100_INTERRUPT_STATUS_FRAME_BUSY BIT(16) +#define DW100_INTERRUPT_STATUS_INT_CLEAR(x) (((x) & GENMASK(7, 0)) << 24) +#define DW100_BUS_CTRL 0x74 +#define DW100_BUS_CTRL_AXI_MASTER_ENABLE BIT(31) +#define DW100_BUS_CTRL1 0x78 +#define DW100_BUS_TIME_OUT_CYCLE 0x7c +#define DW100_DST_IMG_Y_SIZE1 0x80 +#define DW100_DST_IMG_Y_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0)) +#define DW100_DST_IMG_UV_SIZE(sz) (((sz) >> 4) & GENMASK(29, 0)) +#define DW100_DST_IMG_UV_SIZE1 0x84 +#define DW100_DST_IMG_Y_SIZE2 0x88 +#define DW100_DST_IMG_UV_SIZE2 0x8c + +#endif /* _DW100_REGS_H_ */ From patchwork Fri Jul 15 13:53:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xavier Roumegue (OSS)" X-Patchwork-Id: 12919309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F107CCA481 for ; Fri, 15 Jul 2022 13:54:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234657AbiGONyG (ORCPT ); Fri, 15 Jul 2022 09:54:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234466AbiGONyD (ORCPT ); Fri, 15 Jul 2022 09:54:03 -0400 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80048.outbound.protection.outlook.com [40.107.8.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8F9F24F29; Fri, 15 Jul 2022 06:54:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=D0yEuq5WrV/zhCW1xu5LEnos27aK+uRZOyWyIEGhPL59Y74V3iMNlICeJ27+BiF0iSJ9R4vYDuIPgOJGpiXZw8cId26nWHQsUnBIkrBJBu/5A28Eh51LwgDPaFrCAymBIhmjnTHho1mU3s+/9A9BHVv2OIl+jsJA1tV5FmmSxgv1H9CF5SJW2ovpB7Q9y4ACVUtT130wXQft2Q/nLR2rOLtpclzte3wyvD2f5rAUbbqyyieMXF+bXPP15Kp9NXRkEqn0zPwqOYdEQL29fe+k11nSzK1EWkngGbLaYmYBRREuGjrnQIbNtmMjaFfhMctKf58C9680Rb/t29yIlpnB4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Ovrcl+8ua66la0c/B04Ms+KmUl+7NtWMDBTceDurdr4=; b=YkJPovxPOLUD9ktO29UdKwq97agHDnljPezJXLN+k9lhd3ZlMEhm/F950HY1J7/rwRM0spJbjV+LYKuXPxOEEOGtcp/X5U4ilARwg/EvlAPS8qj9B+Dg3zk6p3xlyO7SroZXiHOMcf41YjpGiV7HNCoRj+2zHobA3b1R/D5jS9/JBqSIxTNWFkAZnaCtZc/uZ2JY1pggCRYhXKH9NElg8NPZqFAMdba4yUnHGczCDnUhpv31Upo8WzskNy4+El+nuWhxeyQEnEJ52nS+BPrhm1MlJzxz1EYzIX5KPTKYpkUjJzxmX7J/FhOgqBTUhx7qY9TPiylLqGY+PFMdDIxS0w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ovrcl+8ua66la0c/B04Ms+KmUl+7NtWMDBTceDurdr4=; b=Y9nfuAzR7WUEtNbpuZv4Z8QKhE4RbR6x9LijKtwiUawhf9/5VQQ64RwZSVwVqo0x0cdv6YU2e5cbMcP7XDV3uIJh6cv41AhQzV9B0A1qIvx07khu8NBoGf70bJz0cuG5jkZM+3Oq6sqNGuPT+0cXOHozu7zUM0Y7723hw8eQakc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) by VE1PR04MB6640.eurprd04.prod.outlook.com (2603:10a6:803:122::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5438.12; Fri, 15 Jul 2022 13:53:51 +0000 Received: from PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f]) by PAXPR04MB8703.eurprd04.prod.outlook.com ([fe80::d51c:319c:bf4:199f%5]) with mapi id 15.20.5438.012; Fri, 15 Jul 2022 13:53:51 +0000 From: Xavier Roumegue To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, stanimir.varbanov@linaro.org, laurent.pinchart@ideasonboard.com, tomi.valkeinen@ideasonboard.com, robh+dt@kernel.org, nicolas@ndufresne.ca, alexander.stein@ew.tq-group.com, ezequiel@vanguardiasur.com.ar Cc: Xavier Roumegue , linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 6/6] media: MAINTAINERS: add entry for i.MX8MP DW100 v4l2 mem2mem driver Date: Fri, 15 Jul 2022 15:53:29 +0200 Message-Id: <20220715135329.975400-7-xavier.roumegue@oss.nxp.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> References: <20220715135329.975400-1-xavier.roumegue@oss.nxp.com> X-ClientProxiedBy: PR1P264CA0061.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:2ca::15) To PAXPR04MB8703.eurprd04.prod.outlook.com (2603:10a6:102:21e::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d0347d79-935b-4f27-3a3b-08da6669725f X-MS-TrafficTypeDiagnostic: VE1PR04MB6640:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k1tvcSQpmHyGHuIyHLUXE0YQRf33W1MjoqNvI9uOjSzJK1s6q5zLrT1rlEW3AFKKAw5DkYbd0KlDVpmyLcH+qW3wXPzaj/tw4uTEZb3Zrzy2h8SpPbwJJ6sWGLQSEqri5gQhfW4Pxo91HaJB9ptxYx8lERarDOVaHW/j+eBblsHtKNZjPycr7c52Fi7g0EH8wpKW/I0v2uqFFzhiMsNNKa4DwrSK2OeOFazFQFhAUCSnN5I8sKcaQIQx3YoWObSPr1C070DKouQyXPGeFCm93dVdL2D/wpwCJoqvqWK6zobw3n1JJgOZpgr4cqKX2VucVRxAQAMveyG6LteW6VbHqRv3zP/lZ71c4qdm4zvipyb59PrdDItctUaorvJPXxpvuqrw8tVGxf+L9tV64QUycNC/JBGb0HX1jdnC93trDNpIDMS3SpMO3NsPL+NhRUNv0C/BrE8qOloP6p+upzkIke/eKoCgFs7sK7pzOZXgOp+CYds62H9oo2/NwjB56z21N57hO+wUryU5ItZiuEaA1INBYQt3z82OZAwwlbZhh/Awv3fOtg6oGlFm8MgYDcBxJ41iRVLjxFXB4UmrNYmzix4Jq0FMqxVf/2cQAWMJsZe4BpENmJsBF5ApQiJr0kKh/XwXi7+HOCE361O12P1QisP0NWvp3SryO5uRU6y0MlzS4/zrsW3ddjAnnwbkWBlLWiQk85LjqacAWElpcjxiZmgXv7qMox05452Qf/DHy6cDuorvRCqf+aOjHw4bmYVh X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB8703.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(4636009)(366004)(346002)(376002)(396003)(136003)(39860400002)(6506007)(52116002)(6486002)(86362001)(478600001)(6512007)(66556008)(66476007)(6666004)(5660300002)(41300700001)(38100700002)(66946007)(316002)(2616005)(1076003)(8676002)(2906002)(8936002)(44832011)(7416002)(4326008)(186003)(4744005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jnQyDuce6PS2a8E6dO3qjDCEq67khMxvKrzQvBfQhiOtR3ywPMJApsBOX6HZRWDoaTemHtqxesRg7nPLmGo7aDcSS8+GWWfHbp1dkMMNpG8/7PZCVMmcw4LF2j3fFs3D0Sf71MKmRIqj4hc1qXZxwRXDTbJPBmV5yh63k8drS7G2+l7prTQDb/7LZv45QTdTZ2qbdy0BkAxwobhxFocaYvPVWOuA92Q6fPbPKmDDtj6+PTZeCId9nNTqXAPoQKU6k05tC9J+5+6/QbNgPgISuXKxx7m/CBH+52xg5rGiZhA7itXdGPwb75jplCsAZah3wXbb3Cqk+hWB4DhQk2P24XA23P/RTHfqFDQTncJ/0QOS/8QcA21LaN2FTcOsQPYp6s+X/QWpfaJTVIErPRHPiC3e/OinXQMjwTNPAYAV7/TPQxTI8PiIxXjRYYY4qalvNK7QUEQq5QHRRpR356cZaE01vtwx9e4YrvKCSBx0xL5LwFv+2+3IaBjHDimTXCwL+MbwpEeLeGQ2i6Em3NaeEhUAKtDS5lE3lxifEjEwm3DxyznHDATezEkJLSHch+SzcnxZ8//jQlpO90MIExiu8jhJIqnE2ratNYyrO3yGdGQDdk8vHVjRtAnVa5evucid3vJhq1rcqYbH/GC6M+yn7XEBNrpNY2O5BwKIScDOpAPGqoDtEhzl+4KUBMP8y15NAitVBsrgFQ7dNWyoZDz+9pkvAubhxxxQMgUzoialQvig4EMwMzKAA0GLgLP+62uV7oN3U45z0CqWbYH5qIU2hsVogCek9jGwRwI0Ryte6bEo6tLz/GcAD3ISvrTT8W1V1qsm3HGkmOYr02fPS9PKoDB4MfYPY0WQqVBpxECPOelSTa/mz4Xs9Ure9q9ULYWYhKlH/pzlHGANDIymUziuALfTOxpNWl5hb6/eO8UflYS3njTms08WaAdOVr2sJE8T7bbgRrzl8Pjy1FGyl69PX5+TFJ/fsv9J3FL8ht1EgaY+jGAEA9UjEAU6yAHjihkzKmi5skGE9i3iNoZWaapQUKFS7Km/7R74DO5pxZNTsHdK1BjMB8t5uICgmBNoghnSZVpZ7q01C1DvfGI8QujJAHu5Cs35nZD8S9wyLfZ2f5nUQtjYfIFTQLWgntknXUe267SmQnUjbru4TyoALWPlCYQFo+tJgmOg/apzq7J6Nv3I4RNHg7B6UGt/3QTw7qeBB7dH/cFSvdz0RAIT6eyT8QWMc804JrVkKn6gI8zJSvoa4Qu3tvewr5zOS7ORvVyqDv4PvNXaVoezpsCsEP9cVJW1uYRT76aFi66UpKRqFS6ICnlW5mbg48F714kVd8FDS+hoZtFOzko9B6LKilhIGviTkceW33lfAA3Svt6TsDLAbJdaxQ2Kr/XIltEstQZhlGrPmJzI/+Fo7ZGFeja77dpo2QpnXCVPWu2HBwR9rnp2qTa5aQdFAZCcWjoZa7HA9CKtEguOlviKglNGrS8TxMrSKrSe/UsHUFbKnkgFcRmvfdxmTdyvKADCp7/ap/aL2KvZMj4jACt3ZW3rky+DyE2GNXlxEw4r8j+8P9IuzV6HIrqrCK9ynOdAxMcSwgSLgjMEpjY/QNodUtNlo/qsqHJZO5YVl7Px7JRO5XCJPlocvotEjxNXUq/Ax71AlOkzorlAtpZGwy8T+C5kiiAP7Q== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0347d79-935b-4f27-3a3b-08da6669725f X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8703.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 13:53:50.5288 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nk82IXhBQBAEGZusXAOpRsoolY0apyz66QrVLey235MZRpjlswBm8MF5BcrwGz9I6YWyZWpM0+30ifqSPcsMpg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6640 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add myself as maintainer of the dw100 driver which offers hardware accelerated dewarping operations through a v4l2 mem2mem interface. Signed-off-by: Xavier Roumegue Reviewed-by: Laurent Pinchart --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1fc9ead83d2a..a2e1174bc0be 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14355,6 +14355,15 @@ S: Supported F: Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml F: drivers/nfc/nxp-nci +NXP i.MX 8MP DW100 V4L2 DRIVER +M: Xavier Roumegue +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/nxp,dw100.yaml +F: Documentation/userspace-api/media/drivers/dw100.rst +F: drivers/media/platform/nxp/dw100/ +F: include/uapi/linux/dw100.h + NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER M: Mirela Rabulea R: NXP Linux Team