From patchwork Mon Jul 18 21:30:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12921798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74CF8C433EF for ; Mon, 18 Jul 2022 21:37:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234484AbiGRVhL (ORCPT ); Mon, 18 Jul 2022 17:37:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232009AbiGRVhL (ORCPT ); Mon, 18 Jul 2022 17:37:11 -0400 Received: from proxmox1.postmarketos.org (proxmox1.postmarketos.org [IPv6:2a01:4f8:a0:821d::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D0E9C32476; Mon, 18 Jul 2022 14:37:07 -0700 (PDT) Received: from localhost.localdomain (unknown [81.178.197.238]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by proxmox1.postmarketos.org (Postfix) with ESMTPSA id 585601401E0; Mon, 18 Jul 2022 21:31:07 +0000 (UTC) From: Caleb Connolly To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter , Sumit Semwal , Caleb Connolly , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 1/4] Documentation: dt-bindings: arm: qcom: add google,blueline Date: Mon, 18 Jul 2022 22:30:48 +0100 Message-Id: <20220718213051.1475108-2-caleb@connolly.tech> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220718213051.1475108-1-caleb@connolly.tech> References: <20220718213051.1475108-1-caleb@connolly.tech> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the bindings for the Pixel 3 Based on https://lore.kernel.org/all/20220521164550.91115-7-krzysztof.kozlowski@linaro.org/ Signed-off-by: Caleb Connolly Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b727467e86c6..b3e1004673c7 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -320,6 +320,7 @@ properties: - items: - enum: + - google,blueline - lenovo,yoga-c630 - oneplus,enchilada - oneplus,fajita From patchwork Mon Jul 18 21:30:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12921801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE139CCA490 for ; Mon, 18 Jul 2022 21:37:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236125AbiGRVhe (ORCPT ); Mon, 18 Jul 2022 17:37:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235361AbiGRVhM (ORCPT ); Mon, 18 Jul 2022 17:37:12 -0400 X-Greylist: delayed 358 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 18 Jul 2022 14:37:07 PDT Received: from proxmox1.postmarketos.org (proxmox1.postmarketos.org [213.239.216.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D0BC22E9C3; Mon, 18 Jul 2022 14:37:07 -0700 (PDT) Received: from localhost.localdomain (unknown [81.178.197.238]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by proxmox1.postmarketos.org (Postfix) with ESMTPSA id 9C4471401E4; Mon, 18 Jul 2022 21:31:08 +0000 (UTC) From: Caleb Connolly To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter , Sumit Semwal , Caleb Connolly , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Cc: Amit Pundir , Vinod Koul Subject: [PATCH 2/4] arm64: dts: qcom: add sdm845-google-blueline (Pixel 3) Date: Mon, 18 Jul 2022 22:30:49 +0100 Message-Id: <20220718213051.1475108-3-caleb@connolly.tech> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220718213051.1475108-1-caleb@connolly.tech> References: <20220718213051.1475108-1-caleb@connolly.tech> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Amit Pundir This adds an initial dts for the Blueline (Pixel 3). Supported functionality includes display, Debug UART, UFS, USB-C (peripheral), WiFi, Bluetooth and modem. Bootloader compatible board and msm IDs are needed for the kernel to boot with Pixel3 bootloader, so those are added. GPIOs 0 through 3 and 81 through 84 are configured to not be accessible from the application CPUs, so we mark them as reserved to allow the Pixel 3 to boot. The reserved-memory locations where obtained from downstream using kernel logs: https://gist.github.com/calebccff/090d10bfac3cb9e9bd98dda30b054c96 The rmtfs region is allocated with UIO, making it technically "dynamic". It's address and size can be read from sysfs: blueline:/ # cat /sys/class/uio/uio0/name rmtfs at /sys/class/uio/uio0/maps/map0/addr 0x00000000f2701000 blueline:/ # cat /sys/class/uio/uio0/maps/map0/size 0x0000000000200000 Like the OnePlus 6, it needs 1kB reserved on either side of the rmtfs memory to workaround some XPU bug which would otherwise cause erroneous XPU violations when accessing the rmtfs_mem region. For wifi, the pixel 3 reports a board-id of 0xFF, and downstream only includes a single bdwlan file. The qcom,ath10k-calibration-variant property is set to ensure that the correct calibration data is used. Signed-off-by: Bjorn Andersson [AmitP: Cherry-picked and refactored from Bjorn's db845c dts ("arm64: dts: qcom: Add Dragonboard 845c") https://lkml.org/lkml/2019/6/6/7] Signed-off-by: Amit Pundir [sumits: merged commits to add board and msm ids, gpio range reservation, ufs device-reset gpio and adaptation to v5.5+ changes] Signed-off-by: Sumit Semwal [vinod: Add display nodes] Signed-off-by: Vinod Koul [caleb: remove db845c bits, cleanup, add reserved-memory for modem/wifi] Signed-off-by: Caleb Connolly --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sdm845-google-blueline.dts | 652 ++++++++++++++++++ 2 files changed, 653 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2f8aec2cc6db..c151e17e6eb7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts new file mode 100644 index 000000000000..dec979ad9209 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts @@ -0,0 +1,652 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include +#include +#include +#include + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &rmtfs_mem; + +/ { + model = "Google Pixel 3"; + compatible = "google,blueline", "qcom,sdm845"; + qcom,board-id = <0x00021505 0>; + qcom,msm-id = <321 0x20001>; + + aliases { + serial0 = &uart9; + serial1 = &uart6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + volume-keys { + compatible = "gpio-keys"; + label = "Volume keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&volume_up_gpio>; + + vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mpss_region: memory@8e000000 { + reg = <0 0x8e000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@97800000 { + reg = <0 0x97800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp-mem@97D00000 { + reg = <0 0x97D00000 0 0x800000>; + no-map; + }; + + mba_region: mba@98500000 { + reg = <0 0x98500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@98700000 { + reg = <0 0x98700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@99B00000 { + reg = <0 0x99B00000 0 0x100000>; + no-map; + }; + + /* rmtfs lower guard */ + memory@f2700000 { + reg = <0 0xf2700000 0 0x1000>; + no-map; + }; + + rmtfs_mem: memory@f2701000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf2701000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + /* rmtfs upper guard */ + memory@f2901000 { + reg = <0 0xf2901000 0 0x1000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: vreg-s4a-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pas { + status = "okay"; + + firmware-name = "qcom/sdm845/pixel3/adsp.mbn"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdda_mipi_dsi0_pll: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-boot-on; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3300000>; + qcom,initial-mode = ; + /* + * The touchscreen needs this to be 3.3v, which is apparently + * quite close to the hardware limit for this LDO (3.312v) + * It must be kept in high power mode to prevent TS brownouts + */ + regulator-allowed-modes = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = ; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_mipi_dsi0_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-boot-on; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&cdsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/pixel3/cdsp.mbn"; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&lg_sw43408_in_0>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel@0 { + compatible = "lg,sw43408"; + reg = <0>; + + vddi-supply = <&vreg_l14a_1p88>; + vpnl-supply = <&vreg_l28a_3p0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lg_sw43408_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&lg_sw43408_in_0>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + +&gcc { + protected-clocks = , + , + ; +}; + +&gmu { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/pixel3/a630_zap.mbn"; + }; +}; + +&ipa { + status = "okay"; + + firmware-name = "qcom/sdm845/pixel3/ipa_fws.mbn"; +}; + +&mss_pil { + status = "okay"; + firmware-name = "qcom/sdm845/pixel3/mba.mbn", "qcom/sdm845/pixel3/modem.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&pm8998_gpio { + volume_up_gpio: vol-up-active { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <0>; + }; + + panel_pmgpio_pins: panel-pmgpio-active { + pins = "gpio2", "gpio5"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; +}; + +&pm8998_pon { + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qup_uart6_default { + pinmux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + cts { + pins = "gpio45"; + bias-disable; + }; + + rts-tx { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio48"; + bias-pull-up; + }; +}; + +&qup_uart9_default { + pinconf-tx { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + panel_te_pin: panel-te { + mux { + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + panel_reset_pins: panel-active { + mux { + pins = "gpio6", "gpio52"; + function = "gpio"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + panel_suspend: panel-suspend { + mux { + pins = "gpio6", "gpio52"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + touchscreen_reset: ts-reset { + mux { + pins = "gpio99"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + //output-high; + }; + }; + + touchscreen_pins: ts-pins { + mux { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + touchscreen_i2c_pins: qup-i2c2-gpio { + pins = "gpio27", "gpio28"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&uart9 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <800000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; +}; + +&venus { + status = "okay"; + firmware-name = "qcom/sdm845/oneplus6/venus.mbn"; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; + qcom,ath10k-calibration-variant = "google_blueline"; +}; From patchwork Mon Jul 18 21:30:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12921799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF887CCA485 for ; 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Mon, 18 Jul 2022 21:31:10 +0000 (UTC) From: Caleb Connolly To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter , Sumit Semwal , Caleb Connolly , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Cc: Vinod Koul Subject: [PATCH 3/4] dt-bindings: panel: Add LG SW43408 MIPI-DSI panel Date: Mon, 18 Jul 2022 22:30:50 +0100 Message-Id: <20220718213051.1475108-4-caleb@connolly.tech> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220718213051.1475108-1-caleb@connolly.tech> References: <20220718213051.1475108-1-caleb@connolly.tech> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sumit Semwal LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel. Signed-off-by: Vinod Koul Signed-off-by: Sumit Semwal [caleb: convert to yaml] Signed-off-by: Caleb Connolly --- .../bindings/display/panel/lg,43408.yaml | 41 +++++++++++++++++++ .../display/panel/panel-simple-dsi.yaml | 2 + 2 files changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/lg,43408.yaml diff --git a/Documentation/devicetree/bindings/display/panel/lg,43408.yaml b/Documentation/devicetree/bindings/display/panel/lg,43408.yaml new file mode 100644 index 000000000000..0529a3aa2692 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/lg,43408.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LG SW43408 1080x2160 DSI panel + +maintainers: + - Caleb Connolly + +description: | + This panel is used on the Pixel 3, it is a 60hz OLED panel which + required DSC (Display Stream Compression) and has rounded corners. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: lg,sw43408 + + vddi-supply: true + vpnl-supply: true + reset-gpios: true + + backlight: false + power-supply: false + +additionalProperties: false + +required: + - compatible + - data-mapping + - width-mm + - height-mm + - panel-timing + - port + +... diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml index 2c00813f5d20..4498078cb1ee 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml @@ -45,6 +45,8 @@ properties: - lg,acx467akm-7 # LG Corporation 7" WXGA TFT LCD panel - lg,ld070wx3-sl01 + # LG Corporation sw43408 1080x2160 OLED + - lg,sw43408 # One Stop Displays OSD101T2587-53TS 10.1" 1920x1200 panel - osddisplays,osd101t2587-53ts # Panasonic 10" WUXGA TFT LCD panel From patchwork Mon Jul 18 21:30:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 12921802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64B5ACCA494 for ; Mon, 18 Jul 2022 21:37:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233257AbiGRVhf (ORCPT ); Mon, 18 Jul 2022 17:37:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235303AbiGRVhL (ORCPT ); Mon, 18 Jul 2022 17:37:11 -0400 X-Greylist: delayed 359 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 18 Jul 2022 14:37:08 PDT Received: from proxmox1.postmarketos.org (proxmox1.postmarketos.org [213.239.216.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E262F326CE; Mon, 18 Jul 2022 14:37:07 -0700 (PDT) Received: from localhost.localdomain (unknown [81.178.197.238]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by proxmox1.postmarketos.org (Postfix) with ESMTPSA id 47E341401E9; Mon, 18 Jul 2022 21:31:11 +0000 (UTC) From: Caleb Connolly To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter , Sumit Semwal , Caleb Connolly , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Cc: Vinod Koul Subject: [PATCH 4/4] drm: panel: Add lg sw43408 panel driver Date: Mon, 18 Jul 2022 22:30:51 +0100 Message-Id: <20220718213051.1475108-5-caleb@connolly.tech> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220718213051.1475108-1-caleb@connolly.tech> References: <20220718213051.1475108-1-caleb@connolly.tech> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sumit Semwal LG SW43408 is 1080x2160, 4-lane MIPI-DSI panel, used in some Pixel3 phones. Whatever init sequence we have for this panel isn't capable of initialising it completely, toggling the reset gpio ever causes the panel to die. Until this is resolved we avoid resetting the panel. The disable/unprepare functions only put the panel to sleep mode and disable the backlight. Signed-off-by: Sumit Semwal [vinod: Add DSC support] Signed-off-by: Vinod Koul [caleb: cleanup and support turning off the panel] Signed-off-by: Caleb Connolly --- MAINTAINERS | 8 + drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-lg-sw43408.c | 586 +++++++++++++++++++++++ 4 files changed, 606 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-lg-sw43408.c diff --git a/MAINTAINERS b/MAINTAINERS index f679152bdbad..8a2b954ad140 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6376,6 +6376,14 @@ S: Orphan / Obsolete F: drivers/gpu/drm/i810/ F: include/uapi/drm/i810_drm.h +DRM DRIVER FOR LG SW43408 PANELS +M: Sumit Semwal +M: Caleb Connolly +S: Maintained +T: git git://anongit.freedesktop.org/drm/drm-misc +F: Documentation/devicetree/bindings/display/panel/lg,sw43408-panel.txt +F: drivers/gpu/drm/panel/panel-lg-sw43408.c + DRM DRIVER FOR LVDS PANELS M: Laurent Pinchart L: dri-devel@lists.freedesktop.org diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 38799effd00a..706b112794b9 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -256,6 +256,17 @@ config DRM_PANEL_LEADTEK_LTK500HD1829 24 bit RGB per pixel. It provides a MIPI DSI interface to the host and has a built-in LED backlight. +config DRM_PANEL_LG_SW43408 + tristate "LG SW43408 panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for LG sw43408 panel. + The panel has a 1080x2160 resolution and uses + 24 bit RGB per pixel. It provides a MIPI DSI interface to + the host and has a built-in LED backlight. + config DRM_PANEL_SAMSUNG_LD9040 tristate "Samsung LD9040 RGB/SPI panel" depends on OF && SPI diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 42a7ab54234b..ba26a69b74e7 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o +obj-$(CONFIG_DRM_PANEL_LG_SW43408) += panel-lg-sw43408.o obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o diff --git a/drivers/gpu/drm/panel/panel-lg-sw43408.c b/drivers/gpu/drm/panel/panel-lg-sw43408.c new file mode 100644 index 000000000000..c7b8ec7b970d --- /dev/null +++ b/drivers/gpu/drm/panel/panel-lg-sw43408.c @@ -0,0 +1,586 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Linaro Ltd + * Author: Sumit Semwal + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include