From patchwork Tue Jul 19 08:08:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 12922233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EF61C43334 for ; Tue, 19 Jul 2022 08:09:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 190B611A1DD; Tue, 19 Jul 2022 08:09:12 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by gabe.freedesktop.org (Postfix) with ESMTPS id 05B9F11A1C7 for ; Tue, 19 Jul 2022 08:09:10 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 26J88m7Q051575; Tue, 19 Jul 2022 03:08:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1658218128; bh=mu9BFM9rYVtQQzUO3YjwGa6tpEwrofIGftk9mV+ERTk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bE5dUTqaFXErr/Aqu4CMp9s9loNgrvJwhJljixEcKEWtD50PpRNuAQ4FHnFySn22A ieSjTB0knhKN/mH+sb333Jnkxxj4f1yrnZxu/xy1rojwPvrWPKIWNh/3XIlmSjRNEV EqoOsnqptn+WDOZApbJ/dg+AVR6THAaQeShTNibU= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 26J88mJ9022582 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Jul 2022 03:08:48 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Jul 2022 03:08:48 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Jul 2022 03:08:47 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 26J88lJE011171; Tue, 19 Jul 2022 03:08:47 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski Subject: [PATCH 1/8] dt-bindings: display: ti, am65x-dss: Add port properties for DSS Date: Tue, 19 Jul 2022 13:38:38 +0530 Message-ID: <20220719080845.22122-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220719080845.22122-1-a-bhatia1@ti.com> References: <20220719080845.22122-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree List , Vignesh Raghavendra , Devarsh Thakkar , Linux Kernel List , DRI Development List , Darren Etheridge , Rahul T R , Krunal Bhargav Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add "ti,oldi-mode" property to indicate the tidss driver the OLDI output mode. The 2 OLDI TXes on am625-dss allow a 3 different types of panel connections with the board. 1. Single Link / Single Mode on OLDI TX 0 OR 1. 2. Single Link / Duplicate Mode on OLDI TX 0 and 1. 3. Dual Link / Single Mode on OLDI TX 0 and 1. Add "ti,rgb565-to-888" property to override 16bit output from a videoport for a bridge that only accepts 24bit RGB888 DPI input. On some boards the HDMI bridge takes a 24bit DPI input, but only 16 data pins are actually enabled from the SoC. This new property forces the output to be RGB565 on a specific video port if the bridge requests a 24bit RGB color space. This assumes that the video port is connected like so: SoC : Bridge R0 -> R3 R1 -> R4 R2 -> R5 R3 -> R6 R4 -> R7 G0 -> G2 G1 -> G3 G2 -> G4 G3 -> G5 G4 -> G6 G5 -> G7 B0 -> B3 B1 -> B4 B2 -> B5 B3 -> B6 B4 -> B7 On the bridge side R0->R2, G0->G1, B0->B2 would be tied to ground. The bridge sees 24bits of data, but the lsb's are always zero. Signed-off-by: Aradhya Bhatia --- .../bindings/display/ti/ti,am65x-dss.yaml | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 6bbce921479d..11d9b3821409 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -80,15 +80,35 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: The DSS OLDI output port node form video port 1 + properties: + ti,oldi-mode: + description: TI specific property to indicate the mode the OLDI TXes + and the display panel are connected in. + 0 -> OLDI TXes OFF (driver default for am625-dss) + 1 -> Single link, Single Mode (OLDI0) (driver default for am65x-dss) + 2 -> Single link, Single Mode (OLDI1) + 3 -> Single link, Duplicate Mode + 4 -> Dual link (Only Single Mode) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4] + port@1: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: The DSS DPI output port node from video port 2 + properties: + ti,rgb565-to-888: + description: + property to override DPI output to 16bit for 24bit bridge + type: boolean + ti,am65x-oldi-io-ctrl: $ref: "/schemas/types.yaml#/definitions/phandle" description: @@ -144,6 +164,7 @@ examples: #size-cells = <0>; port@0 { reg = <0>; + ti,oldi-mode = <1>; oldi_out0: endpoint { remote-endpoint = <&lcd_in0>; }; From patchwork Tue Jul 19 08:08:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 12922232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91E74C43334 for ; Tue, 19 Jul 2022 08:09:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9842911A1C8; Tue, 19 Jul 2022 08:09:11 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by gabe.freedesktop.org (Postfix) with ESMTPS id 06F3011A1C8 for ; Tue, 19 Jul 2022 08:09:10 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 26J88nMf051584; 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Tue, 19 Jul 2022 03:08:49 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 26J88m6O121325; Tue, 19 Jul 2022 03:08:49 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski Subject: [PATCH 2/8] dt-bindings: display: ti, am65x-dss: Add IO CTRL property for AM625 OLDI Date: Tue, 19 Jul 2022 13:38:39 +0530 Message-ID: <20220719080845.22122-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220719080845.22122-1-a-bhatia1@ti.com> References: <20220719080845.22122-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree List , Vignesh Raghavendra , Devarsh Thakkar , Linux Kernel List , DRI Development List , Darren Etheridge , Rahul T R , Krunal Bhargav Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add am625-io-ctrl dt property to provide access to the control MMR registers for the OLDI TXes. These registers are used to control the power input to the OLDI TXes as well as to configure them in the Loopback test mode. The MMR IO controller device has been updated since the AM65x SoC and hence a newer property is needed to describe the one in AM625 SoC. Signed-off-by: Aradhya Bhatia --- .../bindings/display/ti/ti,am65x-dss.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 11d9b3821409..672765ad1f30 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -118,12 +118,33 @@ properties: and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI interface to work. + ti,am625-oldi-io-ctrl: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: + phandle to syscon device node mapping OLDI IO_CTRL registers, for + AM625 SoC. The mapped range should point to OLDI0_DAT0_IO_CTRL, + and map the registers up till OLDI_LB_CTRL. This property allows + the driver to control the power delivery to the OLDI TXes and + their loopback control as well. + max-memory-bandwidth: $ref: /schemas/types.yaml#/definitions/uint32 description: Input memory (from main memory to dispc) bandwidth limit in bytes per second +if: + properties: + compatible: + contains: + const: ti,am65x-dss +then: + properties: + ti,am625-oldi-io-ctrl: false +else: + properties: + ti,am65x-oldi-io-ctrl: false + required: - compatible - reg From patchwork Tue Jul 19 08:08:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 12922234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47901C43334 for ; Tue, 19 Jul 2022 08:09:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE86811A1E7; Tue, 19 Jul 2022 08:09:23 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by gabe.freedesktop.org (Postfix) with ESMTPS id B200911A1E9 for ; Tue, 19 Jul 2022 08:09:16 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 26J88pDS051052; Tue, 19 Jul 2022 03:08:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1658218131; bh=YCb88AcpzpvVessHArv3TeJJ9EKUR80VGhAnkSZpiNE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=alHDgU3AjKEHFQcAHJLT8IwCSsXwiv0ls2mu0XbGxnKZoYDpoz48g64dGnIfCwmBT 8cg4gujHay2ZTGWUW21mCVh44Zqy+C5UHQLVYada/J+HawJNym3anpG7GsNo6ANze0 Pfzxc5QTHG6nWsiJvjVXxCcE0/x5qekRxxZJ9/hQ= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 26J88pWC091745 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Jul 2022 03:08:51 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Jul 2022 03:08:50 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Jul 2022 03:08:50 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 26J88oH4020158; Tue, 19 Jul 2022 03:08:50 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski Subject: [PATCH 3/8] drm/tidss: Add support for DSS port properties Date: Tue, 19 Jul 2022 13:38:40 +0530 Message-ID: <20220719080845.22122-4-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220719080845.22122-1-a-bhatia1@ti.com> References: <20220719080845.22122-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree List , Vignesh Raghavendra , Devarsh Thakkar , Linux Kernel List , DRI Development List , Darren Etheridge , Rahul T R , Krunal Bhargav Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support to enable and read the dss port properties. The "ti,oldi-mode" property indicates the tidss driver how many OLDI TXes are enabled as well as which mode do they need to be connected in. The "ti,rgb565_to_888" is a special property that forces the DSS to output 16bit RGB565 data to a 24bit RGB888 bridge. This property can be used when the bridge does not explicity support RGB565. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 55 ++++++++++++++++++++++++++--- drivers/gpu/drm/tidss/tidss_dispc.h | 8 +++++ 2 files changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index f084f0688a54..add725fa682b 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -348,6 +348,10 @@ struct dispc_device { struct dss_vp_data vp_data[TIDSS_MAX_PORTS]; + enum dss_oldi_modes oldi_mode; + + bool rgb565_to_888; + u32 *fourccs; u32 num_fourccs; @@ -2718,6 +2722,42 @@ static void dispc_softreset(struct dispc_device *dispc) dev_warn(dispc->dev, "failed to reset dispc\n"); } +static void dispc_get_port_properties(struct dispc_device *dispc) +{ + u32 i = 0; + struct device_node *dss_ports, *vport; + + dss_ports = of_get_next_child(dispc->dev->of_node, NULL); + + for_each_child_of_node(dss_ports, vport) { + if (dispc->feat->vp_bus_type[i] == DISPC_VP_OLDI) { + if (of_property_read_u32(vport, "ti,oldi-mode", &dispc->oldi_mode)) { + dev_dbg(dispc->dev, "%s: Using OLDI defaults on vp%d.\n", + __func__, i); + if (dispc->feat->subrev == DISPC_AM65X) + dispc->oldi_mode = OLDI_SINGLE_LINK_SINGLE_MODE_0; + else + dispc->oldi_mode = OLDI_MODE_OFF; + } + + /* + * DISPC_AM65X DSS has a singular OLDI TX. It can not work in + * Dual/Duplicate Mode. Forcing defaults. + */ + if (dispc->feat->subrev == DISPC_AM65X && + dispc->oldi_mode > OLDI_SINGLE_LINK_SINGLE_MODE_0) { + dev_dbg(dispc->dev, + "%s: Using default OLDI mode %d. AM65X can not support mode %d.\n", + __func__, OLDI_SINGLE_LINK_SINGLE_MODE_0, dispc->oldi_mode); + dispc->oldi_mode = OLDI_SINGLE_LINK_SINGLE_MODE_0; + } + } else if (dispc->feat->vp_bus_type[i] == DISPC_VP_DPI) { + dispc->rgb565_to_888 = of_property_read_bool(vport, "ti,rgb565-to-888"); + } + i++; + } +} + int dispc_init(struct tidss_device *tidss) { struct device *dev = tidss->dev; @@ -2812,10 +2852,17 @@ int dispc_init(struct tidss_device *tidss) dispc->vp_data[i].gamma_table = gamma_table; } - if (feat->subrev == DISPC_AM65X) { - r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); - if (r) - return r; + if (feat->subrev == DISPC_AM65X || feat->subrev == DISPC_AM625) { + dispc_get_port_properties(dispc); + if (dispc->oldi_mode) { + r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); + if (r) + return r; + } + } else { + /* K2G and J721E DSS do not support these properties */ + dispc->oldi_mode = OLDI_MODE_OFF; + dispc->rgb565_to_888 = false; } dispc->fclk = devm_clk_get(dev, "fck"); diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index a28005dafdc9..de8a95d3e3be 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -64,6 +64,14 @@ enum dispc_dss_subrevision { DISPC_AM625, }; +enum dss_oldi_modes { + OLDI_MODE_OFF, /* OLDI turned off / tied off in IP. */ + OLDI_SINGLE_LINK_SINGLE_MODE_0, /* Single Output over OLDI 0. */ + OLDI_SINGLE_LINK_SINGLE_MODE_1, /* Single Output over OLDI 1. */ + OLDI_SINGLE_LINK_DUPLICATE_MODE, /* Duplicate Output over OLDI 0 and 1. */ + OLDI_DUAL_LINK, /* Combined Output over OLDI 0 and 1. */ +}; + struct dispc_features { int min_pclk_khz; int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE]; From patchwork Tue Jul 19 08:08:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 12922239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72828C43334 for ; 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Tue, 19 Jul 2022 03:08:52 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Jul 2022 03:08:52 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Jul 2022 03:08:52 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 26J88p0U121356; Tue, 19 Jul 2022 03:08:52 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski Subject: [PATCH 4/8] drm/tidss: Add support for Dual Link LVDS Bus Format Date: Tue, 19 Jul 2022 13:38:41 +0530 Message-ID: <20220719080845.22122-5-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220719080845.22122-1-a-bhatia1@ti.com> References: <20220719080845.22122-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree List , Vignesh Raghavendra , Devarsh Thakkar , Linux Kernel List , DRI Development List , Darren Etheridge , Rahul T R , Krunal Bhargav Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The 2 OLDI TXes in the AM625 SoC can be synced together to output a 2K resolution video. Add support in the driver for the discovery of such a dual mode connection on the OLDI video port, using the values of "ti,oldi-mode" property. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 39 +++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index add725fa682b..fb1fdecfc83a 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -853,25 +853,36 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) } } -enum dispc_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 }; +enum dispc_oldi_mode_reg_val { + SPWG_18 = 0, + JEIDA_24 = 1, + SPWG_24 = 2, + DL_SPWG_18 = 4, + DL_JEIDA_24 = 5, + DL_SPWG_24 = 6, +}; struct dispc_bus_format { u32 bus_fmt; u32 data_width; bool is_oldi_fmt; + bool is_dual_link; enum dispc_oldi_mode_reg_val oldi_mode_reg_val; }; static const struct dispc_bus_format dispc_bus_formats[] = { - { MEDIA_BUS_FMT_RGB444_1X12, 12, false, 0 }, - { MEDIA_BUS_FMT_RGB565_1X16, 16, false, 0 }, - { MEDIA_BUS_FMT_RGB666_1X18, 18, false, 0 }, - { MEDIA_BUS_FMT_RGB888_1X24, 24, false, 0 }, - { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, 0 }, - { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, 0 }, - { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, SPWG_18 }, - { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, SPWG_24 }, - { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, JEIDA_24 }, + { MEDIA_BUS_FMT_RGB444_1X12, 12, false, false, 0 }, + { MEDIA_BUS_FMT_RGB565_1X16, 16, false, false, 0 }, + { MEDIA_BUS_FMT_RGB666_1X18, 18, false, false, 0 }, + { MEDIA_BUS_FMT_RGB888_1X24, 24, false, false, 0 }, + { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, false, 0 }, + { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, false, 0 }, + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, false, SPWG_18 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, false, SPWG_24 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, false, JEIDA_24 }, + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, true, DL_SPWG_18 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, true, DL_SPWG_24 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, true, DL_JEIDA_24 }, }; static const @@ -880,9 +891,15 @@ struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc, u32 bus_fmt, u32 bus_flags) { unsigned int i; + bool is_dual_link = false; + + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI && + dispc->oldi_mode == OLDI_DUAL_LINK) + is_dual_link = true; for (i = 0; i < ARRAY_SIZE(dispc_bus_formats); ++i) { - if (dispc_bus_formats[i].bus_fmt == bus_fmt) + if (dispc_bus_formats[i].bus_fmt == bus_fmt && + dispc_bus_formats[i].is_dual_link == is_dual_link) return &dispc_bus_formats[i]; } From patchwork Tue Jul 19 08:08:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 12922236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D995CCA481 for ; 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Tue, 19 Jul 2022 03:08:54 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Jul 2022 03:08:54 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Jul 2022 03:08:53 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 26J88rWf011258; Tue, 19 Jul 2022 03:08:53 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski Subject: [PATCH 5/8] drm/tidss: dt property to force 16bit VP output to a 24bit bridge Date: Tue, 19 Jul 2022 13:38:42 +0530 Message-ID: <20220719080845.22122-6-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220719080845.22122-1-a-bhatia1@ti.com> References: <20220719080845.22122-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree List , Vignesh Raghavendra , Devarsh Thakkar , Linux Kernel List , DRI Development List , Darren Etheridge , Rahul T R , Krunal Bhargav Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Override the DSS Videoport to output 16bit RGB565 instead of 24bit RGB888 when the dt property "ti,rgb565-to-888" has been enanbled. Co-developed-by: Darren Etheridge Signed-off-by: Darren Etheridge Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index fb1fdecfc83a..94fce035c1d7 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -896,6 +896,8 @@ struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc, if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI && dispc->oldi_mode == OLDI_DUAL_LINK) is_dual_link = true; + else if (bus_fmt == MEDIA_BUS_FMT_RGB888_1X24 && dispc->rgb565_to_888) + bus_fmt = MEDIA_BUS_FMT_RGB565_1X16; for (i = 0; i < ARRAY_SIZE(dispc_bus_formats); ++i) { if (dispc_bus_formats[i].bus_fmt == bus_fmt && From patchwork Tue Jul 19 08:08:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 12922235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D1A9C433EF for ; Tue, 19 Jul 2022 08:09:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 64D8F11A211; Tue, 19 Jul 2022 08:09:24 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5BB2411A1E9 for ; Tue, 19 Jul 2022 08:09:17 +0000 (UTC) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 26J88tLk051076; Tue, 19 Jul 2022 03:08:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1658218135; bh=WYUiiaIyxWcoo74LixAH8gcE40YxTMjsX7Qghw4CW60=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IUOM6Udkmic745vevN5St5UdRqnYH3YyhVIh4xgmaqnWxM4ncU/Cnty4feCconh5s btU37evplcndIAPPkdIoFUyc6fcIndTrZdJjEcpz8PhVgP5ednMPtecgy/FRyc3p+5 ya/3Nw+kMegtZqSwu+eMe5zE/qvp85jLbwsbo7Tg= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 26J88twK084620 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Jul 2022 03:08:55 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Jul 2022 03:08:55 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Jul 2022 03:08:55 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 26J88s4a020218; Tue, 19 Jul 2022 03:08:55 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski Subject: [PATCH 6/8] drm/tidss: Add IO CTRL and Power support for OLDI TX in AM625 Date: Tue, 19 Jul 2022 13:38:43 +0530 Message-ID: <20220719080845.22122-7-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220719080845.22122-1-a-bhatia1@ti.com> References: <20220719080845.22122-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree List , Vignesh Raghavendra , Devarsh Thakkar , Linux Kernel List , DRI Development List , Darren Etheridge , Rahul T R , Krunal Bhargav Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The ctrl MMR module of the AM625 is different from the AM65X SoC. As a result, the memory-mapped regsiters that control the OLDI TX power and loopback have diverged in AM625 SoC. Add support for the controller in AM625 and control OLDI. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 70 +++++++++++++++++++----- drivers/gpu/drm/tidss/tidss_dispc_regs.h | 6 ++ 2 files changed, 62 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 94fce035c1d7..c4a5f808648f 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -934,21 +934,57 @@ int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) { - u32 val = power ? 0 : OLDI_PWRDN_TX; + u32 val; if (WARN_ON(!dispc->oldi_io_ctrl)) return; - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, - OLDI_PWRDN_TX, val); + if (dispc->feat->subrev == DISPC_AM65X) { + val = power ? 0 : OLDI_PWRDN_TX; + + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, + OLDI_PWRDN_TX, val); + + } else if (dispc->feat->subrev == DISPC_AM625) { + if (power) { + switch (dispc->oldi_mode) { + case OLDI_SINGLE_LINK_SINGLE_MODE_0: + /* Power down OLDI TX 1*/ + val = OLDI1_PWRDN_TX; + break; + + case OLDI_SINGLE_LINK_SINGLE_MODE_1: + /* Power down OLDI TX 0*/ + val = OLDI0_PWRDN_TX; + break; + + case OLDI_SINGLE_LINK_DUPLICATE_MODE: + case OLDI_DUAL_LINK: + /* No Power down */ + val = 0; + break; + + default: + /* Power down both the OLDI TXes */ + val = OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; + break; + } + } else { + /* Power down both the OLDI TXes */ + val = OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; + } + + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_PD_CTRL, + OLDI0_PWRDN_TX | OLDI1_PWRDN_TX, val); + } } static void dispc_set_num_datalines(struct dispc_device *dispc, @@ -2701,9 +2737,15 @@ static int dispc_iomap_resource(struct platform_device *pdev, const char *name, static int dispc_init_am65x_oldi_io_ctrl(struct device *dev, struct dispc_device *dispc) { - dispc->oldi_io_ctrl = - syscon_regmap_lookup_by_phandle(dev->of_node, - "ti,am65x-oldi-io-ctrl"); + if (dispc->feat->subrev == DISPC_AM65X) + dispc->oldi_io_ctrl = + syscon_regmap_lookup_by_phandle(dev->of_node, + "ti,am65x-oldi-io-ctrl"); + else + dispc->oldi_io_ctrl = + syscon_regmap_lookup_by_phandle(dev->of_node, + "ti,am625-oldi-io-ctrl"); + if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { dispc->oldi_io_ctrl = NULL; } else if (IS_ERR(dispc->oldi_io_ctrl)) { diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tidss/tidss_dispc_regs.h index 13feedfe5d6d..510bee70b3b8 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc_regs.h +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h @@ -238,6 +238,12 @@ enum dispc_common_regs { #define OLDI_DAT3_IO_CTRL 0x0C #define OLDI_CLK_IO_CTRL 0x10 +/* Only for AM625 OLDI TX */ +#define OLDI_PD_CTRL 0x100 +#define OLDI_LB_CTRL 0x104 + #define OLDI_PWRDN_TX BIT(8) +#define OLDI0_PWRDN_TX BIT(0) +#define OLDI1_PWRDN_TX BIT(1) #endif /* __TIDSS_DISPC_REGS_H */ From patchwork Tue Jul 19 08:08:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 12922237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1ED33CCA47F for ; Tue, 19 Jul 2022 08:09:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6230211A203; Tue, 19 Jul 2022 08:09:24 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by gabe.freedesktop.org (Postfix) with ESMTPS id 08E6B11A20A for ; Tue, 19 Jul 2022 08:09:18 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 26J88v5X051606; Tue, 19 Jul 2022 03:08:57 -0500 DKIM-Signature: v=1; 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Tue, 19 Jul 2022 03:08:57 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 26J88uHT020236; Tue, 19 Jul 2022 03:08:56 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski Subject: [PATCH 7/8] drm/tidss: Fix clock request value for OLDI videoports Date: Tue, 19 Jul 2022 13:38:44 +0530 Message-ID: <20220719080845.22122-8-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220719080845.22122-1-a-bhatia1@ti.com> References: <20220719080845.22122-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree List , Vignesh Raghavendra , Devarsh Thakkar , Linux Kernel List , DRI Development List , Darren Etheridge , Rahul T R , Krunal Bhargav Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The OLDI TX(es) require a serial clock which is 7 times the pixel clock of the display panel. When the OLDI is enabled in DSS, the pixel clock input of the corresponding videoport gets a divided-by 7 value of the requested clock. For the am625-dss, the requested clock needs to be 7 times the value. Update the clock frequency by requesting 7 times the value. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index c4a5f808648f..0b9689453ee8 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1326,6 +1326,16 @@ int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, int r; unsigned long new_rate; + /* + * For AM625 OLDI video ports, the requested pixel clock needs to take into account the + * serial clock required for the serialization of DPI signals into LVDS signals. The + * incoming pixel clock on the OLDI video port gets divided by 7 whenever OLDI enable bit + * gets set. + */ + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI && + dispc->feat->subrev == DISPC_AM625) + rate *= 7; + r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); if (r) { dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", From patchwork Tue Jul 19 08:08:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 12922238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA9ADC43334 for ; Tue, 19 Jul 2022 08:09:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AF35311A235; Tue, 19 Jul 2022 08:09:24 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by gabe.freedesktop.org (Postfix) with ESMTPS id 64F2611A20A for ; Tue, 19 Jul 2022 08:09:18 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 26J88xD8051616; Tue, 19 Jul 2022 03:08:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1658218139; bh=Cb7Wkj97XLd+o09FdkfKJN28acdGbBYRIfpnXJmYk4o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=P1omX8Ya6mcd6/txrDL9oiozCYQDQFDV438Sq2Sofbit/qqJWM3rPghpZxZgrLYYr CnTUE5qF9dTlJX4VqrTVNE9MNH5t23UThTufsgJ426cuLvI9418kqih0bazdR2hxH8 rx3ypzk37Pagk06zbLSzYuIew7FL9dj0SBeAu1k0= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 26J88xoL044039 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Jul 2022 03:08:59 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Jul 2022 03:08:58 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Jul 2022 03:08:58 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 26J88vTO020251; Tue, 19 Jul 2022 03:08:58 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Rob Herring , David Airlie , Daniel Vetter , Krzysztof Kozlowski Subject: [PATCH 8/8] drm/tidss: Enable Dual and Duplicate Modes for OLDI Date: Tue, 19 Jul 2022 13:38:45 +0530 Message-ID: <20220719080845.22122-9-a-bhatia1@ti.com> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220719080845.22122-1-a-bhatia1@ti.com> References: <20220719080845.22122-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Devicetree List , Vignesh Raghavendra , Devarsh Thakkar , Linux Kernel List , DRI Development List , Darren Etheridge , Rahul T R , Krunal Bhargav Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The AM625 DSS peripheral supports 2 OLDI TXes which can work to enable 2 duplicated displays of smaller resolutions or enable a single Dual-Link display with a higher resolution (1920x1200). Configure the necessary register to enable the different modes. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 44 +++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 0b9689453ee8..28cb61259471 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1021,8 +1021,8 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, int count = 0; /* - * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC - * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0. + * For the moment MASTERSLAVE, and SRC bits of DISPC_VP_DSS_OLDI_CFG are + * set statically to 0. */ if (fmt->data_width == 24) @@ -1039,7 +1039,45 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, oldi_cfg |= BIT(0); /* ENABLE */ - dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + /* + * As per all the current implementations of DSS, the OLDI TXes are present only on + * hw_videoport = 0 (OLDI TX 0). However, the config register for 2nd OLDI TX (OLDI TX 1) + * is present in the address space of hw_videoport = 1. Hence, using "hw_videoport + 1" to + * configure OLDI TX 1. + */ + + switch (dispc->oldi_mode) { + case OLDI_MODE_OFF: + oldi_cfg &= ~BIT(0); /* DISABLE */ + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + dispc_vp_write(dispc, hw_videoport + 1, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + break; + + case OLDI_SINGLE_LINK_SINGLE_MODE_0: + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + break; + + case OLDI_SINGLE_LINK_SINGLE_MODE_1: + dispc_vp_write(dispc, hw_videoport + 1, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + break; + + case OLDI_SINGLE_LINK_DUPLICATE_MODE: + oldi_cfg |= BIT(5); /* DUPLICATE MODE */ + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + dispc_vp_write(dispc, hw_videoport + 1, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + break; + + case OLDI_DUAL_LINK: + oldi_cfg |= BIT(11); /* DUALMODESYNC */ + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + dispc_vp_write(dispc, hw_videoport + 1, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + break; + + default: + dev_warn(dispc->dev, "%s: Incorrect oldi mode. Returning.\n", + __func__); + return; + } while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) && count < 10000)