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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT036.mail.protection.outlook.com (10.13.177.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5458.17 via Frontend Transport; Wed, 20 Jul 2022 06:00:28 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 20 Jul 2022 01:00:23 -0500 From: Appana Durga Kedareswara rao To: , , , , , , CC: , , , , , , Appana Durga Kedareswara rao Subject: [PATCH v2 1/4] dt-bindings: misc: tmr-manager: Add device-tree binding for TMR Manager Date: Wed, 20 Jul 2022 11:30:13 +0530 Message-ID: <20220720060016.1646317-2-appana.durga.kedareswara.rao@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220720060016.1646317-1-appana.durga.kedareswara.rao@amd.com> References: <20220720060016.1646317-1-appana.durga.kedareswara.rao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1a938a8f-1752-42a6-68d2-08da6a15261c X-MS-TrafficTypeDiagnostic: DM5PR12MB1305:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 06:00:28.8694 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a938a8f-1752-42a6-68d2-08da6a15261c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1305 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220719_230034_548630_173FC63D X-CRM114-Status: GOOD ( 14.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Appana Durga Kedareswara rao Triple Modular Redundancy(TMR) subsystem contains three microblaze cores, subsystem is fault-tolerant and continues to operate nominally after encountering an error. Together with the capability to detect and recover from errors, the implementation ensures the reliability of the entire subsystem. TMR Manager is responsible for performing recovery of the subsystem detects the fault via a break signal it invokes microblaze software break handler which calls the tmr manager driver api to update the error count and status. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Appana Durga Kedareswara rao Reviewed-by: Krzysztof Kozlowski --- Changes for v2: --> Improved description for xlnx,magic1 property as suggested by Krzysztof. --> Fixed style issues (indentation of example node title description etc..) .../bindings/misc/xlnx,tmr-manager.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml new file mode 100644 index 000000000000..f7e6ac1d5867 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Triple Modular Redundancy(TMR) Manager IP + +maintainers: + - Appana Durga Kedareswara rao + +description: | + The Triple Modular Redundancy(TMR) Manager is responsible for handling the + TMR subsystem state, including fault detection and error recovery. The core + is triplicated in each of the sub-blocks in the TMR subsystem, and provides + majority voting of its internal state. + +properties: + compatible: + enum: + - xlnx,tmr-manager-1.0 + + reg: + maxItems: 1 + + xlnx,magic1: + minimum: 0 + maximum: 255 + description: + Magic byte 1, When configured it allows the controller to perform + recovery. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic1 + +additionalProperties: false + +examples: + - | + tmr-manager@44a10000 { + compatible = "xlnx,tmr-manager-1.0"; + reg = <0x44a10000 0x10000>; + xlnx,magic1 = <0x46>; + }; From patchwork Wed Jul 20 06:00:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara rao X-Patchwork-Id: 12923528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C9B1C433EF for ; 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Wed, 20 Jul 2022 01:00:27 -0500 From: Appana Durga Kedareswara rao To: , , , , , , CC: , , , , , , Appana Durga Kedareswara rao Subject: [PATCH v2 2/4] drivers: misc: Add Support for TMR Manager Date: Wed, 20 Jul 2022 11:30:14 +0530 Message-ID: <20220720060016.1646317-3-appana.durga.kedareswara.rao@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220720060016.1646317-1-appana.durga.kedareswara.rao@amd.com> References: <20220720060016.1646317-1-appana.durga.kedareswara.rao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1986e1e9-793f-4b35-45a1-08da6a152ed5 X-MS-TrafficTypeDiagnostic: BN7PR12MB2595:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jGuiPlKIQg+kTkooQmHVywKm3TNDq1UKG7w6xA8Nr4zMW051daKGLg6nBK8NjRzZCjd42fsnmcskPOZN79cVYgGSJMqTr+qP66YDf9aP+DozBNAZ11C/qJ/sjwR1FYC8Qjrcv4tmZpXD7XRC1sztATZ7QkBWvbtO2kMFEjl/wC3bhohzVLrsZGNJBr4vsoOPEFuaorFwAp0qJb8bbEJHF81hUceb9MKor75NuUWx1bLC6XWWYRRrJZm4KyAgZpmGpU4l9CfObRpaujTxHFZKlBtD4tVIMoUW8dR1wO4OZTvBSzW9ps1BcReWEYnDUZ8UbNrv8AziTe/UpDccIBfYBZToHCmwXzSblLwOPGE+fbB9gPi8FvqGKV1wJLfKA2OHT0fct8VEQCTLo9E7e9uOSWsYqRYXn+7hlHiJ20+T0L7F6o7d0EwAh1VMuB+Ca89JuFQM14liJPisFzzNihJXpV0RbpH5rAeFBWkNrgwT0DAB51wgOa+kTQDTgz0tUy7G4FOzsXqey8yWhWuLFvDfFMdrvNajvbShTQ1VcFlsZloCEVJgt0IDk1JEla6gCeKslgrx/ltLVjYE8aYQ83n4pOSgIHgfm03QGj8zw/sZRl2dCMe1Aj9hozHJ7jpiye1dNeXToUv5IXFsQIHOVXlkzi/SwMThOAjU3ypLym2kU6C3zndzaHT1f+WMC96QfHh5KhEasHJkkFV2qK61DU6hC9U/EM46BFYQyUIax8WAEo2iyY4gyAwapJJt2//8gpPW+B/NnfNT8zZ5blA059TTPQw1fL1O3jCT2AHB9mZZVDiW6wL5WK7GgdUwcV9fZ9khUvkmaXYhkUz3rYj5HfT87yjZvWm3QtGESFOUJdyywfUqmOcWhll3dOD2VHV6b2Ty X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(376002)(346002)(136003)(396003)(39860400002)(40470700004)(36840700001)(46966006)(47076005)(426003)(356005)(86362001)(16526019)(81166007)(82310400005)(1076003)(82740400003)(8936002)(2906002)(2616005)(5660300002)(26005)(36756003)(103116003)(336012)(83380400001)(186003)(966005)(70206006)(8676002)(40480700001)(4326008)(30864003)(478600001)(41300700001)(70586007)(36860700001)(40460700003)(54906003)(107886003)(316002)(110136005)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 06:00:43.8151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1986e1e9-793f-4b35-45a1-08da6a152ed5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2595 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220719_230049_328803_6107D7BD X-CRM114-Status: GOOD ( 25.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Appana Durga Kedareswara rao Triple Modular Redundancy(TMR) subsystem contains three microblaze cores, subsystem is fault-tolerant and continues to operate nominally after encountering an error. Together with the capability to detect and recover from errors, the implementation ensures the reliability of the entire subsystem. TMR Manager is responsible for performing recovery of the subsystem detects the fault via a break signal it invokes microblaze software break handler which calls the tmr manager driver api to update the error count and status, added support for fault detection feature via sysfs interface. Usage: To know the hardware status: cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/status To know the break handler count(Error count): cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/errcnt Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Appana Durga Kedareswara rao --- Changes for v2: --> Added Examples for sysfs entries --> Removed uneeded struct dev from the driver private structure --> Fixed style issues (Used resource_size_t instead of uintptr_t) --> Updated driver to use sysfs_emit() API instead of sprintf() API --> Added error checks wherever applicable. --> Fixed sysfs registration. .../testing/sysfs-driver-xilinx-tmr-manager | 27 ++ MAINTAINERS | 7 + drivers/misc/Kconfig | 10 + drivers/misc/Makefile | 1 + drivers/misc/xilinx_tmr_manager.c | 253 ++++++++++++++++++ 5 files changed, 298 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager create mode 100644 drivers/misc/xilinx_tmr_manager.c diff --git a/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager new file mode 100644 index 000000000000..fc5fe7e22b09 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager @@ -0,0 +1,27 @@ +What: /sys/devices/platform/amba_pl//status +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file provides the status of the tmr manager + useful for getting the status of fault. + This file cannot be written. + Example: + # cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/status + Lockstep mismatch between processor 1 and 2 + Lockstep mismatch between processor 2 and 3 + +What: /sys/devices/platform/amba_pl//errcnt +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file provides the fault detection count. + This file cannot be written. + Example: + # cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/errcnt + 1 + +What: /sys/devices/platform/amba_pl//dis_block_break +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file enables the break signal. + This file is write only. + Example: + # echo 1 > /sys/devices/platform/amba_pl/44a10000.tmr_manager/dis_block_break diff --git a/MAINTAINERS b/MAINTAINERS index 651616ed8ae2..732fd9ae7d9f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13080,6 +13080,13 @@ W: http://www.monstr.eu/fdt/ T: git git://git.monstr.eu/linux-2.6-microblaze.git F: arch/microblaze/ +MICROBLAZE TMR MANAGER +M: Appana Durga Kedareswara rao +S: Supported +F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager +F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml +F: drivers/misc/xilinx_tmr_manager.c + MICROCHIP AT91 DMA DRIVERS M: Ludovic Desroches M: Tudor Ambarus diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 41d2bb0ae23a..555ae2e33b91 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -483,6 +483,16 @@ config OPEN_DICE If unsure, say N. +config TMR_MANAGER + bool "Select TMR Manager" + depends on MICROBLAZE && MB_MANAGER + help + This option enables the driver developed for TMR Manager. The Triple + Modular Redundancy(TMR) manager provides support for fault detection + via sysfs interface. + + Say N here unless you know what you are doing. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 70e800e9127f..28b9803f909b 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -60,3 +60,4 @@ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o obj-$(CONFIG_OPEN_DICE) += open-dice.o +obj-$(CONFIG_TMR_MANAGER) += xilinx_tmr_manager.o diff --git a/drivers/misc/xilinx_tmr_manager.c b/drivers/misc/xilinx_tmr_manager.c new file mode 100644 index 000000000000..dbeca18c409f --- /dev/null +++ b/drivers/misc/xilinx_tmr_manager.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx TMR Subsystem. + * + * Copyright (C) 2022 Xilinx, Inc. + * + * Description: + * This driver is developed for TMR Manager,The Triple Modular Redundancy(TMR) + * Manager is responsible for handling the TMR subsystem state, including + * fault detection and error recovery. The core is triplicated in each of + * the sub-blocks in the TMR subsystem, and provides majority voting of + * its internal state provides soft error detection, correction and + * recovery. Error detection feature is provided through sysfs + * entries which allow the user to observer the TMR microblaze + * status. + */ + +#include +#include +#include + +/* TMR Manager Register offsets */ +#define XTMR_MANAGER_CR_OFFSET 0x0 +#define XTMR_MANAGER_FFR_OFFSET 0x4 +#define XTMR_MANAGER_CMR0_OFFSET 0x8 +#define XTMR_MANAGER_CMR1_OFFSET 0xC +#define XTMR_MANAGER_BDIR_OFFSET 0x10 +#define XTMR_MANAGER_SEMIMR_OFFSET 0x1C + +/* Register Bitmasks/shifts */ +#define XTMR_MANAGER_CR_MAGIC1_MASK GENMASK(7, 0) +#define XTMR_MANAGER_CR_MAGIC2_MASK GENMASK(15, 8) +#define XTMR_MANAGER_CR_RIR_MASK BIT(16) +#define XTMR_MANAGER_FFR_LM12_MASK BIT(0) +#define XTMR_MANAGER_FFR_LM13_MASK BIT(1) +#define XTMR_MANAGER_FFR_LM23_MASK BIT(2) + +#define XTMR_MANAGER_CR_MAGIC2_SHIFT 4 +#define XTMR_MANAGER_CR_RIR_SHIFT 16 +#define XTMR_MANAGER_CR_BB_SHIFT 18 + +#define XTMR_MANAGER_MAGIC1_MAX_VAL 255 + +/** + * struct xtmr_manager_dev - Driver data for TMR Manager + * @regs: device physical base address + * @cr_val: control register value + * @magic1: Magic 1 hardware configuration value + * @err_cnt: error statistics count + * @phys_baseaddr: Physical base address + */ +struct xtmr_manager_dev { + void __iomem *regs; + u32 cr_val; + u32 magic1; + u32 err_cnt; + resource_size_t phys_baseaddr; +}; + +/* IO accessors */ +static inline void xtmr_manager_write(struct xtmr_manager_dev *xtmr_manager, + u32 addr, u32 value) +{ + iowrite32(value, xtmr_manager->regs + addr); +} + +static inline u32 xtmr_manager_read(struct xtmr_manager_dev *xtmr_manager, + u32 addr) +{ + return ioread32(xtmr_manager->regs + addr); +} + +static void xmb_manager_reset_handler(struct xtmr_manager_dev *xtmr_manager) +{ + /* Clear the FFR Register contents as a part of recovery process. */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_FFR_OFFSET, 0); +} + +static void xmb_manager_update_errcnt(struct xtmr_manager_dev *xtmr_manager) +{ + xtmr_manager->err_cnt++; +} + +static ssize_t errcnt_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct xtmr_manager_dev *xtmr_manager = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%x\n", xtmr_manager->err_cnt); +} +static DEVICE_ATTR_RO(errcnt); + +static ssize_t status_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct xtmr_manager_dev *xtmr_manager = dev_get_drvdata(dev); + size_t ffr; + int len = 0; + + ffr = xtmr_manager_read(xtmr_manager, XTMR_MANAGER_FFR_OFFSET); + if ((ffr & XTMR_MANAGER_FFR_LM12_MASK) == XTMR_MANAGER_FFR_LM12_MASK) { + len += sysfs_emit_at(buf, len, "Lockstep mismatch between "); + len += sysfs_emit_at(buf, len, "processor 1 and 2\n"); + } + + if ((ffr & XTMR_MANAGER_FFR_LM13_MASK) == XTMR_MANAGER_FFR_LM13_MASK) { + len += sysfs_emit_at(buf, len, "Lockstep mismatch between "); + len += sysfs_emit_at(buf, len, "processor 1 and 3\n"); + } + + if ((ffr & XTMR_MANAGER_FFR_LM23_MASK) == XTMR_MANAGER_FFR_LM23_MASK) { + len += sysfs_emit_at(buf, len, "Lockstep mismatch between "); + len += sysfs_emit_at(buf, len, "processor 2 and 3\n"); + } + + return len; +} +static DEVICE_ATTR_RO(status); + +static ssize_t dis_block_break_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct xtmr_manager_dev *xtmr_manager = dev_get_drvdata(dev); + int ret; + long value; + + ret = kstrtoul(buf, 16, &value); + if (ret) + return ret; + + if (value > 1) + return -EINVAL; + + /* unblock the break signal*/ + xtmr_manager->cr_val &= ~(1 << XTMR_MANAGER_CR_BB_SHIFT); + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET, + xtmr_manager->cr_val); + return size; +} +static DEVICE_ATTR_WO(dis_block_break); + +static struct attribute *xtmr_manager_dev_attrs[] = { + &dev_attr_dis_block_break.attr, + &dev_attr_status.attr, + &dev_attr_errcnt.attr, + NULL, +}; +ATTRIBUTE_GROUPS(xtmr_manager_dev); + +static void xtmr_manager_init(struct xtmr_manager_dev *xtmr_manager) +{ + /* Clear the SEM interrupt mask register to disable the interrupt */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_SEMIMR_OFFSET, 0); + + /* Allow recovery reset by default */ + xtmr_manager->cr_val = (1 << XTMR_MANAGER_CR_RIR_SHIFT) | + xtmr_manager->magic1; + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET, + xtmr_manager->cr_val); + /* + * Configure Break Delay Initialization Register to zero so that + * break occurs immediately + */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_BDIR_OFFSET, 0); + + /* + * To come out of break handler need to block the break signal + * in the tmr manager, update the xtmr_manager cr_val for the same + */ + xtmr_manager->cr_val |= (1 << XTMR_MANAGER_CR_BB_SHIFT); + + /* + * When the break vector gets asserted because of error injection, + * the break signal must be blocked before exiting from the + * break handler, Below api updates the TMR manager address and + * control register and error counter callback arguments, + * which will be used by the break handler to block the + * break and call the callback function. + */ + xmb_manager_register(xtmr_manager->phys_baseaddr, xtmr_manager->cr_val, + (void *)xmb_manager_update_errcnt, + xtmr_manager, (void *)xmb_manager_reset_handler); +} + +/** + * xtmr_manager_probe - Driver probe function + * @pdev: Pointer to the platform_device structure + * + * This is the driver probe routine. It does all the memory + * allocation and creates sysfs entries for the device. + * + * Return: 0 on success and failure value on error + */ +static int xtmr_manager_probe(struct platform_device *pdev) +{ + struct xtmr_manager_dev *xtmr_manager; + struct resource *res; + int err; + + xtmr_manager = devm_kzalloc(&pdev->dev, sizeof(*xtmr_manager), + GFP_KERNEL); + if (!xtmr_manager) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + xtmr_manager->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(xtmr_manager->regs)) + return PTR_ERR(xtmr_manager->regs); + + xtmr_manager->phys_baseaddr = res->start; + + err = of_property_read_u32(pdev->dev.of_node, "xlnx,magic1", + &xtmr_manager->magic1); + if (err < 0) { + dev_err(&pdev->dev, "unable to read xlnx,magic1 property"); + return err; + } + + if (xtmr_manager->magic1 > XTMR_MANAGER_MAGIC1_MAX_VAL) { + dev_err(&pdev->dev, "invalid xlnx,magic1 property value"); + return -EINVAL; + } + + /* Initialize TMR Manager */ + xtmr_manager_init(xtmr_manager); + + platform_set_drvdata(pdev, xtmr_manager); + + return 0; +} + +static const struct of_device_id xtmr_manager_of_match[] = { + { + .compatible = "xlnx,tmr-manager-1.0", + }, + { /* end of table */ } +}; +MODULE_DEVICE_TABLE(of, xtmr_manager_of_match); + +static struct platform_driver xtmr_manager_driver = { + .driver = { + .name = "xilinx-tmr_manager", + .of_match_table = xtmr_manager_of_match, + .dev_groups = xtmr_manager_dev_groups, + }, + .probe = xtmr_manager_probe, +}; +module_platform_driver(xtmr_manager_driver); + +MODULE_AUTHOR("Xilinx, Inc"); +MODULE_DESCRIPTION("Xilinx TMR Manager Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Jul 20 06:00:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Appana Durga Kedareswara rao X-Patchwork-Id: 12923525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35F2CC43334 for ; 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Wed, 20 Jul 2022 01:00:31 -0500 From: Appana Durga Kedareswara rao To: , , , , , , CC: , , , , , , Appana Durga Kedareswara rao Subject: [PATCH v2 3/4] dt-bindings: misc: tmr-inject: Add device-tree binding for TMR Inject Date: Wed, 20 Jul 2022 11:30:15 +0530 Message-ID: <20220720060016.1646317-4-appana.durga.kedareswara.rao@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220720060016.1646317-1-appana.durga.kedareswara.rao@amd.com> References: <20220720060016.1646317-1-appana.durga.kedareswara.rao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8fb2966f-88ff-48fd-843a-08da6a152889 X-MS-TrafficTypeDiagnostic: CY4PR12MB1496:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: x1SJV2owB5jqT5ViGBIw7TrKyGoo/3eTKZKAqnblCF2Nh0CDbnNvKCooresJ+d3vvN6zpZqSZEyS87xKwz3weUz2Gq1CRvYkqs3rEoSsT6bfaN7r9U0FADxt4k0pRw7oMriHlywKhSj7j7c7voJsvoI21+ZhXeOQws0b/Ttpww8O9guEHayA/Oi1qlg5oknCOJHYVgEhT+mQrlQ4Wcg0cOhmwnWFPRDwbJ9F333A16QGbBlsXLgxx3BLjyE445a/jAMBqpYRmjv1kHMNcWRowY1LIpij+MmfG98VFYWqgGYYWnkhL9/UpKb2L934D0wn2wOYfvyZizBlvgYY/r3ldosQuPgd5aowirEV0Rr5gbf4AjSGTxQ/ly0Gepd+pYtIuy5xSr0ir9g/aBf6V/K8ndAWoP+GNWH9/gKneCYGm/R0fKzV4TklRQNqrk+9dwceDVhPyF9SIPMQP0RXbq1dnG9DjWg5+eDyCsbNxKT7WF1Ra7mmnd4rpmZZMXgcr8xXsL1l2UtZfM6m7XWDwn/YUFvQLimeVP0kNpiawoi9mRAxN3VsPrSj4fTB4J6kXk5QxKJ/77G3TsPF1YEaLy9xqHBAkMDtDAl2t+ilZfl0EjroWlFiNn21ziPOW54BBZR53GdIe+959n3WqcDatQo9Ev1wdkzs1oIGZoE5lhtnuRLour/o/yQpFzmlahZHm/0CiCrw9pcOu7gnlZk3mztgY2R9BCy83TcnLm+BV0U0MnYDRvr+m38lytzlXPtE4RvPYttPiDAxZq8e/J6SFunyQO0Rx3bSNieHdRkUFHO7hwRI83KNtkRosfTyw6mZUBBRNwJBnWxe8FvbJpKrDsTJeialHOtxHJCqNpucAKl2tEuGeHZDn1XE2BD9A8qk73duh0ia8ZLAEWAqwtFccqdlVzksPZyjR884/2lzi613RDE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(346002)(136003)(376002)(39860400002)(396003)(36840700001)(46966006)(40470700004)(4326008)(82310400005)(8936002)(8676002)(36860700001)(2906002)(70206006)(86362001)(81166007)(70586007)(5660300002)(40460700003)(83380400001)(107886003)(47076005)(2616005)(186003)(16526019)(54906003)(966005)(356005)(41300700001)(336012)(110136005)(6666004)(36756003)(478600001)(316002)(103116003)(40480700001)(26005)(82740400003)(426003)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 06:00:33.2523 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8fb2966f-88ff-48fd-843a-08da6a152889 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1496 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220719_230037_773248_94938ED2 X-CRM114-Status: GOOD ( 13.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Appana Durga Kedareswara rao The Triple Modular Redundancy(TMR) Inject core provides functional fault injection by changing selected MicroBlaze instructions, which provides the possibility to verify that the TMR subsystem error detection and fault recovery logic is working properly. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Appana Durga Kedareswara rao Reviewed-by: Krzysztof Kozlowski --- Changes for v2: --> Improved description for xlnx,magic property as suggested by Krzysztof. --> Fixed style issues (indentation of example node title description etc..) .../bindings/misc/xlnx,tmr-inject.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml b/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml new file mode 100644 index 000000000000..cb14ea73fb4c --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-inject.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Triple Modular Redundancy(TMR) Inject IP + +maintainers: + - Appana Durga Kedareswara rao + +description: | + The Triple Modular Redundancy(TMR) Inject core provides functional fault + injection by changing selected MicroBlaze instructions, which provides the + possibility to verify that the TMR subsystem error detection and fault + recovery logic is working properly. + +properties: + compatible: + enum: + - xlnx,tmr-inject-1.0 + + reg: + maxItems: 1 + + xlnx,magic: + minimum: 0 + maximum: 255 + description: | + Magic number, When configured it allows the controller to perform + recovery. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic + +additionalProperties: false + +examples: + - | + fault-inject@44a30000 { + compatible = "xlnx,tmr-inject-1.0"; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT004.mail.protection.outlook.com (10.13.176.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5458.17 via Frontend Transport; Wed, 20 Jul 2022 06:00:37 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 20 Jul 2022 01:00:35 -0500 From: Appana Durga Kedareswara rao To: , , , , , , CC: , , , , , , Appana Durga Kedareswara rao Subject: [PATCH v2 4/4] drivers: misc: Add Support for TMR Inject IP Date: Wed, 20 Jul 2022 11:30:16 +0530 Message-ID: <20220720060016.1646317-5-appana.durga.kedareswara.rao@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220720060016.1646317-1-appana.durga.kedareswara.rao@amd.com> References: <20220720060016.1646317-1-appana.durga.kedareswara.rao@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1c1d0600-6a38-4e98-0c5e-08da6a152b06 X-MS-TrafficTypeDiagnostic: MN2PR12MB4222:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 06:00:37.4239 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c1d0600-6a38-4e98-0c5e-08da6a152b06 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4222 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220719_230041_910246_71092A6A X-CRM114-Status: GOOD ( 30.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Appana Durga Kedareswara rao The Triple Modular Redundancy(TMR) provides functional fault injection by changing selected MicroBlaze instructions, which provides the possibility to verify that the TMR subsystem error detection and fault recovery logic is working properly, provided sysfs entries which allow the user to inject a fault. Usage: echo 1 > /sys/devices/platform/amba_pl/44a30000.tmr_inject/inject_err Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Appana Durga Kedareswara rao --- Changes for v2: --> Added Examples for sysfs entries --> Removed uneeded struct dev from the driver private structure --> Updated driver to use sysfs_emit() API instead of sprintf() API --> Added error checks wherever applicable. --> Fixed sysfs registration. .../testing/sysfs-driver-xilinx-tmr-inject | 16 ++ MAINTAINERS | 7 + drivers/misc/Kconfig | 10 + drivers/misc/Makefile | 1 + drivers/misc/xilinx_tmr_inject.c | 186 ++++++++++++++++++ 5 files changed, 220 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-xilinx-tmr-inject create mode 100644 drivers/misc/xilinx_tmr_inject.c diff --git a/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-inject b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-inject new file mode 100644 index 000000000000..d274b30ee24c --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-inject @@ -0,0 +1,16 @@ +What: /sys/devices/platform/amba_pl//inject_err +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file allows to inject fault using tmr inject. + This file is write only. + Example: + # echo 1 > /sys/devices/platform/amba_pl/44a30000.tmr_inject/inject_err + +What: /sys/devices/platform/amba_pl//inject_cpuid +Date: June 2022 +Contact: appana.durga.rao@xilinx.com +Description: This control file allows to configure the CPU identifier + to enable fault injection. + This file is write only. + Example: + # echo 1 > /sys/devices/platform/amba_pl/44a30000.tmr_inject/inject_cpuid diff --git a/MAINTAINERS b/MAINTAINERS index 732fd9ae7d9f..c903b45c204a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13087,6 +13087,13 @@ F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml F: drivers/misc/xilinx_tmr_manager.c +MICROBLAZE TMR INJECT +M: Appana Durga Kedareswara rao +S: Supported +F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-inject +F: Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml +F: drivers/misc/xilinx_tmr_inject.c + MICROCHIP AT91 DMA DRIVERS M: Ludovic Desroches M: Tudor Ambarus diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 555ae2e33b91..0989c36f3051 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -493,6 +493,16 @@ config TMR_MANAGER Say N here unless you know what you are doing. +config TMR_INJECT + bool "Select TMR Inject" + depends on TMR_MANAGER + help + This option enables the driver developed for TMR Inject. + The Triple Modular Redundancy(TMR) Inject provides + fault injection. + + Say N here unless you know what you are doing. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 28b9803f909b..e9d0a709e207 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -61,3 +61,4 @@ obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o obj-$(CONFIG_OPEN_DICE) += open-dice.o obj-$(CONFIG_TMR_MANAGER) += xilinx_tmr_manager.o +obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o diff --git a/drivers/misc/xilinx_tmr_inject.c b/drivers/misc/xilinx_tmr_inject.c new file mode 100644 index 000000000000..930d89e90b61 --- /dev/null +++ b/drivers/misc/xilinx_tmr_inject.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Xilinx TMR Inject IP. + * + * Copyright (C) 2022 Xilinx, Inc. + * + * Description: + * This driver is developed for TMR Inject IP,The Triple Modular Redundancy(TMR) + * Inject provides fault injection. + * Fault injection and detection features are provided through sysfs entries + * which allow the user to generate a fault. + */ + +#include +#include +#include + +/* TMR Inject Register offsets */ +#define XTMR_INJECT_CR_OFFSET 0x0 +#define XTMR_INJECT_AIR_OFFSET 0x4 +#define XTMR_INJECT_IIR_OFFSET 0xC +#define XTMR_INJECT_EAIR_OFFSET 0x10 +#define XTMR_INJECT_ERR_OFFSET 0x204 + +/* Register Bitmasks/shifts */ +#define XTMR_INJECT_CR_CPUID_SHIFT 8 +#define XTMR_INJECT_CR_IE_SHIFT 10 +#define XTMR_INJECT_IIR_ADDR_MASK GENMASK(31, 16) + +#define XTMR_INJECT_MAGIC_MAX_VAL 255 + +/** + * struct xtmr_inject_dev - Driver data for TMR Inject + * @regs: device physical base address + * @cr_val: control register value + * @magic: Magic hardware configuration value + * @err_cnt: error statistics count + */ +struct xtmr_inject_dev { + void __iomem *regs; + u32 cr_val; + u32 magic; + u32 err_cnt; +}; + +/* IO accessors */ +static inline void xtmr_inject_write(struct xtmr_inject_dev *xtmr_inject, + u32 addr, u32 value) +{ + iowrite32(value, xtmr_inject->regs + addr); +} + +static inline u32 xtmr_inject_read(struct xtmr_inject_dev *xtmr_inject, + u32 addr) +{ + return ioread32(xtmr_inject->regs + addr); +} + +static ssize_t inject_err_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t size) +{ + int ret; + long value; + + ret = kstrtoul(buf, 16, &value); + if (ret) + return ret; + + if (value > 1) + return -EINVAL; + + xmb_inject_err(); + + return size; +} +static DEVICE_ATTR_WO(inject_err); + +static ssize_t inject_cpuid_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct xtmr_inject_dev *xtmr_inject = dev_get_drvdata(dev); + int ret; + long value; + + ret = kstrtoul(buf, 0, &value); + if (ret) + return ret; + + if (value > 3) + return -EINVAL; + + xtmr_inject->cr_val |= (value << XTMR_INJECT_CR_CPUID_SHIFT); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_CR_OFFSET, + xtmr_inject->cr_val); + + return size; +} +static DEVICE_ATTR_WO(inject_cpuid); + +static struct attribute *xtmr_inject_dev_attrs[] = { + &dev_attr_inject_err.attr, + &dev_attr_inject_cpuid.attr, + NULL, +}; +ATTRIBUTE_GROUPS(xtmr_inject_dev); + +static void xtmr_inject_init(struct xtmr_inject_dev *xtmr_inject) +{ + /* Allow fault injection */ + xtmr_inject->cr_val = xtmr_inject->magic | + (1 << XTMR_INJECT_CR_IE_SHIFT) | + (1 << XTMR_INJECT_CR_CPUID_SHIFT); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_CR_OFFSET, + xtmr_inject->cr_val); + /* Initialize the address inject and instruction inject registers */ + xtmr_inject_write(xtmr_inject, XTMR_INJECT_AIR_OFFSET, + XMB_INJECT_ERR_OFFSET); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_IIR_OFFSET, + XMB_INJECT_ERR_OFFSET & XTMR_INJECT_IIR_ADDR_MASK); +} + +/** + * xtmr_inject_probe - Driver probe function + * @pdev: Pointer to the platform_device structure + * + * This is the driver probe routine. It does all the memory + * allocation and creates sysfs entries for the device. + * + * Return: 0 on success and failure value on error + */ +static int xtmr_inject_probe(struct platform_device *pdev) +{ + struct xtmr_inject_dev *xtmr_inject; + int err; + + xtmr_inject = devm_kzalloc(&pdev->dev, sizeof(*xtmr_inject), + GFP_KERNEL); + if (!xtmr_inject) + return -ENOMEM; + + xtmr_inject->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(xtmr_inject->regs)) + return PTR_ERR(xtmr_inject->regs); + + err = of_property_read_u32(pdev->dev.of_node, "xlnx,magic", + &xtmr_inject->magic); + if (err < 0) { + dev_err(&pdev->dev, "unable to read xlnx,magic property"); + return err; + } + + if (xtmr_inject->magic > XTMR_INJECT_MAGIC_MAX_VAL) { + dev_err(&pdev->dev, "invalid xlnx,magic property value"); + return -EINVAL; + } + + /* Initialize TMR Inject */ + xtmr_inject_init(xtmr_inject); + + platform_set_drvdata(pdev, xtmr_inject); + + return 0; +} + +static const struct of_device_id xtmr_inject_of_match[] = { + { + .compatible = "xlnx,tmr-inject-1.0", + }, + { /* end of table */ } +}; +MODULE_DEVICE_TABLE(of, xtmr_inject_of_match); + +static struct platform_driver xtmr_inject_driver = { + .driver = { + .name = "xilinx-tmr_inject", + .of_match_table = xtmr_inject_of_match, + .dev_groups = xtmr_inject_dev_groups, + }, + .probe = xtmr_inject_probe, +}; +module_platform_driver(xtmr_inject_driver); +MODULE_AUTHOR("Xilinx, Inc"); +MODULE_DESCRIPTION("Xilinx TMR Inject Driver"); +MODULE_LICENSE("GPL");