From patchwork Thu Jul 21 16:57:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 12925622 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 216DBC43334 for ; Thu, 21 Jul 2022 16:57:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232217AbiGUQ5V (ORCPT ); Thu, 21 Jul 2022 12:57:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232624AbiGUQ5U (ORCPT ); Thu, 21 Jul 2022 12:57:20 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0053189A6D; Thu, 21 Jul 2022 09:57:18 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,183,1654527600"; d="scan'208";a="126927672" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 22 Jul 2022 01:57:18 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3FDFC400854E; Fri, 22 Jul 2022 01:57:14 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 1/2] dt-bindings: pinctrl: rzg2l-pinctrl: Add macros for IRQ0-7 Date: Thu, 21 Jul 2022 17:57:00 +0100 Message-Id: <20220721165701.17888-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220721165701.17888-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220721165701.17888-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add macros for IRQ0-7 which map to SPI1-8 so that it can be used in dts/i. Signed-off-by: Lad Prabhakar --- v1->v2 * New patch --- include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h index c78ed5e5efb7..6aae2ac206d6 100644 --- a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h +++ b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h @@ -20,4 +20,14 @@ /* Convert a port and pin label to its global pin index */ #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin)) +/* IRQ0-7 map to SPI1-8 */ +#define RZG2L_IRQ0 1 +#define RZG2L_IRQ1 2 +#define RZG2L_IRQ2 3 +#define RZG2L_IRQ3 4 +#define RZG2L_IRQ4 5 +#define RZG2L_IRQ5 6 +#define RZG2L_IRQ6 7 +#define RZG2L_IRQ7 8 + #endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */ From patchwork Thu Jul 21 16:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 12925624 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85F87C43334 for ; Thu, 21 Jul 2022 16:57:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233023AbiGUQ5f (ORCPT ); Thu, 21 Jul 2022 12:57:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232862AbiGUQ5Z (ORCPT ); Thu, 21 Jul 2022 12:57:25 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id DCAA489EB4; Thu, 21 Jul 2022 09:57:22 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,183,1654527600"; d="scan'208";a="126927675" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 22 Jul 2022 01:57:21 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E89414011419; Fri, 22 Jul 2022 01:57:18 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 2/2] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} Date: Thu, 21 Jul 2022 17:57:01 +0100 Message-Id: <20220721165701.17888-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220721165701.17888-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220721165701.17888-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 and ETH1 respectively. Signed-off-by: Lad Prabhakar --- v1->v2 * Used macros of IRQ numbers --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 9410796c8ad6..3ffda0d3fa01 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -120,6 +122,8 @@ phy1: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -171,7 +175,8 @@ eth0_pins: eth0 { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - ; /* ET0_RXD3 */ + , /* ET0_RXD3 */ + ; /* IRQ2 */ }; eth1_pins: eth1 { @@ -189,7 +194,8 @@ eth1_pins: eth1 { , /* ET1_RXD0 */ , /* ET1_RXD1 */ , /* ET1_RXD2 */ - ; /* ET1_RXD3 */ + , /* ET1_RXD3 */ + ; /* IRQ3 */ }; gpio-sd0-pwr-en-hog {