From patchwork Fri Jul 22 08:44:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12926149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18A6EC43334 for ; Fri, 22 Jul 2022 08:44:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234589AbiGVIow (ORCPT ); Fri, 22 Jul 2022 04:44:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234470AbiGVIor (ORCPT ); Fri, 22 Jul 2022 04:44:47 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F3D239F07F; Fri, 22 Jul 2022 01:44:37 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,185,1654527600"; d="scan'208";a="128768950" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 22 Jul 2022 17:44:37 +0900 Received: from localhost.localdomain (unknown [10.226.92.254]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A27CA4228715; Fri, 22 Jul 2022 17:44:33 +0900 (JST) From: Biju Das To: Vinod Koul Cc: Biju Das , Colin Ian King , Dan Carpenter , Lad Prabhakar , dmaengine@vger.kernel.org, Mark Brown , Geert Uytterhoeven , Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4] dmaengine: sh: rz-dmac: Add device_synchronize callback Date: Fri, 22 Jul 2022 09:44:30 +0100 Message-Id: <20220722084430.969333-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Some on-chip peripheral modules(for eg:- rspi) on RZ/G2L SoC use the same signal for both interrupt and DMA transfer requests. The signal works as a DMA transfer request signal by setting DMARS, and subsequent interrupt requests to the interrupt controller are masked. We can re-enable the interrupt by clearing the DMARS. This patch adds device_synchronize callback for clearing DMARS and thereby allowing DMA consumers to switch to interrupt mode. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v3->v4: * Increased delay_us 10->100us and timeout_us 1ms->100ms. v2->v3: * Fixed commit description * Added check if the DMA operation has been completed or terminated, and wait (sleep) if needed. v1->v2: * No change --- drivers/dma/sh/rz-dmac.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index ee2872e7d64c..476847a4916b 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -630,6 +631,21 @@ static void rz_dmac_virt_desc_free(struct virt_dma_desc *vd) */ } +static void rz_dmac_device_synchronize(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); + struct rz_dmac *dmac = to_rz_dmac(chan->device); + u32 chstat; + int ret; + + ret = read_poll_timeout(rz_dmac_ch_readl, chstat, !(chstat & CHSTAT_EN), + 100, 100000, false, channel, CHSTAT, 1); + if (ret < 0) + dev_warn(dmac->dev, "DMA Timeout"); + + rz_dmac_set_dmars_register(dmac, channel->index, 0); +} + /* * ----------------------------------------------------------------------------- * IRQ handling @@ -909,6 +925,7 @@ static int rz_dmac_probe(struct platform_device *pdev) engine->device_config = rz_dmac_config; engine->device_terminate_all = rz_dmac_terminate_all; engine->device_issue_pending = rz_dmac_issue_pending; + engine->device_synchronize = rz_dmac_device_synchronize; engine->copy_align = DMAENGINE_ALIGN_1_BYTE; dma_set_max_seg_size(engine->dev, U32_MAX);