From patchwork Fri Jul 22 15:11:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 12926555 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DAB9C433EF for ; Fri, 22 Jul 2022 15:12:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235605AbiGVPMN (ORCPT ); Fri, 22 Jul 2022 11:12:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229936AbiGVPMK (ORCPT ); Fri, 22 Jul 2022 11:12:10 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4C9A0951EC; Fri, 22 Jul 2022 08:12:09 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,186,1654527600"; d="scan'208";a="127045517" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 23 Jul 2022 00:12:09 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 90C7B432D9F0; Sat, 23 Jul 2022 00:12:05 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 1/3] dt-bindings: interrupt-controller: Add macros for NMI and IRQ0-7 interrupts present on RZ/G2L SoC Date: Fri, 22 Jul 2022 16:11:53 +0100 Message-Id: <20220722151155.21100-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220722151155.21100-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220722151155.21100-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on RZ/G2L (and alike) SoC's so that these can be used in the first cell of Signed-off-by: Lad Prabhakar Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- v3: * New patch as suggested by Biju and Geert. --- .../interrupt-controller/irqc-rzg2l.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h new file mode 100644 index 000000000000..34ce778885a1 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family IRQC bindings. + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_IRQC_RZG2L_H +#define __DT_BINDINGS_IRQC_RZG2L_H + +/* NMI maps to SPI0 */ +#define RZG2L_NMI 0 + +/* IRQ0-7 map to SPI1-8 */ +#define RZG2L_IRQ0 1 +#define RZG2L_IRQ1 2 +#define RZG2L_IRQ2 3 +#define RZG2L_IRQ3 4 +#define RZG2L_IRQ4 5 +#define RZG2L_IRQ5 6 +#define RZG2L_IRQ6 7 +#define RZG2L_IRQ7 8 + +#endif /* __DT_BINDINGS_IRQC_RZG2L_H */ From patchwork Fri Jul 22 15:11:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 12926556 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D542CCA489 for ; Fri, 22 Jul 2022 15:12:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235627AbiGVPMP (ORCPT ); Fri, 22 Jul 2022 11:12:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235619AbiGVPMO (ORCPT ); Fri, 22 Jul 2022 11:12:14 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BF93297D70; Fri, 22 Jul 2022 08:12:13 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,186,1654527600"; d="scan'208";a="127045522" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 23 Jul 2022 00:12:13 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9EDF6432D9F0; Sat, 23 Jul 2022 00:12:09 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 2/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property Date: Fri, 22 Jul 2022 16:11:54 +0100 Message-Id: <20220722151155.21100-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220722151155.21100-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220722151155.21100-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Update description for '#interrupt-cells' property to utilize the RZG2L_{NMI,IRQX} for the first cell defined in the include/dt-bindings/interrupt-controller/irqc-rzg2l.h file. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3: * New patch --- .../bindings/interrupt-controller/renesas,rzg2l-irqc.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index 33b90e975e33..ea7db3618b23 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -31,8 +31,9 @@ properties: - const: renesas,rzg2l-irqc '#interrupt-cells': - description: The first cell should contain external interrupt number (IRQ0-7) and the - second cell is used to specify the flag. + description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the + include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second + cell is used to specify the flag. const: 2 '#address-cells': From patchwork Fri Jul 22 15:11:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 12926557 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDA3BC43334 for ; Fri, 22 Jul 2022 15:12:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235689AbiGVPM1 (ORCPT ); Fri, 22 Jul 2022 11:12:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235655AbiGVPMU (ORCPT ); Fri, 22 Jul 2022 11:12:20 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E2BDE9748E; Fri, 22 Jul 2022 08:12:18 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,186,1654527600"; d="scan'208";a="128798713" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 Jul 2022 00:12:17 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C3D1E432D9F7; Sat, 23 Jul 2022 00:12:13 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} Date: Fri, 22 Jul 2022 16:11:55 +0100 Message-Id: <20220722151155.21100-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220722151155.21100-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220722151155.21100-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 and ETH1 respectively. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3 * Included irqc-rzg2l.h header v1->v2 * Used macros of IRQ numbers --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 9410796c8ad6..c4faff092380 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */ @@ -94,6 +95,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -120,6 +123,8 @@ phy1: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -171,7 +176,8 @@ eth0_pins: eth0 { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - ; /* ET0_RXD3 */ + , /* ET0_RXD3 */ + ; /* IRQ2 */ }; eth1_pins: eth1 { @@ -189,7 +195,8 @@ eth1_pins: eth1 { , /* ET1_RXD0 */ , /* ET1_RXD1 */ , /* ET1_RXD2 */ - ; /* ET1_RXD3 */ + , /* ET1_RXD3 */ + ; /* IRQ3 */ }; gpio-sd0-pwr-en-hog {