From patchwork Mon Jul 25 09:28:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12927918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84D57C433EF for ; Mon, 25 Jul 2022 09:34:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231561AbiGYJc1 (ORCPT ); Mon, 25 Jul 2022 05:32:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229822AbiGYJc1 (ORCPT ); Mon, 25 Jul 2022 05:32:27 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF55913E8A for ; Mon, 25 Jul 2022 02:32:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658741546; x=1690277546; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sYCLhLPVwk8pA42DL08CmkRgLi2ztKgNK8cqO0fxJiw=; b=Ri4cWoU0bx6U5dvRSrArAJ0B+v+EMkyuh5P3QS+jcLfw2EIM7Ap9NcqZ 6B8aRF3nznGtttbFC9EkjdpPMgdts5kmj0Edc/f4B3ulZOUy2Knvv2ypi L3Oc11Dq9qKlDjVZeUOdtnz3deeiV29Cph5m7cn/EZnBPMaCxOAFAp5TP wKSCVvDc75XBUuvUaM628CL29CMYdLV0fM4ashVotAaLImf5/w85+8xIo FD7RwQnTDWJY8bZ3OCA6X2e01NWjZf4qSk1ByvcRFZM4FW3MXIAayQzHE J6s8ywF4E+uBWOHWSavOH5+8AybHb+8L2VRXuxAIn2EPX9EWx+kALxvPD A==; X-IronPort-AV: E=McAfee;i="6400,9594,10418"; a="286414815" X-IronPort-AV: E=Sophos;i="5.93,192,1654585200"; d="scan'208";a="286414815" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2022 02:32:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,192,1654585200"; d="scan'208";a="667421123" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by fmsmga004.fm.intel.com with ESMTP; 25 Jul 2022 02:32:24 -0700 From: Tianfei Zhang To: mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, lee.jones@linaro.org, russell.h.weight@intel.com Cc: hao.wu@intel.com, trix@redhat.com, Tianfei Zhang Subject: [PATCH v2 1/3] mfd: intel-m10-bmc: add m10bmc_sys_update_bits API Date: Mon, 25 Jul 2022 05:28:34 -0400 Message-Id: <20220725092836.647028-2-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220725092836.647028-1-tianfei.zhang@intel.com> References: <20220725092836.647028-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adds register access helper functions for M10BMC. m10bmc_raw_update_bits() uses to update m10bmc register bits per addr. m10bmc_sys_update_bits() uses to update m10bmc system register bits per offset. Signed-off-by: Tianfei Zhang --- include/linux/mfd/intel-m10-bmc.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index f0044b14136e..8e434886a5a1 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -133,6 +133,8 @@ struct intel_m10bmc { * * m10bmc_raw_read - read m10bmc register per addr * m10bmc_sys_read - read m10bmc system register per offset + * m10bmc_raw_update_bits - update m10bmc register bits per addr + * m10bmc_sys_update_bits - update m10bmc system register bits per offset */ static inline int m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, @@ -148,6 +150,20 @@ m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, return ret; } +static inline int +m10bmc_raw_update_bits(struct intel_m10bmc *m10bmc, unsigned int addr, + unsigned int msk, unsigned int val) +{ + int ret; + + ret = regmap_update_bits(m10bmc->regmap, addr, msk, val); + if (ret) + dev_err(m10bmc->dev, "fail to update reg bits %x: %d\n", + addr, ret); + + return ret; +} + /* * The base of the system registers could be configured by HW developers, and * in HW SPEC, the base is not added to the addresses of the system registers. @@ -158,5 +174,7 @@ m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, */ #define m10bmc_sys_read(m10bmc, offset, val) \ m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val) +#define m10bmc_sys_update_bits(m10bmc, offset, msk, val) \ + m10bmc_raw_update_bits(m10bmc, M10BMC_SYS_BASE + (offset), msk, val) #endif /* __MFD_INTEL_M10_BMC_H */ From patchwork Mon Jul 25 09:28:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12927920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55DEDC43334 for ; Mon, 25 Jul 2022 09:34:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231592AbiGYJca (ORCPT ); Mon, 25 Jul 2022 05:32:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229822AbiGYJca (ORCPT ); Mon, 25 Jul 2022 05:32:30 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3251113E8A for ; Mon, 25 Jul 2022 02:32:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658741549; x=1690277549; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5TEQ7BCkmI2NF0aPeH24rvD+ypN3W1LUUZXaaeM7Pjo=; b=mupBV4aCx+vdo3SeyXtySnMuPwReFrPyvI/ShkF/ON/Tj1suNlVdgDkn iXzpQi7Np25ER0JKf34c+df9UzBeuuYlQ5XhPp6CvUJp+a5lktIyK3C8F hNRqDyu/JDrtmYls/9Q6VtfNpHKdDI+Bx+aNH7iKv5UpS///RMk3NQ7XE AmPs+/CSdTw/B7IO4au1rUV5V4i7Ek6CeIo3E88lLsvbK5S2dr7P7aqJI 6zXD7N5OvwjqhhKE9cJ1b43F6vTeRCBPl7Ix3MOtFISkOpYSQZbP5UJxs A2B+01r5tyi1nzKeDvIaFIN5M6mkJ1OFRPMudu8+o1KNDjWsaleKlsxwM w==; X-IronPort-AV: E=McAfee;i="6400,9594,10418"; a="286414823" X-IronPort-AV: E=Sophos;i="5.93,192,1654585200"; d="scan'208";a="286414823" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2022 02:32:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,192,1654585200"; d="scan'208";a="667421148" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by fmsmga004.fm.intel.com with ESMTP; 25 Jul 2022 02:32:26 -0700 From: Tianfei Zhang To: mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, lee.jones@linaro.org, russell.h.weight@intel.com Cc: hao.wu@intel.com, trix@redhat.com, Tianfei Zhang Subject: [PATCH v2 2/3] fpga: m10bmc-sec: add sysfs to reload FPGA/BMC images Date: Mon, 25 Jul 2022 05:28:35 -0400 Message-Id: <20220725092836.647028-3-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220725092836.647028-1-tianfei.zhang@intel.com> References: <20220725092836.647028-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Russ Weight Add the available_images and image_load sysfs files. The available_images file returns a space separated list of key words that may be written into the image_load file. These keywords describe an FPGA, BMC, or firmware image in FLASH or EEPROM storage that may be loaded. The image_load sysfs file may be written with a key word to trigger a reload of an FPGA, BMC, or firmware image from FLASH or EEPROM. Signed-off-by: Russ Weight Signed-off-by: Tianfei Zhang --- v2: adds the steps for how to use the "image_load" sysfs file. --- .../sysfs-driver-intel-m10-bmc-sec-update | 34 ++++++ drivers/fpga/intel-m10-bmc-sec-update.c | 104 ++++++++++++++++++ 2 files changed, 138 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update index 0a41afe0ab4c..3d8f04ca6f1b 100644 --- a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update +++ b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update @@ -59,3 +59,37 @@ Contact: Russ Weight Description: Read only. Returns number of times the secure update staging area has been flashed. Format: "%u". + +What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../control/available_images +Date: July 2022 +KernelVersion: 5.20 +Contact: Russ Weight +Description: Read-only. This file returns a space separated list of + key words that may be written into the image_load file + described below. These keywords decribe an FPGA, BMC, + or firmware image in FLASH or EEPROM storage that may + be loaded. + +What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../control/image_load +Date: July 2022 +KernelVersion: 5.20 +Contact: Russ Weight +Description: Write-only. A key word may be written to this file to + trigger a reload of an FPGA, BMC, or firmware image from + FLASH or EEPROM. Refer to the available_images file for a + list of supported key words for the underlying device. + Writing an unsupported string to this file will result in + EINVAL being returned. + It should remove all of resources related to the old FPGA/BMC + image before trigger the image reload otherwise the host system + may crash. We recommended that follow the below steps or directly + use the OPAE RSU script to perform the reload for FPGA/BMC image. + Here is the steps to trigger the reload for FPGA/BMC image: + 1. disable the AER of the FPGA card. + 2. unbind the PFs/VFs which have bound with VFIO/UIO driver. + 3. trigger image reload via "image_load" sysfs file. + 4. remove all of PCI devices of the FPGA card via + "/sys/bus/pci/devices/xxxx/remove" sysfs file. + 5. wait 10 seconds. + 6. re-scan the PCI bus via "/sys/bus/pci/rescan" sysfs file. + 7. enable the AER of the FPGA card. diff --git a/drivers/fpga/intel-m10-bmc-sec-update.c b/drivers/fpga/intel-m10-bmc-sec-update.c index 72c677c910de..640690e6c131 100644 --- a/drivers/fpga/intel-m10-bmc-sec-update.c +++ b/drivers/fpga/intel-m10-bmc-sec-update.c @@ -14,6 +14,8 @@ #include #include +struct image_load; + struct m10bmc_sec { struct device *dev; struct intel_m10bmc *m10bmc; @@ -21,6 +23,12 @@ struct m10bmc_sec { char *fw_name; u32 fw_name_id; bool cancel_request; + struct image_load *image_load; /* terminated with { } member */ +}; + +struct image_load { + const char *name; + int (*load_image)(struct m10bmc_sec *sec); }; static DEFINE_XARRAY_ALLOC(fw_upload_xa); @@ -137,6 +145,54 @@ DEVICE_ATTR_SEC_CSK_RO(pr, PR_PROG_ADDR + CSK_VEC_OFFSET); #define FLASH_COUNT_SIZE 4096 /* count stored as inverted bit vector */ +static ssize_t available_images_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct m10bmc_sec *sec = dev_get_drvdata(dev); + const struct image_load *hndlr; + ssize_t count = 0; + + for (hndlr = sec->image_load; hndlr->name; hndlr++) { + count += scnprintf(buf + count, PAGE_SIZE - count, + "%s ", hndlr->name); + } + + buf[count - 1] = '\n'; + + return count; +} +static DEVICE_ATTR_RO(available_images); + +static ssize_t image_load_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct m10bmc_sec *sec = dev_get_drvdata(dev); + const struct image_load *hndlr; + int ret = -EINVAL; + + for (hndlr = sec->image_load; hndlr->name; hndlr++) { + if (sysfs_streq(buf, hndlr->name)) { + ret = hndlr->load_image(sec); + break; + } + } + + return ret ? : count; +} +static DEVICE_ATTR_WO(image_load); + +static struct attribute *m10bmc_control_attrs[] = { + &dev_attr_available_images.attr, + &dev_attr_image_load.attr, + NULL, +}; + +static struct attribute_group m10bmc_control_attr_group = { + .name = "control", + .attrs = m10bmc_control_attrs, +}; + static ssize_t flash_count_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -195,6 +251,7 @@ static struct attribute_group m10bmc_security_attr_group = { static const struct attribute_group *m10bmc_sec_attr_groups[] = { &m10bmc_security_attr_group, + &m10bmc_control_attr_group, NULL, }; @@ -208,6 +265,52 @@ static void log_error_regs(struct m10bmc_sec *sec, u32 doorbell) dev_err(sec->dev, "RSU auth result: 0x%08x\n", auth_result); } +static int m10bmc_sec_bmc_image_load(struct m10bmc_sec *sec, + unsigned int val) +{ + u32 doorbell; + int ret; + + if (val > 1) { + dev_err(sec->dev, "invalid reload val = %d\n", val); + return -EINVAL; + } + + ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell); + if (ret) + return ret; + + if (doorbell & DRBL_REBOOT_DISABLED) + return -EBUSY; + + return m10bmc_sys_update_bits(sec->m10bmc, M10BMC_DOORBELL, + DRBL_CONFIG_SEL | DRBL_REBOOT_REQ, + FIELD_PREP(DRBL_CONFIG_SEL, val) | + DRBL_REBOOT_REQ); +} + +static int m10bmc_sec_bmc_image_load_0(struct m10bmc_sec *sec) +{ + return m10bmc_sec_bmc_image_load(sec, 0); +} + +static int m10bmc_sec_bmc_image_load_1(struct m10bmc_sec *sec) +{ + return m10bmc_sec_bmc_image_load(sec, 1); +} + +static struct image_load m10bmc_image_load_hndlrs[] = { + { + .name = "bmc_factory", + .load_image = m10bmc_sec_bmc_image_load_1, + }, + { + .name = "bmc_user", + .load_image = m10bmc_sec_bmc_image_load_0, + }, + {} +}; + static enum fw_upload_err rsu_check_idle(struct m10bmc_sec *sec) { u32 doorbell; @@ -565,6 +668,7 @@ static int m10bmc_sec_probe(struct platform_device *pdev) sec->dev = &pdev->dev; sec->m10bmc = dev_get_drvdata(pdev->dev.parent); dev_set_drvdata(&pdev->dev, sec); + sec->image_load = m10bmc_image_load_hndlrs; ret = xa_alloc(&fw_upload_xa, &sec->fw_name_id, sec, xa_limit_32b, GFP_KERNEL); From patchwork Mon Jul 25 09:28:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12927919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46C92C433EF for ; Mon, 25 Jul 2022 09:34:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232643AbiGYJcc (ORCPT ); Mon, 25 Jul 2022 05:32:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229822AbiGYJcc (ORCPT ); Mon, 25 Jul 2022 05:32:32 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58F6713E8A for ; Mon, 25 Jul 2022 02:32:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658741551; x=1690277551; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5OhNO3QKRYcfdKbQEgyyRfE3Soczzj0MVnPRAls7E4g=; b=EWfyjpQsfgM6I53gfuiittmeLTXHiwl04hdnllUO22k9BSQGTy165Iw4 wwuwB7bO3ZZUD2fibVLroX2XrO0rYdP/oY69mnRkIqhsop1gSTwOaYGiK SO9KZMipBjlFZpwdybCAnIPVMvVcPnZOiOa8KgpgX24wQSOi6FVG9LLWe W878rrFy+y31AAgrhXMvTCDGGde3xRf9fg/ttgFJ6F1jOpnNi5S+pTYs6 1h2Ilzj1+c/lL7vSTVmPjJp2x/5nLpF9k9wYQPgeQ7KDfIyNLk70NVJAN gOm70GKOJdREwFCNxEwdi6uxX6csL5pjBNCk0q/8l5w0UeMITjQnjWagV A==; X-IronPort-AV: E=McAfee;i="6400,9594,10418"; a="286414831" X-IronPort-AV: E=Sophos;i="5.93,192,1654585200"; d="scan'208";a="286414831" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2022 02:32:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,192,1654585200"; d="scan'208";a="667421160" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by fmsmga004.fm.intel.com with ESMTP; 25 Jul 2022 02:32:29 -0700 From: Tianfei Zhang To: mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, lee.jones@linaro.org, russell.h.weight@intel.com Cc: hao.wu@intel.com, trix@redhat.com, Tianfei Zhang Subject: [PATCH v2 3/3] fpga: m10bmc-sec: add m10bmc_sec_retimer_load callback Date: Mon, 25 Jul 2022 05:28:36 -0400 Message-Id: <20220725092836.647028-4-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220725092836.647028-1-tianfei.zhang@intel.com> References: <20220725092836.647028-1-tianfei.zhang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Russ Weight Create m10bmc_sec_retimer_load() callback function to provide a trigger to update a new retimer (Intel C827 Ethernet transceiver) firmware on Intel PAC N3000 Card. Signed-off-by: Russ Weight Signed-off-by: Tianfei Zhang --- drivers/fpga/intel-m10-bmc-sec-update.c | 146 ++++++++++++++++++++++++ include/linux/mfd/intel-m10-bmc.h | 31 +++++ 2 files changed, 177 insertions(+) diff --git a/drivers/fpga/intel-m10-bmc-sec-update.c b/drivers/fpga/intel-m10-bmc-sec-update.c index 640690e6c131..707dfd8a1931 100644 --- a/drivers/fpga/intel-m10-bmc-sec-update.c +++ b/drivers/fpga/intel-m10-bmc-sec-update.c @@ -299,6 +299,148 @@ static int m10bmc_sec_bmc_image_load_1(struct m10bmc_sec *sec) return m10bmc_sec_bmc_image_load(sec, 1); } +static int trigger_retimer_eeprom_load(struct m10bmc_sec *sec) +{ + struct intel_m10bmc *m10bmc = sec->m10bmc; + unsigned int val; + int ret; + + ret = m10bmc_sys_update_bits(m10bmc, M10BMC_DOORBELL, + DRBL_PKVL_EEPROM_LOAD_SEC, + DRBL_PKVL_EEPROM_LOAD_SEC); + if (ret) + return ret; + + /* + * If the current NIOS FW supports this retimer update feature, then + * it will clear the same PKVL_EEPROM_LOAD bit in 2 seconds. Otherwise + * the driver needs to clear the PKVL_EEPROM_LOAD bit manually and + * return an error code. + */ + ret = regmap_read_poll_timeout(m10bmc->regmap, + M10BMC_SYS_BASE + M10BMC_DOORBELL, val, + (!(val & DRBL_PKVL_EEPROM_LOAD_SEC)), + M10BMC_PKVL_LOAD_INTERVAL_US, + M10BMC_PKVL_LOAD_TIMEOUT_US); + if (ret == -ETIMEDOUT) { + dev_err(sec->dev, "PKVL_EEPROM_LOAD clear timedout\n"); + m10bmc_sys_update_bits(m10bmc, M10BMC_DOORBELL, + DRBL_PKVL_EEPROM_LOAD_SEC, 0); + ret = -ENODEV; + } else if (ret) { + dev_err(sec->dev, "poll EEPROM_LOAD error %d\n", ret); + } + + return ret; +} + +static int poll_retimer_eeprom_load_done(struct m10bmc_sec *sec) +{ + struct intel_m10bmc *m10bmc = sec->m10bmc; + unsigned int doorbell; + int ret; + + /* + * RSU_STAT_PKVL_REJECT indicates that the current image is + * already programmed. RSU_PROG_PKVL_PROM_DONE that the firmware + * update process has finished, but does not necessarily indicate + * a successful update. + */ + ret = regmap_read_poll_timeout(m10bmc->regmap, + M10BMC_SYS_BASE + M10BMC_DOORBELL, + doorbell, + ((rsu_prog(doorbell) == + RSU_PROG_PKVL_PROM_DONE) || + (rsu_stat(doorbell) == + RSU_STAT_PKVL_REJECT)), + M10BMC_PKVL_PRELOAD_INTERVAL_US, + M10BMC_PKVL_PRELOAD_TIMEOUT_US); + if (ret) { + if (ret == -ETIMEDOUT) + dev_err(sec->dev, + "Doorbell check timedout: 0x%08x\n", doorbell); + else + dev_err(sec->dev, "poll Doorbell error\n"); + return ret; + } + + if (rsu_stat(doorbell) == RSU_STAT_PKVL_REJECT) { + dev_err(sec->dev, "duplicate image rejected\n"); + return -ECANCELED; + } + + return 0; +} + +static int poll_retimer_preload_done(struct m10bmc_sec *sec) +{ + struct intel_m10bmc *m10bmc = sec->m10bmc; + unsigned int val; + int ret; + + /* + * Wait for the updated firmware to be loaded by the PKVL device + * and confirm that the updated firmware is operational + */ + ret = regmap_read_poll_timeout(m10bmc->regmap, + M10BMC_SYS_BASE + M10BMC_PKVL_POLL_CTRL, val, + ((val & M10BMC_PKVL_PRELOAD) == M10BMC_PKVL_PRELOAD), + M10BMC_PKVL_PRELOAD_INTERVAL_US, + M10BMC_PKVL_PRELOAD_TIMEOUT_US); + if (ret) { + dev_err(sec->dev, "poll M10BMC_PKVL_PRELOAD error %d\n", ret); + return ret; + } + + if ((val & M10BMC_PKVL_UPG_STATUS_MASK) != M10BMC_PKVL_UPG_STATUS_GOOD) { + dev_err(sec->dev, "error detected during upgrade\n"); + return -EIO; + } + + return 0; +} + +static int retimer_check_idle(struct m10bmc_sec *sec) +{ + u32 doorbell; + int ret; + + ret = m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell); + if (ret) + return -EIO; + + if (rsu_prog(doorbell) != RSU_PROG_IDLE && + rsu_prog(doorbell) != RSU_PROG_RSU_DONE && + rsu_prog(doorbell) != RSU_PROG_PKVL_PROM_DONE) { + log_error_regs(sec, doorbell); + return -EBUSY; + } + + return 0; +} + +static int m10bmc_sec_retimer_eeprom_load(struct m10bmc_sec *sec) +{ + int ret; + + ret = retimer_check_idle(sec); + if (ret) + goto exit; + + ret = trigger_retimer_eeprom_load(sec); + if (ret) + goto exit; + + ret = poll_retimer_eeprom_load_done(sec); + if (ret) + goto exit; + + ret = poll_retimer_preload_done(sec); + +exit: + return ret; +} + static struct image_load m10bmc_image_load_hndlrs[] = { { .name = "bmc_factory", @@ -308,6 +450,10 @@ static struct image_load m10bmc_image_load_hndlrs[] = { .name = "bmc_user", .load_image = m10bmc_sec_bmc_image_load_0, }, + { + .name = "retimer_fw", + .load_image = m10bmc_sec_retimer_eeprom_load, + }, {} }; diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h index 8e434886a5a1..23025e4d2779 100644 --- a/include/linux/mfd/intel-m10-bmc.h +++ b/include/linux/mfd/intel-m10-bmc.h @@ -36,6 +36,37 @@ #define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24) #define M10BMC_VER_LEGACY_INVALID 0xffffffff +/* Retimer related registers, in system register region */ +#define M10BMC_PKVL_POLL_CTRL 0x80 +#define M10BMC_PKVL_A_PRELOAD BIT(16) +#define M10BMC_PKVL_A_PRELOAD_TO BIT(17) +#define M10BMC_PKVL_A_DATA_TOO_BIG BIT(18) +#define M10BMC_PKVL_A_HDR_CKSUM BIT(20) +#define M10BMC_PKVL_B_PRELOAD BIT(24) +#define M10BMC_PKVL_B_PRELOAD_TO BIT(25) +#define M10BMC_PKVL_B_DATA_TOO_BIG BIT(26) +#define M10BMC_PKVL_B_HDR_CKSUM BIT(28) + +#define M10BMC_PKVL_PRELOAD (M10BMC_PKVL_A_PRELOAD | M10BMC_PKVL_B_PRELOAD) +#define M10BMC_PKVL_PRELOAD_TIMEOUT (M10BMC_PKVL_A_PRELOAD_TO | \ + M10BMC_PKVL_B_PRELOAD_TO) +#define M10BMC_PKVL_DATA_TOO_BIG (M10BMC_PKVL_A_DATA_TOO_BIG | \ + M10BMC_PKVL_B_DATA_TOO_BIG) +#define M10BMC_PKVL_HDR_CHECKSUM (M10BMC_PKVL_A_HDR_CKSUM | \ + M10BMC_PKVL_B_HDR_CKSUM) + +#define M10BMC_PKVL_UPG_STATUS_MASK (M10BMC_PKVL_PRELOAD | M10BMC_PKVL_PRELOAD_TIMEOUT |\ + M10BMC_PKVL_DATA_TOO_BIG | M10BMC_PKVL_HDR_CHECKSUM) +#define M10BMC_PKVL_UPG_STATUS_GOOD (M10BMC_PKVL_PRELOAD | M10BMC_PKVL_HDR_CHECKSUM) + +/* interval 100ms and timeout 2s */ +#define M10BMC_PKVL_LOAD_INTERVAL_US (100 * 1000) +#define M10BMC_PKVL_LOAD_TIMEOUT_US (2 * 1000 * 1000) + +/* interval 100ms and timeout 30s */ +#define M10BMC_PKVL_PRELOAD_INTERVAL_US (100 * 1000) +#define M10BMC_PKVL_PRELOAD_TIMEOUT_US (30 * 1000 * 1000) + /* Secure update doorbell register, in system register region */ #define M10BMC_DOORBELL 0x400