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[88.207.96.123]) by smtp.googlemail.com with ESMTPSA id h14-20020aa7de0e000000b0043a7404314csm7124969edv.8.2022.07.25.06.15.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 06:15:27 -0700 (PDT) From: Robert Marko To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lars.povlsen@microchip.com, Steen.Hegelund@microchip.com, UNGLinuxDriver@microchip.com, arnd@arndb.de, alexandre.belloni@bootlin.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 1/2] arm64: dts: microchip: sparx5: remove PSCI Date: Mon, 25 Jul 2022 15:15:20 +0200 Message-Id: <20220725131521.607904-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220725_061533_745542_2A3B6AA6 X-CRM114-Status: GOOD ( 11.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that is shipped does not implement it as well. I have tried flashing the latest vendor BSP U-boot which did not work. After contacting Microchip, they confirmed that there is no ATF for the SoC nor PSCI implementation which is unfortunate in 2022. So, disable PSCI as otherwise kernel crashes as soon as it tries probing PSCI with, and the crash is only visible if earlycon is used. Tested on PCB134 with eMMC (VSC5640EV). Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 2dd5e38820b1..38da24c1796c 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -61,11 +61,6 @@ arm-pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - timer { compatible = "arm,armv8-timer"; interrupts = , From patchwork Mon Jul 25 13:15:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12928056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9994C43334 for ; Mon, 25 Jul 2022 13:16:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Th2nOoEPuIo2n5dEpqNLgbSTDIRfzphfCM3H9vNQV1E=; b=knIbdKjLQCFOD4 BCGPu3M8IYu6QPS7XMRkjNG+GxEWOJozzht+bFDTUNzPXDgqS6XsuzItd71UOsZ6/2XkymJLxAwdQ f6o1n+ycJS5OZsMof8dD5eEWADsJy+mQvQepjva+gTjPFMpV5jTPp2DpT86BYVQPDQwglJ1POBFj5 Olh7UuHLKSYUz1NYYhslD5s5LvK72xvz2DsDLdbdWMjikI54fycIJEoy6WHIq9QLQ9J2+LjdmeVaR dVsOCPEBeSGepnE9dYnwn7ZHjR72g4SMFPj+HWoGqXN7DFpuf4im1nhJt4DK1fgNhLulyvC1Rnyfm Q3lwfo7Ak8oQo2pFgRWA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oFxvt-009vum-KQ; Mon, 25 Jul 2022 13:15:38 +0000 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oFxvp-009vrZ-3f for linux-arm-kernel@lists.infradead.org; Mon, 25 Jul 2022 13:15:35 +0000 Received: by mail-ej1-x635.google.com with SMTP id b11so20442207eju.10 for ; Mon, 25 Jul 2022 06:15:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=domnjDOtqAB91aCICPafBq6z6sV4iwkBiMXWT2WHMNE=; b=G3FoQYpQwwLsTTQFIeiZbihJ6qL3bfM62n8yx0JoT6U1YSSv7j2zORAJNDXPT2zq36 56zFvFBs6je5wRPYEXG9jbC8jIiva/L91gp3xJOyueqlQCzIiXVifilDDP/tsX2+UYfz YwKK15/hkp0xWntlDLdUL+5SjyZ5p3DXJjZgXbrM2UC1GcsZtQxjORxjyolADy6IzI5D VQeuDgrVPqx1+9GZoVNXNKrZJF2HddkjM1/qfqrxk1H4Gr9e2ETV9fMssw2PkJMsvIcW 9tLE7uZaJtVPWdWlAlEVOmmYsu7ZBVOsHLoFkgMuqUfNJCHivVtYm7ZAD3KLJA09hFVa p+BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=domnjDOtqAB91aCICPafBq6z6sV4iwkBiMXWT2WHMNE=; b=uvx8Onm0/1jGhSHGGzS6z9qbEkV5Rm21xVbQsJum4SF7W1t/AdF/LwMl1EONHcWk6s 3UOm6fQta+JvlDY6oZ8lyqmdCNc0nMEABSWpbme+mXKYaGmmozlJ2+5NdVboI9tpH6TM NYA47O+f9ChXAo71/6WuK+IFx1v6ZexD1wrt9AJb64OiQNPaSisXV0MFpY2OLMyNDyU0 4UV04XtIsYgXs+ZGO9EGXXfz6O1YH2Yr3YfOax9ZwLztJreEljuViMxkbesb7UbG4sSi O/Zjk3SgGtATK9048UGuVosRZO8AMTcUZ68bLVjk30nskTdXckl3bvdxMt9CjJjGhowB 3OPw== X-Gm-Message-State: AJIora8FmEeDs4l90GO3K63mPabLHlWAUNp8a3lvrGC6p44xSzyRS9ud padnlDG8aPNcrLxN4R5Aa+45Kg== X-Google-Smtp-Source: AGRyM1vbn0uxKG9yd38dm3MoY+VQP7HLeT05n7Y7EhUdFNEBm839y34wCEkIz97+vzXzKukkr8//jw== X-Received: by 2002:a17:906:9b09:b0:72b:9612:d373 with SMTP id eo9-20020a1709069b0900b0072b9612d373mr9842259ejc.606.1658754931016; Mon, 25 Jul 2022 06:15:31 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-96-123.xnet.hr. [88.207.96.123]) by smtp.googlemail.com with ESMTPSA id h14-20020aa7de0e000000b0043a7404314csm7124969edv.8.2022.07.25.06.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 06:15:29 -0700 (PDT) From: Robert Marko To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lars.povlsen@microchip.com, Steen.Hegelund@microchip.com, UNGLinuxDriver@microchip.com, arnd@arndb.de, alexandre.belloni@bootlin.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 2/2] arm64: dts: microchip: sparx5: dont use PSCI for core bringup Date: Mon, 25 Jul 2022 15:15:21 +0200 Message-Id: <20220725131521.607904-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220725131521.607904-1-robert.marko@sartura.hr> References: <20220725131521.607904-1-robert.marko@sartura.hr> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220725_061533_382629_0F22A605 X-CRM114-Status: GOOD ( 12.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As described in previous commit, PSCI is not implemented on this SoC at all, so use spin-tables to bringup the cores. Tested on PCB134 with eMMC (VSC5640EV). Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 38da24c1796c..ea2b07ca2887 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -40,14 +40,16 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; next-level-cache = <&L2_0>; }; L2_0: l2-cache0 {