From patchwork Mon Jul 25 16:39:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 12928270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57F0CCCA48D for ; Mon, 25 Jul 2022 16:39:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236329AbiGYQjN (ORCPT ); Mon, 25 Jul 2022 12:39:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236322AbiGYQjM (ORCPT ); Mon, 25 Jul 2022 12:39:12 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D97591CFEA; Mon, 25 Jul 2022 09:39:11 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3FC7CD6E; Mon, 25 Jul 2022 09:39:12 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.28.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 76B953F73D; Mon, 25 Jul 2022 09:39:11 -0700 (PDT) From: Jeremy Linton To: linux-pci@vger.kernel.org Cc: will@kernel.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lpieralisi@kernel.org, kw@linux.com, mark.rutland@arm.com, sudeep.holla@arm.com, boqun.feng@gmail.com, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH 1/4] arm64: smccc: Add PCI SMCCCs Date: Mon, 25 Jul 2022 11:39:02 -0500 Message-Id: <20220725163905.2024437-2-jeremy.linton@arm.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220725163905.2024437-1-jeremy.linton@arm.com> References: <20220725163905.2024437-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Arm defined a set of SMC calls for accessing PCIe config space in The Arm PCI Configuration Space Access Firmware Interface: https://developer.arm.com/documentation/den0115/latest Add the definitions. Signed-off-by: Jeremy Linton --- include/linux/arm-smccc.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 220c8c60e021..1071a997ba98 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -182,6 +182,35 @@ ARM_SMCCC_OWNER_STANDARD, \ 0x53) +/* PCI ECAM conduit (defined by ARM DEN0115A) */ +#define SMCCC_PCI_VERSION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, 0x0130) + +#define SMCCC_PCI_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, 0x0131) + +#define SMCCC_PCI_READ \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, 0x0132) + +#define SMCCC_PCI_WRITE \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, 0x0133) + +#define SMCCC_PCI_SEG_INFO \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, 0x0134) + +#define SMCCC_PCI_SEG_INFO_START_BUS GENMASK(7, 0) +#define SMCCC_PCI_SEG_INFO_END_BUS GENMASK(15, 8) + /* * Return codes defined in ARM DEN 0070A * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C From patchwork Mon Jul 25 16:39:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 12928271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53D1AC43334 for ; Mon, 25 Jul 2022 16:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236384AbiGYQjU (ORCPT ); Mon, 25 Jul 2022 12:39:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236366AbiGYQjQ (ORCPT ); Mon, 25 Jul 2022 12:39:16 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 90D251D0D7; Mon, 25 Jul 2022 09:39:13 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1666139F; Mon, 25 Jul 2022 09:39:13 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.28.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2424C3F73D; Mon, 25 Jul 2022 09:39:13 -0700 (PDT) From: Jeremy Linton To: linux-pci@vger.kernel.org Cc: will@kernel.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lpieralisi@kernel.org, kw@linux.com, mark.rutland@arm.com, sudeep.holla@arm.com, boqun.feng@gmail.com, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH 2/4] arm64: PCI: Enable SMC conduit Date: Mon, 25 Jul 2022 11:39:03 -0500 Message-Id: <20220725163905.2024437-3-jeremy.linton@arm.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220725163905.2024437-1-jeremy.linton@arm.com> References: <20220725163905.2024437-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Given that most arm64 platforms' PCI implementations need quirks to deal with problematic config accesses, this is a good place to apply a firmware abstraction. The ARM PCI Configuration Space Access Firmware Interface specification details a standard SMC conduit designed to provide a simple PCI config accessor. This specification enhances the existing ACPI/PCI abstraction and expects power, config, etc., is handled by the platform. It also is very explicit that the resulting config space registers must behave as is specified by the PCI specification. Hook the ACPI/PCI config path, and when missing MCFG data is detected, attempt to probe the SMC conduit. If the conduit exists and responds to the requested segment, provided by the ACPI namespace, attach a custom pci_ecam_ops which redirects all config read/write requests to the firmware. The Arm PCI Configuration Space Access Firmware Interface: https://developer.arm.com/documentation/den0115/latest Signed-off-by: Jeremy Linton --- arch/arm64/kernel/pci.c | 109 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index 2276689b5411..beb4289a7471 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -122,6 +123,112 @@ static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) return status; } +int pcie_has_fw_conduit(void) +{ + struct arm_smccc_res res; + + if (arm_smccc_1_1_get_conduit() == SMCCC_CONDUIT_NONE) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(SMCCC_PCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + if ((int)res.a0 < 0) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(SMCCC_PCI_FEATURES, + SMCCC_PCI_WRITE, 0, 0, 0, 0, 0, 0, &res); + if ((int)res.a0 < 0) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(SMCCC_PCI_FEATURES, + SMCCC_PCI_READ, 0, 0, 0, 0, 0, 0, &res); + if ((int)res.a0 < 0) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(SMCCC_PCI_FEATURES, + SMCCC_PCI_SEG_INFO, 0, 0, 0, 0, 0, 0, &res); + if ((int)res.a0 < 0) + return -EOPNOTSUPP; + + return 0; +} + +static int smccc_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct arm_smccc_res res; + + devfn |= bus->number << 8; + devfn |= bus->domain_nr << 16; + + arm_smccc_1_1_invoke(SMCCC_PCI_READ, devfn, where, size, + 0, 0, 0, 0, &res); + if (res.a0) { + *val = ~0; + return -PCIBIOS_BAD_REGISTER_NUMBER; + } + + *val = res.a1; + return PCIBIOS_SUCCESSFUL; +} + +static int smccc_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct arm_smccc_res res; + + devfn |= bus->number << 8; + devfn |= bus->domain_nr << 16; + + arm_smccc_1_1_invoke(SMCCC_PCI_WRITE, devfn, where, size, val, + 0, 0, 0, &res); + if (res.a0) + return -PCIBIOS_BAD_REGISTER_NUMBER; + + return PCIBIOS_SUCCESSFUL; +} + +static const struct pci_ecam_ops smccc_pcie_ops = { + .pci_ops = { + .read = smccc_pcie_config_read, + .write = smccc_pcie_config_write, + } +}; + + +struct pci_config_window * +pci_setup_fw_mapping(struct device *dev, u16 seg, struct resource *bus_res) +{ + struct arm_smccc_res res; + struct pci_config_window *cfg; + + arm_smccc_1_1_invoke(SMCCC_PCI_SEG_INFO, seg, 0, 0, 0, 0, 0, 0, &res); + if ((int)res.a0 < 0) { + pr_warn("PCI: SMC segment %d doesn't exist\n", seg); + return NULL; + } + + if (FIELD_GET(SMCCC_PCI_SEG_INFO_START_BUS, res.a1) != bus_res->start || + FIELD_GET(SMCCC_PCI_SEG_INFO_END_BUS, res.a1) != bus_res->end) { + pr_warn("PCI: SMC segment %d doesn't match ACPI description\n", seg); + return NULL; + } + + cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); + if (!cfg) + return NULL; + + cfg->parent = dev; + cfg->ops = &smccc_pcie_ops; + cfg->busr.start = FIELD_GET(SMCCC_PCI_SEG_INFO_START_BUS, res.a1); + cfg->busr.end = FIELD_GET(SMCCC_PCI_SEG_INFO_END_BUS, res.a1); + cfg->busr.flags = IORESOURCE_BUS; + cfg->res.name = "PCI SMCCC"; + + pr_info("PCI: SMC conduit attached to segment %d\n", seg); + + return cfg; +} + /* * Lookup the bus range for the domain in MCFG, and set up config space * mapping. @@ -140,6 +247,8 @@ pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); if (ret) { + if (!pcie_has_fw_conduit()) + return pci_setup_fw_mapping(dev, seg, bus_res); dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); return NULL; } From patchwork Mon Jul 25 16:39:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 12928272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64B17CCA48A for ; Mon, 25 Jul 2022 16:39:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236404AbiGYQjW (ORCPT ); Mon, 25 Jul 2022 12:39:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236338AbiGYQjQ (ORCPT ); Mon, 25 Jul 2022 12:39:16 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D2B7F1CFFB; Mon, 25 Jul 2022 09:39:14 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2CD1D152B; Mon, 25 Jul 2022 09:39:15 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.28.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 63D843F73D; Mon, 25 Jul 2022 09:39:14 -0700 (PDT) From: Jeremy Linton To: linux-pci@vger.kernel.org Cc: will@kernel.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lpieralisi@kernel.org, kw@linux.com, mark.rutland@arm.com, sudeep.holla@arm.com, boqun.feng@gmail.com, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH 3/4] PCI: host-generic: Add firmware managed config ops Date: Mon, 25 Jul 2022 11:39:04 -0500 Message-Id: <20220725163905.2024437-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220725163905.2024437-1-jeremy.linton@arm.com> References: <20220725163905.2024437-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The generic PCI host driver leaves the configuration and mgmt of the clock/phy/etc on PCI root ports to the firmware and PCIe defined mechanisms as is done on UEFI/ACPI systems. If the PCIe config operations were abstracted as well then a number of the resulting Linux PCie drivers would no longer be needed. Given that Arm has standardized a generic SMC conduit for reading and writing the PCIe config space. Using it on DT based systems seems a natural way to reduce some of the driver diversity on DT based systems as well. This patch adds a compatible type "pci-host-smc-generic" which expects that the 'reg' property of the root port is missing, and the PCI SMCCC exists. When that happens it binds the SMC to the pci_ecam_ops. Signed-off-by: Jeremy Linton --- drivers/pci/controller/pci-host-common.c | 34 ++++++++++++++++------- drivers/pci/controller/pci-host-generic.c | 6 ++++ 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c index d3924a44db02..2673fd81d3e0 100644 --- a/drivers/pci/controller/pci-host-common.c +++ b/drivers/pci/controller/pci-host-common.c @@ -20,22 +20,41 @@ static void gen_pci_unmap_cfg(void *ptr) pci_ecam_free((struct pci_config_window *)ptr); } +__weak int pcie_has_fw_conduit(void) +{ + return -EOPNOTSUPP; +} + +__weak struct pci_config_window *pci_setup_fw_mapping(struct device *dev, + u16 seg, struct resource *bus_res) +{ + return NULL; +} + static struct pci_config_window *gen_pci_init(struct device *dev, - struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops) + struct pci_host_bridge *bridge) { int err; struct resource cfgres; struct resource_entry *bus; struct pci_config_window *cfg; + const struct pci_ecam_ops *ops; + + bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!bus) + return ERR_PTR(-ENODEV); err = of_address_to_resource(dev->of_node, 0, &cfgres); if (err) { + if (!pcie_has_fw_conduit()) + return pci_setup_fw_mapping(dev, bridge->busnr, bus->res); + dev_err(dev, "missing \"reg\" property\n"); return ERR_PTR(err); } - bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); - if (!bus) + ops = of_device_get_match_data(dev); + if (!ops) return ERR_PTR(-ENODEV); cfg = pci_ecam_create(dev, &cfgres, bus->res, ops); @@ -54,11 +73,6 @@ int pci_host_common_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct pci_host_bridge *bridge; struct pci_config_window *cfg; - const struct pci_ecam_ops *ops; - - ops = of_device_get_match_data(&pdev->dev); - if (!ops) - return -ENODEV; bridge = devm_pci_alloc_host_bridge(dev, 0); if (!bridge) @@ -69,7 +83,7 @@ int pci_host_common_probe(struct platform_device *pdev) of_pci_check_probe_only(); /* Parse and map our Configuration Space windows */ - cfg = gen_pci_init(dev, bridge, ops); + cfg = gen_pci_init(dev, bridge); if (IS_ERR(cfg)) return PTR_ERR(cfg); @@ -78,7 +92,7 @@ int pci_host_common_probe(struct platform_device *pdev) pci_add_flags(PCI_REASSIGN_ALL_BUS); bridge->sysdata = cfg; - bridge->ops = (struct pci_ops *)&ops->pci_ops; + bridge->ops = (struct pci_ops *)&cfg->ops->pci_ops; bridge->msi_domain = true; return pci_host_probe(bridge); diff --git a/drivers/pci/controller/pci-host-generic.c b/drivers/pci/controller/pci-host-generic.c index 63865aeb636b..d20d33b3c689 100644 --- a/drivers/pci/controller/pci-host-generic.c +++ b/drivers/pci/controller/pci-host-generic.c @@ -56,6 +56,9 @@ static const struct pci_ecam_ops pci_dw_ecam_bus_ops = { } }; +static const struct pci_ecam_ops pci_generic_smc_ops = { +}; + static const struct of_device_id gen_pci_of_match[] = { { .compatible = "pci-host-cam-generic", .data = &gen_pci_cfg_cam_bus_ops }, @@ -63,6 +66,9 @@ static const struct of_device_id gen_pci_of_match[] = { { .compatible = "pci-host-ecam-generic", .data = &pci_generic_ecam_ops }, + { .compatible = "pci-host-smc-generic", + .data = &pci_generic_smc_ops }, + { .compatible = "marvell,armada8k-pcie-ecam", .data = &pci_dw_ecam_bus_ops }, From patchwork Mon Jul 25 16:39:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 12928273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E365ECCA473 for ; Mon, 25 Jul 2022 16:39:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236425AbiGYQjX (ORCPT ); Mon, 25 Jul 2022 12:39:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236347AbiGYQjR (ORCPT ); Mon, 25 Jul 2022 12:39:17 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 129FA1D303; Mon, 25 Jul 2022 09:39:16 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 654AA153B; Mon, 25 Jul 2022 09:39:16 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.28.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9B5163F73D; Mon, 25 Jul 2022 09:39:15 -0700 (PDT) From: Jeremy Linton To: linux-pci@vger.kernel.org Cc: will@kernel.org, bhelgaas@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lpieralisi@kernel.org, kw@linux.com, mark.rutland@arm.com, sudeep.holla@arm.com, boqun.feng@gmail.com, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH 4/4] dt-bindings: PCI: Note the use of pci-host-smc-generic Date: Mon, 25 Jul 2022 11:39:05 -0500 Message-Id: <20220725163905.2024437-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220725163905.2024437-1-jeremy.linton@arm.com> References: <20220725163905.2024437-1-jeremy.linton@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Note the addition of pci-host-smc-generic for firmware based config assistance, and the relaxation of the 'reg' property for such machines. Signed-off-by: Jeremy Linton --- .../bindings/pci/host-generic-pci.yaml | 24 ++++++++++++++----- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml index 6bcaa8f2c3cf..b4471617fa46 100644 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml @@ -18,10 +18,11 @@ description: | presenting a set of fixed windows describing a subset of IO, Memory and Configuration Spaces. - Configuration Space is assumed to be memory-mapped (as opposed to being - accessed via an ioport) and laid out with a direct correspondence to the - geography of a PCI bus address by concatenating the various components to - form an offset. + Configuration Space is assumed to be laid out with a direct correspondence + to the geography of a PCI bus address by concatenating the various components + to form an offset. The CAM and ECAM mechanisms require a memory mapped + interface, while the SMC traps to the firmware to perform config space + reads and writes decoded similarly to the ECAM mapping. For CAM, this 24-bit offset is: @@ -86,6 +87,7 @@ properties: enum: - pci-host-cam-generic - pci-host-ecam-generic + - pci-host-smc-generic reg: description: @@ -93,7 +95,8 @@ properties: bus. The base address corresponds to the first bus in the "bus-range" property. If no "bus-range" is specified, this will be bus 0 (the default). Some host controllers have a 2nd non-compliant address range, - so 2 entries are allowed. + so 2 entries are allowed. Machines which implement the Arm PCI SMCCC spec + must not provide this property. minItems: 1 maxItems: 2 @@ -109,7 +112,6 @@ properties: required: - compatible - - reg - ranges allOf: @@ -123,6 +125,16 @@ allOf: required: - dma-coherent + - if: + properties: + compatible: + not: + contains: + const: pci-host-smc-generic + then: + required: + - reg + - if: properties: compatible: