From patchwork Tue Aug 2 17:57:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAF1DC00140 for ; Tue, 2 Aug 2022 17:58:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234970AbiHBR62 (ORCPT ); Tue, 2 Aug 2022 13:58:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230319AbiHBR61 (ORCPT ); Tue, 2 Aug 2022 13:58:27 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F6154F67E for ; Tue, 2 Aug 2022 10:58:25 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id c22so7579610wmr.2 for ; Tue, 02 Aug 2022 10:58:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vuo/vfkePpTgDDEhsrHOq8e5JZuKt6L4eA032kLF7mw=; b=PnFR54/krkQJBd9Cf9a4Xk/Fct0bWlowlgRa8ZaGY0hDslopTBk/b9JuMhEE9wm0nj f9CPxt4/15USCxyOb217JyqZOsQiP71VknMujxa5tmHdA9j3grppFgZSa9oqCWasMW3X txoksfC18gjyehYqyKNPtqZ4iYmIzSLBx9gFa9dYdLB5kX1fLLZpG/fADDodDAvQ1PtN SguY7LD2ouWC1j5H065nWm5J44FSj+T9zZmpase271yDX06aSD6u2v8YGIjDyfhAX4Ap 3QM+OZJ7Wxo1toFmslEvOmVhaDxVBB0YAAsfT0YMVsS6xXy//CvoCTVYgfPLxQuA1OmZ tygQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vuo/vfkePpTgDDEhsrHOq8e5JZuKt6L4eA032kLF7mw=; b=DDo+kZpGbrkRBF2muwDhJrXDAAGOXPQNKKLR2y46m+a7YSBJLL91d4utRydstn0QGG zCG9dNk+9UgTET7LEAsO0pyz1xI9D2PhP/1XLDMpRjHjfOYKCqO0I6+tVxuHzWPFnwuH ucjoJp+9taWiXkRy2VLERQlHOXHDjpIOF8/8w78ALCt+o6qeo6f/HaUubFI7KYu50tWd BUqgWOTxKqlpD4HFVZKR0LK6+2/qhu8YhGEB95zEnNYbx088YN5gBaFxdYExRtbAone+ gG2flH//FSOeyWe32olsnnqu1Z5BAo84X5LEaM+210uIpjMI5yMNH6p6DVKTbOshslth udIw== X-Gm-Message-State: ACgBeo2bRGnN67Qb7IVl89HG0ulP9DhP8TYDX8UVG5J7i/+X3wVucEH7 u+P/q9VGT+kxBTyEUKCbOPLVWpwPs3OHKg== X-Google-Smtp-Source: AA6agR7fgM/0HFHd9EIUlLwNLdq6e6BT/2vkCwL/gzJY507E1BFT1d+PE2SL6vS8x8gdqvrg6ZKFTQ== X-Received: by 2002:a05:600c:40cf:b0:3a3:1fd6:47b7 with SMTP id m15-20020a05600c40cf00b003a31fd647b7mr406810wmh.32.1659463103860; Tue, 02 Aug 2022 10:58:23 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:58:23 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 01/11] spi: dw: define capability for enhanced spi Date: Tue, 2 Aug 2022 18:57:45 +0100 Message-Id: <20220802175755.6530-2-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Some Synopsys SSI controllers support enhanced SPI which includes Dual mode, Quad mode and Octal mode. Define the capability and mention it in the controller supported modes. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 4 ++++ drivers/spi/spi-dw.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index f87d97ccd2d6..97e72da7c120 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -917,6 +917,10 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) master->use_gpio_descriptors = true; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; + if (dws->caps & DW_SPI_CAP_EXT_SPI) + master->mode_bits |= SPI_TX_DUAL | SPI_RX_DUAL | + SPI_TX_QUAD | SPI_RX_QUAD | + SPI_TX_OCTAL | SPI_RX_OCTAL; if (dws->caps & DW_SPI_CAP_DFS32) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); else diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 9e8eb2b52d5c..71d18e9291a3 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -32,6 +32,7 @@ /* DW SPI controller capabilities */ #define DW_SPI_CAP_CS_OVERRIDE BIT(0) #define DW_SPI_CAP_DFS32 BIT(1) +#define DW_SPI_CAP_EXT_SPI BIT(2) /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */ #define DW_SPI_CTRLR0 0x00 From patchwork Tue Aug 2 17:57:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F5BDC00140 for ; Tue, 2 Aug 2022 17:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235314AbiHBR6d (ORCPT ); Tue, 2 Aug 2022 13:58:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232787AbiHBR6c (ORCPT ); Tue, 2 Aug 2022 13:58:32 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6384A4BD1D for ; Tue, 2 Aug 2022 10:58:31 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id z17so14126261wrq.4 for ; Tue, 02 Aug 2022 10:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4xON5/1RnjBTHOYTi8U3eC1G9Pht10d2+/+PE/oCDM8=; b=kDBdO+hRY7GGEfK3BrZAjRifF/FxSnBpdqBE5RTRkvK2+41NZPoMQ0DSrbX5Vq63HN jv2F8RuSflT3kmgJsznZ3Vw+ZM4dzzIlaiARzmp2HMjwZlnF0DvBYwBSJpO9JQqz/2ua AkF0nVK+2CZw2K/6HS4JmJJBjFCta96WWyKXdyEuNAvWx/fo5qH0VfCLOrYf8o5k5Vey Hzs0Vr/sNMNFqdUZMfRIS8dAE3tgh/r8nRH0luf+CqcDgalKNwOUgYd1XOaewHP3JrfG 0PLyhMwOlNBy0XdpblT15qNlmuMhaSeqqCvRNMJrI8WnPEw0xtU8BVoDh0wK8u3763rj 9lhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4xON5/1RnjBTHOYTi8U3eC1G9Pht10d2+/+PE/oCDM8=; b=AMKEdSpQggKC9XRixi/eDMBbxFdcg4wOjqtbR6Sfov8DZyUe6ePyZy/O7kF9wNtpwU SFZUu7nTgN0dUnovhMFM8Yc00X1NpDRJEmgy47iN0IuUcIvJexV15sJ9/0CUgEmxkgoj EwIPwEBmyuUfHzJHus8jJoQ/09Dq832nY4/2J6rFQyokDN7WtCVQ2oijwXnCdNBFeDNe 8Kfvwvx61TPCZ2eseJob0D4bggd1sKe+zO4TuXwa6XJeCWX36w3wiGeZWvAIkp55Ytaj /Yrbr64jRw/ZIVEqgRM9Jr1idwzMvZ6dk7uAuYN3jvmjwZgpLK5Bg5PSlNdwSX0qv5UQ xVkA== X-Gm-Message-State: ACgBeo0qjqxPpsPVyg+e8USbrv3YJ8v2T9wFW0tI5JA+RsA4uSA6g4JC lv3+feakabiKWsr1+mBBZMM5vw== X-Google-Smtp-Source: AA6agR7f7dwanjYpEbjx2VufVCj+4oz4IFATBDBtRwOoC0bEAehgEene0qb5B2gm0Y13e+MUYyqOLQ== X-Received: by 2002:adf:e28c:0:b0:21e:660e:26aa with SMTP id v12-20020adfe28c000000b0021e660e26aamr13777281wri.345.1659463110904; Tue, 02 Aug 2022 10:58:30 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:58:30 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 02/11] spi: dw: add check for support of dual/quad/octal Date: Tue, 2 Aug 2022 18:57:46 +0100 Message-Id: <20220802175755.6530-3-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Before doing the mem op spi controller will be queried about the buswidths it supports. Add the dual/quad/octal if the controller has the DW_SPI_CAP_EXT_SPI capability. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 97e72da7c120..77529e359b6d 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -488,8 +488,23 @@ static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op) static bool dw_spi_supports_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { - if (op->data.buswidth > 1 || op->addr.buswidth > 1 || - op->dummy.buswidth > 1 || op->cmd.buswidth > 1) + struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller); + + /* + * Only support TT0 mode in enhanced SPI for now. + * TT0 = Instruction and Address will be sent in + * Standard SPI Mode. + */ + if (op->addr.buswidth > 1 || op->dummy.buswidth > 1 || + op->cmd.buswidth > 1) + return false; + + /* In enhanced SPI 1, 2, 4, 8 all are valid modes. */ + if (op->data.buswidth > 1 && (!(dws->caps & DW_SPI_CAP_EXT_SPI))) + return false; + + /* Only support upto 32 bit address in enhanced SPI for now. */ + if (op->data.buswidth > 1 && op->addr.nbytes > 4) return false; return spi_mem_default_supports_op(mem, op); From patchwork Tue Aug 2 17:57:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8B84C19F28 for ; Tue, 2 Aug 2022 17:58:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235209AbiHBR6p (ORCPT ); Tue, 2 Aug 2022 13:58:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235394AbiHBR6l (ORCPT ); Tue, 2 Aug 2022 13:58:41 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90B4E50042 for ; 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Define a configuration variable to keep the mode based on the buswidth, which will then be used to update CR0. If the transfer is using dual/quad/octal mode then mark enhanced_spi as true. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 29 +++++++++++++++++++++++++++++ drivers/spi/spi-dw.h | 7 +++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 77529e359b6d..8c84a2e991b5 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -333,6 +333,14 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, /* CTRLR0[11:10] Transfer Mode */ cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode); + if (dws->caps & DW_SPI_CAP_EXT_SPI) { + if (cfg->spi_frf) + cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK, + cfg->spi_frf); + else + cr0 &= ~DW_HSSI_CTRLR0_SPI_FRF_MASK; + } + dw_writel(dws, DW_SPI_CTRLR0, cr0); if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD || @@ -679,10 +687,31 @@ static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller); + bool enhanced_spi = false; struct dw_spi_cfg cfg; unsigned long flags; int ret; + if (dws->caps & DW_SPI_CAP_EXT_SPI) { + switch (op->data.buswidth) { + case 2: + cfg.spi_frf = DW_SSI_CTRLR0_SPI_FRF_DUAL_SPI; + enhanced_spi = true; + break; + case 4: + cfg.spi_frf = DW_SSI_CTRLR0_SPI_FRF_QUAD_SPI; + enhanced_spi = true; + break; + case 8: + cfg.spi_frf = DW_SSI_CTRLR0_SPI_FRF_OCT_SPI; + enhanced_spi = true; + break; + default: + cfg.spi_frf = 0; + break; + } + } + /* * Collect the outbound data into a single buffer to speed the * transmission up at least on the initial stage. diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 71d18e9291a3..b8cc20e0deaa 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -96,6 +96,12 @@ #define DW_HSSI_CTRLR0_SRL BIT(13) #define DW_HSSI_CTRLR0_MST BIT(31) +/* Bit fields in CTRLR0 for enhanced SPI */ +#define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22) +#define DW_SSI_CTRLR0_SPI_FRF_DUAL_SPI 0x1 +#define DW_SSI_CTRLR0_SPI_FRF_QUAD_SPI 0x2 +#define DW_SSI_CTRLR0_SPI_FRF_OCT_SPI 0x3 + /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK GENMASK(15, 0) @@ -136,6 +142,7 @@ struct dw_spi_cfg { u8 dfs; u32 ndf; u32 freq; + u8 spi_frf; }; struct dw_spi; From patchwork Tue Aug 2 17:57:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBD56C00140 for ; Tue, 2 Aug 2022 17:58:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236133AbiHBR66 (ORCPT ); Tue, 2 Aug 2022 13:58:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235806AbiHBR6s (ORCPT ); Tue, 2 Aug 2022 13:58:48 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CE5E5004C for ; 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Tue, 02 Aug 2022 10:58:44 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:58:44 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 04/11] spi: dw: use TMOD_RO to read in enhanced spi modes Date: Tue, 2 Aug 2022 18:57:48 +0100 Message-Id: <20220802175755.6530-5-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org When we are using the enhanced spi modes we can not use EEPROM Read. The Synopsys datasheet mentions EEPROM Read is not applicable in enhanced SPI modes. We will need to use Receive only mode. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 8c84a2e991b5..8e624620864f 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -727,7 +727,10 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) cfg.dfs = 8; cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq); if (op->data.dir == SPI_MEM_DATA_IN) { - cfg.tmode = DW_SPI_CTRLR0_TMOD_EPROMREAD; + if (enhanced_spi) + cfg.tmode = DW_SPI_CTRLR0_TMOD_RO; + else + cfg.tmode = DW_SPI_CTRLR0_TMOD_EPROMREAD; cfg.ndf = op->data.nbytes; } else { cfg.tmode = DW_SPI_CTRLR0_TMOD_TO; From patchwork Tue Aug 2 17:57:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4985CC00140 for ; Tue, 2 Aug 2022 17:59:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236095AbiHBR7U (ORCPT ); Tue, 2 Aug 2022 13:59:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236110AbiHBR66 (ORCPT ); Tue, 2 Aug 2022 13:58:58 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACFB851410 for ; Tue, 2 Aug 2022 10:58:53 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id q30so14396014wra.11 for ; Tue, 02 Aug 2022 10:58:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MZTeoa87dfvJFG/ev+WcWMi6pJYHv4C0u5fdzNHZAPI=; b=KFQxbUGkbdnNFcpFvYllrGe2i0Oqt50GRp+xE1pLOFLMhInNKQfn+3LZZGA/cGowMi t2EfJVFt5mxOPw7T0ZE8McatT2X2faWr9NAd7sR7tVZDPDPDpgL8WIs9cjr15H0gI9nf aeJziL/uxBJfcwY+IIY1wRxhP+Y07KO/IgsJzMMOVIPYCMR/G4k7QMyN3iaXmEoKPu0S 5cEn2u8XF+bUkVehjle1MTjgz85hZf2O4nALxHMcgKsJ6MtDGbk5MBFTtbSq2xHYqd54 Vnv5CGE4MQf/BO9OH4wRG1NGsgIrIk4LWRgt0/wLBER++g+wZm5dRt+XIMzf0V5ywZwf flPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MZTeoa87dfvJFG/ev+WcWMi6pJYHv4C0u5fdzNHZAPI=; b=T5b6svHgU62lmotT1B8Q5B9/Oo8HUfh6Pqr1rGm6Nm6OQs5nyGmajWGDPL+P94mX0L 7FrVRh4ZVZVGsa27DgNRqeyJc3sVYACezmniUo4RcD6yMyA18qJPY89KfyWUXDljh9eF q1SuHvMsLGd5Cwp2jJ6vhokAhuiJ2/7pKCEiyxJRP9cQs6FGsNGi5U7N1b1pTDSy8QL2 3Nx5nZLW29Xe/HRHbEyIlukA0ix+emqlGNGPMcP0vkLKWH/kGVnTl5w/U3g1an0a3Olm v3FgNrsryMlpQKs7yc2wOIjdXZhiVBBBhkaC0iFlgdXhwRvRj4hEMidIaSg/YoBGQcHO jF5w== X-Gm-Message-State: ACgBeo04WF8ltL17qcx1J6a5DhQ2VhGnOCXG5QVCRcCLEXIbR88DueyV dDutJayxnA+IRVQAoiuW30apvA== X-Google-Smtp-Source: AA6agR79yXvPO2icms6I7OLPLmvO8VuEh5kLencnb2xoh+3znDhpOEYXIDS0kCA0vjDXdTCpQd9ACw== X-Received: by 2002:a05:6000:42:b0:21f:dc5:5ce0 with SMTP id k2-20020a056000004200b0021f0dc55ce0mr14429646wrx.12.1659463131961; Tue, 02 Aug 2022 10:58:51 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:58:51 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 05/11] spi: dw: define SPI_CTRLR0 register and its fields Date: Tue, 2 Aug 2022 18:57:49 +0100 Message-Id: <20220802175755.6530-6-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Synopsys SSI controllers supporting enhanced SPI mode of operation has SPI Control Register at offset 0xf4 which controls the following: CLK_STRETCH_EN: Enables clock stretching capability in SPI transfers. In case of write, if the FIFO becomes empty DWC_ssi will stretch the clock until FIFO has enough data to continue the transfer. In case of read, if the receive FIFO becomes full DWC_ssi will stop the clock until data has been read from the FIFO. WAIT_CYCLES: Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. INST_L: Dual/Quad/Octal mode instruction length in bits. ADDR_L: defines Length of Address to be transmitted. For now, we are only using 32bit Address length and 8 bit Instruction length. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index b8cc20e0deaa..a7a4637d6d32 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -63,6 +63,17 @@ #define DW_SPI_RX_SAMPLE_DLY 0xf0 #define DW_SPI_CS_OVERRIDE 0xf4 +/* Register offsets (Defined in DWC SSI 1.03a) */ +#define DW_HSSI_SPI_CTRLR0 0xf4 + +/* Bit fields in SPI_CTRLR0 (Defined in DWC SSI 1.03a) */ +#define DW_HSSI_SPI_CTRLR0_CLK_STRETCH_EN BIT(30) +#define DW_HSSI_SPI_CTRLR0_WAIT_CYCLE_MASK GENMASK(15, 11) +#define DW_HSSI_SPI_CTRLR0_INST_L_MASK GENMASK(9, 8) +#define DW_HSSI_SPI_CTRLR0_INST_L8 0x2 +#define DW_HSSI_SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2) +#define DW_HSSI_SPI_CTRLR0_ADDR_L32 0x8 + /* Bit fields in CTRLR0 (DWC APB SSI) */ #define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0) #define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16) From patchwork Tue Aug 2 17:57:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F8E7C00140 for ; Tue, 2 Aug 2022 17:59:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236225AbiHBR7f (ORCPT ); Tue, 2 Aug 2022 13:59:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236002AbiHBR7I (ORCPT ); Tue, 2 Aug 2022 13:59:08 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90F3550707 for ; Tue, 2 Aug 2022 10:59:00 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id v131-20020a1cac89000000b003a4bb3f786bso3505563wme.0 for ; Tue, 02 Aug 2022 10:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E4UV8naDvq3qTPSo5The0YIEVHRxQNXYLDteElqpqxc=; b=JEDdNc+SdwY9H7WGJA/h7gfZJT/8n7093kHisyTqxAECd0XnvlBbQZPIby2t91lvs5 LwH14ohei4NP0alduv/V0qZNQS4aFVRdknb/bzMN/PJw7g6OqHbHN45n7QV9eMFVulDN lvoMfjg9Est6l4Za5WJgVpfPqmIKkkDI6g+PnCExjWG667VSPxy9SQbJsrh+Rs18O0vj mU4AU/FbZJx0qYraQEtsdCA1xbB/0QUP1aSHd2S5YBzRaeLqseMTUJd3veDbC1ct/5Me MMb7VTgOaHgYubha4E0KnM8S1fU3RKhvIwoZfMSHCfmAjC44SmnSiNeEDxneVkMRsyPR rCfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E4UV8naDvq3qTPSo5The0YIEVHRxQNXYLDteElqpqxc=; b=Z+pP3f/jrrW2C5wajr8KrCioM2ECx9x2nPZG/KRlewX9YS9QPqjrR03Z0b76qnU+Km KNMuMGyNSRPbNha0YxV53L4Ezov0PfttkL7hVK8fB4zLNfABoWVhMSD1nDc5T0aowjw5 1g4JBFdr9qmBpmrQn/nsPARbbqXdZ/yG5KnmySCQdpPOlo+yPs/CyRo7/bMGLV01N2M1 fhfsGubPAps1OFPI2KzDI6Mjx3ufGgic3PU0FRUXQpFHD3lB0WbTRWLoLD9qUI1caw7Q te5tz+Sv/oj94N1r4exRGm0OQi/8vXHHkeP0MiGioZROy0QAdXcKwGuREjSaaaYpSS0b Uhhg== X-Gm-Message-State: ACgBeo2hCYbCvvYHWBvrlekaeo/VvmrXTFHwlUMWHfuHxCsGGQqVI3nL 2fDIM/+GcuW412OOnxCyVjUShQ== X-Google-Smtp-Source: AA6agR5oi5bh7J5T4XlHOaXxcqmZnSljMBeaUPSklXYLtjxO0JSI4hGEjQ3l7B3fG9zxrUDs2BCG4g== X-Received: by 2002:a7b:cbc4:0:b0:3a3:745d:ae5e with SMTP id n4-20020a7bcbc4000000b003a3745dae5emr411727wmi.12.1659463139006; Tue, 02 Aug 2022 10:58:59 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:58:58 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 06/11] spi: dw: update SPI_CTRLR0 register Date: Tue, 2 Aug 2022 18:57:50 +0100 Message-Id: <20220802175755.6530-7-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org If the controller supports enhanced SPI modes then update the register or reset the register if the transfer is not using dual/quad/octal mode. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 8e624620864f..9d499bdf2ce6 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -676,6 +676,32 @@ static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) dw_spi_enable_chip(dws, 1); } +static void update_spi_ctrl0(struct dw_spi *dws, const struct spi_mem_op *op, bool enable) +{ + u32 spi_ctrlr0; + + spi_ctrlr0 = dw_readl(dws, DW_HSSI_SPI_CTRLR0); + if (enable) { + spi_ctrlr0 |= FIELD_PREP(DW_HSSI_SPI_CTRLR0_WAIT_CYCLE_MASK, + op->dummy.nbytes * BITS_PER_BYTE); + /* 8 bit instruction length */ + spi_ctrlr0 |= FIELD_PREP(DW_HSSI_SPI_CTRLR0_INST_L_MASK, + DW_HSSI_SPI_CTRLR0_INST_L8); + /* 32 bit address length */ + spi_ctrlr0 |= FIELD_PREP(DW_HSSI_SPI_CTRLR0_ADDR_L_MASK, + DW_HSSI_SPI_CTRLR0_ADDR_L32); + /* Enable clock stretching */ + spi_ctrlr0 |= DW_HSSI_SPI_CTRLR0_CLK_STRETCH_EN; + } else { + spi_ctrlr0 &= ~DW_HSSI_SPI_CTRLR0_WAIT_CYCLE_MASK; + spi_ctrlr0 &= ~DW_HSSI_SPI_CTRLR0_INST_L_MASK; + spi_ctrlr0 &= ~DW_HSSI_SPI_CTRLR0_ADDR_L_MASK; + spi_ctrlr0 &= ~DW_HSSI_SPI_CTRLR0_CLK_STRETCH_EN; + } + + dw_writel(dws, DW_HSSI_SPI_CTRLR0, spi_ctrlr0); +} + /* * The SPI memory operation implementation below is the best choice for the * devices, which are selected by the native chip-select lane. It's @@ -738,6 +764,9 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) dw_spi_enable_chip(dws, 0); + if (dws->caps & DW_SPI_CAP_EXT_SPI) + update_spi_ctrl0(dws, op, enhanced_spi); + dw_spi_update_config(dws, mem->spi, &cfg); dw_spi_mask_intr(dws, 0xff); From patchwork Tue Aug 2 17:57:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A999C00140 for ; Tue, 2 Aug 2022 17:59:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236731AbiHBR7k (ORCPT ); Tue, 2 Aug 2022 13:59:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236546AbiHBR7Q (ORCPT ); Tue, 2 Aug 2022 13:59:16 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7298D50074 for ; Tue, 2 Aug 2022 10:59:06 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id q30so14396713wra.11 for ; Tue, 02 Aug 2022 10:59:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sl9Z98LrR1HGqesJuJI9JTYA1Pp0siEP1pFEoTfJVN4=; b=BraroAuIQqADk1cnPCUB+aLh71k99p66yNBjBE+daWZAXJlSqonJQiZ0FlH0EOzoWp qty7Gm9qCLCWysfVI6MKR3XEewBIan5xCzCgYM1vIWkV0Xhihh1EqDMYCmA3yG0OvsSP Vesref23GBooU7Y2ju9GiSMdXRzuYjwBDnOzRYUAs4cCxLUpB6XRzTiWq4DCt+s+pvUt ZNNPNHDsVuSMY4oojQy4b1QjHXc8NAZbRnObtruXL7xw1g+ckQ0/k+N7YRV2qcLZBsnj 5RRCUZvQgrpfIR75YsbOKLcogkxtn5cKFehPjzxmzCaaXnianjUUOqYVHWgBfcQXrZ2B jZtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sl9Z98LrR1HGqesJuJI9JTYA1Pp0siEP1pFEoTfJVN4=; b=GNiUyN62CxDsXp3aEA3w36tTxFHxPOqJKyr46bJYZswejtapSx4Gdix3GL96pBAp0/ poMfh0TTyEfuNxAgH1TP0ccw84mcyqTgyjIE9Rx0M0MfUZO//r0DBPkyXEN0Cm/5MVVd TlSwepK4bqYTOFKi3QEZ7WabLkgew6WrOji9Vyek9YSGUQWaDkj0EHC2Vgou/hzukbDe VEZCXd8K9DeKryT8x/HZ9/7M2HG+MI8LQ0hzKf7Fwv0sKN+2BL8j6FRmlhjSN1eqiufa WPKBVy2a9E9pfpBbMynkMOtqvuUOtHV4znX5zxBdxYu50SpHzk/VLoO2R4NqyzqPp2Tj imiA== X-Gm-Message-State: ACgBeo3Qsr/4G4Zn4MfQPF4z2K6Vt65ojYd9Pv/q6LGsBj9ZaRJ+vkp3 HQs9VWaZa/LnXYKv07h3L48+Xg== X-Google-Smtp-Source: AA6agR66+Jqszo7T/0P1VL5IUVzXM9piN1M4GBE4tIZBTx475dA6PJNPHMkQlN3ie5uOahqE3xClRQ== X-Received: by 2002:a05:6000:230:b0:21e:cf23:499f with SMTP id l16-20020a056000023000b0021ecf23499fmr14072388wrz.29.1659463146015; Tue, 02 Aug 2022 10:59:06 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:59:05 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 07/11] spi: dw: update NDF while writing in enhanced spi mode Date: Tue, 2 Aug 2022 18:57:51 +0100 Message-Id: <20220802175755.6530-8-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org If the transfer of Transmit only mode is using dual/quad/octal SPI then NDF needs to be updated with the number of data frames. If the Transmit FIFO goes empty in-between, DWC_ssi masks the serial clock and wait for rest of the data until the programmed amount of frames are transferred successfully. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 9d499bdf2ce6..8cb30540ad5b 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -344,7 +344,9 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, dw_writel(dws, DW_SPI_CTRLR0, cr0); if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD || - cfg->tmode == DW_SPI_CTRLR0_TMOD_RO) + cfg->tmode == DW_SPI_CTRLR0_TMOD_RO || + (cfg->tmode == DW_SPI_CTRLR0_TMOD_TO && + (dws->caps & DW_SPI_CAP_EXT_SPI) && cfg->spi_frf)) dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); /* Note DW APB SSI clock divider doesn't support odd numbers */ @@ -760,6 +762,8 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) cfg.ndf = op->data.nbytes; } else { cfg.tmode = DW_SPI_CTRLR0_TMOD_TO; + if (enhanced_spi) + cfg.ndf = op->data.nbytes; } dw_spi_enable_chip(dws, 0); From patchwork Tue Aug 2 17:57:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0849EC19F28 for ; Tue, 2 Aug 2022 17:59:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236639AbiHBR7u (ORCPT ); Tue, 2 Aug 2022 13:59:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235806AbiHBR7W (ORCPT ); Tue, 2 Aug 2022 13:59:22 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA6555004E for ; Tue, 2 Aug 2022 10:59:13 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id j15so10731135wrr.2 for ; Tue, 02 Aug 2022 10:59:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TuVepJCF1VhVPp+n/Z+Mnas7S62uFs9HoLlJ9erehas=; b=Kh3BCvMHHboARNWPh+RZPNmF9sYIrBO7nPt45FCa8GN9tB2w9qCoaNVgD3b7jnUHMl S6lPilv9DEklvzoPj1XutlezBbig85yBT9g26SOg//OLdG6RpUQLCtj7wKaoI0TzRJJx UWLYQpS0UkouP83VdDHyBdnn9wIuQjFnBf4En4VYF04AWxJoKo5b6z2FRdlquLqvIFXE tiosmLf5zMLjPbPy7zk2eQBazgs3kg7cRpEXo2MJLws0+/jN7vfhfIBZ6fDxgsXmymMO Va5KIYInk+h90EiUizduw1QJzA8+UpOpvHCg9eMcUZUxhMn83wvo6iD5BYS2UWGLqMth FL0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TuVepJCF1VhVPp+n/Z+Mnas7S62uFs9HoLlJ9erehas=; b=6dGukvizflTnVEpxoKlKc+baapah3FUPv0Gx9Dha0qasYUuokGHD79dRgcgcxFoTqD clNGgpvyZpRx7Oqfnpew5eAO3dXsjhcuMAVVBj93OULNpZksYkkiZxmh1urNV3DLu71Y hSZ8kjzq9bZCipHpDI0n1yBZ6jcpR7xBNMDEjNe3MFxVtKygUjiGO1F9AIYSJebh6EJN DAC/bJ+hsmwe5Uy29zXxtvjoVFJRH4uXk8AyWw8YtYTG2Fc9uf9Cyd8DX7NHRgcg0UjN C8RXyhQebjuozJKHmBZqTJ9oxPXU0tMkVduE4gME+xIOk0ibfxhljuh+xH+BGJAZQ99N teTg== X-Gm-Message-State: ACgBeo1hFBh1wdOWP2LvnT2dV2I6OHeXt8ROSgakYz4suOHlBSEPUs5x PI3H2UR5MAHTBG1hkSubsnJ5/g== X-Google-Smtp-Source: AA6agR7iyUkADRLOH839oPzAEPSkTF/AuRmupZXbEonsdqFKTvF5lHGdTGS+I/IpSwJQEMuG1V69qw== X-Received: by 2002:a5d:584f:0:b0:21d:bcd6:5c8e with SMTP id i15-20020a5d584f000000b0021dbcd65c8emr13590680wrf.60.1659463153096; Tue, 02 Aug 2022 10:59:13 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.59.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:59:12 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 08/11] spi: dw: update buffer for enhanced spi mode Date: Tue, 2 Aug 2022 18:57:52 +0100 Message-Id: <20220802175755.6530-9-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org In enhanced spi mode we will be writing the address to a single FIFO location instead of writing to multiple FIFOs in the standard SPI mode. Save the cmd and address bytes in the buffer accordingly. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 55 ++++++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 8cb30540ad5b..2564a2276572 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -520,7 +520,8 @@ static bool dw_spi_supports_mem_op(struct spi_mem *mem, return spi_mem_default_supports_op(mem, op); } -static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op) +static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op, + bool enhanced_spi) { unsigned int i, j, len; u8 *out; @@ -548,17 +549,57 @@ static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op) */ for (i = 0; i < op->cmd.nbytes; ++i) out[i] = DW_SPI_GET_BYTE(op->cmd.opcode, op->cmd.nbytes - i - 1); - for (j = 0; j < op->addr.nbytes; ++i, ++j) - out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1); - for (j = 0; j < op->dummy.nbytes; ++i, ++j) - out[i] = 0x0; + + if (enhanced_spi) { + /* + * Fill the remaining spaces of dws->reg_io_width bytes + * size register with zero for cmd. + */ + for (; i < dws->reg_io_width; ++i) + out[i] = 0; + /* + * Copy the address bytes in dws->reg_io_width bytes size + * register and fill remaining spaces with zero. + */ + for (j = op->addr.nbytes; j > 0; ++i, --j) + out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j); + for (j = op->addr.nbytes; j < dws->reg_io_width; ++i, ++j) + out[i] = 0; + } else { + for (j = 0; j < op->addr.nbytes; ++i, ++j) + out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1); + } + + if (!enhanced_spi) { + /* + * dummy bytes are not needed in enhanced mode as + * wait_cycles specified as number of SPI clock cycles + * between control frames transmit and data reception + * will be mentioned in enhanced spi mode. + */ + for (j = 0; j < op->dummy.nbytes; ++i, ++j) + out[i] = 0x0; + } if (op->data.dir == SPI_MEM_DATA_OUT) memcpy(&out[i], op->data.buf.out, op->data.nbytes); dws->n_bytes = 1; dws->tx = out; - dws->tx_len = len; + + if (enhanced_spi) { + /* + * In enhanced mode cmd will be one FIFO and address + * will be one more FIFO. + */ + dws->tx_len = 1; + if (op->addr.nbytes) + dws->tx_len += 1; + if (op->data.dir == SPI_MEM_DATA_OUT) + dws->tx_len += op->data.nbytes; + } else { + dws->tx_len = len; + } if (op->data.dir == SPI_MEM_DATA_IN) { dws->rx = op->data.buf.in; dws->rx_len = op->data.nbytes; @@ -744,7 +785,7 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) * Collect the outbound data into a single buffer to speed the * transmission up at least on the initial stage. */ - ret = dw_spi_init_mem_buf(dws, op); + ret = dw_spi_init_mem_buf(dws, op, enhanced_spi); if (ret) return ret; From patchwork Tue Aug 2 17:57:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FE7CC00140 for ; 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Tue, 02 Aug 2022 10:59:19 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 09/11] spi: dw: prepare the transfer routine for enhanced mode Date: Tue, 2 Aug 2022 18:57:53 +0100 Message-Id: <20220802175755.6530-10-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The transfer routine of dual/quad/octal is similar to standard SPI mode except that we do not need to worry about CS being de-asserted and we will be writing the address to a single FIFO location. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-core.c | 141 +++++++++++++++++++++++++++++++++----- 1 file changed, 125 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 2564a2276572..d6afa75e7023 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -712,6 +712,28 @@ static int dw_spi_wait_mem_op_done(struct dw_spi *dws) return 0; } +static void ext_transfer_delay(struct dw_spi *dws) +{ + struct spi_delay delay; + unsigned long ns, us; + u32 nents; + + nents = dw_readl(dws, DW_SPI_TXFLR); + ns = NSEC_PER_SEC / dws->current_freq * nents; + ns *= dws->n_bytes * BITS_PER_BYTE; + if (ns <= NSEC_PER_USEC) { + delay.unit = SPI_DELAY_UNIT_NSECS; + delay.value = ns; + } else { + us = DIV_ROUND_UP(ns, NSEC_PER_USEC); + delay.unit = SPI_DELAY_UNIT_USECS; + delay.value = clamp_val(us, 0, USHRT_MAX); + } + /* wait until there is some space in TX FIFO */ + while (!(dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_TF_NOT_FULL)) + spi_delay_exec(&delay, NULL); +} + static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) { dw_spi_enable_chip(dws, 0); @@ -719,6 +741,82 @@ static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) dw_spi_enable_chip(dws, 1); } +static int enhanced_transfer(struct dw_spi *dws, struct spi_device *spi, + const struct spi_mem_op *op) +{ + u32 max, txw = 0, rxw; + bool cs_done = false; + void *buf = dws->tx; + int ret; + + /* Send cmd as 32 bit value */ + if (buf) { + txw = *(u32 *)(buf); + dw_write_io_reg(dws, DW_SPI_DR, txw); + buf += 4; + dws->tx_len--; + if (op->addr.nbytes) { + /* + * Send address as 32 bit value if address + * is present in the instruction. + */ + txw = *(u32 *)(buf); + dw_write_io_reg(dws, DW_SPI_DR, txw); + buf += 4; + dws->tx_len--; + } + } + + do { + max = min_t(u32, dws->tx_len, dws->fifo_len - + dw_readl(dws, DW_SPI_TXFLR)); + while (max--) { + if (buf) { + txw = *(u8 *)(buf); + buf += dws->n_bytes; + } + dw_write_io_reg(dws, DW_SPI_DR, txw); + --dws->tx_len; + } + /* Enable CS after filling up FIFO */ + if (!cs_done) { + dw_spi_set_cs(spi, false); + cs_done = true; + } + ext_transfer_delay(dws); + if (!dws->tx_len && !dws->rx_len) { + /* + * We only need to wait for done if there is + * nothing to receive and there is nothing more + * to transmit. If we are receiving, then the + * wait cycles will make sure we wait. + */ + ret = dw_spi_wait_mem_op_done(dws); + if (ret) + return ret; + } + } while (dws->tx_len); + + buf = dws->rx; + while (dws->rx_len) { + max = dw_spi_rx_max(dws); + + while (max--) { + rxw = dw_read_io_reg(dws, DW_SPI_DR); + if (buf) { + *(u8 *)(buf) = rxw; + buf += dws->n_bytes; + } + --dws->rx_len; + } + + ret = dw_spi_check_status(dws, true); + if (ret) + return ret; + } + return 0; +} + static void update_spi_ctrl0(struct dw_spi *dws, const struct spi_mem_op *op, bool enable) { u32 spi_ctrlr0; @@ -846,25 +944,36 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) * manually restricting the SPI bus frequency using the * dws->max_mem_freq parameter. */ - local_irq_save(flags); - preempt_disable(); + if (!enhanced_spi) { + local_irq_save(flags); + preempt_disable(); - ret = dw_spi_write_then_read(dws, mem->spi); + ret = dw_spi_write_then_read(dws, mem->spi); - local_irq_restore(flags); - preempt_enable(); + local_irq_restore(flags); + preempt_enable(); - /* - * Wait for the operation being finished and check the controller - * status only if there hasn't been any run-time error detected. In the - * former case it's just pointless. In the later one to prevent an - * additional error message printing since any hw error flag being set - * would be due to an error detected on the data transfer. - */ - if (!ret) { - ret = dw_spi_wait_mem_op_done(dws); - if (!ret) - ret = dw_spi_check_status(dws, true); + /* + * Wait for the operation being finished and check the + * controller status only if there hasn't been any + * run-time error detected. In the former case it's + * just pointless. In the later one to prevent an + * additional error message printing since any hw error + * flag being set would be due to an error detected on + * the data transfer. + */ + if (!ret) { + ret = dw_spi_wait_mem_op_done(dws); + if (!ret) + ret = dw_spi_check_status(dws, true); + } + } else { + /* + * We donot need to disable IRQs as clock stretching will + * be enabled in enhanced mode which will prevent CS + * from being de-assert. + */ + ret = enhanced_transfer(dws, mem->spi, op); } dw_spi_stop_mem_op(dws, mem->spi); From patchwork Tue Aug 2 17:57:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A3DAC19F28 for ; Tue, 2 Aug 2022 18:00:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236454AbiHBSAJ (ORCPT ); Tue, 2 Aug 2022 14:00:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236031AbiHBR7i (ORCPT ); Tue, 2 Aug 2022 13:59:38 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C434451A3D for ; Tue, 2 Aug 2022 10:59:28 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id r1-20020a05600c35c100b003a326685e7cso895702wmq.1 for ; Tue, 02 Aug 2022 10:59:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GcoYEB+LR9XunENDegpBIP0LqpENWfoItafTlDKOv+I=; b=WMOKG78H365a+1ElleuamwOz5x7nE0mLG5uTbACzumPhRGmXv5sfab7nXNUXyJdJMI DPhDLCcfuHwwQcC7c5okRHgmuwAtp3QP27/pORFDgtfkIWXiASsO8Bq+zPe0/KGUpE1L +Ik6nx+dxN8mlk2tdCHFhuvYghGT2IcziEpmNxv7ur3VBpxILD5yuQ2W8muRXiC862sO 2nbXa9dp2dof6J/8Jpiu7kUqHGJgdmNIkUiiTFpazlhkyXn5ZNo0X6mXdYgY+6l5hU3B c+SB1ZSOXOPDNESG7khQQgVLGRJlZO0sCCgfxrbBYfAi6H03cUSZWg6zysJrcIBhNGYJ iDIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GcoYEB+LR9XunENDegpBIP0LqpENWfoItafTlDKOv+I=; b=JUtXJWYYPHiEXg91SUJD8rihasaVIvy24pWTt7lIGCtn98mRlmbDKIz/TCWAZo+JKI dOMADXqtWA6HkVqXzmfDgRAZtJVCi6hGyAs4Rl5tlLSQplJzcapaVSY7JUrvWyctyJOA edJ3qZ67XqfDq39WQR+53tovJHwbptNJOhKOmXiMw7LUEMGlUBk6kK+ujiAolNoFUkvt b0qkrQXH1gCs1+9qyx5x7qqf5300QASpnVppAqu6Cg0zJktR9VB+SNztcjmVDBhaXKXw 7M4Mr/sHpTrjyQgDAZzX9LoTskwzz8mlluzL5znY4wqbsmlf8rHcM7SjZpYr/WVzzFlH vO8g== X-Gm-Message-State: ACgBeo17riPSRd4imJjRvQFUAWVRmcYEBJ5XuT7DZ3sQPYVZxjlTzhnL nzLJbO9jMGD6b7oTjbTLuv7JhQ== X-Google-Smtp-Source: AA6agR7FIi17LUA0EXeBzFgwdWxt0gU7tveiwLFLYacKYX2TSURwQiGl8iMhtl52FemdGm66uw4aQA== X-Received: by 2002:a05:600c:3786:b0:3a3:19d4:293f with SMTP id o6-20020a05600c378600b003a319d4293fmr404947wmr.116.1659463167235; Tue, 02 Aug 2022 10:59:27 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:59:26 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 10/11] spi: dw-apb-ssi: add generic 1.03a version Date: Tue, 2 Aug 2022 18:57:54 +0100 Message-Id: <20220802175755.6530-11-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Ben Dooks Add new snps,dw-ssi-1.03a version to the bindings. Signed-off-by: Ben Dooks Signed-off-by: Sudip Mukherjee Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 37c3c272407d..35aa04a85813 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -45,6 +45,7 @@ properties: enum: - snps,dw-apb-ssi - snps,dwc-ssi-1.01a + - snps,dwc-ssi-1.03a - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller items: - enum: From patchwork Tue Aug 2 17:57:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudip Mukherjee X-Patchwork-Id: 12934950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53F6CC00140 for ; Tue, 2 Aug 2022 18:00:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236103AbiHBSAY (ORCPT ); Tue, 2 Aug 2022 14:00:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235472AbiHBR7t (ORCPT ); Tue, 2 Aug 2022 13:59:49 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFCC8501B1 for ; Tue, 2 Aug 2022 10:59:35 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id m41-20020a05600c3b2900b003a4e094256eso1354130wms.0 for ; Tue, 02 Aug 2022 10:59:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dksoanYJoZO8G01KR5WlaEaO1JRamu4a/M2lotcY4Us=; b=cJzyb6w6buAT4Si/LRbYnFJOIEuXMT96PIUp3Cza/fREQOsThox0SJ6o43dJ8Pk7Jn LfbiSVkviFwvZJBQYr+raawJje3EleuA5fdAPHnphp2Gh1S+bSPoAjazyFNpL/0wjZQW mOTBUX6qkVmcZV7JM1FeRCSGNHWmpzJO/bCYb3K7vNQzTFwsx7cf9jAMIsz3SpL6mAE5 Z8hr56URVZjl1JOV3bZ0qHtEl1yYfNR/kIMtfv42fk1H7agRsFbQ1duZeLMGWewzeqeB qiezCxTu4w6G496EFPEw+GTc0UbnK0C1sRsu5WZjzMToAq1sWQQGA/LPMsWMW06ELxj3 zuKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dksoanYJoZO8G01KR5WlaEaO1JRamu4a/M2lotcY4Us=; b=QyqcgF/2EP9u/fgdqybweL5uhtPYzScTKBWBV589gqvy8LOopCMO2ZV0nz/LKcc/zU Kvb9jX7hV7KcRRdNF0eysJZYp8jSa0rPJJB0Qu0vSL/3J1gzsyfUVnlGmeX8efEd97Sd XMU8KBJj+Qae6cImrbT+BrsTU6TwJTuOexAGa1KwRy1wlxAzt0ZbNL40U9KU5W79XHEJ 6SMKa1t48QXUjzpzJ98UryeT1V07Uze+nYarh+Q6Osq8J0dHEr1afblDh/M2gfT138RZ maOFWhuR3CyIQcqPojuJKidJNXeREZmPGSn9WYFAeKEQc2vWcOXJ2Y1W9n1q1+NfMlaP qVYA== X-Gm-Message-State: ACgBeo0O7r5d2+vQq8x26BcWsDTDUL/6UNx20316ftdfuy0xyGnAWRSv Pcf370+qzqfdCFh6V2OKZskxNg== X-Google-Smtp-Source: AA6agR557a68A28uaXoSIeKdmvNzbTM0Ny3U/oteTSHz5ZHwIapC+B9nEc6H0RjuhnZ2aK0AhXbE5g== X-Received: by 2002:a1c:2783:0:b0:3a2:fd82:bf46 with SMTP id n125-20020a1c2783000000b003a2fd82bf46mr382235wmn.29.1659463174307; Tue, 02 Aug 2022 10:59:34 -0700 (PDT) Received: from debian.office.codethink.co.uk ([2405:201:8005:8149:e5c9:c0ac:4d82:e94b]) by smtp.gmail.com with ESMTPSA id 9-20020a05600c020900b003a3187a2d4csm23318222wmi.22.2022.08.02.10.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Aug 2022 10:59:33 -0700 (PDT) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com, william.salmon@sifive.com, adnan.chowdhury@sifive.com, ben.dooks@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeegar.lakhani@sifive.com, Sudip Mukherjee Subject: [PATCH 11/11] spi: dw: initialize dwc-ssi-1.03a controller Date: Tue, 2 Aug 2022 18:57:55 +0100 Message-Id: <20220802175755.6530-12-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com> References: <20220802175755.6530-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Define the initialization of dwc-ssi-1.03a controller and mark it with the capability of enhanced SPI supporting dual/quad/octal modes of transfer. Signed-off-by: Sudip Mukherjee --- drivers/spi/spi-dw-mmio.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 26c40ea6dd12..db80e0645172 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -237,6 +237,15 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static int dw_spi_hssi_ext_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + dwsmmio->dws.ip = DW_HSSI_ID; + dwsmmio->dws.caps = DW_SPI_CAP_EXT_SPI; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +361,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "snps,dwc-ssi-1.03a", dw_spi_hssi_ext_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);