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Signed-off-by: Shenwei Wang --- .../bindings/gpio/fsl,imx8-scu-gpio.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/fsl,imx8-scu-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/fsl,imx8-scu-gpio.yaml b/Documentation/devicetree/bindings/gpio/fsl,imx8-scu-gpio.yaml new file mode 100644 index 000000000000..d06e91402666 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/fsl,imx8-scu-gpio.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/fsl,imx8-scu-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO driver over IMX SCU firmware API + +maintainers: + - Shenwei Wang + +description: | + This module provides the standard interface to control the + resource pins in SCU domain on i.MX8 platforms. + +properties: + compatible: + enum: + - fsl,imx8-scu-gpio + + "#gpio-cells": + const: 2 + + gpio-controller: true + +required: + - compatible + - "#gpio-cells" + - gpio-controller + +additionalProperties: false + +examples: + - | + gpio@scu { + compatible = "fsl,imx8-scu-gpio"; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the description for imx-scu gpio subnode. Signed-off-by: Shenwei Wang --- Documentation/devicetree/bindings/firmware/fsl,scu.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml index b40b0ef56978..080955b6edd8 100644 --- a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml +++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml @@ -30,6 +30,11 @@ properties: Clock controller node that provides the clocks controlled by the SCU $ref: /schemas/clock/fsl,scu-clk.yaml + gpio: + description: + GPIO control over the SCU firmware APIs + $ref: /schemas/gpio/fsl,imx8-scu-gpio.yaml + ocotp: description: OCOTP controller node provided by the SCU From patchwork Thu Aug 4 18:49:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 12936613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEB1CC19F2A for ; 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Received: from AM9PR04MB8274.eurprd04.prod.outlook.com (2603:10a6:20b:3e8::23) by AM6PR04MB3992.eurprd04.prod.outlook.com (2603:10a6:209:50::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.16; Thu, 4 Aug 2022 18:50:21 +0000 Received: from AM9PR04MB8274.eurprd04.prod.outlook.com ([fe80::747c:397f:a003:dbca]) by AM9PR04MB8274.eurprd04.prod.outlook.com ([fe80::747c:397f:a003:dbca%5]) with mapi id 15.20.5504.015; Thu, 4 Aug 2022 18:50:21 +0000 From: Shenwei Wang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linus.walleij@linaro.org, brgl@bgdev.pl, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shenwei Wang Subject: [PATCH v1 3/3] firmware: imx: add imx-scu GPIO driver Date: Thu, 4 Aug 2022 13:49:08 -0500 Message-Id: <20220804184908.470216-4-shenwei.wang@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220804184908.470216-1-shenwei.wang@nxp.com> References: <20220804184908.470216-1-shenwei.wang@nxp.com> X-ClientProxiedBy: MN2PR03CA0029.namprd03.prod.outlook.com (2603:10b6:208:23a::34) To AM9PR04MB8274.eurprd04.prod.outlook.com (2603:10a6:20b:3e8::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ebc9bde4-dd0f-479a-a5a4-08da764a2eb3 X-MS-TrafficTypeDiagnostic: AM6PR04MB3992:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eE7qzfHdH7pnlMx1eSJb06ebrXQyJENCE+fj82Q+tnWWkRWoYTk4OrBxZMyik2rIZoteQ84DcRscQ6ktPLEl9yYmN80Qbb7+jizTkkltCh5YXIMOsmoZZQeWkhucBU7GffBA++Nw3GWc0iEUkKe/xh1DTbnszg9rk6SYXyyOYDIJRpQcuAzZndQu+AAK1Z30pYtnRQPhKyz+83FzJI9rmf352OCJGyYe7xkuAPmcnJ9MRJrlczHTOIb4CggFv8mPg+EiaKegVN2kpOUStvw0JwAjLYDvBxSnNO8yNcW865TYBwUIbecmHr27HSyywii4BpKYsOWTAM3L48eAEvcLm6X6xvu3I4UNHDCeMNQpYiO9w5gdZbtbXpKuRbk8LdcFsOyblrtSgxgbsZRzANw37bElp4emm+/hGzWrfdzKwGNI6RV1f0tkcgi9/+qwBO74BJvqapju/jJOIJXs2xol9yrDR7CIOxYmvbRTt9VzKVVoqJsJILefnyMa+lA9nATd/xtJ4gzPJgBnWYdNcPCKBU3fi9lCRhX3IafuRcElEKTfQ0PJ7Nykd27Hwe5lCgA0f94MtVNBMqC66YSf1fyFmAt28lFCLVokIbl7XkqsukDAZknQ/w2Erl7uPYFpCcs3TTmK+UcayDmZPtA1bkqyPxpJaKlxzQ8T44AfeXMb2MESwYIYWpJk8FJs9aG6vhlWey7eS6EDNKVyBq3hNmvusgrJmPNvoYErS3ABe0YpS4vZGjfGQ2y6rAlEnTcIeH0tJZxIDyhFhSezZh3n7aLGfA7auJgRBQU0b9Dc48e4TAdxiDXnR/gZRksTqzmQ0yiVWN9D3G8Dz09snI0X6cVG7QGAilltzZAgNcYZQxscCai0kQHpjNjcP4Jn0MP0VB7eXIxgCvQtmtkDtAVHcOWD/K0fCZmRH96utzvaDtMFl+qjXkdbLOSFBHAUIrmX3zTp9/Y28OT5r4eFXqd/saU07+d3on3yDZr17KoGt92syYIQMpWcPcFvA/xPJ8rsqUXlwNHsbSrGBWS+n/Gabdctis+m3uFq1zGKe+AoMLCyadApuaH3csAz3zmxDCE6LVwfMaLarobcMF5WrRYJNzmf5nxNfiM/3Y4lGELAUikxE+FLjjjpC8c7q4EX+SssK+EGuBEAu8KQ1qb4eDLhEIScyqMulVafpDQJ3jXBukzN16vBu2mGOM9nBuaJZye3ALAfxMAZzwL6XwuBAQZif4BMeht87SKnzqe0Khsk4hxeiatpCfWbONNfRrYN2YfA3zs+SdWn28gZXbj5dO3wD2doplu2MOX7bwZeabVsYfobQdApCRwgEClcrHHTkEo/h+VNONJMcIAc9Rwd8ZoWoWfNC4/naxw70uyL5UvlyF9D0IXGWkUlCTQ/V2a8PCwm/IPhVib0K16ZHLlce3F3/j1fe2iAGouNzCqLA2PCllCr/bQ0FP1Wt8xDKiXoH54yTUz5jeOLEJp19/+ggOjNULJUPctARnzkJGkGCHrM0cuObk/wJdBy9SNZKxgspb4ba7pV1G5d7SGfq2Yjphn5GufY1wMJlguahuJcSgmzqFfBnws+R/SPaLHVAFCEcpXnu1mH X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ebc9bde4-dd0f-479a-a5a4-08da764a2eb3 X-MS-Exchange-CrossTenant-AuthSource: AM9PR04MB8274.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2022 18:50:21.0466 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: fBhUKRSmrjH432Z5msc4yxRMEml1aM1G/BwgztSilYmPAm3rW6DdHh2w8x/yA8SY8fW0ZxUroC96y6xGEExCzw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB3992 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220804_115030_308154_4D122FEA X-CRM114-Status: GOOD ( 23.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SCU firmware on i.MX8 platforms provides a set of APIs to control the GPIO PINs on the SCU domain. This patch implements the standard GPIO driver interface to access those PINs on the SCU domain over the SCU APIs. Signed-off-by: Shenwei Wang --- drivers/firmware/imx/Kconfig | 6 ++ drivers/firmware/imx/Makefile | 1 + drivers/firmware/imx/imx-scu-gpio.c | 139 ++++++++++++++++++++++++++++ 3 files changed, 146 insertions(+) create mode 100644 drivers/firmware/imx/imx-scu-gpio.c diff --git a/drivers/firmware/imx/Kconfig b/drivers/firmware/imx/Kconfig index c027d99f2a59..484c13f3149a 100644 --- a/drivers/firmware/imx/Kconfig +++ b/drivers/firmware/imx/Kconfig @@ -28,3 +28,9 @@ config IMX_SCU_PD depends on IMX_SCU help The System Controller Firmware (SCFW) based power domain driver. + +config IMX_SCU_GPIO + def_bool y + depends on IMX_SCU + help + Say Y here to enable the imx8 gpio over SCFW MISC API diff --git a/drivers/firmware/imx/Makefile b/drivers/firmware/imx/Makefile index b76acbade2a0..436476502bd8 100644 --- a/drivers/firmware/imx/Makefile +++ b/drivers/firmware/imx/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_IMX_DSP) += imx-dsp.o obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o +obj-$(CONFIG_IMX_SCU_GPIO) += imx-scu-gpio.o obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o diff --git a/drivers/firmware/imx/imx-scu-gpio.c b/drivers/firmware/imx/imx-scu-gpio.c new file mode 100644 index 000000000000..2f4a991a9ad6 --- /dev/null +++ b/drivers/firmware/imx/imx-scu-gpio.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2021~2022 NXP + * + * The driver exports a standard gpiochip interface + * to control the PIN resources on SCU domain. + */ + +#include +#include +#include +#include +#include + +struct scu_gpio_priv { + struct gpio_chip chip; + struct mutex lock; + struct device *dev; + struct imx_sc_ipc *handle; +}; + +static unsigned int scu_rsrc_arr[] = { + IMX_SC_R_BOARD_R0, + IMX_SC_R_BOARD_R1, + IMX_SC_R_BOARD_R2, + IMX_SC_R_BOARD_R3, + IMX_SC_R_BOARD_R4, + IMX_SC_R_BOARD_R5, + IMX_SC_R_BOARD_R6, + IMX_SC_R_BOARD_R7, +}; + +static int imx_scu_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct scu_gpio_priv *priv = gpiochip_get_data(chip); + int level; + int err; + + if (offset >= chip->ngpio) + return -EINVAL; + + mutex_lock(&priv->lock); + + /* to read PIN state via scu api */ + err = imx_sc_misc_get_control(priv->handle, + scu_rsrc_arr[offset], 0, &level); + mutex_unlock(&priv->lock); + + if (err) { + dev_err(priv->dev, "SCU get failed: %d\n", err); + return err; + } + + return level; +} + +static void imx_scu_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct scu_gpio_priv *priv = gpiochip_get_data(chip); + int err; + + if (offset >= chip->ngpio) + return; + + mutex_lock(&priv->lock); + + /* to set PIN output level via scu api */ + err = imx_sc_misc_set_control(priv->handle, + scu_rsrc_arr[offset], 0, value); + mutex_unlock(&priv->lock); + + if (err) + dev_err(priv->dev, "SCU set (%d) failed: %d\n", + scu_rsrc_arr[offset], err); +} + +static int imx_scu_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + if (offset >= chip->ngpio) + return -EINVAL; + + return GPIO_LINE_DIRECTION_OUT; +} + +static int imx_scu_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct scu_gpio_priv *priv; + struct gpio_chip *gc; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ret = imx_scu_get_handle(&priv->handle); + if (ret) + return ret; + + priv->dev = dev; + mutex_init(&priv->lock); + + gc = &priv->chip; + gc->base = -1; + gc->parent = dev; + gc->ngpio = sizeof(scu_rsrc_arr)/sizeof(unsigned int); + gc->label = dev_name(dev); + gc->get = imx_scu_gpio_get; + gc->set = imx_scu_gpio_set; + gc->get_direction = imx_scu_gpio_get_direction; + + platform_set_drvdata(pdev, priv); + + return devm_gpiochip_add_data(dev, gc, priv); +} + +static const struct of_device_id imx_scu_gpio_dt_ids[] = { + { .compatible = "fsl,imx8-scu-gpio" }, + { /* sentinel */ } +}; + +static struct platform_driver imx_scu_gpio_driver = { + .driver = { + .name = "gpio-imx-scu", + .of_match_table = imx_scu_gpio_dt_ids, + }, + .probe = imx_scu_gpio_probe, +}; + +static int __init _imx_scu_gpio_init(void) +{ + return platform_driver_register(&imx_scu_gpio_driver); +} + +subsys_initcall_sync(_imx_scu_gpio_init); + +MODULE_AUTHOR("Shenwei Wang "); +MODULE_DESCRIPTION("NXP GPIO over IMX SCU API"); +MODULE_LICENSE("GPL");