From patchwork Fri Aug 5 20:27:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12937684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85680C00140 for ; Fri, 5 Aug 2022 20:27:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241253AbiHEU1p (ORCPT ); Fri, 5 Aug 2022 16:27:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234198AbiHEU1m (ORCPT ); Fri, 5 Aug 2022 16:27:42 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4911F1EAD7 for ; Fri, 5 Aug 2022 13:27:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659731261; x=1691267261; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ePNL/BJVpo/bbOEHJwf0YabY4J1SL9la5lwC9AtaukM=; b=nwAyjVqfXY/c1DgJW/ZBLAsf3m033/zUeISOjPxf/lTUfqjSgFTaMVxx eckX2LVGpJkJIX2l9Ww52fZ6IUFeugximnIZ1EO/3yKp31CuRnSrSc5kh SFYBzYmSoXGqAgSgxK92MUeMlXuFP3WeaHUZ0cDluwdokCY1xsqqvdgBm soaeeVYw0OFpVg/ArwT3DeoaWzv4ycWsmu4N4XazIpc59RFpn9RoReXum NjKHmab+jNo6PhjxzzA8k1bUj0+tW/+LCL/+prxmPU6sSYpLdGEdC3gWS k5SDR8ZBeNoB6aFmnfbTiuhbC4a+GXt1OXMzVQnEhH2N9dxPRN2CbSIxD Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="290291228" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="290291228" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:27:40 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="600473571" Received: from jivaldiv-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.255.228.201]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:27:40 -0700 Subject: [PATCH v2 1/3] cxl/region: Move HPA setup to cxl_region_attach() From: Dan Williams To: linux-cxl@vger.kernel.org Cc: Jonathan Cameron , Vishal Verma , vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, dave.jiang@intel.com Date: Fri, 05 Aug 2022 13:27:40 -0700 Message-ID: <165973126020.1526540.14701949254436069807.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <165973125417.1526540.14425647258796609596.stgit@dwillia2-xfh.jf.intel.com> References: <165973125417.1526540.14425647258796609596.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org A recent bug fix added the setup of the endpoint decoder interleave geometry settings to cxl_region_attach(). Move the HPA setup there as well to keep all endpoint decoder parameter setting in a central location. For symmetry, move endpoint HPA teardown to cxl_region_detach(), and for switches move HPA setup / teardown to cxl_port_{setup,reset}_targets(). Cc: Jonathan Cameron Signed-off-by: Vishal Verma Signed-off-by: Dan Williams Reviewed-by: Ira Weiny Reviewed-by: Jonathan Cameron --- drivers/cxl/core/hdm.c | 26 ++------------------------ drivers/cxl/core/region.c | 24 ++++++++++++++++++++++-- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 8143e2615957..e096f74e19df 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -499,28 +499,6 @@ static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl) CXL_HDM_DECODER0_CTRL_TYPE); } -static void cxld_set_hpa(struct cxl_decoder *cxld, u64 *base, u64 *size) -{ - struct cxl_region *cxlr = cxld->region; - struct cxl_region_params *p = &cxlr->params; - - cxld->hpa_range = (struct range) { - .start = p->res->start, - .end = p->res->end, - }; - - *base = p->res->start; - *size = resource_size(p->res); -} - -static void cxld_clear_hpa(struct cxl_decoder *cxld) -{ - cxld->hpa_range = (struct range) { - .start = 0, - .end = -1, - }; -} - static int cxlsd_set_targets(struct cxl_switch_decoder *cxlsd, u64 *tgt) { struct cxl_dport **t = &cxlsd->target[0]; @@ -601,7 +579,8 @@ static int cxl_decoder_commit(struct cxl_decoder *cxld) ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->id)); cxld_set_interleave(cxld, &ctrl); cxld_set_type(cxld, &ctrl); - cxld_set_hpa(cxld, &base, &size); + base = cxld->hpa_range.start; + size = range_len(&cxld->hpa_range); writel(upper_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id)); writel(lower_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id)); @@ -674,7 +653,6 @@ static int cxl_decoder_reset(struct cxl_decoder *cxld) ctrl &= ~CXL_HDM_DECODER0_CTRL_COMMIT; writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id)); - cxld_clear_hpa(cxld); writel(0, hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(id)); writel(0, hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(id)); writel(0, hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id)); diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 40f04c543e41..e71077beb021 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1044,6 +1044,10 @@ static int cxl_port_setup_targets(struct cxl_port *port, cxld->interleave_ways = iw; cxld->interleave_granularity = ig; + cxld->hpa_range = (struct range) { + .start = p->res->start, + .end = p->res->end, + }; dev_dbg(&cxlr->dev, "%s:%s iw: %d ig: %d\n", dev_name(port->uport), dev_name(&port->dev), iw, ig); add_target: @@ -1070,13 +1074,21 @@ static void cxl_port_reset_targets(struct cxl_port *port, struct cxl_region *cxlr) { struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr); + struct cxl_decoder *cxld; /* * After the last endpoint has been detached the entire cxl_rr may now * be gone. */ - if (cxl_rr) - cxl_rr->nr_targets_set = 0; + if (!cxl_rr) + return; + cxl_rr->nr_targets_set = 0; + + cxld = cxl_rr->decoder; + cxld->hpa_range = (struct range) { + .start = 0, + .end = -1, + }; } static void cxl_region_teardown_targets(struct cxl_region *cxlr) @@ -1257,6 +1269,10 @@ static int cxl_region_attach(struct cxl_region *cxlr, cxled->cxld.interleave_ways = p->interleave_ways; cxled->cxld.interleave_granularity = p->interleave_granularity; + cxled->cxld.hpa_range = (struct range) { + .start = p->res->start, + .end = p->res->end, + }; return 0; @@ -1315,6 +1331,10 @@ static int cxl_region_detach(struct cxl_endpoint_decoder *cxled) } p->targets[cxled->pos] = NULL; p->nr_targets--; + cxled->cxld.hpa_range = (struct range) { + .start = 0, + .end = -1, + }; /* notify the region driver that one of its targets has departed */ up_write(&cxl_region_rwsem); From patchwork Fri Aug 5 20:27:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12937686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2670DC25B06 for ; Fri, 5 Aug 2022 20:27:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234198AbiHEU1t (ORCPT ); Fri, 5 Aug 2022 16:27:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241265AbiHEU1s (ORCPT ); Fri, 5 Aug 2022 16:27:48 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 513841EAD7 for ; Fri, 5 Aug 2022 13:27:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659731267; x=1691267267; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PefBthYFNcXmD0ngjLtBQzW6Hi3DAaM/+fOCkGKfQyA=; b=RBCmCuzBHxO9n/JcLJ3Y0acQIS5Ae3XD3si/mwXgL6ljOMv8nJdv0HVS KmzqOvpLN1rdU3sEj4Yc1PBjcopfHgy9IELouzNs1aMSvPoTPXs9/UIAS hhnkcf1nLsCCBJv1W55yFVpkEGyZJxSSVCmH5V/a1//m/UWupw58bcYCO NQBnkW52Jtw5Q3yACLmuJ+jZzlldeikrj9ddoiRRGU91oMpAX/gz1PwZ5 sfG8+pb5HtbG+XIWledqRjNx7MB7l4PIVdo+Jvm3+pgazWdf1uUVTg1JT HprBZ/xIg/dc8wmzeG4EqbXPASFkOAWg42RaLxBlS7jjLSk7t4lyK9vcl A==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="273331425" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="273331425" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:27:46 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="663123821" Received: from jivaldiv-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.255.228.201]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:27:46 -0700 Subject: [PATCH v2 2/3] cxl/region: Fix x1 interleave to greater than x1 interleave routing From: Dan Williams To: linux-cxl@vger.kernel.org Cc: Jonathan Cameron , vishal.l.verma@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, dave.jiang@intel.com Date: Fri, 05 Aug 2022 13:27:45 -0700 Message-ID: <165973126583.1526540.657948655360009242.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <165973125417.1526540.14425647258796609596.stgit@dwillia2-xfh.jf.intel.com> References: <165973125417.1526540.14425647258796609596.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org In cases where the decode fans out as it traverses downstream, the interleave granularity needs to increment to identify the port selector bits out of the remaining address bits. For example, recall that with an x2 parent port intereleave (IW == 1), the downstream decode for children of those ports will either see address bit IG+8 always set, or address bit IG+8 always clear. So if the child port needs to select a downstream port it can only use address bits starting at IG+9 (where IG and IW are the CXL encoded values for interleave granularity (ilog2(ig) - 8) and ways (ilog2(iw))). When the parent port interleave is x1 no such masking occurs and the child port can maintain the granularity that was routed to the parent port. Reported-by: Jonathan Cameron Signed-off-by: Dan Williams Reviewed-by: Vishal Verma Reviewed-by: Ira Weiny Reviewed-by: Jonathan Cameron Tested-by: Jonathan Cameron #via qemu --- drivers/cxl/core/region.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index e71077beb021..641bc6344a4a 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1025,7 +1025,11 @@ static int cxl_port_setup_targets(struct cxl_port *port, return rc; } - if (cxl_rr->nr_targets > 1) { + /* + * If @parent_port is masking address bits, pick the next unused address + * bit to route @port's targets. + */ + if (parent_iw > 1 && cxl_rr->nr_targets > 1) { u32 address_bit = max(peig + peiw, eiw + peig); eig = address_bit - eiw + 1; From patchwork Fri Aug 5 20:27:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12937687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 155E7C00140 for ; Fri, 5 Aug 2022 20:27:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241387AbiHEU1y (ORCPT ); Fri, 5 Aug 2022 16:27:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241265AbiHEU1x (ORCPT ); Fri, 5 Aug 2022 16:27:53 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA7852C12F for ; Fri, 5 Aug 2022 13:27:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659731272; x=1691267272; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZRWV1+5opmHqObzKTIWZnpxPfi226yRiosWga7WU20U=; b=KdLZMUwre+d/Ce9weIChQnGXdTxY9Bh5lTPzmjTAuPY9ZRT69r6ssZEK Gp/f5zyO9cAY1PuDsf4exDS/UjdcrZltfBcMedpAU32fVDzIBMtpEtWFA RtBmKGw5NF216EBDUTxNyMfd7L7aGibtSd+ybZ0P7vXYqfxL7lTdRYCQ4 sDrmlVxV8WC7Ou9d169VfKB97yVsC9rq4fj31d8ZoWS8Ek4ckOGAQXW1I SSO3xlzDXAPPX4+S5TyHGi7EUQmrtQtycoQcNTTvoulOcs2/a2416ywex YFeubAttQB0NgqEQ2j3VIR0YueaqqOsnd9fYra2bIKsXH5xDsiogEjQ2z Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="287847941" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="287847941" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:27:52 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="779855809" Received: from jivaldiv-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.255.228.201]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:27:52 -0700 Subject: [PATCH v2 3/3] cxl/region: Disallow region granularity != window granularity From: Dan Williams To: linux-cxl@vger.kernel.org Cc: Jonathan Cameron , Vishal Verma , vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, dave.jiang@intel.com Date: Fri, 05 Aug 2022 13:27:51 -0700 Message-ID: <165973127171.1526540.9923273539049172976.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <165973125417.1526540.14425647258796609596.stgit@dwillia2-xfh.jf.intel.com> References: <165973125417.1526540.14425647258796609596.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The endpoint decode granularity must be <= the window granularity otherwise capacity in the endpoints is lost in the decode. Consider an attempt to have a region granularity of 512 with 4 devices within a window that maps 2 host bridges at a granularity of 256 bytes: HPA DPA Offset HB Port EP 0x0 0x0 0 0 0 0x100 0x0 1 0 2 0x200 0x100 0 0 0 0x300 0x100 1 0 2 0x400 0x200 0 1 1 0x500 0x200 1 1 3 0x600 0x300 0 1 1 0x700 0x300 1 1 3 0x800 0x400 0 0 0 0x900 0x400 1 0 2 0xA00 0x500 0 0 0 0xB00 0x500 1 0 2 Notice how endpoint0 maps HPA 0x0 and 0x200 correctly, but then HPA 0x800 results in DPA 0x200 to 0x400 on endpoint0 being not skipped. Fix this by restricing the region granularity to be equal to the window granularity resulting in the following for a x4 region under a x2 window at a granularity of 256. HPA DPA Offset HB Port EP 0x0 0x0 0 0 0 0x100 0x0 1 0 2 0x200 0x0 0 1 1 0x300 0x0 1 1 3 0x400 0x100 0 0 0 0x500 0x100 1 0 2 0x600 0x100 0 1 1 0x700 0x100 1 1 3 Not that it ever made practical sense to support region granularity > window granularity. The window rotates host bridges causing endpoints to never see a consecutive stream of requests at the desired granularity without breaks to issue cycles to the other host bridge. Fixes: 80d10a6cee05 ("cxl/region: Add interleave geometry attributes") Cc: Jonathan Cameron Reviewed-by: Vishal Verma Signed-off-by: Dan Williams Reviewed-by: Ira Weiny Reviewed-by: Jonathan Cameron --- drivers/cxl/core/region.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 641bc6344a4a..401148016978 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -395,13 +395,14 @@ static ssize_t interleave_granularity_store(struct device *dev, return rc; /* - * Disallow region granularity less than root granularity to - * simplify the implementation. Otherwise, region's with a - * granularity less than the root interleave result in needing - * multiple endpoints to support a single slot in the - * interleave. + * When the host-bridge is interleaved, disallow region granularity != + * root granularity. Regions with a granularity less than the root + * interleave result in needing multiple endpoints to support a single + * slot in the interleave (possible to suport in the future). Regions + * with a granularity greater than the root interleave result in invalid + * DPA translations (invalid to support). */ - if (val < cxld->interleave_granularity) + if (cxld->interleave_ways > 1 && val != cxld->interleave_granularity) return -EINVAL; rc = down_write_killable(&cxl_region_rwsem);