From patchwork Fri Aug 5 20:37:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12937689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93857C00140 for ; Fri, 5 Aug 2022 20:38:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236380AbiHEUiB (ORCPT ); Fri, 5 Aug 2022 16:38:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234198AbiHEUiA (ORCPT ); Fri, 5 Aug 2022 16:38:00 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7264331F for ; Fri, 5 Aug 2022 13:37:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659731879; x=1691267879; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zfjsMIkbOzg0Kth9pZ5DX0mgXo6XF1g850I23O2ZjSQ=; b=FlQTps70HjWnvXLjlr69NE8jUteSdpkOeb6xCNd2P/X2CQLnGRrbv7fj 35UVXQW7pRbtRgPR2BW1qqzu/VJ8NU1tj1hyWk1mzXYXXU617FcQodRnO t+x2S/tdAcN4l1ydeGlctLu1aEgUMJBVJgmJ8X4ougSgJ37lPUn5opm6x oxa++2ejl4dufuVkKe9glocidLD9ULGkTu/FDc+yJbSAWHYE8rlQ/oVau T6VRjBnaGf7eOuGWZ1wsJ56r5RxoriWL2m5phyANKHN6CIpHlirPK4Jjn GaakBjg7KwTMiJhTFZZOwGPkIIkOfl7drRJep7PfjzxC3T0lnvFfVdtWg w==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="277209716" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="277209716" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:37:59 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="931355660" Received: from jivaldiv-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.255.228.201]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:37:57 -0700 Subject: [ndctl PATCH 1/6] cxl/test: Validate endpoint interleave geometry From: Dan Williams To: linux-cxl@vger.kernel.org Cc: Jonathan Cameron , vishal.l.verma@intel.com, dave.jiang@intel.com, ira.weiny@intel.com, alison.schofield@intel.com Date: Fri, 05 Aug 2022 13:37:56 -0700 Message-ID: <165973187660.1528532.13832323649814892720.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> References: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Check that endpoint interleave geometry settings are updated once the endpoint decoders are associated with a region. Reported-by: Jonathan Cameron Signed-off-by: Dan Williams --- test/cxl-region-sysfs.sh | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/test/cxl-region-sysfs.sh b/test/cxl-region-sysfs.sh index 2582edb3f306..110e03709e39 100644 --- a/test/cxl-region-sysfs.sh +++ b/test/cxl-region-sysfs.sh @@ -44,8 +44,8 @@ uuidgen > /sys/bus/cxl/devices/$region/uuid # setup interleave geometry nr_targets=${#endpoint[@]} echo $nr_targets > /sys/bus/cxl/devices/$region/interleave_ways -g=$(cat /sys/bus/cxl/devices/$decoder/interleave_granularity) -echo $g > /sys/bus/cxl/devices/$region/interleave_granularity +r_ig=$(cat /sys/bus/cxl/devices/$decoder/interleave_granularity) +echo $r_ig > /sys/bus/cxl/devices/$region/interleave_granularity echo $((nr_targets * (256<<20))) > /sys/bus/cxl/devices/$region/size # grab the list of memdevs grouped by host-bridge interleave position @@ -96,6 +96,22 @@ do done echo "$region added ${#endpoint[@]} targets: ${endpoint[@]}" +# validate all endpoint decoders have the correct setting +region_size=$(cat /sys/bus/cxl/devices/$region/size) +region_base=$(cat /sys/bus/cxl/devices/$region/resource) +for i in ${endpoint[@]} +do + iw=$(cat /sys/bus/cxl/devices/$i/interleave_ways) + ig=$(cat /sys/bus/cxl/devices/$i/interleave_granularity) + [ $iw -ne $nr_targets ] && err "$LINENO: decoder: $i iw: $iw targets: $nr_targets" + [ $ig -ne $r_ig] && err "$LINENO: decoder: $i ig: $ig root ig: $r_ig" + + sz=$(cat /sys/bus/cxl/devices/$i/size) + res=$(cat /sys/bus/cxl/devices/$i/start) + [ $sz -ne $region_size ] && err "$LINENO: decoder: $i sz: $sz region_size: $region_size" + [ $res -ne $region_base ] && err "$LINENO: decoder: $i base: $res region_base: $region_base" +done + # walk up the topology and commit all decoders echo 1 > /sys/bus/cxl/devices/$region/commit From patchwork Fri Aug 5 20:38:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12937690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3798BC00140 for ; Fri, 5 Aug 2022 20:38:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236583AbiHEUiF (ORCPT ); Fri, 5 Aug 2022 16:38:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234198AbiHEUiE (ORCPT ); Fri, 5 Aug 2022 16:38:04 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3B7EDFA for ; Fri, 5 Aug 2022 13:38:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659731883; x=1691267883; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MdnkW3zHJpxjY07Rupkb3kS0eWfU8z0wceaky1oj0rE=; b=fIKPA+aNxGUsYnfC+YFUAB+BihSon+ZfppAZeOVfE+nfLA/xlE0EFLvW hHEBkpXHk9A0uhEiX/OGyNN8q37mHW3qSsMrrPqOSxwD7TJQ+jNeY565o KIZZ4piJw8ym4lzxkFh5IGTzTutBtzXpKYAkb9pTIGtCfIkcsHz792yK6 0DxGffy6z8onNmGDOKzV8+QoBv+Hi4aYzNoVEQ7rGQ2oCmjqfnTF8FY1T O6boKjW3n/Ux8EVNED4Vge9r0VykHq0zYqdMmU14uLrC8FDrvuGtMFQJS D8ggUN+S6zQ1K3STxJMyJwN5AJeJL2jODhc4pHIbtvPqduDQ4nKGtIBHe g==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="277209725" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="277209725" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:03 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="603714849" Received: from jivaldiv-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.255.228.201]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:03 -0700 Subject: [ndctl PATCH 2/6] cxl/list: Add interleave parameters to decoder listings From: Dan Williams To: linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, dave.jiang@intel.com, ira.weiny@intel.com, alison.schofield@intel.com Date: Fri, 05 Aug 2022 13:38:03 -0700 Message-ID: <165973188300.1528532.222988685552982872.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> References: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Emit interleave_ways and interleave_granularity in decoder output. Signed-off-by: Dan Williams --- cxl/json.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/cxl/json.c b/cxl/json.c index ad93413b5f05..36b76d34b4e5 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -466,6 +466,26 @@ struct json_object *util_cxl_decoder_to_json(struct cxl_decoder *decoder, json_object_object_add(jdecoder, "size", jobj); } + val = cxl_decoder_get_interleave_ways(decoder); + if (val < UINT_MAX) { + jobj = json_object_new_int(val); + if (jobj) + json_object_object_add(jdecoder, "interleave_ways", + jobj); + + /* granularity is a don't care if not interleaving */ + if (val > 1) { + val = cxl_decoder_get_interleave_granularity(decoder); + if (val < UINT_MAX) { + jobj = json_object_new_int(val); + if (jobj) + json_object_object_add( + jdecoder, + "interleave_granularity", jobj); + } + } + } + if (size == 0) { jobj = json_object_new_string("disabled"); if (jobj) From patchwork Fri Aug 5 20:38:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12937691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8335C00140 for ; Fri, 5 Aug 2022 20:38:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234198AbiHEUiL (ORCPT ); Fri, 5 Aug 2022 16:38:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236727AbiHEUiK (ORCPT ); Fri, 5 Aug 2022 16:38:10 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B432531F for ; Fri, 5 Aug 2022 13:38:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659731889; x=1691267889; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=580o0fZSfeMUexRJckcK5xaYxR6kecesWhqv4qC6SRw=; b=IPnXggjtrx5mDgl1gnX0vqo8WgUKepfJT45TQ/gqHSdpn6o7k3LyPcwV zUB/rqxhSf/w97qPY4/8iFUaWVe8xsezvK+uOWd+mbWmh+p8JCwz07Aoz NcR0pfV2og2Tb8Qvm5zY1TkgTyEoKf4sOuDyPeTdzrQW3NVnWVgR6SPRx szNl5NoqUb4u+fj5OWU6ZuMpv8hBE0VPc5Efhm55Mz8+g56UFY8se82zD w6XT57n8fLA5QVSX2iVHXcck2OYtf0Zn3TJoDrjVE+T7ep9CwaEJpueDJ if+tVIm4xmDgtmyOAfVGVnrmtgg+r/YKtPFdFHApDGVhN9PMlOLathDzw A==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="290293693" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="290293693" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:09 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="693117973" Received: from jivaldiv-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.255.228.201]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:09 -0700 Subject: [ndctl PATCH 3/6] cxl/list: Add region to decoder listings From: Dan Williams To: linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, dave.jiang@intel.com, ira.weiny@intel.com, alison.schofield@intel.com Date: Fri, 05 Aug 2022 13:38:08 -0700 Message-ID: <165973188860.1528532.17427805440366364536.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> References: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org While decoders can be matched with regions by physical address, or filtered by region, it is also useful to get a plain listing of the association. Signed-off-by: Dan Williams --- Documentation/cxl/lib/libcxl.txt | 7 +++++++ cxl/json.c | 8 ++++++++ cxl/lib/libcxl.c | 34 ++++++++++++++++++++++++++++++++++ cxl/lib/libcxl.sym | 1 + cxl/libcxl.h | 1 + 5 files changed, 51 insertions(+) diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt index 7a38ce4a54e2..72641699633b 100644 --- a/Documentation/cxl/lib/libcxl.txt +++ b/Documentation/cxl/lib/libcxl.txt @@ -398,6 +398,7 @@ int cxl_decoder_set_dpa_size(struct cxl_decoder *decoder, unsigned long long siz const char *cxl_decoder_get_devname(struct cxl_decoder *decoder); int cxl_decoder_get_id(struct cxl_decoder *decoder); int cxl_decoder_get_nr_targets(struct cxl_decoder *decoder); +struct cxl_region *cxl_decoder_get_region(struct cxl_decoder *decoder); enum cxl_decoder_target_type { CXL_DECODER_TTYPE_UNKNOWN, @@ -446,6 +447,12 @@ Platform firmware may setup the CXL decode hierarchy before the OS boots, and may additionally require that the OS not change the decode settings. This property is indicated by the cxl_decoder_is_locked() API. +When a decoder is associated with a region cxl_decoder_get_region() +returns that region object. Note that it is only applicable to switch +and endpoint decoders as root decoders have a 1:N relationship with +regions. Use cxl_region_foreach() for the similar functionality for +root decoders. + ==== TARGETS A root or switch level decoder takes an SPA (system-physical-address) as input and routes it to a downstream port. Which downstream port depends diff --git a/cxl/json.c b/cxl/json.c index 36b76d34b4e5..82e3c552cdb1 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -442,6 +442,7 @@ struct json_object *util_cxl_decoder_to_json(struct cxl_decoder *decoder, const char *devname = cxl_decoder_get_devname(decoder); struct cxl_port *port = cxl_decoder_get_port(decoder); struct json_object *jdecoder, *jobj; + struct cxl_region *region; u64 val, size; jdecoder = json_object_new_object(); @@ -486,6 +487,13 @@ struct json_object *util_cxl_decoder_to_json(struct cxl_decoder *decoder, } } + region = cxl_decoder_get_region(decoder); + if (region) { + jobj = json_object_new_string(cxl_region_get_devname(region)); + if (jobj) + json_object_object_add(jdecoder, "region", jobj); + } + if (size == 0) { jobj = json_object_new_string("disabled"); if (jobj) diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index 5001c5685d74..aec3671b1625 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -2019,6 +2019,40 @@ cxl_decoder_get_interleave_ways(struct cxl_decoder *decoder) return decoder->interleave_ways; } +CXL_EXPORT struct cxl_region * +cxl_decoder_get_region(struct cxl_decoder *decoder) +{ + struct cxl_port *port = cxl_decoder_get_port(decoder); + struct cxl_ctx *ctx = cxl_decoder_get_ctx(decoder); + char *path = decoder->dev_buf; + char buf[SYSFS_ATTR_SIZE]; + struct cxl_region *region; + struct cxl_decoder *iter; + int rc; + + if (cxl_port_is_root(port)) + return NULL; + + sprintf(path, "%s/region", decoder->dev_path); + rc = sysfs_read_attr(ctx, path, buf); + if (rc < 0) { + err(ctx, "failed to read region name: %s\n", strerror(-rc)); + return NULL; + } + + if (strcmp(buf, "") == 0) + return NULL; + + while (!cxl_port_is_root(port)) + port = cxl_port_get_parent(port); + + cxl_decoder_foreach(port, iter) + cxl_region_foreach(iter, region) + if (strcmp(cxl_region_get_devname(region), buf) == 0) + return region; + return NULL; +} + CXL_EXPORT struct cxl_region * cxl_decoder_create_pmem_region(struct cxl_decoder *decoder) { diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 6bf3e91bdecc..573fcdf532d6 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -213,4 +213,5 @@ global: cxl_ep_decoder_get_memdev; cxl_decoder_get_interleave_granularity; cxl_decoder_get_interleave_ways; + cxl_decoder_get_region; } LIBCXL_2; diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 0b84977c2a2c..4b5490986a2a 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -185,6 +185,7 @@ bool cxl_decoder_is_locked(struct cxl_decoder *decoder); unsigned int cxl_decoder_get_interleave_granularity(struct cxl_decoder *decoder); unsigned int cxl_decoder_get_interleave_ways(struct cxl_decoder *decoder); +struct cxl_region *cxl_decoder_get_region(struct cxl_decoder *decoder); struct cxl_region *cxl_decoder_create_pmem_region(struct cxl_decoder *decoder); struct cxl_decoder *cxl_decoder_get_by_name(struct cxl_ctx *ctx, const char *ident); From patchwork Fri Aug 5 20:38:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12937692 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA44DC00140 for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="291059544" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="291059544" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:15 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="554233184" Received: from jivaldiv-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.255.228.201]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:14 -0700 Subject: [ndctl PATCH 4/6] cxl/list: Filter decoders by region From: Dan Williams To: linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, dave.jiang@intel.com, ira.weiny@intel.com, alison.schofield@intel.com Date: Fri, 05 Aug 2022 13:38:14 -0700 Message-ID: <165973189465.1528532.9072953032089147905.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> References: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org With a region name in hand, it is useful to be able to filter all the decoders in the topology that are mapping that region. Signed-off-by: Dan Williams --- cxl/filter.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/cxl/filter.c b/cxl/filter.c index 38ece5528794..9a3de8c75387 100644 --- a/cxl/filter.c +++ b/cxl/filter.c @@ -652,6 +652,26 @@ struct cxl_region *util_cxl_region_filter(struct cxl_region *region, } +static struct cxl_decoder * +util_cxl_decoder_filter_by_region(struct cxl_decoder *decoder, + const char *__ident) +{ + struct cxl_region *region; + + if (!__ident) + return decoder; + + region = cxl_decoder_get_region(decoder); + if (!region) + return NULL; + + region = util_cxl_region_filter(region, __ident); + if (!region) + return NULL; + + return decoder; +} + static unsigned long params_to_flags(struct cxl_filter_params *param) { unsigned long flags = 0; @@ -790,6 +810,9 @@ static void walk_decoders(struct cxl_port *port, struct cxl_filter_params *p, if (!util_cxl_decoder_filter_by_memdev( decoder, p->memdev_filter, p->serial_filter)) goto walk_children; + if (!util_cxl_decoder_filter_by_region(decoder, + p->region_filter)) + goto walk_children; if (!p->idle && cxl_decoder_get_size(decoder) == 0) continue; jdecoder = util_cxl_decoder_to_json(decoder, flags); From patchwork Fri Aug 5 20:38:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12937693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABC42C00140 for ; Fri, 5 Aug 2022 20:38:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237641AbiHEUiX (ORCPT ); Fri, 5 Aug 2022 16:38:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236727AbiHEUiV (ORCPT ); Fri, 5 Aug 2022 16:38:21 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 699BCDFA for ; Fri, 5 Aug 2022 13:38:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659731901; x=1691267901; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fTkPZf5LUDV9uSdQ8Nq40J4VCpvD6Kql8fzcFn4kgVc=; b=b+xaWp3MU9n99c3O5+Ck7mXRO1dvR3LWbnLNaQ/rUwVhn8fa0Rg6WWqd zNDfKC2pXJOw78IixbgWtI7kz0uPSUixEsD065B2li1bs33vFcLMTZeVl /mhFnP+PfOKtHxbTO+03fdbgHQGIWOpA5WIRMxSp5SiKEbqxJXF4qLG4X k+D4D9YGvw1HkYiIVm2Vr1+diiFffWwB9uu7JxRCBb4E2KHEtB7xOHlxZ qRjzlk5Ng18xZMP3en6+tfL8KtIvZeWCCIB/SXh/CRFQe6wuy+Ym2WEOU G5wwZmwpwrH7zPuLUfThJVLck8CDQysAwgMg8I8vkZ0l8xCPQtZwtwGN/ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="290293762" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="290293762" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:21 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="693118037" Received: from jivaldiv-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.255.228.201]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:20 -0700 Subject: [ndctl PATCH 5/6] cxl/list: Add 'depth' to port listings From: Dan Williams To: linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, dave.jiang@intel.com, ira.weiny@intel.com, alison.schofield@intel.com Date: Fri, 05 Aug 2022 13:38:20 -0700 Message-ID: <165973190022.1528532.6351628365510289908.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> References: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Simplify the task of determining how deep a port is in the hierarchy by just emitting what libcxl already counted. This is useful for validating interleave math. Signed-off-by: Dan Williams --- Documentation/cxl/lib/libcxl.txt | 1 + cxl/json.c | 4 ++++ cxl/lib/libcxl.c | 5 +++++ cxl/lib/libcxl.sym | 1 + cxl/libcxl.h | 1 + 5 files changed, 12 insertions(+) diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt index 72641699633b..5efa60124111 100644 --- a/Documentation/cxl/lib/libcxl.txt +++ b/Documentation/cxl/lib/libcxl.txt @@ -290,6 +290,7 @@ int cxl_port_is_enabled(struct cxl_port *port); bool cxl_port_is_root(struct cxl_port *port); bool cxl_port_is_switch(struct cxl_port *port); bool cxl_port_is_endpoint(struct cxl_port *port); +int cxl_port_get_depth(struct cxl_port *port); bool cxl_port_hosts_memdev(struct cxl_port *port, struct cxl_memdev *memdev); int cxl_port_get_nr_dports(struct cxl_port *port); ---- diff --git a/cxl/json.c b/cxl/json.c index 82e3c552cdb1..7aefcadb0795 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -761,6 +761,10 @@ static struct json_object *__util_cxl_port_to_json(struct cxl_port *port, if (jobj) json_object_object_add(jport, "host", jobj); + jobj = json_object_new_int(cxl_port_get_depth(port)); + if (jobj) + json_object_object_add(jport, "depth", jobj); + if (!cxl_port_is_enabled(port)) { jobj = json_object_new_string("disabled"); if (jobj) diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index aec3671b1625..4b78ecc1d115 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -2309,6 +2309,11 @@ CXL_EXPORT bool cxl_port_is_endpoint(struct cxl_port *port) return port->type == CXL_PORT_ENDPOINT; } +CXL_EXPORT int cxl_port_get_depth(struct cxl_port *port) +{ + return port->depth; +} + CXL_EXPORT struct cxl_bus *cxl_port_get_bus(struct cxl_port *port) { struct cxl_bus *bus; diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 573fcdf532d6..7dc3eee8a63c 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -96,6 +96,7 @@ global: cxl_port_get_parent; cxl_port_is_root; cxl_port_is_switch; + cxl_port_get_depth; cxl_port_to_bus; cxl_port_is_endpoint; cxl_port_to_endpoint; diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 4b5490986a2a..aa0a89d91b30 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -89,6 +89,7 @@ int cxl_port_is_enabled(struct cxl_port *port); struct cxl_port *cxl_port_get_parent(struct cxl_port *port); bool cxl_port_is_root(struct cxl_port *port); bool cxl_port_is_switch(struct cxl_port *port); +int cxl_port_get_depth(struct cxl_port *port); struct cxl_bus *cxl_port_to_bus(struct cxl_port *port); bool cxl_port_is_endpoint(struct cxl_port *port); struct cxl_endpoint *cxl_port_to_endpoint(struct cxl_port *port); From patchwork Fri Aug 5 20:38:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12937694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D739DC00140 for ; Fri, 5 Aug 2022 20:38:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236727AbiHEUi3 (ORCPT ); Fri, 5 Aug 2022 16:38:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237607AbiHEUi1 (ORCPT ); Fri, 5 Aug 2022 16:38:27 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41965E03 for ; Fri, 5 Aug 2022 13:38:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659731907; x=1691267907; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rWsllSkyx2RG5Grpr1DiiLPjziQsHokfjNNJ9pf0mqc=; b=kSNV39Z9j1jx41ZSvXgrUkxYHZVswuluM27j11//j3LDTGN2+uCX7lsv 6oPTVc65ebF4QWOmm1CEU+ZbjwVR9s8ivPjHV/OhoJuhUzAa08Jpt8mgi 8t15MXruuSmb+JY5UGC/sjjqO008hDBrHmaHILKwVPFX4Q4bQo3d4a8RK uUrrFD/QKx+DMPh809fqJs0khZPM3E9SmZPd0BytwlEwZL93oK02jpDkB RXoq5NYF0BiYw54gfuzwwRiQdR5S19iENWB9f6QeTuibLSHzaD6Kfcfrs JlxV20DR/eRsQW3oFtSJJBXR1yl0CBzBZ2aYhex3vAdYvfiWlSrcOKr0Y A==; X-IronPort-AV: E=McAfee;i="6400,9594,10430"; a="289044334" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="289044334" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:27 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="671815294" Received: from jivaldiv-mobl.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.255.228.201]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 13:38:26 -0700 Subject: [ndctl PATCH 6/6] cxl/test: Validate switch port settings in cxl-region-sysfs.sh From: Dan Williams To: linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, dave.jiang@intel.com, ira.weiny@intel.com, alison.schofield@intel.com Date: Fri, 05 Aug 2022 13:38:26 -0700 Message-ID: <165973190625.1528532.12244196912617964754.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> References: <165973187080.1528532.8097010788284626448.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org A recent kernel fix to add the missing update of endpoint decoder HPA range settings regressed switch decoder HPA range settings. Add validation for switch port settings to avoid regressions like that going forward. Signed-off-by: Dan Williams --- test/cxl-region-sysfs.sh | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/test/cxl-region-sysfs.sh b/test/cxl-region-sysfs.sh index 110e03709e39..ae0f55653814 100644 --- a/test/cxl-region-sysfs.sh +++ b/test/cxl-region-sysfs.sh @@ -112,6 +112,38 @@ do [ $res -ne $region_base ] && err "$LINENO: decoder: $i base: $res region_base: $region_base" done +# validate all switch decoders have the correct settings +nr_switches=$((nr_targets/2)) +nr_host_bridges=$((nr_switches/2)) +nr_switch_decoders=$((nr_switches + nr_host_bridges)) + +json=$($CXL list -D -r $region -d switch) +readarray -t switch_decoders < <(echo $json | jq -r ".[].decoder") + +[ ${#switch_decoders[@]} -ne $nr_switch_decoders ] && err \ +"$LINENO: expected $nr_switch_decoders got ${#switch_decoders[@]} switch decoders" + +for i in ${switch_decoders[@]} +do + decoder=$(echo $json | jq -r ".[] | select(.decoder == \"$i\")") + id=${i#decoder} + port_id=${id%.*} + depth=$($CXL list -p $port_id -S | jq -r ".[].depth") + iw=$(echo $decoder | jq -r ".interleave_ways") + ig=$(echo $decoder | jq -r ".interleave_granularity") + + [ $iw -ne 2 ] && err "$LINENO: decoder: $i iw: $iw targets: 2" + [ $ig -ne $((r_ig << depth)) ] && err \ + "$LINENO: decoder: $i ig: $ig switch_ig: $((r_ig << depth))" + + res=$(echo $decoder | jq -r ".resource") + sz=$(echo $decoder | jq -r ".size") + [ $sz -ne $region_size ] && err \ + "$LINENO: decoder: $i sz: $sz region_size: $region_size" + [ $res -ne $region_base ] && err \ + "$LINENO: decoder: $i base: $res region_base: $region_base" +done + # walk up the topology and commit all decoders echo 1 > /sys/bus/cxl/devices/$region/commit