From patchwork Fri Aug 5 20:51:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe JAILLET X-Patchwork-Id: 12937698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27672C00140 for ; Fri, 5 Aug 2022 20:53:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=WZdtk3y01Lu3ZA+V2v01/Lq7XyhF3udCegbf/VMhQi8=; b=Qr9K9RM+Hn2T7z DpQ0qkddOWytp62L+TnTSICOI1ocZ+rvh+6i1r4RJ1LadQNg6LzffWRsxhTxXihmDLHuYrULHnUn3 Amg/5rgfokryLlTneLu+o1H6W/gMlim34j1IgvKmmEOCLtMKkDQyL2PN6R8jvTZkeFDtW9Z0vm/lh 14XzPLbC/prH1pQgfonDBOrNTFzfTYzXmHKa6yho3SxU4V69s3upAT72JhspvsSYADL9EqXyqRZwZ plLokLrfVfivOwtx741PH2mYIV7VrKpPauUdq5cQFSXQVJwVlvD8LnwrtF08dTqmrrHAXkjx4o+fn /G1qJdYNYZ7vNPdT7tdg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oK4Id-000cQF-Sj; Fri, 05 Aug 2022 20:52:03 +0000 Received: from smtp09.smtpout.orange.fr ([80.12.242.131] helo=smtp.smtpout.orange.fr) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oK4Ia-000cMt-D6 for linux-arm-kernel@lists.infradead.org; Fri, 05 Aug 2022 20:52:02 +0000 Received: from pop-os.home ([90.11.190.129]) by smtp.orange.fr with ESMTPA id K4IPokAJ0sKAkK4IPorqln; Fri, 05 Aug 2022 22:51:50 +0200 X-ME-Helo: pop-os.home X-ME-Auth: YWZlNiIxYWMyZDliZWIzOTcwYTEyYzlhMmU3ZiQ1M2U2MzfzZDfyZTMxZTBkMTYyNDBjNDJlZmQ3ZQ== X-ME-Date: Fri, 05 Aug 2022 22:51:50 +0200 X-ME-IP: 90.11.190.129 From: Christophe JAILLET To: Will Deacon , Mark Rutland , Robin Murphy Cc: linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org, Christophe JAILLET , linux-arm-kernel@lists.infradead.org Subject: [PATCH] perf/arm_pmu_platform: Fix an error message related to dev_err_probe() usage Date: Fri, 5 Aug 2022 22:51:12 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220805_135200_607436_F24E007E X-CRM114-Status: GOOD ( 14.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org dev_err() is a macro that expand dev_fmt, but dev_err_probe() is a function and cannot perform this macro expansion. So hard code the "hw perfevents: " prefix and dd a comment explaining why. Fixes: 11fa1dc8020a ("perf/arm_pmu_platform: Use dev_err_probe() for IRQ errors") Signed-off-by: Christophe JAILLET --- Untested, but I can't see how it could work. --- drivers/perf/arm_pmu_platform.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm_pmu_platform.c b/drivers/perf/arm_pmu_platform.c index 513de1f54e2d..02cca4b8f0fd 100644 --- a/drivers/perf/arm_pmu_platform.c +++ b/drivers/perf/arm_pmu_platform.c @@ -101,8 +101,11 @@ static int pmu_parse_irqs(struct arm_pmu *pmu) struct device *dev = &pdev->dev; num_irqs = platform_irq_count(pdev); - if (num_irqs < 0) - return dev_err_probe(dev, num_irqs, "unable to count PMU IRQs\n"); + if (num_irqs < 0) { + /* dev_err_probe() does not handle dev_pm, so hard-code the prefix */ + return dev_err_probe(dev, num_irqs, + "hw perfevents: unable to count PMU IRQs\n"); + } /* * In this case we have no idea which CPUs are covered by the PMU.