From patchwork Mon Aug 8 08:05:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12938566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8DF57C00140 for ; Mon, 8 Aug 2022 08:06:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1Ii0XrP7+Z658b5nzYxK9jzH2h021EjGuMuwFYFqY4Q=; b=Ien7Y0Jn1XPfyL m9gRnNKh3SAiTlOHMr86EaPGo2n56C1g/KwSOEOsjnAUyx226U+06jXJfeuqcSpGvafbnyM3ee9dO 6jpejmoTdeBekYoKHJCZCGQ2kSIHoR9Q5R4BC9/I6co1QgVOstnMt/oJxQBy51YyC1hPtzzHHdhVQ NjZeXUkgxH4iTITkx/WaseO29LPvIoN33ZFDQpYi5eI7tBrftJ45wPvUBMvTM5TiNxWuSfXvTiGfD dxFKLugAjz0bfYYmtNIS2ZPagmVGEV5k7cBgbV5D12eX31/xB4IEwgN+TVlPPusKaDeK/XDyLLUjB XQGdTEbYZjG1lfKR5KVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oKxmK-00CIjN-N0; Mon, 08 Aug 2022 08:06:24 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oKxmF-00CIgo-Tl for linux-riscv@lists.infradead.org; Mon, 08 Aug 2022 08:06:23 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 278C560EB8; Mon, 8 Aug 2022 08:06:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8661C43470; Mon, 8 Aug 2022 08:06:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659945978; bh=E9+7aC4Yw8oq+CFp7IBpO6wuIDD2IWECqn1vNuAh4Gg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z0qSkbBljX/OZVI0viXnuLml2pfStiIeGHBuHL3siHSedGE3HFxJdpmfkjTY9a4o2 f5NMfXHQKQHILSlbZ1zG2pisBhbG7vz014u3Y8Sp2Oz9cu+qVCv7crr5i34VxSOz/8 XdZ+Ln/igjZG2mQylv4rBO7mxi0r7j8Nf/S4X9deoEe+uC5XXgDh6+sP2fRdNioMi5 UCeotd8qCbNhW8Si/WhecVACDm2EMuIWOPIm+Bc3nUYy2bw0BBOwjV1WAVbKfLD+Pp e4bTQ01W5hKN5m7clD3wp5pv+E0xom6T3Qym7q5pccVtQRktYW7+v+vDOS3scds5ch W3IXChEmQpSkQ== From: guoren@kernel.org To: tj@kernel.org, cl@linux.com, palmer@dabbelt.com, will@kernel.org, catalin.marinas@arm.com, peterz@infradead.org, arnd@arndb.de Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH 1/4] vmstat: percpu: Rename HAVE_CMPXCHG_LOCAL to HAVE_CMPXCHG_PERCPU_BYTE Date: Mon, 8 Aug 2022 04:05:57 -0400 Message-Id: <20220808080600.3346843-2-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220808080600.3346843-1-guoren@kernel.org> References: <20220808080600.3346843-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220808_010620_217123_EE5C36A2 X-CRM114-Status: GOOD ( 12.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The name HAVE_CMPXCHG_LOCAL is confused with using cmpxchg_local, but vmstat needs this_cpu_cmpxchg_1. Rename would clarify the meaning, and maybe we could remove cmpxchg(64)_local API (Only drivers/iommu/intel used) in the future. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- .../features/locking/cmpxchg-local/arch-support.txt | 6 +++--- arch/Kconfig | 2 +- arch/arm64/Kconfig | 2 +- arch/s390/Kconfig | 2 +- arch/x86/Kconfig | 2 +- mm/vmstat.c | 4 ++-- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/Documentation/features/locking/cmpxchg-local/arch-support.txt b/Documentation/features/locking/cmpxchg-local/arch-support.txt index 8b1a8d9e1c79..4d4c5c2fa66d 100644 --- a/Documentation/features/locking/cmpxchg-local/arch-support.txt +++ b/Documentation/features/locking/cmpxchg-local/arch-support.txt @@ -1,7 +1,7 @@ # -# Feature name: cmpxchg-local -# Kconfig: HAVE_CMPXCHG_LOCAL -# description: arch supports the this_cpu_cmpxchg() API +# Feature name: cmpxchg-percpu-byte +# Kconfig: HAVE_CMPXCHG_PERCPU_BYTE +# description: arch supports the this_cpu_cmpxchg_1() API # ----------------------- | arch |status| diff --git a/arch/Kconfig b/arch/Kconfig index f330410da63a..81800cdfe161 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -471,7 +471,7 @@ config HAVE_ALIGNED_STRUCT_PAGE on a struct page for better performance. However selecting this might increase the size of a struct page by a word. -config HAVE_CMPXCHG_LOCAL +config HAVE_CMPXCHG_PERCPU_BYTE bool config HAVE_CMPXCHG_DOUBLE diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 571cc234d0b3..24a82bdc766a 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -175,7 +175,7 @@ config ARM64 select HAVE_EBPF_JIT select HAVE_C_RECORDMCOUNT select HAVE_CMPXCHG_DOUBLE - select HAVE_CMPXCHG_LOCAL + select HAVE_CMPXCHG_PERCPU_BYTE select HAVE_CONTEXT_TRACKING_USER select HAVE_DEBUG_KMEMLEAK select HAVE_DMA_CONTIGUOUS diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 318fce77601d..ac03af800bf7 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -151,7 +151,7 @@ config S390 select HAVE_ARCH_VMAP_STACK select HAVE_ASM_MODVERSIONS select HAVE_CMPXCHG_DOUBLE - select HAVE_CMPXCHG_LOCAL + select HAVE_CMPXCHG_PERCPU_BYTE select HAVE_DEBUG_KMEMLEAK select HAVE_DMA_CONTIGUOUS select HAVE_DYNAMIC_FTRACE diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f9920f1341c8..5f4f6df7b89f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -184,7 +184,7 @@ config X86 select HAVE_ARCH_WITHIN_STACK_FRAMES select HAVE_ASM_MODVERSIONS select HAVE_CMPXCHG_DOUBLE - select HAVE_CMPXCHG_LOCAL + select HAVE_CMPXCHG_PERCPU_BYTE select HAVE_CONTEXT_TRACKING_USER if X86_64 select HAVE_CONTEXT_TRACKING_USER_OFFSTACK if HAVE_CONTEXT_TRACKING_USER select HAVE_C_RECORDMCOUNT diff --git a/mm/vmstat.c b/mm/vmstat.c index 373d2730fcf2..b2fc6d28d3b2 100644 --- a/mm/vmstat.c +++ b/mm/vmstat.c @@ -554,9 +554,9 @@ void __dec_node_page_state(struct page *page, enum node_stat_item item) } EXPORT_SYMBOL(__dec_node_page_state); -#ifdef CONFIG_HAVE_CMPXCHG_LOCAL +#ifdef CONFIG_HAVE_CMPXCHG_PERCPU_BYTE /* - * If we have cmpxchg_local support then we do not need to incur the overhead + * If we have this_cpu_cmpxchg_1 arch support then we do not need to incur the overhead * that comes with local_irq_save/restore if we use this_cpu_cmpxchg. * * mod_state() modifies the zone counter state through atomic per cpu From patchwork Mon Aug 8 08:05:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12938567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42730C25B0C for ; Mon, 8 Aug 2022 08:06:38 +0000 (UTC) DKIM-Signature: v=1; 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Mon, 08 Aug 2022 08:06:27 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 671BCB80E06; Mon, 8 Aug 2022 08:06:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41B85C433D6; Mon, 8 Aug 2022 08:06:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659945983; bh=88SuZrvyL3jeJFfiTyPwnClk88QEzLMNBQPdHR9UyV4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l4y7FiXxZ/3MlZLfl2cFaqKyz++tjbho4X9H2WHIaHFWDO4xvCWc/zx2pMZCTmn1s ckSQaw7NQ6Pqz1tTx6Tj19+TmTFv7OFhio/a29OboGFsDXyep7pzvjqsiQNxyO9FF8 p2aDspkgMOSU5FhziAy1LKzLPD2ko78xk4r2x57YV9o0MIoXHwXL96EdPbdabgQeAS EdUXQszkHktiCCDhkjmXnsppif1V4ZcWpmuIL4c0cvc4Hj6+/4REakl2Cpfo583b+7 9UEzb9BTXhYAvRoSLdFQpCxHzQSmUyE+M/pct1EIEP/461VqY22RUwFR861/Tn25c0 mmkj+T+xM93yA== From: guoren@kernel.org To: tj@kernel.org, cl@linux.com, palmer@dabbelt.com, will@kernel.org, catalin.marinas@arm.com, peterz@infradead.org, arnd@arndb.de Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH 2/4] arm64: percpu: Use generic PERCPU_RW_OPS Date: Mon, 8 Aug 2022 04:05:58 -0400 Message-Id: <20220808080600.3346843-3-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220808080600.3346843-1-guoren@kernel.org> References: <20220808080600.3346843-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220808_010626_094484_8974CECD X-CRM114-Status: UNSURE ( 8.09 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The generic percpu implementation also using READ_ONCE()/WRITE_ONCE(). And the generic even give a better __native_word() check. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/arm64/include/asm/percpu.h | 33 --------------------------------- 1 file changed, 33 deletions(-) diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h index b9ba19dbdb69..a58de20d742a 100644 --- a/arch/arm64/include/asm/percpu.h +++ b/arch/arm64/include/asm/percpu.h @@ -52,17 +52,6 @@ static inline unsigned long __kern_my_cpu_offset(void) #define __my_cpu_offset __kern_my_cpu_offset() #endif -#define PERCPU_RW_OPS(sz) \ -static inline unsigned long __percpu_read_##sz(void *ptr) \ -{ \ - return READ_ONCE(*(u##sz *)ptr); \ -} \ - \ -static inline void __percpu_write_##sz(void *ptr, unsigned long val) \ -{ \ - WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \ -} - #define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ static inline void \ __percpu_##name##_case_##sz(void *ptr, unsigned long val) \ @@ -120,10 +109,6 @@ __percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \ __PERCPU_RET_OP_CASE(w, , name, 32, op_llsc, op_lse) \ __PERCPU_RET_OP_CASE( , , name, 64, op_llsc, op_lse) -PERCPU_RW_OPS(8) -PERCPU_RW_OPS(16) -PERCPU_RW_OPS(32) -PERCPU_RW_OPS(64) PERCPU_OP(add, add, stadd) PERCPU_OP(andnot, bic, stclr) PERCPU_OP(or, orr, stset) @@ -168,24 +153,6 @@ PERCPU_RET_OP(add, add, ldadd) __retval; \ }) -#define this_cpu_read_1(pcp) \ - _pcp_protect_return(__percpu_read_8, pcp) -#define this_cpu_read_2(pcp) \ - _pcp_protect_return(__percpu_read_16, pcp) -#define this_cpu_read_4(pcp) \ - _pcp_protect_return(__percpu_read_32, pcp) -#define this_cpu_read_8(pcp) \ - _pcp_protect_return(__percpu_read_64, pcp) - -#define this_cpu_write_1(pcp, val) \ - _pcp_protect(__percpu_write_8, pcp, (unsigned long)val) -#define this_cpu_write_2(pcp, val) \ - _pcp_protect(__percpu_write_16, pcp, (unsigned long)val) -#define this_cpu_write_4(pcp, val) \ - _pcp_protect(__percpu_write_32, pcp, (unsigned long)val) -#define this_cpu_write_8(pcp, val) \ - _pcp_protect(__percpu_write_64, pcp, (unsigned long)val) - #define this_cpu_add_1(pcp, val) \ _pcp_protect(__percpu_add_case_8, pcp, val) #define this_cpu_add_2(pcp, val) \ From patchwork Mon Aug 8 08:05:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12938568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59B48C00140 for ; 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Mon, 08 Aug 2022 08:06:33 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oKxmQ-00CImr-Df for linux-riscv@lists.infradead.org; Mon, 08 Aug 2022 08:06:31 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 54E9160E2D; Mon, 8 Aug 2022 08:06:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C072DC433C1; Mon, 8 Aug 2022 08:06:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659945987; bh=O8oJK7US06ctrbwrFK6AhnyYDVDe+qcc6oGaVuVbZgk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ucjfa6QfVZzSkAjPgs+tH771FrLQURJA+lcfQx6r7YbD4/+oWwzq9VqbkDhxMtwpK M4PQGbG9i9IrK4C4ChmTS4G1RxftMkmtv+4DPkPXeyMRy6mGr0g9hTpi9pVm4oPLBF 2VBprduojP+o/X10wgiUPiiGuTuRr5E0du2iCpuUnjFCKhFMAxAZp9E95f0X7OMEld UDMFlZGorX/8I81qppDNYpfJnEVKmX2T9U7Rg4KI0L7QxH8n6SSsc85degeud2H7xx NPxf9DwuyYqcgXaP2tca9Gm+PAByQH5Jlt6ZZaiKfUCOSUsXpOEk0SCiumE8caJhVy L8mCL/mnosJuw== From: guoren@kernel.org To: tj@kernel.org, cl@linux.com, palmer@dabbelt.com, will@kernel.org, catalin.marinas@arm.com, peterz@infradead.org, arnd@arndb.de Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH 3/4] riscv: percpu: Implement this_cpu operations Date: Mon, 8 Aug 2022 04:05:59 -0400 Message-Id: <20220808080600.3346843-4-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220808080600.3346843-1-guoren@kernel.org> References: <20220808080600.3346843-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220808_010630_565765_76A5B964 X-CRM114-Status: GOOD ( 13.37 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren This patch provides riscv specific implementations for the this_cpu operations. We use atomic operations as appropriate (32 & 64 width). Use AMO instructions listed below for percpu, others are generic: - amoadd.w/d - amoand.w/d - amoor.w/d - amoswap.w/d Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/percpu.h | 104 ++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 arch/riscv/include/asm/percpu.h diff --git a/arch/riscv/include/asm/percpu.h b/arch/riscv/include/asm/percpu.h new file mode 100644 index 000000000000..f41d339c41f3 --- /dev/null +++ b/arch/riscv/include/asm/percpu.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _ASM_RISCV_PERCPU_H +#define _ASM_RISCV_PERCPU_H + +#include + +#define __PERCPU_OP_CASE(asm_type, name, sz, asm_op) \ +static inline void \ +__percpu_##name##_case_##sz(void *ptr, ulong val) \ +{ \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " zero, %1, (%0)" \ + : \ + : "r" (ptr), "r" (val) \ + : "memory"); \ +} + +#define __PERCPU_RET_OP_CASE(asm_type, name, sz, asm_op, c_op) \ +static inline u##sz \ +__percpu_##name##_return_case_##sz(void *ptr, ulong val) \ +{ \ + u##sz ret; \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " %0, %2, (%1)" \ + : "=r" (ret) \ + : "r" (ptr), "r" (val) \ + : "memory"); \ + \ + return ret c_op val; \ +} + +#ifdef CONFIG_64BIT +#define PERCPU_OP(name, asm_op) \ + __PERCPU_OP_CASE(w, name, 32, asm_op) \ + __PERCPU_OP_CASE(d, name, 64, asm_op) + +#define PERCPU_RET_OP(name, asm_op, c_op) \ + __PERCPU_RET_OP_CASE(w, name, 32, asm_op, c_op) \ + __PERCPU_RET_OP_CASE(d, name, 64, asm_op, c_op) +#else /* CONFIG_32BIT */ +#define PERCPU_OP(name, asm_op) \ + __PERCPU_OP_CASE(w, name, 32, asm_op) + +#define PERCPU_RET_OP(name, asm_op, c_op) \ + __PERCPU_RET_OP_CASE(w, name, 32, asm_op, c_op) +#endif /* CONFIG_64BIT */ + +PERCPU_OP(add, add) +PERCPU_OP(and, and) +PERCPU_OP(or, or) +PERCPU_RET_OP(add, add, +) + +#undef __PERCPU_OP_CASE +#undef __PERCPU_RET_OP_CASE +#undef PERCPU_OP +#undef PERCPU_RET_OP + +#define _pcp_protect(op, pcp, ...) \ +({ \ + preempt_disable_notrace(); \ + op(raw_cpu_ptr(&(pcp)), __VA_ARGS__); \ + preempt_enable_notrace(); \ +}) + +#define _pcp_protect_return(op, pcp, args...) \ +({ \ + typeof(pcp) __retval; \ + preempt_disable_notrace(); \ + if (__native_word(pcp)) \ + __retval = (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args);\ + else \ + BUILD_BUG(); \ + preempt_enable_notrace(); \ + __retval; \ +}) + +#define this_cpu_add_4(pcp, val) \ + _pcp_protect(__percpu_add_case_32, pcp, val) +#define this_cpu_add_return_4(pcp, val) \ + _pcp_protect_return(__percpu_add_return_case_32, pcp, val) +#define this_cpu_and_4(pcp, val) \ + _pcp_protect(__percpu_and_case_32, pcp, val) +#define this_cpu_or_4(pcp, val) \ + _pcp_protect(__percpu_or_case_32, pcp, val) +#define this_cpu_xchg_4(pcp, val) \ + _pcp_protect_return(xchg_relaxed, pcp, val) + +#ifdef CONFIG_64BIT +#define this_cpu_add_8(pcp, val) \ + _pcp_protect(__percpu_add_case_64, pcp, val) +#define this_cpu_add_return_8(pcp, val) \ + _pcp_protect_return(__percpu_add_return_case_64, pcp, val) +#define this_cpu_and_8(pcp, val) \ + _pcp_protect(__percpu_and_case_64, pcp, val) +#define this_cpu_or_8(pcp, val) \ + _pcp_protect(__percpu_or_case_64, pcp, val) +#define this_cpu_xchg_8(pcp, val) \ + _pcp_protect_return(xchg_relaxed, pcp, val) +#endif /* CONFIG_64BIT */ + +#include + +#endif /* _ASM_RISCV_PERCPU_H */ From patchwork Mon Aug 8 08:06:00 2022 Content-Type: text/plain; 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Mon, 8 Aug 2022 08:06:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659945992; bh=oWHU2Ny0CiPTyM5UPNfWTzYpuhtDEvS9sEcV0SmxrWI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K+G5/KlKkwLY6Ebo0r9E4N9FTGmZ3uTMDSuv6U5mVHrwZNbrUvgGeha8qE07emesC AxKPZwDNHOJ55bTsRJj1B/IMUBmJ6GmRHn/ocEqzyL+oQCmraI6vWcbeDuk9CVuwhW lSMe3UykOCmyl3FoFMv8HolaRexAg50Y5cqmRZvFSRhrboZEBa38LgHhDyLLFweBeD baRNoe+3NxAne8mCvrm2Ycw426nWoJYE4Osn+UmQw7iWDSY1QEjPEfjRotALSX/kmP Kum5pUZJ92+uJ0ahWtd71O4QR+uGf6bZF56r0QT4CiKRUKeayXfKf2J4ID+0DbmMlJ werEzzwgbePQQ== From: guoren@kernel.org To: tj@kernel.org, cl@linux.com, palmer@dabbelt.com, will@kernel.org, catalin.marinas@arm.com, peterz@infradead.org, arnd@arndb.de Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Guo Ren Subject: [RFC PATCH 4/4] riscv: cmpxchg: Remove unused cmpxchg(64)_local Date: Mon, 8 Aug 2022 04:06:00 -0400 Message-Id: <20220808080600.3346843-5-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220808080600.3346843-1-guoren@kernel.org> References: <20220808080600.3346843-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220808_010633_242688_5248AC8D X-CRM114-Status: UNSURE ( 8.27 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Only cmpxchg64_local is used in drivers/iommu/intel/iommu.c, and cmpxchg_local has been deprecated in common part. So cmpxchg_local is unecessary to riscv. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/cmpxchg.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 12debce235e5..0407680b13ad 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -345,19 +345,10 @@ _o_, _n_, sizeof(*(ptr))); \ }) -#define arch_cmpxchg_local(ptr, o, n) \ - (__cmpxchg_relaxed((ptr), (o), (n), sizeof(*(ptr)))) - #define arch_cmpxchg64(ptr, o, n) \ ({ \ BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ arch_cmpxchg((ptr), (o), (n)); \ }) -#define arch_cmpxchg64_local(ptr, o, n) \ -({ \ - BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - arch_cmpxchg_relaxed((ptr), (o), (n)); \ -}) - #endif /* _ASM_RISCV_CMPXCHG_H */