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Wed, 10 Aug 2022 05:21:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT006.mail.protection.outlook.com (10.13.174.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5525.11 via Frontend Transport; Wed, 10 Aug 2022 05:21:03 +0000 Received: from bhadra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 10 Aug 2022 00:20:41 -0500 From: Manali Shukla To: , CC: , Subject: [kvm-unit-tests PATCH v2 1/4] x86: nSVM: Add an exception test framework and tests Date: Wed, 10 Aug 2022 05:20:27 +0000 Message-ID: <20220810052027.7575-1-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220810050738.7442-1-manali.shukla@amd.com> References: <20220810050738.7442-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a73fcf63-8eeb-416c-0d9b-08da7a901f13 X-MS-TrafficTypeDiagnostic: SJ0PR12MB7082:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2022 05:21:03.9380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a73fcf63-8eeb-416c-0d9b-08da7a901f13 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7082 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Set up a test framework that verifies an exception occurring in L2 is forwarded to the right place (L1 or L2). It adds an exception test array and exception callbacks to that array. Tests two conditions for each exception. 1) Exception generated in L2, is handled by L2 when L2 exception handler is registered. 2) Exception generated in L2, is handled by L1 when intercept exception bit map is set in L1. Add testing for below exceptions: (#GP, #UD, #DE, #DB, #AC) 1. #GP is generated in c by non-canonical access in L2. 2. #UD is generated by calling "ud2" instruction in L2. 3. #DE is generated using instrumented code which generates divide by zero condition. 4. #DB is generated by setting TF bit before entering to L2. 5. #AC is genrated by writing 8 bytes to 4 byte aligned address in L2 user mode when AM bit is set in CR0 register and AC bit is set in RFLAGS. Signed-off-by: Manali Shukla --- x86/svm_tests.c | 114 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/x86/svm_tests.c b/x86/svm_tests.c index e2ec954..7544034 100644 --- a/x86/svm_tests.c +++ b/x86/svm_tests.c @@ -10,6 +10,7 @@ #include "isr.h" #include "apic.h" #include "delay.h" +#include "x86/usermode.h" #define SVM_EXIT_MAX_DR_INTERCEPT 0x3f @@ -3289,6 +3290,118 @@ static void svm_intr_intercept_mix_smi(void) svm_intr_intercept_mix_run_guest(NULL, SVM_EXIT_SMI); } +static void svm_l2_gp_test(struct svm_test *test) +{ + *(volatile u64 *)NONCANONICAL = 0; +} + +static void svm_l2_ud_test(struct svm_test *test) +{ + asm volatile ("ud2"); +} + +static void svm_l2_de_test(struct svm_test *test) +{ + asm volatile ( + "xor %%eax, %%eax\n\t" + "xor %%ebx, %%ebx\n\t" + "xor %%edx, %%edx\n\t" + "idiv %%ebx\n\t" + ::: "eax", "ebx", "edx"); +} + +static void svm_l2_db_test(struct svm_test *test) +{ + write_rflags(read_rflags() | X86_EFLAGS_TF); +} + +static uint64_t usermode_callback(void) +{ + /* + * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. + * Disclaimer: It is assumed that the stack pointer is aligned + * on a 16-byte boundary as x86_64 stacks should be. + */ + asm volatile("movq $0, -0x4(%rsp)"); + + return 0; +} + +static void svm_l2_ac_test(struct svm_test *test) +{ + bool hit_ac = false; + + write_cr0(read_cr0() | X86_CR0_AM); + write_rflags(read_rflags() | X86_EFLAGS_AC); + + run_in_user(usermode_callback, AC_VECTOR, 0, 0, 0, 0, &hit_ac); + report(hit_ac, "Usermode #AC handled in L2"); + vmmcall(); +} + +struct svm_exception_test { + u8 vector; + void (*guest_code)(struct svm_test*); +}; + +struct svm_exception_test svm_exception_tests[] = { + { GP_VECTOR, svm_l2_gp_test }, + { UD_VECTOR, svm_l2_ud_test }, + { DE_VECTOR, svm_l2_de_test }, + { DB_VECTOR, svm_l2_db_test }, + { AC_VECTOR, svm_l2_ac_test }, +}; + +static u8 svm_exception_test_vector; + +static void svm_exception_handler(struct ex_regs *regs) +{ + report(regs->vector == svm_exception_test_vector, + "Handling %s in L2's exception handler", + exception_mnemonic(svm_exception_test_vector)); + vmmcall(); +} + +static void handle_exception_in_l2(u8 vector) +{ + handler old_handler = handle_exception(vector, svm_exception_handler); + svm_exception_test_vector = vector; + + report(svm_vmrun() == SVM_EXIT_VMMCALL, + "%s handled by L2", exception_mnemonic(vector)); + + handle_exception(vector, old_handler); +} + +static void handle_exception_in_l1(u32 vector) +{ + u32 old_ie = vmcb->control.intercept_exceptions; + + vmcb->control.intercept_exceptions |= (1ULL << vector); + + report(svm_vmrun() == (SVM_EXIT_EXCP_BASE + vector), + "%s handled by L1", exception_mnemonic(vector)); + + vmcb->control.intercept_exceptions = old_ie; +} + +static void svm_exception_test(void) +{ + struct svm_exception_test *t; + int i; + + for (i = 0; i < ARRAY_SIZE(svm_exception_tests); i++) { + t = &svm_exception_tests[i]; + test_set_guest(t->guest_code); + + handle_exception_in_l2(t->vector); + vmcb_ident(vmcb); + + handle_exception_in_l1(t->vector); + vmcb_ident(vmcb); + } +} + struct svm_test svm_tests[] = { { "null", default_supported, default_prepare, default_prepare_gif_clear, null_test, @@ -3389,6 +3502,7 @@ struct svm_test svm_tests[] = { TEST(svm_nm_test), TEST(svm_int3_test), TEST(svm_into_test), + TEST(svm_exception_test), TEST(svm_lbrv_test0), TEST(svm_lbrv_test1), TEST(svm_lbrv_test2), From patchwork Wed Aug 10 05:21:02 2022 Content-Type: text/plain; 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Wed, 10 Aug 2022 05:21:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT035.mail.protection.outlook.com (10.13.175.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5525.11 via Frontend Transport; Wed, 10 Aug 2022 05:21:52 +0000 Received: from bhadra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 10 Aug 2022 00:21:46 -0500 From: Manali Shukla To: , CC: , Subject: [kvm-unit-tests PATCH v2 2/4] x86: nSVM: Move #BP test to exception test framework Date: Wed, 10 Aug 2022 05:21:02 +0000 Message-ID: <20220810052102.7591-1-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220810050738.7442-1-manali.shukla@amd.com> References: <20220810050738.7442-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fa966391-b371-4c7e-3b84-08da7a903c39 X-MS-TrafficTypeDiagnostic: DM6PR12MB4499:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2022 05:21:52.8422 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa966391-b371-4c7e-3b84-08da7a903c39 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4499 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Remove boiler plate code for #BP test and move #BP exception test in exception test framework. Signed-off-by: Manali Shukla --- x86/svm_tests.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/x86/svm_tests.c b/x86/svm_tests.c index 7544034..b36aec1 100644 --- a/x86/svm_tests.c +++ b/x86/svm_tests.c @@ -2804,26 +2804,11 @@ static void svm_into_test(void) "#OF is generated in L2 exception handler"); } -static int bp_test_counter; - -static void guest_test_bp_handler(struct ex_regs *r) -{ - bp_test_counter++; -} - -static void svm_bp_test_guest(struct svm_test *test) +static void svm_l2_bp_test(struct svm_test *test) { asm volatile("int3"); } -static void svm_int3_test(void) -{ - handle_exception(BP_VECTOR, guest_test_bp_handler); - test_set_guest(svm_bp_test_guest); - report(svm_vmrun() == SVM_EXIT_VMMCALL && bp_test_counter == 1, - "#BP is handled in L2 exception handler"); -} - static int nm_test_counter; static void guest_test_nm_handler(struct ex_regs *r) @@ -3350,6 +3335,7 @@ struct svm_exception_test svm_exception_tests[] = { { DE_VECTOR, svm_l2_de_test }, { DB_VECTOR, svm_l2_db_test }, { AC_VECTOR, svm_l2_ac_test }, + { BP_VECTOR, svm_l2_bp_test }, }; static u8 svm_exception_test_vector; @@ -3500,7 +3486,6 @@ struct svm_test svm_tests[] = { TEST(svm_vmload_vmsave), TEST(svm_test_singlestep), TEST(svm_nm_test), - TEST(svm_int3_test), TEST(svm_into_test), TEST(svm_exception_test), TEST(svm_lbrv_test0), From patchwork Wed Aug 10 05:22:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 12940233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 526C8C00140 for ; Wed, 10 Aug 2022 05:22:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230493AbiHJFWw (ORCPT ); Wed, 10 Aug 2022 01:22:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230165AbiHJFWv (ORCPT ); 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Signed-off-by: Manali Shukla --- x86/svm_tests.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/x86/svm_tests.c b/x86/svm_tests.c index b36aec1..b0f0980 100644 --- a/x86/svm_tests.c +++ b/x86/svm_tests.c @@ -2756,15 +2756,7 @@ static void pause_filter_test(void) } } - -static int of_test_counter; - -static void guest_test_of_handler(struct ex_regs *r) -{ - of_test_counter++; -} - -static void svm_of_test_guest(struct svm_test *test) +static void svm_l2_of_test(struct svm_test *test) { struct far_pointer32 fp = { .offset = (uintptr_t)&&into, @@ -2796,14 +2788,6 @@ into: __builtin_unreachable(); } -static void svm_into_test(void) -{ - handle_exception(OF_VECTOR, guest_test_of_handler); - test_set_guest(svm_of_test_guest); - report(svm_vmrun() == SVM_EXIT_VMMCALL && of_test_counter == 1, - "#OF is generated in L2 exception handler"); -} - static void svm_l2_bp_test(struct svm_test *test) { asm volatile("int3"); @@ -3336,6 +3320,7 @@ struct svm_exception_test svm_exception_tests[] = { { DB_VECTOR, svm_l2_db_test }, { AC_VECTOR, svm_l2_ac_test }, { BP_VECTOR, svm_l2_bp_test }, + { OF_VECTOR, svm_l2_of_test }, }; static u8 svm_exception_test_vector; @@ -3486,7 +3471,6 @@ struct svm_test svm_tests[] = { TEST(svm_vmload_vmsave), TEST(svm_test_singlestep), TEST(svm_nm_test), - TEST(svm_into_test), TEST(svm_exception_test), TEST(svm_lbrv_test0), TEST(svm_lbrv_test1), From patchwork Wed Aug 10 05:23:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 12940234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66C05C00140 for ; Wed, 10 Aug 2022 05:23:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230322AbiHJFXi (ORCPT ); Wed, 10 Aug 2022 01:23:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230119AbiHJFXh (ORCPT ); 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Wed, 10 Aug 2022 00:23:30 -0500 From: Manali Shukla To: , CC: , Subject: [kvm-unit-tests PATCH v2 4/4] x86: nSVM: Move part of #NM test to exception test framework Date: Wed, 10 Aug 2022 05:23:13 +0000 Message-ID: <20220810052313.7630-1-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220810050738.7442-1-manali.shukla@amd.com> References: <20220810050738.7442-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b0e56345-06c7-4025-367a-08da7a907817 X-MS-TrafficTypeDiagnostic: BN6PR12MB1508:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RfqS9zaytDsR9CxylkUQ6DExeLUvBaxWcQrVb/pYnJLCcTIzqfmSrPl8lzIQsPPq1npIrg8Upt+TIwt2JzFrgZu6/gKt7s0QWV0xkw7CK6FIdojzlGPPN6rwozSlBPO4MwyxxsCQ0C/YIIlo8COYrNc3odHY456mXzzFX6kLPET+QBwHDEgoIWv9iLHGjPrqMO9AAuZ7yPQQZo9KgyVm17sdrmEm6d39XlwihtdC4m/ZrQQlj/D6YWl/OuTi/avHRfPnjyyVQJC0wYaq7rTjC7HVuK/taTeUO3gREJjoYCkikCY1iBreyYjDmdLhbuZOt0MarpSWarMZJodWrTnsmSagDsZIM44PR/XK7PymLGAgcgMGNYozN1bOsKpku5JS0aQhmKZyc2Ey5MPmPD1hhjUGyKqHCRN8a351t2itL5Qvomf6jhQMQtJ7V+wZG2isPRDq7WBNjyWUQsNLK2WrMeyMJd1LSi8rooh8+zhCI4n4hCwcylaipsz4omAv06cpZn14loyA98fdywEys9CpVXDIo5SO3vvgH3xQ9HR7D5268vwF/NOKahSMVOiYMgZRl9K0ArunRF9BDjifSth1j8uX2oEEhurJMZ89wHZP29Eiue6nu6jWBuw7PlaOrmLbmjKejWRVFb5+nLvFUic0gcfGgs71sksyI07HUukvWqcKaCywNcw9pPM4jriiFE0/sLMY3m+oKNbQwuhsw5G0Hyf0RNb1rmwQQqQPLa7z8C5B1mFWgZticLpk0/5cfRCggnlREe2lustOEG823gcQ+jqG7oRSgQ8dSPuPIMJ379J68IgxvhrW5unp8AeJ+hocWTLvvgLgtXfGWsWs4Fq/Rg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(376002)(396003)(39860400002)(346002)(136003)(40470700004)(36840700001)(46966006)(1076003)(83380400001)(36756003)(2906002)(82740400003)(8676002)(4326008)(40460700003)(2616005)(426003)(47076005)(6666004)(26005)(336012)(7696005)(16526019)(186003)(41300700001)(70586007)(70206006)(44832011)(36860700001)(8936002)(5660300002)(82310400005)(478600001)(86362001)(40480700001)(81166007)(110136005)(316002)(54906003)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2022 05:23:33.3294 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0e56345-06c7-4025-367a-08da7a907817 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1508 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Remove the boiler plate code for #NM test and move #NM exception test in exception test framework. Keep the test case for the condition where #NM exception is not generated as it is. Signed-off-by: Manali Shukla --- x86/svm_tests.c | 44 ++++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/x86/svm_tests.c b/x86/svm_tests.c index b0f0980..2ed65c3 100644 --- a/x86/svm_tests.c +++ b/x86/svm_tests.c @@ -2807,34 +2807,18 @@ static void svm_nm_test_guest(struct svm_test *test) asm volatile("fnop"); } -/* This test checks that: - * - * (a) If CR0.TS is set in L2, #NM is handled by L2 when - * just an L2 handler is registered. - * - * (b) If CR0.TS is cleared and CR0.EM is set, #NM is handled - * by L2 when just an l2 handler is registered. - * - * (c) If CR0.TS and CR0.EM are cleared in L2, no exception - * is generated. +/* + * If CR0.TS and CR0.EM are cleared in L2, no exception + * is generated. */ - static void svm_nm_test(void) { handle_exception(NM_VECTOR, guest_test_nm_handler); write_cr0(read_cr0() & ~X86_CR0_TS); test_set_guest(svm_nm_test_guest); - vmcb->save.cr0 = vmcb->save.cr0 | X86_CR0_TS; - report(svm_vmrun() == SVM_EXIT_VMMCALL && nm_test_counter == 1, - "fnop with CR0.TS set in L2, #NM is triggered"); - - vmcb->save.cr0 = (vmcb->save.cr0 & ~X86_CR0_TS) | X86_CR0_EM; - report(svm_vmrun() == SVM_EXIT_VMMCALL && nm_test_counter == 2, - "fnop with CR0.EM set in L2, #NM is triggered"); - vmcb->save.cr0 = vmcb->save.cr0 & ~(X86_CR0_TS | X86_CR0_EM); - report(svm_vmrun() == SVM_EXIT_VMMCALL && nm_test_counter == 2, + report(svm_vmrun() == SVM_EXIT_VMMCALL && nm_test_counter == 0, "fnop with CR0.TS and CR0.EM unset no #NM excpetion"); } @@ -3308,6 +3292,24 @@ static void svm_l2_ac_test(struct svm_test *test) vmmcall(); } +/* + * If CR0.TS is set in L2, #NM is generared + */ +static void svm_l2_nm_test(struct svm_test *svm) +{ + write_cr0(read_cr0() | X86_CR0_TS); + asm volatile("fnop"); +} + +/* + * If CR0.TS is cleared and CR0.EM is set, #NM is generated + */ +static void svm_l2_nm_test1(struct svm_test *svm) +{ + write_cr0((read_cr0() & ~X86_CR0_TS) | X86_CR0_EM); + asm volatile("fnop"); +} + struct svm_exception_test { u8 vector; void (*guest_code)(struct svm_test*); @@ -3321,6 +3323,8 @@ struct svm_exception_test svm_exception_tests[] = { { AC_VECTOR, svm_l2_ac_test }, { BP_VECTOR, svm_l2_bp_test }, { OF_VECTOR, svm_l2_of_test }, + { NM_VECTOR, svm_l2_nm_test }, + { NM_VECTOR, svm_l2_nm_test1 }, }; static u8 svm_exception_test_vector;