From patchwork Thu Aug 11 18:52:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Koller X-Patchwork-Id: 12941699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B7EDC25B0C for ; Thu, 11 Aug 2022 18:52:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235976AbiHKSwV (ORCPT ); Thu, 11 Aug 2022 14:52:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235967AbiHKSwR (ORCPT ); Thu, 11 Aug 2022 14:52:17 -0400 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FC969DF98 for ; Thu, 11 Aug 2022 11:52:16 -0700 (PDT) Received: by mail-pf1-x449.google.com with SMTP id z5-20020a056a001d8500b0052e691eed53so7916450pfw.13 for ; Thu, 11 Aug 2022 11:52:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc; bh=zz99fKzwjwDHJo8VLz/7LS0wHhldAxFtS0b0KytwMEA=; b=mMsWaCnsqnOEQ6Bvki66q5wsRB1x/slSTddPfkvkrLtK6Q+LOEU1HNlHVTL8/bp1Iw Ji1uYYaunHXFkpuA+lePaCSi8rwJBS/RA8E8gCrGQ7ZZ2s2notMohma6oUFzZeFpK8li KE3JiZwdZLer9YdEAbUC0Z09HDEFBLkDSdNDttDL7RjedJGa5GTryHXGXXYyr+Xy+BG8 kNFXct3+hZh8ApS+9newCGooHT4N9OsiMyyasWVx4OnAvg9mYu77X4T9kUDnmM2Rjfw2 GA5GNrNJOVXo8I34xra58Kt666Cpz6ss7J0gOLTiPxVIEEok84r+SiqjdTNtSh4SRmcJ x/Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc; bh=zz99fKzwjwDHJo8VLz/7LS0wHhldAxFtS0b0KytwMEA=; b=YY2BkSLyI4cG1MQAcIkAF/0u9AQrndP6dXFS19Ykpv00FdxrvligdT63pz/x/Zb9ox 4MwLCZCcV0e97gPmbrdA/0RLgnHJM1f/+OAK6sdDO58sXZGWwGINq4H9jB/0rDSs7E2n 0kNb7vdj/D9wvRPurAsz3m3hHKbWo5wf8FXFBnOydUEg+fsoOJNhcaoQfVfyftfE4tkp mNuV9dvsK00siFd0wKj/wAexLQL60OQV9L9cpBhAbJknu4tqafyMJ5aA2rh61DgJeKpe Ttq+GoxOXCSw8IcQE9nTibPtREZpzh/qjztDhIMDzJd8MzR5hYcmXAFcOG+71OCwuFYD Xkow== X-Gm-Message-State: ACgBeo2kCbXE3OSJuhhjaSaWCZbH+3AU3WWwFCNvZ0ye16bK9QYinRsZ Ba+0acINowcGJenM+6oe51mb971M1oFlPOZhQBc0XV9Y9V1elOllH2YtGXEmsL3eKmVYDo1qLXX b/Bf74F0y27LCRYAmDnu5vh4L7VUJxqnWH4k15tM5HO4v7XK195pbP1KuLa5Fcdw= X-Google-Smtp-Source: AA6agR6KCV4zKclcwL7i7wND5hfdvI19kKOD0HMnJIDp9WuoEU90pLaAs38vmeyM2AskMn48YMCmelVVkyiWvw== X-Received: from ricarkol2.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:62fe]) (user=ricarkol job=sendgmr) by 2002:a17:90a:9ce:b0:1f3:c90:6e99 with SMTP id 72-20020a17090a09ce00b001f30c906e99mr10125701pjo.211.1660243935689; Thu, 11 Aug 2022 11:52:15 -0700 (PDT) Date: Thu, 11 Aug 2022 11:52:07 -0700 In-Reply-To: <20220811185210.234711-1-ricarkol@google.com> Message-Id: <20220811185210.234711-2-ricarkol@google.com> Mime-Version: 1.0 References: <20220811185210.234711-1-ricarkol@google.com> X-Mailer: git-send-email 2.37.1.559.g78731f0fdb-goog Subject: [kvm-unit-tests PATCH v4 1/4] arm: pmu: Add missing isb()'s after sys register writing From: Ricardo Koller To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, andrew.jones@linux.dev Cc: maz@kernel.org, alexandru.elisei@arm.com, eric.auger@redhat.com, oliver.upton@linux.dev, reijiw@google.com, Ricardo Koller Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org There are various pmu tests that require an isb() between enabling counting and the actual counting. This can lead to count registers reporting less events than expected; the actual enabling happens after some events have happened. For example, some missing isb()'s in the pmu-sw-incr test lead to the following errors on bare-metal: INFO: pmu: pmu-sw-incr: SW_INCR counter #0 has value 4294967280 PASS: pmu: pmu-sw-incr: PWSYNC does not increment if PMCR.E is unset FAIL: pmu: pmu-sw-incr: counter #1 after + 100 SW_INCR FAIL: pmu: pmu-sw-incr: counter #0 after + 100 SW_INCR INFO: pmu: pmu-sw-incr: counter values after 100 SW_INCR #0=82 #1=98 PASS: pmu: pmu-sw-incr: overflow on counter #0 after 100 SW_INCR SUMMARY: 4 tests, 2 unexpected failures Add the missing isb()'s on all failing tests, plus some others that seem required: - after clearing the overflow signal in the IRQ handler to make spurious interrupts less likely. - after direct writes to PMSWINC_EL0 for software to read the correct value for PMEVNCTR0_EL0 (from ARM DDI 0487H.a, page D13-5237). Reviewed-by: Alexandru Elisei Signed-off-by: Ricardo Koller --- arm/pmu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 15c542a2..4c601b05 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -307,6 +307,7 @@ static void irq_handler(struct pt_regs *regs) } } write_sysreg(ALL_SET, pmovsclr_el0); + isb(); } else { pmu_stats.unexpected = true; } @@ -534,10 +535,12 @@ static void test_sw_incr(void) write_sysreg_s(0x3, PMCNTENSET_EL0); write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); + isb(); for (i = 0; i < 100; i++) write_sysreg(0x1, pmswinc_el0); + isb(); report_info("SW_INCR counter #0 has value %ld", read_regn_el0(pmevcntr, 0)); report(read_regn_el0(pmevcntr, 0) == PRE_OVERFLOW, "PWSYNC does not increment if PMCR.E is unset"); @@ -547,10 +550,12 @@ static void test_sw_incr(void) write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); write_sysreg_s(0x3, PMCNTENSET_EL0); set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); + isb(); for (i = 0; i < 100; i++) write_sysreg(0x3, pmswinc_el0); + isb(); report(read_regn_el0(pmevcntr, 0) == 84, "counter #1 after + 100 SW_INCR"); report(read_regn_el0(pmevcntr, 1) == 100, "counter #0 after + 100 SW_INCR"); @@ -618,9 +623,12 @@ static void test_chained_sw_incr(void) write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); + isb(); + for (i = 0; i < 100; i++) write_sysreg(0x1, pmswinc_el0); + isb(); report(!read_sysreg(pmovsclr_el0) && (read_regn_el0(pmevcntr, 1) == 1), "no overflow and chain counter incremented after 100 SW_INCR/CHAIN"); report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0), @@ -634,9 +642,12 @@ static void test_chained_sw_incr(void) write_regn_el0(pmevcntr, 1, ALL_SET); write_sysreg_s(0x3, PMCNTENSET_EL0); set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); + isb(); + for (i = 0; i < 100; i++) write_sysreg(0x1, pmswinc_el0); + isb(); report((read_sysreg(pmovsclr_el0) == 0x2) && (read_regn_el0(pmevcntr, 1) == 0) && (read_regn_el0(pmevcntr, 0) == 84), @@ -821,10 +832,14 @@ static void test_overflow_interrupt(void) report(expect_interrupts(0), "no overflow interrupt after preset"); set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); + isb(); + for (i = 0; i < 100; i++) write_sysreg(0x2, pmswinc_el0); + isb(); set_pmcr(pmu.pmcr_ro); + isb(); report(expect_interrupts(0), "no overflow interrupt after counting"); /* enable interrupts */ @@ -879,6 +894,7 @@ static bool check_cycles_increase(void) set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ set_pmcr(get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E); + isb(); for (int i = 0; i < NR_SAMPLES; i++) { uint64_t a, b; @@ -894,6 +910,7 @@ static bool check_cycles_increase(void) } set_pmcr(get_pmcr() & ~PMU_PMCR_E); + isb(); return success; } From patchwork Thu Aug 11 18:52:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Koller X-Patchwork-Id: 12941700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FF0DC25B06 for ; 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Thu, 11 Aug 2022 11:52:17 -0700 (PDT) Date: Thu, 11 Aug 2022 11:52:08 -0700 In-Reply-To: <20220811185210.234711-1-ricarkol@google.com> Message-Id: <20220811185210.234711-3-ricarkol@google.com> Mime-Version: 1.0 References: <20220811185210.234711-1-ricarkol@google.com> X-Mailer: git-send-email 2.37.1.559.g78731f0fdb-goog Subject: [kvm-unit-tests PATCH v4 2/4] arm: pmu: Add reset_pmu() for 32-bit arm From: Ricardo Koller To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, andrew.jones@linux.dev Cc: maz@kernel.org, alexandru.elisei@arm.com, eric.auger@redhat.com, oliver.upton@linux.dev, reijiw@google.com, Ricardo Koller Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a 32-bit arm version of reset_pmu(). Add all the necessary register definitions as well. Signed-off-by: Ricardo Koller --- arm/pmu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arm/pmu.c b/arm/pmu.c index 4c601b05..a5260178 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -93,7 +93,10 @@ static struct pmu pmu; #define PMSELR __ACCESS_CP15(c9, 0, c12, 5) #define PMXEVTYPER __ACCESS_CP15(c9, 0, c13, 1) #define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1) +#define PMCNTENCLR __ACCESS_CP15(c9, 0, c12, 2) +#define PMOVSR __ACCESS_CP15(c9, 0, c12, 3) #define PMCCNTR32 __ACCESS_CP15(c9, 0, c13, 0) +#define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2) #define PMCCNTR64 __ACCESS_CP15_64(0, c9) static inline uint32_t get_id_dfr0(void) { return read_sysreg(ID_DFR0); } @@ -145,6 +148,19 @@ static inline void precise_instrs_loop(int loop, uint32_t pmcr) : "cc"); } +static void pmu_reset(void) +{ + /* reset all counters, counting disabled at PMCR level*/ + set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); + /* Disable all counters */ + write_sysreg(ALL_SET, PMCNTENCLR); + /* clear overflow reg */ + write_sysreg(ALL_SET, PMOVSR); + /* disable overflow interrupts on all counters */ + write_sysreg(ALL_SET, PMINTENCLR); + isb(); +} + /* event counter tests only implemented for aarch64 */ static void test_event_introspection(void) {} static void test_event_counter_config(void) {} From patchwork Thu Aug 11 18:52:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Koller X-Patchwork-Id: 12941701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32FF5C25B0C for ; Thu, 11 Aug 2022 18:52:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236022AbiHKSwZ (ORCPT ); Thu, 11 Aug 2022 14:52:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236000AbiHKSwV (ORCPT ); Thu, 11 Aug 2022 14:52:21 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AC699DB7C for ; Thu, 11 Aug 2022 11:52:20 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-32851d0f8beso157618607b3.22 for ; Thu, 11 Aug 2022 11:52:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc; bh=hZ5qGKKiUKkw1fqPsVoeWYEgPkjp69U3hEQvPplzfvk=; b=GU5lkgJX69idfN2d8JbckBIkC4aHLRil8U4m/JOxyBQ0FK87bDtii7WCALqoXtsYEu 8gt3Oi7J6uaZ7e77mig5FNqzNOAEz8h0GA21MH/Qy6x/l7lH1i2Cwj1wfI4cU5Ssjj9q xSIUnJyrv7l9JbMaz6NOwDRKQoNGbrRgLmtLx5uVvTyL0SY+SflE9iphBpBO2Zyfg1H0 4LDMkO4qiSOAqzVLSzqPwPbJTvbqNnm457gBp1yAt4sGcru0y/w3USkBBvk+M39juQ5o uaJlabuMoyHSrfc+SIWXoQKDDtfD0GDcwK0gkzyIinHiHXRmF+4ShhXkXZ4orxtUgzuj KStA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc; bh=hZ5qGKKiUKkw1fqPsVoeWYEgPkjp69U3hEQvPplzfvk=; b=bANFzQABSLJpyO7kRrb/tzmsLuucBZoos/nPVbMJZO6tlrFeab3uf8hrBrCTeSXxHt dlAsTH1LaVeuMOZa/LZvP0qyg2gG5ip7MMTa6GeQLlc/vpn8JbUEvFUPSajL6NGD9DpI OWJjQEg46zvkU9LUdp7g8sLAqJLcD8cbDVX24qdVw8yza3xT+ffBg2blP70fUj8MAf+s 7qKblcAJgl1YCrcJHjY/2EIL89P+IqSA+DhGr52jbjcNE63g8SoN9E2+q64ssl59mc8I dzIruXPtiOFGCrshgKUK32z2iUYrwd1qqFBJH/m3Ndk1imPNx5dSXVHtISQBDyJGZHus 4Zqg== X-Gm-Message-State: ACgBeo1vzPqbGBuJKlefwnFU07kTdHR/YqbKvi2P2x74c0EA/XPpYXll ZfpxPXcHnb3rmyL0CR9fLsxpcPJH9WLUEnZUGSt1MnsNuZoByY3QAFufS7HRvGaScrm0H7tYPfm FA5DhxvSZawTmGNdjFhCuTTfzYEF/UYAS56iTKj5xE/lrh6C/FibEd/sdxsNpYBc= X-Google-Smtp-Source: AA6agR70CWqtzcvuMK/sClY7Dw2wWjBzu7ZjCcMyhILiex8btb4PBZ86HtRsiEPXyfjMX31didUmEKfO3RYZ8g== X-Received: from ricarkol2.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:62fe]) (user=ricarkol job=sendgmr) by 2002:a81:9b47:0:b0:325:2240:ce5 with SMTP id s68-20020a819b47000000b0032522400ce5mr620224ywg.210.1660243939175; Thu, 11 Aug 2022 11:52:19 -0700 (PDT) Date: Thu, 11 Aug 2022 11:52:09 -0700 In-Reply-To: <20220811185210.234711-1-ricarkol@google.com> Message-Id: <20220811185210.234711-4-ricarkol@google.com> Mime-Version: 1.0 References: <20220811185210.234711-1-ricarkol@google.com> X-Mailer: git-send-email 2.37.1.559.g78731f0fdb-goog Subject: [kvm-unit-tests PATCH v4 3/4] arm: pmu: Reset the pmu registers before starting some tests From: Ricardo Koller To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, andrew.jones@linux.dev Cc: maz@kernel.org, alexandru.elisei@arm.com, eric.auger@redhat.com, oliver.upton@linux.dev, reijiw@google.com, Ricardo Koller Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some registers like the PMOVS reset to an architecturally UNKNOWN value. Most tests expect them to be reset (mostly zeroed) using pmu_reset(). Add a pmu_reset() on all the tests that need one. As a bonus, fix a couple of comments related to the register state before a sub-test. Reviewed-by: Eric Auger Signed-off-by: Ricardo Koller --- arm/pmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index a5260178..756e0d26 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -842,7 +842,7 @@ static void test_overflow_interrupt(void) write_regn_el0(pmevcntr, 1, PRE_OVERFLOW); isb(); - /* interrupts are disabled */ + /* interrupts are disabled (PMINTENSET_EL1 == 0) */ mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); report(expect_interrupts(0), "no overflow interrupt after preset"); @@ -858,7 +858,7 @@ static void test_overflow_interrupt(void) isb(); report(expect_interrupts(0), "no overflow interrupt after counting"); - /* enable interrupts */ + /* enable interrupts (PMINTENSET_EL1 <= ALL_SET) */ pmu_reset_stats(); @@ -906,6 +906,7 @@ static bool check_cycles_increase(void) bool success = true; /* init before event access, this test only cares about cycle count */ + pmu_reset(); set_pmcntenset(1 << PMU_CYCLE_IDX); set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ @@ -960,6 +961,7 @@ static bool check_cpi(int cpi) uint32_t pmcr = get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E; /* init before event access, this test only cares about cycle count */ + pmu_reset(); set_pmcntenset(1 << PMU_CYCLE_IDX); set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ From patchwork Thu Aug 11 18:52:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Koller X-Patchwork-Id: 12941702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 600B4C25B0D for ; Thu, 11 Aug 2022 18:52:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236024AbiHKSw0 (ORCPT ); Thu, 11 Aug 2022 14:52:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235971AbiHKSwW (ORCPT ); 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Thu, 11 Aug 2022 11:52:20 -0700 (PDT) Date: Thu, 11 Aug 2022 11:52:10 -0700 In-Reply-To: <20220811185210.234711-1-ricarkol@google.com> Message-Id: <20220811185210.234711-5-ricarkol@google.com> Mime-Version: 1.0 References: <20220811185210.234711-1-ricarkol@google.com> X-Mailer: git-send-email 2.37.1.559.g78731f0fdb-goog Subject: [kvm-unit-tests PATCH v4 4/4] arm: pmu: Check for overflow in the low counter in chained counters tests From: Ricardo Koller To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, andrew.jones@linux.dev Cc: maz@kernel.org, alexandru.elisei@arm.com, eric.auger@redhat.com, oliver.upton@linux.dev, reijiw@google.com, Ricardo Koller Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A chained event overflowing on the low counter can set the overflow flag in PMOVS. KVM does not set it, but real HW and the fast-model seem to. Moreover, the AArch64.IncrementEventCounter() pseudocode in the ARM ARM (DDI 0487H.a, J1.1.1 "aarch64/debug") also sets the PMOVS bit on overflow. The pmu chain tests fail on bare metal when checking the overflow flag of the low counter _not_ being set on overflow. Fix by checking for overflow. Note that this test fails in KVM without the respective fix. Reviewed-by: Eric Auger Signed-off-by: Ricardo Koller --- arm/pmu.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index 756e0d26..cd47b14b 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -599,7 +599,7 @@ static void test_chained_counters(void) precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); report(read_regn_el0(pmevcntr, 1) == 1, "CHAIN counter #1 incremented"); - report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #1"); + report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #1"); /* test 64b overflow */ @@ -611,7 +611,7 @@ static void test_chained_counters(void) precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0)); report(read_regn_el0(pmevcntr, 1) == 2, "CHAIN counter #1 set to 2"); - report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #2"); + report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #2"); write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); write_regn_el0(pmevcntr, 1, ALL_SET); @@ -619,7 +619,7 @@ static void test_chained_counters(void) precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0)); report(!read_regn_el0(pmevcntr, 1), "CHAIN counter #1 wrapped"); - report(read_sysreg(pmovsclr_el0) == 0x2, "overflow on chain counter"); + report(read_sysreg(pmovsclr_el0) == 0x3, "overflow on even and odd counters"); } static void test_chained_sw_incr(void) @@ -645,8 +645,9 @@ static void test_chained_sw_incr(void) write_sysreg(0x1, pmswinc_el0); isb(); - report(!read_sysreg(pmovsclr_el0) && (read_regn_el0(pmevcntr, 1) == 1), - "no overflow and chain counter incremented after 100 SW_INCR/CHAIN"); + report((read_sysreg(pmovsclr_el0) == 0x1) && + (read_regn_el0(pmevcntr, 1) == 1), + "overflow and chain counter incremented after 100 SW_INCR/CHAIN"); report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0), read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); @@ -664,10 +665,10 @@ static void test_chained_sw_incr(void) write_sysreg(0x1, pmswinc_el0); isb(); - report((read_sysreg(pmovsclr_el0) == 0x2) && + report((read_sysreg(pmovsclr_el0) == 0x3) && (read_regn_el0(pmevcntr, 1) == 0) && (read_regn_el0(pmevcntr, 0) == 84), - "overflow on chain counter and expected values after 100 SW_INCR/CHAIN"); + "expected overflows and values after 100 SW_INCR/CHAIN"); report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0), read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); } @@ -747,8 +748,9 @@ static void test_chain_promotion(void) report_info("MEM_ACCESS counter #0 has value 0x%lx", read_regn_el0(pmevcntr, 0)); - report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0), - "CHAIN counter enabled: CHAIN counter was incremented and no overflow"); + report((read_regn_el0(pmevcntr, 1) == 1) && + (read_sysreg(pmovsclr_el0) == 0x1), + "CHAIN counter enabled: CHAIN counter was incremented and overflow"); report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); @@ -775,8 +777,9 @@ static void test_chain_promotion(void) report_info("MEM_ACCESS counter #0 has value 0x%lx", read_regn_el0(pmevcntr, 0)); - report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0), - "32b->64b: CHAIN counter incremented and no overflow"); + report((read_regn_el0(pmevcntr, 1) == 1) && + (read_sysreg(pmovsclr_el0) == 0x1), + "32b->64b: CHAIN counter incremented and overflow"); report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); @@ -884,8 +887,8 @@ static void test_overflow_interrupt(void) write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); isb(); mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); - report(expect_interrupts(0), - "no overflow interrupt expected on 32b boundary"); + report(expect_interrupts(0x1), + "expect overflow interrupt on 32b boundary"); /* overflow on odd counter */ pmu_reset_stats(); @@ -893,8 +896,8 @@ static void test_overflow_interrupt(void) write_regn_el0(pmevcntr, 1, ALL_SET); isb(); mem_access_loop(addr, 400, pmu.pmcr_ro | PMU_PMCR_E); - report(expect_interrupts(0x2), - "expect overflow interrupt on odd counter"); + report(expect_interrupts(0x3), + "expect overflow interrupt on even and odd counter"); } #endif