From patchwork Thu Aug 11 20:33:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12941716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AE99C25B0C for ; Thu, 11 Aug 2022 20:33:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235976AbiHKUd2 (ORCPT ); Thu, 11 Aug 2022 16:33:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235787AbiHKUd0 (ORCPT ); Thu, 11 Aug 2022 16:33:26 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B0299F0FA for ; Thu, 11 Aug 2022 13:33:18 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id m17-20020a7bce11000000b003a5bedec07bso1490937wmc.0 for ; Thu, 11 Aug 2022 13:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=44JZfQo8qBDZMgfCdrZJwZLuiR284QlmRSCfMxTvtpo=; b=Rg+2K2aUJR5EC4EzeEhjweVggh3LGAxXDW+n+myh6+YEfAOfixSRbOplNLuQc+hbCh k+KeOqNm6R7kogF4zChBu0vPRB6/t4pC7dpmsahLZa0MR1bkVO2XWKiYhLL+J8YqQUDk ZtKBGxLruXNAffh3BmuL+H6PQwULOjdofcVTtJDehPnCkEwCuYwFQvxMN+8on0EzLv0W 8hG4NzCnIC7nauXERnsjmeIsK9LpEBmZMluKZGrodeAYGFQJLpKQqnVMGITSegeShwjt CAS9qdr1VnbdcCuBIY3JiurrcquUlr5/UocbOVp2P97KWNRvHxATlrQBQ9jfvz51J/Lu zNfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=44JZfQo8qBDZMgfCdrZJwZLuiR284QlmRSCfMxTvtpo=; b=yE9gDmIPbOmrPSSHLsvOlWA1mja0AM5yT5SW9fAXM9sRFEP+MxQJD/8FxRIAnA0Yqx 7s3+SzcOf8t/+AJuUmd5+jVedkWuj2glp1YWnC2iR4/jcZShTwU83yHcjGL1PU/GsAMO 24xDC7rsBjBTdePyVnUQljxZ3joKZ+y3S1p6dIixsgIhoKmeQXMnGzO5I8jfm9a4mvAZ 3L39L6jOzeb+7NeaFN/rAvz7aqBPSmN0cOGKiygNcmy09+jNgipEK7385EI4/yfSPhWP Cq7TGFcccwx1tArbLS+9qiD3ueE4RolE4DZIW6wAE388HfVSjO4w4yixo/NTyAY8r9f/ zUXg== X-Gm-Message-State: ACgBeo0v0INZLrUKNzWnrAR4DbXIDoNlAhmncoKcseTiFTvPWnTBF9Bq inx7gKpYlRK/huXNCHPqHuDhhQ== X-Google-Smtp-Source: AA6agR5N8mHJgZv+snXP8haUdkqppQ+4312cBLsCj598n23ICeGirf1H5+hFJyDA92da/FyY+BkSUQ== X-Received: by 2002:a05:600c:3845:b0:3a3:19e8:829e with SMTP id s5-20020a05600c384500b003a319e8829emr6647580wmr.11.1660249996798; Thu, 11 Aug 2022 13:33:16 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i12-20020adfefcc000000b0021f1ec8776fsm86643wrp.61.2022.08.11.13.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 13:33:16 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 1/4] dt-bindings: PCI: fu740-pci: fix missing clock-names Date: Thu, 11 Aug 2022 21:33:04 +0100 Message-Id: <20220811203306.179744-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220811203306.179744-1-mail@conchuod.ie> References: <20220811203306.179744-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley The commit in the fixes tag removed the clock-names property from the SiFive FU740 PCI Controller dt-binding, but it was already in the dts for the FU740. dtbs_check was not able to pick up on this at the time but v2022.08 of dt-schema now can: arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dtb: pcie@e00000000: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: linux/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml The Linux driver does not use this property, but outside of the kernel this property may have users. Re-add the property and its "clocks" dependency. Fixes: b92225b034c0 ("dt-bindings: PCI: designware: Fix 'unevaluatedProperties' warnings") Signed-off-by: Conor Dooley --- I went back and forth on removing the property from the dts, but this seems like the change that is more conservative.. --- .../devicetree/bindings/pci/sifive,fu740-pcie.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml index 195e6afeb169..c7a9a2dc0fa6 100644 --- a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml @@ -51,6 +51,12 @@ properties: description: A phandle to the PCIe power up reset line. maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + const: pcie_aux + pwren-gpios: description: Should specify the GPIO for controlling the PCI bus device power on. maxItems: 1 From patchwork Thu Aug 11 20:33:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12941715 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 998F4C19F2A for ; Thu, 11 Aug 2022 20:33:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235764AbiHKUd3 (ORCPT ); Thu, 11 Aug 2022 16:33:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235793AbiHKUd0 (ORCPT ); Thu, 11 Aug 2022 16:33:26 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B9AB9F0F5 for ; Thu, 11 Aug 2022 13:33:19 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id z16so22486407wrh.12 for ; Thu, 11 Aug 2022 13:33:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=QxkmtF8asgPVQHFJENq/ehachAsL+qmscZvCCu05yWc=; b=XaRcrphLz19LTNxZ0dzKwHA8K/MkiviSjiw49WVWXeVE5qRONAyZyq8QlcuzrvefVq DVNMQX04znal0vPNRmcNC3MbIYAUaAwumKVcp1t0JK2JWpjZ/cp5ve/O9xgtHIB9jYp1 a8nRH+Wy1LAZE51EqhGYykiH3KzE9PEX9dP0kwd3yenGFVrqs5lMmYFvz3ozZW8IIaAJ Bj4EyFhC9G2D5gf3y3F2K/Htv7ZqH11Y9ovKD1Bz7OjfH17QcK/dDGLuF9YkGgrMvCco 4DIJtEW+NiKBMz3o+dzkdKU5lyhNrWpghKTXW2kDbXlMfdJOmER6MuwSLRX/k4n+MNIT Ftcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=QxkmtF8asgPVQHFJENq/ehachAsL+qmscZvCCu05yWc=; b=2Oc9s5AW6KUY/cqim0HTavPRub/ctHXPj9YeMrtpGZBqwcQmJyb3stCJWv+L1I5T0K ixREnIvWEBOuqwAEXaHcEMcLa6X2YsQBHi2O+N5jA1xqFIckm1Vun//rCkK/dPuiui5r bSItjkkB3pvbTyWztN9I0IyD5lx8SjYd+rXcB/7rM6EkYTeQcj2zPkEsJKe1mkqcpr1y 8WI0u0rudwazPNU0lhxRLzZJU79QPXhb18J/RImPcawl0qoZTsQ9uuG+W+hsE/cbbapG 8tceWFSDBRivOJXctgSqI/7hX7jI80gL9pg3lXmbLMwtof+bXcOruNsRt1RoczoDWL/a DP+Q== X-Gm-Message-State: ACgBeo3nd8RzcB3SoMakHkG7K6tFkdiPAXoQjyY3gMQtLubah2jYzGxD hlD9tQOq2wj9g311uIqGrRDkNw== X-Google-Smtp-Source: AA6agR5//7v1W6BSWMIoYqn+Fu+wgEM3FNII37M+y/PlRKeC6C5AWj7949Ozxp/ApCOBEqaRSPZzpw== X-Received: by 2002:a5d:59a5:0:b0:222:c5a5:59c4 with SMTP id p5-20020a5d59a5000000b00222c5a559c4mr337239wrr.656.1660249997915; Thu, 11 Aug 2022 13:33:17 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i12-20020adfefcc000000b0021f1ec8776fsm86643wrp.61.2022.08.11.13.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 13:33:17 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 2/4] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties Date: Thu, 11 Aug 2022 21:33:05 +0100 Message-Id: <20220811203306.179744-3-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220811203306.179744-1-mail@conchuod.ie> References: <20220811203306.179744-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley Upgrading dt-schema to v2022.08 reveals unevaluatedProperties issues that were not previously visible, such as the missing clocks and clock-names properties for PolarFire SoC's PCI controller: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml The clocks are required to enable interfaces between the FPGA fabric and the core complex, so add them to the binding. Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") Signed-off-by: Conor Dooley --- .../bindings/pci/microchip,pcie-host.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index edb4f81253c8..2a2166f09e2c 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -25,6 +25,31 @@ properties: - const: cfg - const: apb + clocks: + description: + Fabric Interface Controllers, FICs, are the interface between the FPGA + fabric and the core complex on PolarFire SoC. The FICs require two clocks, + one from each side of the interface. The "FIC clocks" described by this + property are on the core complex side & communication through a FIC is not + possible unless it's corresponding clock is enabled. A clock must be + enabled for each of the interfaces the root port is connected through. + minItems: 1 + items: + - description: FIC0's clock + - description: FIC1's clock + - description: FIC2's clock + - description: FIC3's clock + + clock-names: + items: + enum: + - fic0 + - fic1 + - fic2 + - fic3 + minItems: 1 + maxItems: 4 + interrupts: minItems: 1 items: From patchwork Thu Aug 11 20:33:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12941714 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15711C19F2D for ; Thu, 11 Aug 2022 20:33:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235948AbiHKUd1 (ORCPT ); Thu, 11 Aug 2022 16:33:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235759AbiHKUd0 (ORCPT ); Thu, 11 Aug 2022 16:33:26 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90EB89F180 for ; Thu, 11 Aug 2022 13:33:20 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id v3so22625077wrp.0 for ; Thu, 11 Aug 2022 13:33:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=BMoCBhZDWFVbCIulovqGFO1GGwjU3Gb2EjVAgLDr/kM=; b=e1haM7gYHDueJmKbGFqDqB0CwdhTeSa2E4wt4JmEDSJbRCc95HOzVyhmhAR1aZMqqx WxkA1FzPGcrae9KDWdzDMQHZEb1i39i7aAL9rQ0/XQMl0cjzp27sbySRBMnLhzbUHVO9 p7YPgrN5/LQYBe6cKzpCPAwLYeTnzOked1Fp12KP22d+INh+NSfPUx4OvjJU/VCDd81U gwIKYZTkvJayzWTODqIsBm7Mc+j7idl/i5AbrnvDIsmPMmT2pRhWCHNWRNL/NjJQmAK3 REtDrCKW9kfVEhaxxP06EjHEUcaXvACDZ9Cu7GF6pF7rHNRdKy1UlQE0Abl+CgWbWCRX qlpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=BMoCBhZDWFVbCIulovqGFO1GGwjU3Gb2EjVAgLDr/kM=; b=RaoVF6SYeJ+cGJmZsoaJ075NaXoa5Qv1l8vjk6OSrMu4fC/O5Aq+C6VMRs79rh/OSy Y1PyKWnAPfoEz+TblTKmXauLV0zEvph8HsqjQGO9pL+Zvf+Pu96Shgwif68mnQBzoOsP ZvLVvWILBkPUwQIFvbtoDJh/SsinUNbvMX8y2JlolLEsOynJk4DzRrTEFRfJrBv5/a1J RwNFxUCC4ojL4Fkrb+0fpfNxuLmXzYyDQ3ATVOpou3eDhLU14/pq75anoWGA3iBfLrsW xPrmMMpYHqn0SxjUx5QrSTkFVneNeUI/9rXUIqkNMzYYKcglTeVxMdhNeAjOp+kIRhM7 Zq+w== X-Gm-Message-State: ACgBeo2IL5OO/05aQY6o45x1FfF0UcWe6LX/AO0MVnay6vzbyFMtPyIb Um0qbdktIKZhSXV/n2dc3uhy2A== X-Google-Smtp-Source: AA6agR7XEt/HJ/k3HAKtCMICn0MmET4kycwS554nxvopStvc3/5uFdV66pz7zYk7eLXXULU8iWeBFw== X-Received: by 2002:a5d:44c8:0:b0:21e:b750:2bda with SMTP id z8-20020a5d44c8000000b0021eb7502bdamr351862wrr.338.1660249999075; Thu, 11 Aug 2022 13:33:19 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i12-20020adfefcc000000b0021f1ec8776fsm86643wrp.61.2022.08.11.13.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 13:33:18 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 3/4] dt-bindings: PCI: microchip,pcie-host: fix incorrect child node name Date: Thu, 11 Aug 2022 21:33:06 +0100 Message-Id: <20220811203306.179744-4-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220811203306.179744-1-mail@conchuod.ie> References: <20220811203306.179744-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley v2022.08 of dt-schema improved checking of unevaluatedProperties, and exposed a previously unseen warning for the PCIe controller's interrupt controller node name: arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml Make the property in the binding match the node name actually used in the dts. Fixes: dcd49679fb3a ("dt-bindings: PCI: Fix 'unevaluatedProperties' warnings") Signed-off-by: Conor Dooley --- This is another one Rob where I feel like I'm doing the wrong thing. The Linux driver gets the child node without using the name, but another OS etc could in theory (or reality), right? --- .../devicetree/bindings/pci/microchip,pcie-host.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 2a2166f09e2c..9b123bcd034c 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -71,7 +71,7 @@ properties: msi-parent: description: MSI controller the device is capable of using. - interrupt-controller: + legacy-interrupt-controller: type: object properties: '#address-cells': @@ -125,7 +125,7 @@ examples: msi-controller; bus-range = <0x00 0x7f>; ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>; - pcie_intc0: interrupt-controller { + pcie_intc0: legacy-interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; From patchwork Thu Aug 11 20:33:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12941717 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E91AC282E7 for ; Thu, 11 Aug 2022 20:33:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235462AbiHKUd3 (ORCPT ); Thu, 11 Aug 2022 16:33:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235848AbiHKUd0 (ORCPT ); Thu, 11 Aug 2022 16:33:26 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2D6A9F189 for ; Thu, 11 Aug 2022 13:33:21 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id z12so22544121wrs.9 for ; Thu, 11 Aug 2022 13:33:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=ClSH5MXXgUZguA19Coz32EYS83xElJy9jIFIyLAmeC4=; b=HHhe+yarKbkwIYZ1mXaOthZ0VXyo310D1cBk8s8PGKXtS+FAnYRo1gNG6ylVj/7gLo BD1+qLMXw3jHjaKmycrt6e1OAv4CCWriwslsnWnsihoR/ceQgpKaw/ZZ6agol8h0tpdV l02Ole49suUd2QEsa7+uNZY+ANEboqWovjQ41L3onQLVlcUDQTarQNGtsJLt8FArM1MM H2MDT+rXQSH4wqI56vlK6Bwt19CVBV2XqoaYwT8ClmSccYovi+z7rS+pap22DWMy7KMA jJBA8lhBOgEw9qEA4SepES7pXBFrOAfewHEorcKXkVi7YaO9c1U7I4skrO+n+EWweBdU rtFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=ClSH5MXXgUZguA19Coz32EYS83xElJy9jIFIyLAmeC4=; b=iEeivnSZfCeG9TtB98ZAqx5VgZWfykE8ABnHiAgU+6kD81BqYLwkIaZGzSnYJXYVDq czjqKp+YFtTXgCzZbxUcJIXgrVSNIWgZyN1ny/bhzuteHxTP/GJuvBoX7ZTO6DYoQfd8 +tZ4Spu14sRmRdqwQOSbvfULaTOZhU7OulGL6JnDRos+Y1W5Xly4kqElkdSelbXSHwbd QcZ0KaJIOVBuvgxFfj5p8dLZ25+zGeQjZAibZIdeqPR0UgqvAW+EaP0qurDGIsFVgLOk Si4NlciZZ32Vxo3WY5xQ80LTqHE4Pui+G2eGjeuJdUDIDqSAMonW2LoXG/vTSZQujPb1 MZbw== X-Gm-Message-State: ACgBeo30KoBfoHpEqm6LhyeOSyP4E3V29CcPcXLHmtUCCsEDuXN0UBO5 tH6sjF0R5iZ9oKL/Qf2kxa3DlQ== X-Google-Smtp-Source: AA6agR4uUqIg2eHjtpt4HwLt+LlA2AAP/WjAN+bsQ7P2wHGzFMVwBV3+ZG92fs39ZgDOkKMy3JKrZg== X-Received: by 2002:a5d:4345:0:b0:21a:3b82:ad57 with SMTP id u5-20020a5d4345000000b0021a3b82ad57mr361149wrr.176.1660250000231; Thu, 11 Aug 2022 13:33:20 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i12-20020adfefcc000000b0021f1ec8776fsm86643wrp.61.2022.08.11.13.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 13:33:19 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property Date: Thu, 11 Aug 2022 21:33:07 +0100 Message-Id: <20220811203306.179744-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220811203306.179744-1-mail@conchuod.ie> References: <20220811203306.179744-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Conor Dooley When the PCI controller node was added to the PolarFire SoC dtsi, dt-schema was not able to detect the presence of some undocumented properties due to how it handled unevaluatedProperties. v2022.08 introduces better validation, producing the following error: arch/riscv/boot/dts/microchip/mpfs-polarberry.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley --- I feel like there's a pretty good chance that this is not the way this should have been done and the property should be marked as deprecated but I don't know enough about PCI to answer that. --- .../devicetree/bindings/pci/microchip,pcie-host.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 9b123bcd034c..9ac34b33c4b2 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -71,6 +71,17 @@ properties: msi-parent: description: MSI controller the device is capable of using. + microchip,axi-m-atr0: + description: | + Depending on the FPGA bitstream, the AXIM address translation table in the + PCIe controllers bridge layer may need to be configured. Use this property + to set the address offset. For more information, see Section 1.3.3, + "PCIe/AXI4 Address Translation" of the PolarFire SoC PCIe User Guide: + https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 2 + maxItems: 2 + legacy-interrupt-controller: type: object properties: