From patchwork Fri Aug 12 09:53:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 12942074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED449C00140 for ; Fri, 12 Aug 2022 09:54:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB675905EF; Fri, 12 Aug 2022 09:54:09 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97093905EF; Fri, 12 Aug 2022 09:54:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660298044; x=1691834044; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=h1Lv1FkCTrVQ5bAD+XXqpaazyTn8gMGQvZSV42JgBYA=; b=N1YVU1Qt5f49B8rtedOXjAgbWJJzmvsVGO5L7hg40yDVDaLZp7DX2qlA s9qYUQH1RqHYV0IhhSVVCQ2r0gtB6zlQFqwVNO1JwIG7zW+3v2J3Hl+5z rr2Vbmu6sScuuzveYQUpwugWmCe8u254O8JEgsXow5Y0J6KTFVIMK6WUA PQfqonwDAnDDPdztaKzcLpZesGausPX6lTb3zk9U5iu+m0i9PSibBpukY cUOUxnP7eF40Si8P411J/Iug7ff4a2FC6eM+SxQUplOw7FGM2BkBjkcYC P0Onvyd0M/9zzU79PE457wHmYO4M9djf2b8A0fbg55sLiuEUa1Ro3ZWk8 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10436"; a="292359342" X-IronPort-AV: E=Sophos;i="5.93,231,1654585200"; d="scan'208";a="292359342" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 02:54:03 -0700 X-IronPort-AV: E=Sophos;i="5.93,231,1654585200"; d="scan'208";a="634588833" Received: from jkrzyszt-mobl1.ger.corp.intel.com (HELO jkrzyszt-mobl1.lan) ([10.213.22.182]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 02:54:00 -0700 From: Janusz Krzysztofik To: igt-dev@lists.freedesktop.org Date: Fri, 12 Aug 2022 11:53:44 +0200 Message-Id: <20220812095346.45379-1-janusz.krzysztofik@linux.intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 1/3] tests/gem_exec_fence: Fix wrong engine checked for store_dword capability X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Chris Wilson , Mauro Carvalho Chehab Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Commit ed7c8cfb67e3 ("tests/i915/gem_exec_fence: Add __for_each_physical_engine to utilize all engines."), while replacing depraciated for_each_physical_engine(e, fd) loop with __for_each_physical_engine(fd, e2) and gem_can_store_dword() inside that loop with gem_class_can_store_dword(), didn't switch to e2 consequently -- eb_ring(e) argument of gem_can_store_dword() was replaced with e->class passed to gem_class_can_store_dword() instead of e2->class. As a result, a batch that stores dword is now submitted to all engines, also those that don't support that operation. Fix it. Signed-off-by: Janusz Krzysztofik Cc: Mauro Carvalho Chehab Reviewed-by: Mauro Carvalho Chehab --- tests/i915/gem_exec_fence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c index 7ff7614dad..048870053a 100644 --- a/tests/i915/gem_exec_fence.c +++ b/tests/i915/gem_exec_fence.c @@ -331,7 +331,7 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, i = 0; for_each_ctx_engine(fd, ctx, e2) { - if (!gem_class_can_store_dword(fd, e->class)) + if (!gem_class_can_store_dword(fd, e2->class)) continue; if (flags & NONBLOCK) { From patchwork Fri Aug 12 09:53:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 12942076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1505CC25B0E for ; Fri, 12 Aug 2022 09:55:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90DB6AB4FF; Fri, 12 Aug 2022 09:54:13 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 812E298CD9; Fri, 12 Aug 2022 09:54:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660298047; x=1691834047; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=olE+kcSLMFIzY0K6/Tm3ZPC6nm8PiVyXuhkfNx+snNY=; b=XTXH/LpEkcjBe5R41TnqDdLgqiD7RrLWkX1dt9+4aYCXhsoXwskbPWwe 0AtJXpdOTfdA/mDxPj6aD/+YIXZZl7JUG3ysNAAA+PPKJso1nd1/om8F+ M9efx7dKKSz9h2UTcHJj+Nt//SlrUBeVHHDj4ss8ZwzyufGKg3E/+f6MN lCVy5ytjqjQZpPiqkrtxiZJ506ooSi1oAHfz0HklnsxpGGAR+I1+Wgz0R 8psGDhm954o4Q6oDCt+BJtPWicbZBhXdG6rK9acpBoJlmoO9Duob3QH+c nu9hpy0TZGtVWv5Of2+ClZOnVhpUMt8Lapb3Kt8wzJNlbmZ2B7+at+7KV w==; X-IronPort-AV: E=McAfee;i="6400,9594,10436"; a="292359349" X-IronPort-AV: E=Sophos;i="5.93,231,1654585200"; d="scan'208";a="292359349" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 02:54:07 -0700 X-IronPort-AV: E=Sophos;i="5.93,231,1654585200"; d="scan'208";a="634588848" Received: from jkrzyszt-mobl1.ger.corp.intel.com (HELO jkrzyszt-mobl1.lan) ([10.213.22.182]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 02:54:03 -0700 From: Janusz Krzysztofik To: igt-dev@lists.freedesktop.org Date: Fri, 12 Aug 2022 11:53:45 +0200 Message-Id: <20220812095346.45379-2-janusz.krzysztofik@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220812095346.45379-1-janusz.krzysztofik@linux.intel.com> References: <20220812095346.45379-1-janusz.krzysztofik@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t v2 2/3] tests/gem_exec_fence: Exclude 0 from use in store batches X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Chris Wilson , Mauro Carvalho Chehab Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" When i = 0, condition out[i] == i will be true even if a batch supposed to store i in out[i] fails. Don't use i = 0 in batches that store values in out[i]. v2: still check for out[0] == 0 (Chris) Signed-off-by: Janusz Krzysztofik Cc: Chris Wilson Cc: Mauro Carvalho Chehab Reviewed-by: Mauro Carvalho Chehab --- tests/i915/gem_exec_fence.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c index 048870053a..78d83460f7 100644 --- a/tests/i915/gem_exec_fence.c +++ b/tests/i915/gem_exec_fence.c @@ -334,6 +334,8 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, if (!gem_class_can_store_dword(fd, e2->class)) continue; + i++; + if (flags & NONBLOCK) { igt_store_word(fd, ahnd, ctx, e2, spin->out_fence, scratch, scratch_offset, i, i); @@ -345,8 +347,6 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, put_ahnd(ahnd); } } - - i++; } igt_spin_busywait_until_started(spin); @@ -356,7 +356,7 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, if ((flags & HANG) == 0) { /* Check for invalidly completing the task early */ igt_assert(fence_busy(spin->out_fence)); - for (int n = 0; n < i; n++) + for (int n = 0; n <= i; n++) igt_assert_eq_u32(out[n], 0); igt_spin_end(spin); @@ -366,8 +366,11 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, gem_set_domain(fd, scratch, I915_GEM_DOMAIN_GTT, 0); igt_assert(!fence_busy(spin->out_fence)); - while ((flags & HANG) == 0 && i--) - igt_assert_eq_u32(out[i], i); + if ((flags & HANG) == 0) { + do + igt_assert_eq_u32(out[i], i); + while (i--); + } munmap(out, 4096); igt_spin_free(fd, spin); From patchwork Fri Aug 12 09:53:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 12942075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F6A1C25B0E for ; Fri, 12 Aug 2022 09:54:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3118DAB509; Fri, 12 Aug 2022 09:54:39 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C0DB95B02; Fri, 12 Aug 2022 09:54:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660298051; x=1691834051; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vZiKSmzL434Dq7bbCKIN8+f6ZG4pGpEwmsK7TsYvirs=; b=Y3YNb9sqT0Bufl2l4rLgHkEpiJk27qoDMlct3EGgS/+StlbAf0ka0Mzw qSX4hjfwLfbX2oY3dpqzSzeBaG8LQCYtGk8oPh5S+nxy6wGIh1V96pZKd lxISNrCzjbEnxL3eA8/AMj71Cx24z2vU5Ytg7vjQuqg+7+1mwk3C1D7+1 RCrcXyLpmRDBBI1E/4GvKkvhMiFdf7NZiEhcyVxc8bGDVhCQwMGuy5DkB 62ImjUCObjB73O7MEMuM1hoj1gkxjB7Iqcfe89AV2yGzOJQrP/r/Y/PR1 0/XjCwbpOAYjKhm7T7OEuWAPDhoweNRK1wJbG/akBHLR1pnHlwQldQilS Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10436"; a="292359360" X-IronPort-AV: E=Sophos;i="5.93,231,1654585200"; d="scan'208";a="292359360" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 02:54:11 -0700 X-IronPort-AV: E=Sophos;i="5.93,231,1654585200"; d="scan'208";a="634588874" Received: from jkrzyszt-mobl1.ger.corp.intel.com (HELO jkrzyszt-mobl1.lan) ([10.213.22.182]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 02:54:07 -0700 From: Janusz Krzysztofik To: igt-dev@lists.freedesktop.org Date: Fri, 12 Aug 2022 11:53:46 +0200 Message-Id: <20220812095346.45379-3-janusz.krzysztofik@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220812095346.45379-1-janusz.krzysztofik@linux.intel.com> References: <20220812095346.45379-1-janusz.krzysztofik@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t v3 3/3] tests/gem_exec_fence: Restore pre-hang checks in *await-hang scenarios X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Chris Wilson , Mauro Carvalho Chehab Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Commit c8f6aaf32d83 "tests/gem_exec_fence: Check stored values only for valid workloads" resolved an issue, observed in *await-hang scenarios, where a fence exposed by an invalid spin batch was signaled asynchronously to pending checks for depended test batches still waiting for that fence. Those checks have been disabled, weakening those scenarios. This change restores the pre-hang checks to the extent possible when the invalid spin batch may trigger an immediate reset. If we are lucky enough to take a snapshot of the object supposed to be still not modified by store batches after we confirm that the spin batch has started and before the fence is signaled, we use that copy to verify if the fence dependent batches are still blocked. Running the *await-hang subtests multiple times in CI should build our confidence in their results. v2: preserve checking the pipeline runs ahead of the hang (Chris) v3: use a more simple 'best effort' approach suggested by Chris Signed-off-by: Janusz Krzysztofik Cc: Chris Wilson Cc: Mauro Carvalho Chehab Reviewed-by: Mauro Carvalho Chehab --- tests/i915/gem_exec_fence.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c index 78d83460f7..f24bebdb7d 100644 --- a/tests/i915/gem_exec_fence.c +++ b/tests/i915/gem_exec_fence.c @@ -21,6 +21,7 @@ * IN THE SOFTWARE. */ +#include #include #include #include @@ -307,12 +308,12 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, const struct intel_execution_engine2 *e, unsigned flags) { + uint64_t scratch_offset, ahnd = get_reloc_ahnd(fd, ctx->id); const struct intel_execution_engine2 *e2; uint32_t scratch = gem_create(fd, 4096); + uint32_t *out, tmp[4096 / sizeof(*out)]; igt_spin_t *spin; - uint32_t *out; - uint64_t scratch_offset, ahnd = get_reloc_ahnd(fd, ctx->id); - int i; + int i, n; scratch_offset = get_offset(ahnd, scratch, 4096, 0); @@ -353,11 +354,20 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx, /* Long, but not too long to anger preemption disable checks */ usleep(50 * 1000); /* 50 ms, typical preempt reset is 150+ms */ + /* + * Check for invalidly completing the task early. + * In -hang variants, invalid spin batch may trigger an immediate reset, + * then we are able to verify if store batches haven't been started yet + * only if the fence of the spin batch is still busy. + * Just run *await-hang subtest multiple times to build confidence. + */ + memcpy(tmp, out, (i + 1) * sizeof(*out)); + if (fence_busy(spin->out_fence)) { + for (n = 0; n <= i; n++) + igt_assert_eq_u32(tmp[n], 0); + } if ((flags & HANG) == 0) { - /* Check for invalidly completing the task early */ igt_assert(fence_busy(spin->out_fence)); - for (int n = 0; n <= i; n++) - igt_assert_eq_u32(out[n], 0); igt_spin_end(spin); }