From patchwork Fri Aug 12 12:47:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12942227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 400A6C00140 for ; Fri, 12 Aug 2022 12:48:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238229AbiHLMs5 (ORCPT ); Fri, 12 Aug 2022 08:48:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234491AbiHLMsz (ORCPT ); Fri, 12 Aug 2022 08:48:55 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DAE9A59A9; Fri, 12 Aug 2022 05:48:54 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27CCl30F016158; Fri, 12 Aug 2022 12:48:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=dya0fLoAOCmYNy5RotDtfzyWRvJBmjadgH4N4VQrQRY=; b=eR6liqccJeQ/pZr6ZEeE3CLeoYsQWL2IAuBkadI0Z6cNJB3cXlOkEv1UTQsn4ciP0A++ 1q2g7ILALyIkC+6RUXighKghzgYfx2GYF7qdUdz45sZ0l6Rb7GIJaMvVf5KQf7XieIx6 TPHJnggwaf5+yaytiwnOr/VlPcc3FBq5KWFbyQmHMYehQ/VUyX1EKrJygSM8KBdPzKID 3pFuoKsPr/Haq3U2RrY56aXHKry6R/FzZYmd/ztOXtJVxC+kkxDQpN7C3iIFB+GjpaKR hI4Mouvu7VJC+Kb3cEu4fdnd/8hyLM+3rGc8xf+Oj63ePCGwcKNhmQPbY1B+mNqQ+zwg hg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3hw3a6ukty-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Aug 2022 12:48:14 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27CCmD0C025699 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Aug 2022 12:48:13 GMT Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 12 Aug 2022 05:48:08 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH v4 1/7] dt-bindings: remoteproc: qcom: Add SC7280 ADSP support Date: Fri, 12 Aug 2022 18:17:40 +0530 Message-ID: <1660308466-410-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> References: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -i4uscqwj9A1PtFmpEhTM-cv5P6_JRD_ X-Proofpoint-ORIG-GUID: -i4uscqwj9A1PtFmpEhTM-cv5P6_JRD_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_08,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 spamscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208120034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add ADSP PIL loading support for SC7280 SoCs. Signed-off-by: Srinivasa Rao Mandadapu --- .../bindings/remoteproc/qcom,sc7280-adsp-pil.yaml | 189 +++++++++++++++++++++ 1 file changed, 189 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml new file mode 100644 index 0000000..e656cc8 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 ADSP Peripheral Image Loader + +maintainers: + - Srinivasa Rao Mandadapu + +description: + This document defines the binding for a component that loads and boots firmware + on the Qualcomm Technology Inc. ADSP. + +properties: + compatible: + enum: + - qcom,sc7280-adsp-pil + + reg: + minItems: 1 + items: + - description: qdsp6ss register + - description: efuse q6ss register + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + clocks: + items: + - description: XO clock + - description: GCC CFG NOC LPASS clock + - description: LPASS AHBS AON clock + - description: LPASS AHBM AON clock + - description: QDSP XO clock + - description: Q6SP6SS SLEEP clock + - description: Q6SP6SS CORE clock + + clock-names: + items: + - const: xo + - const: gcc_cfg_noc_lpass + - const: lpass_ahbs_aon_cbcr + - const: lpass_ahbm_aon_cbcr + - const: qdsp6ss_xo + - const: qdsp6ss_sleep + - const: qdsp6ss_core + + power-domains: + items: + - description: LCX power domain + + resets: + items: + - description: PDC AUDIO SYNC RESET + - description: CC LPASS restart + + reset-names: + items: + - const: pdc_sync + - const: cc_lpass + + memory-region: + maxItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + qcom,adsp-memory-regions: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Each entry consists of 4 integers and represents the + list of memory regions accessed by ADSP firmware. + items: + items: + - description: | + "iova reg" indicates the address of virtual memory region. + - description: | + "physical reg" indicates the address of phyical memory region. + - description: | + "size" indicates the offset memory region. + - description: | + "access level" indicates the read, read and write access levels. + minimum: 0 + maximum: 1 + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle reference to a syscon representing TCSR followed by the + three offsets within syscon for q6, modem and nc halt registers. + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop the modem + + qcom,smem-state-names: + $ref: /schemas/types.yaml#/definitions/string + description: The names of the state bits used for SMP2P output + items: + - const: stop + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - reset-names + - qcom,halt-regs + - memory-region + - qcom,smem-states + - qcom,smem-state-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + remoteproc@3000000 { + compatible = "qcom,sc7280-adsp-pil"; + reg = <0x03000000 0x5000>, + <0x355B000 0x10>; + + interrupts-extended = <&pdc 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CFG_NOC_LPASS_CLK>, + <&lpasscc LPASS_Q6SS_AHBM_CLK>, + <&lpasscc LPASS_Q6SS_AHBS_CLK>, + <&lpasscc LPASS_QDSP6SS_XO_CLK>, + <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>, + <&lpasscc LPASS_QDSP6SS_CORE_CLK>; + clock-names = "xo", "gcc_cfg_noc_lpass", + "lpass_ahbs_aon_cbcr", + "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", + "qdsp6ss_sleep", "qdsp6ss_core"; + + power-domains = <&rpmhpd SC7280_LCX>; + + resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>, + <&aoss_reset AOSS_CC_LPASS_RESTART>; + reset-names = "pdc_sync", "cc_lpass"; + + qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + qcom,adsp-memory-regions = <0x00100000 0x00100000 0x4000 0>, + <0x00113000 0x00113000 0x1000 0>, + <0x00117000 0x00117000 0x2000 1>; + }; From patchwork Fri Aug 12 12:47:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12942228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 622DFC25B0E for ; Fri, 12 Aug 2022 12:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238360AbiHLMtB (ORCPT ); Fri, 12 Aug 2022 08:49:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234491AbiHLMtA (ORCPT ); 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Fri, 12 Aug 2022 12:48:20 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27CCmINl025741 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Aug 2022 12:48:18 GMT Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 12 Aug 2022 05:48:13 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH v4 2/7] remoteproc: qcom: Add flag in adsp private data structure Date: Fri, 12 Aug 2022 18:17:41 +0530 Message-ID: <1660308466-410-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> References: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: copSmyWlielgGD2onpc2GpBOjj_3-430 X-Proofpoint-GUID: copSmyWlielgGD2onpc2GpBOjj_3-430 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_08,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208120034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add flag in qcom_adsp private data structure and initialize it to distinguish ADSP and WPSS modules. Signed-off-by: Srinivasa Rao Mandadapu --- Changes since V3: -- Rename is_adsp_sb_needed to adsp_sandbox_needed. Changes since V2: -- Add is_adsp_sb_needed flag instead of is_wpss. drivers/remoteproc/qcom_q6v5_adsp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index 2f3b9f5..d0b767f 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -62,6 +62,7 @@ struct adsp_pil_data { const char *sysmon_name; int ssctl_id; bool is_wpss; + bool adsp_sandbox_needed; bool auto_boot; const char **clk_ids; @@ -99,6 +100,7 @@ struct qcom_adsp { phys_addr_t mem_reloc; void *mem_region; size_t mem_size; + bool adsp_sandbox_needed; struct device *proxy_pds[QCOM_Q6V5_RPROC_PROXY_PD_MAX]; size_t proxy_pd_count; @@ -602,6 +604,8 @@ static int adsp_probe(struct platform_device *pdev) adsp->dev = &pdev->dev; adsp->rproc = rproc; adsp->info_name = desc->sysmon_name; + adsp->adsp_sandbox_needed = desc->adsp_sandbox_needed; + platform_set_drvdata(pdev, adsp); if (desc->is_wpss) From patchwork Fri Aug 12 12:47:42 2022 Content-Type: text/plain; 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Signed-off-by: Srinivasa Rao Mandadapu --- Changes since V3: -- Rename is_adsp_sb_needed to adsp_sandbox_needed. -- Update sc7280 compatible name entry in sorted order. Changes since V2: -- Initialize is_adsp_sb_needed flag. -- Remove empty proxy pds array. drivers/remoteproc/qcom_q6v5_adsp.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index d0b767f..6d409ca 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -701,6 +701,22 @@ static const struct adsp_pil_data adsp_resource_init = { }, }; +static const struct adsp_pil_data adsp_sc7280_resource_init = { + .crash_reason_smem = 423, + .firmware_name = "adsp.mbn", + .load_state = "adsp", + .ssr_name = "lpass", + .sysmon_name = "adsp", + .ssctl_id = 0x14, + .is_wpss = false, + .adsp_sandbox_needed = true, + .auto_boot = true, + .clk_ids = (const char*[]) { + "gcc_cfg_noc_lpass", NULL + }, + .num_clks = 1, +}; + static const struct adsp_pil_data cdsp_resource_init = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", @@ -739,6 +755,7 @@ static const struct adsp_pil_data wpss_resource_init = { static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init }, + { .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init }, { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init }, { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init }, { }, From patchwork Fri Aug 12 12:47:43 2022 Content-Type: text/plain; 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Fri, 12 Aug 2022 12:48:29 GMT Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 12 Aug 2022 05:48:24 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH v4 4/7] remoteproc: qcom: Replace hard coded values with macros Date: Fri, 12 Aug 2022 18:17:43 +0530 Message-ID: <1660308466-410-5-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> References: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: -aCgXiQv_6JWU7QasTCsg4O8vjt92OWc X-Proofpoint-GUID: -aCgXiQv_6JWU7QasTCsg4O8vjt92OWc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_08,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 mlxscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208120034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace hard coded values of QDSP6 boot control reg params with appropriate macro names. Signed-off-by: Srinivasa Rao Mandadapu Reviewed-by: Dmitry Baryshkov --- drivers/remoteproc/qcom_q6v5_adsp.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index 6d409ca..701a615 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -54,6 +54,9 @@ #define QCOM_Q6V5_RPROC_PROXY_PD_MAX 3 +#define LPASS_BOOT_CORE_START BIT(0) +#define LPASS_BOOT_CMD_START BIT(0) + struct adsp_pil_data { int crash_reason_smem; const char *firmware_name; @@ -366,10 +369,10 @@ static int adsp_start(struct rproc *rproc) writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG); /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */ - writel(0x1, adsp->qdsp6ss_base + CORE_START_REG); + writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG); /* Trigger boot FSM to start QDSP6 */ - writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG); + writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG); /* Wait for core to come out of reset */ ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG, From patchwork Fri Aug 12 12:47:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12942231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 752F6C00140 for ; Fri, 12 Aug 2022 12:49:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238816AbiHLMt1 (ORCPT ); Fri, 12 Aug 2022 08:49:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238726AbiHLMtS (ORCPT ); Fri, 12 Aug 2022 08:49:18 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64CA7AE9E3; Fri, 12 Aug 2022 05:49:16 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27C9Fukg023372; Fri, 12 Aug 2022 12:48:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=XD8p0yeIP6FHp1zRXk2g6v1Fja3jOBHVk/L7ZMjGmI8=; b=djmMC0PGL6Ah4cts32FVB8kPNT7ZlM2031TqXqaR7/MFxq+Q7Mt7nDRHlTyubE73FIu6 So0oVyqvH14q+FsWsmEJcKDxNlNo05CMAWtuUi2PE4jALddnOYkRDeBcsPLi+mbs7a0Y U4uCtDX2+a3O7o5FoIH9Jt4b8eet44CTvvMrv8krRUGzebKKpL2UHW/8JndKT3pXBSCr Ly0H5T9Gy51mMOPn5ZdzuGAPbytMeqMr9JjNbwviKXrJo89FzpZRNeGeTbj4QvstUYWO 7BWPw2nmdDjczPyhTopldxnKFs0/DYaKzqPnuG4HjoSeP/UfanTwGJBxsi/pD5IuWZ+y Tg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3hw89x2dwh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Aug 2022 12:48:35 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27CCmZdE025821 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Aug 2022 12:48:35 GMT Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 12 Aug 2022 05:48:29 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH v4 5/7] remoteproc: qcom: Add efuse evb selection control Date: Fri, 12 Aug 2022 18:17:44 +0530 Message-ID: <1660308466-410-6-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> References: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: f7vZIr98btRgWbMegtNVSYxi7AHQVZ-H X-Proofpoint-ORIG-GUID: f7vZIr98btRgWbMegtNVSYxi7AHQVZ-H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_08,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxlogscore=984 lowpriorityscore=0 phishscore=0 clxscore=1015 spamscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208120034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add efuse evb selection control and enable it for starting ADSP. Signed-off-by: Srinivasa Rao Mandadapu --- drivers/remoteproc/qcom_q6v5_adsp.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index 701a615..b0a63a0 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -56,6 +56,7 @@ #define LPASS_BOOT_CORE_START BIT(0) #define LPASS_BOOT_CMD_START BIT(0) +#define LPASS_EFUSE_Q6SS_EVB_SEL 0x0 struct adsp_pil_data { int crash_reason_smem; @@ -86,6 +87,7 @@ struct qcom_adsp { struct clk_bulk_data *clks; void __iomem *qdsp6ss_base; + void __iomem *lpass_efuse; struct reset_control *pdc_sync_reset; struct reset_control *restart; @@ -368,6 +370,9 @@ static int adsp_start(struct rproc *rproc) /* Program boot address */ writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG); + if (adsp->lpass_efuse) + writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse); + /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */ writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG); @@ -522,6 +527,11 @@ static int adsp_init_mmio(struct qcom_adsp *adsp, return PTR_ERR(adsp->qdsp6ss_base); } + adsp->lpass_efuse = devm_platform_ioremap_resource_byname(pdev, "lpass_efuse"); + if (IS_ERR(adsp->lpass_efuse)) { + adsp->lpass_efuse = NULL; + dev_dbg(adsp->dev, "failed to map LPASS efuse registers\n"); + } syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0); if (!syscon) { dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); From patchwork Fri Aug 12 12:47:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12942232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F57DC00140 for ; Fri, 12 Aug 2022 12:49:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238790AbiHLMto (ORCPT ); Fri, 12 Aug 2022 08:49:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238541AbiHLMt1 (ORCPT ); Fri, 12 Aug 2022 08:49:27 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44180B14C8; Fri, 12 Aug 2022 05:49:22 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27C42jdq005470; Fri, 12 Aug 2022 12:48:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=a+QGBmbNFdR2vKT3kyFf/ptdMLT43Mr+6NgGXTuTQz0=; b=oYl1fK689FnXwwSCRgxlz4Dmq5Rhu7za2lgVgBqQH6mquOWAidyB5FvrFvo6Mng1BGl0 PiKlyYlFsQvOay1BFNvTZqvDpxiPsm2npW/ydLaDXgY2nrrcOU817IKZPRzhZM9LdCq+ d2k9jkGAglhyjTMC2vz73laz/dDrTmBwEk8TB1xzMcccu/Chd6Ids1D2wIGf5+Ar6TYw b34ELDIYcrSYvgIcBOZcgNysoEa5wdKG8Pyc7AO4BJZtaYaJfpxY7BU+S4qo7Ey1bP11 0ojb0OJYe7mXnAzC1Upm0TKQpPscfvqfxIkyVedaYr4wx1M+W+NB4OU1FSOD2LuGlbun pQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3hwa8d268r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Aug 2022 12:48:41 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27CCme48022688 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Aug 2022 12:48:40 GMT Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 12 Aug 2022 05:48:35 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH v4 6/7] remoteproc: qcom: Add support for memory sandbox Date: Fri, 12 Aug 2022 18:17:45 +0530 Message-ID: <1660308466-410-7-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> References: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JO6DNBlbzhSNoSEv96XbvinEyL4uBo3S X-Proofpoint-ORIG-GUID: JO6DNBlbzhSNoSEv96XbvinEyL4uBo3S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_08,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208120034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update pil driver with SMMU mapping for allowing authorised memory access to ADSP firmware, by reading required memory regions either from device tree file or from resource table embedded in ADSP binary header. Signed-off-by: Srinivasa Rao Mandadapu Reported-by: kernel test robot --- Changes since V3: -- Rename is_adsp_sb_needed to adsp_sandbox_needed. -- Add smmu unmapping in error case and in adsp stop. Changes since V2: -- Replace platform_bus_type with adsp->dev->bus. -- Use API of_parse_phandle_with_args() instead of of_parse_phandle_with_fixed_args(). -- Replace adsp->is_wpss with adsp->is_adsp. -- Update error handling in adsp_start(). drivers/remoteproc/qcom_q6v5_adsp.c | 172 +++++++++++++++++++++++++++++++++++- 1 file changed, 170 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index b0a63a0..ca45d2c 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -48,6 +49,8 @@ #define LPASS_PWR_ON_REG 0x10 #define LPASS_HALTREQ_REG 0x0 +#define SID_MASK_DEFAULT 0xF + #define QDSP6SS_XO_CBCR 0x38 #define QDSP6SS_CORE_CBCR 0x20 #define QDSP6SS_SLEEP_CBCR 0x3c @@ -78,7 +81,7 @@ struct adsp_pil_data { struct qcom_adsp { struct device *dev; struct rproc *rproc; - + struct iommu_domain *iommu_dom; struct qcom_q6v5 q6v5; struct clk *xo; @@ -333,6 +336,155 @@ static int adsp_load(struct rproc *rproc, const struct firmware *fw) return 0; } +static void adsp_of_unmap_smmu(struct iommu_domain *iommu_dom, const __be32 *prop, int len) +{ + unsigned long mem_phys; + unsigned long iova; + unsigned int mem_size; + int access_level; + int i; + + for (i = 0; i < len; i++) { + iova = be32_to_cpu(prop[i++]); + mem_phys = be32_to_cpu(prop[i++]); + mem_size = be32_to_cpu(prop[i++]); + access_level = be32_to_cpu(prop[i]); + iommu_unmap(iommu_dom, iova, mem_size); + } +} + +static void adsp_rproc_unmap_smmu(struct rproc *rproc, int len) +{ + struct fw_rsc_devmem *rsc_fw; + struct fw_rsc_hdr *hdr; + int offset; + int i; + + for (i = 0; i < len; i++) { + offset = rproc->table_ptr->offset[i]; + hdr = (void *)rproc->table_ptr + offset; + rsc_fw = (struct fw_rsc_devmem *)hdr + sizeof(*hdr); + + iommu_unmap(rproc->domain, rsc_fw->da, rsc_fw->len); + } +} + +static void adsp_unmap_smmu(struct rproc *rproc) +{ + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; + const __be32 *prop; + unsigned int len; + + prop = of_get_property(adsp->dev->of_node, "qcom,adsp-memory-regions", &len); + if (prop) { + adsp_of_unmap_smmu(adsp->iommu_dom, prop, len); + } else { + if (rproc->table_ptr) + adsp_rproc_unmap_smmu(rproc, rproc->table_ptr->num); + } +} + +static int adsp_map_smmu(struct qcom_adsp *adsp, struct rproc *rproc) +{ + struct of_phandle_args args; + struct fw_rsc_devmem *rsc_fw; + struct fw_rsc_hdr *hdr; + const __be32 *prop; + long long sid; + unsigned long mem_phys; + unsigned long iova; + unsigned int mem_size; + unsigned int flag; + unsigned int len; + int access_level; + int offset; + int ret; + int rc; + int i; + + rc = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args); + if (rc < 0) + sid = -1; + else + sid = args.args[0] & SID_MASK_DEFAULT; + + adsp->iommu_dom = iommu_domain_alloc(adsp->dev->bus); + if (!adsp->iommu_dom) { + dev_err(adsp->dev, "failed to allocate iommu domain\n"); + ret = -ENOMEM; + goto domain_free; + } + + ret = iommu_attach_device(adsp->iommu_dom, adsp->dev); + if (ret) { + dev_err(adsp->dev, "could not attach device ret = %d\n", ret); + ret = -EBUSY; + goto detach_device; + } + + /* Add SID configuration for ADSP Firmware to SMMU */ + adsp->mem_phys = adsp->mem_phys | (sid << 32); + + ret = iommu_map(adsp->iommu_dom, adsp->mem_phys, adsp->mem_phys, + adsp->mem_size, IOMMU_READ | IOMMU_WRITE); + if (ret) { + dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n"); + goto sid_unmap; + } + + prop = of_get_property(adsp->dev->of_node, "qcom,adsp-memory-regions", &len); + if (prop) { + len /= sizeof(__be32); + for (i = 0; i < len; i++) { + iova = be32_to_cpu(prop[i++]); + mem_phys = be32_to_cpu(prop[i++]); + mem_size = be32_to_cpu(prop[i++]); + access_level = be32_to_cpu(prop[i]); + + if (access_level) + flag = IOMMU_READ | IOMMU_WRITE; + else + flag = IOMMU_READ; + + ret = iommu_map(adsp->iommu_dom, iova, mem_phys, mem_size, flag); + if (ret) { + dev_err(adsp->dev, "failed to map addr = %p mem_size = %x\n", + &(mem_phys), mem_size); + goto smmu_unmap; + } + } + } else { + if (!rproc->table_ptr) + goto sid_unmap; + + for (i = 0; i < rproc->table_ptr->num; i++) { + offset = rproc->table_ptr->offset[i]; + hdr = (void *)rproc->table_ptr + offset; + rsc_fw = (struct fw_rsc_devmem *)hdr + sizeof(*hdr); + + ret = iommu_map(rproc->domain, rsc_fw->da, rsc_fw->pa, + rsc_fw->len, rsc_fw->flags); + if (ret) { + pr_err("%s; unable to map adsp memory address\n", __func__); + goto rproc_smmu_unmap; + } + } + } + return 0; +rproc_smmu_unmap: + adsp_rproc_unmap_smmu(rproc, i); + goto sid_unmap; +smmu_unmap: + adsp_of_unmap_smmu(adsp->iommu_dom, prop, i); +sid_unmap: + iommu_unmap(adsp->iommu_dom, adsp->mem_phys, adsp->mem_size); +detach_device: + iommu_domain_free(adsp->iommu_dom); +domain_free: + return ret; +} + + static int adsp_start(struct rproc *rproc) { struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; @@ -343,9 +495,16 @@ static int adsp_start(struct rproc *rproc) if (ret) return ret; + if (adsp->adsp_sandbox_needed) { + ret = adsp_map_smmu(adsp, rproc); + if (ret) { + dev_err(adsp->dev, "ADSP smmu mapping failed\n"); + goto disable_irqs; + } + } ret = clk_prepare_enable(adsp->xo); if (ret) - goto disable_irqs; + goto adsp_smmu_unmap; ret = qcom_rproc_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); @@ -401,6 +560,12 @@ static int adsp_start(struct rproc *rproc) qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); disable_xo_clk: clk_disable_unprepare(adsp->xo); +adsp_smmu_unmap: + if (adsp->adsp_sandbox_needed) { + iommu_unmap(adsp->iommu_dom, adsp->mem_phys, adsp->mem_size); + adsp_unmap_smmu(rproc); + iommu_domain_free(adsp->iommu_dom); + } disable_irqs: qcom_q6v5_unprepare(&adsp->q6v5); @@ -429,6 +594,9 @@ static int adsp_stop(struct rproc *rproc) if (ret) dev_err(adsp->dev, "failed to shutdown: %d\n", ret); + if (adsp->adsp_sandbox_needed) + adsp_unmap_smmu(rproc); + handover = qcom_q6v5_unprepare(&adsp->q6v5); if (handover) qcom_adsp_pil_handover(&adsp->q6v5); From patchwork Fri Aug 12 12:47:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12942233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD3DEC00140 for ; Fri, 12 Aug 2022 12:49:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238738AbiHLMtu (ORCPT ); Fri, 12 Aug 2022 08:49:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238512AbiHLMtf (ORCPT ); Fri, 12 Aug 2022 08:49:35 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51269B0B39; Fri, 12 Aug 2022 05:49:28 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27C6J8QP018855; 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Fri, 12 Aug 2022 12:48:46 GMT Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 12 Aug 2022 05:48:40 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH v4 7/7] remoteproc: qcom: Update QDSP6 out-of-reset timeout value Date: Fri, 12 Aug 2022 18:17:46 +0530 Message-ID: <1660308466-410-8-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> References: <1660308466-410-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fC-krQFFdLXL9taM3xBUEmkcBkOGChpN X-Proofpoint-ORIG-GUID: fC-krQFFdLXL9taM3xBUEmkcBkOGChpN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_08,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 phishscore=0 adultscore=0 malwarescore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208120034 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update QDSP6 out-of-reset timeout value to 1 second, as sometimes ADSP boot failing on SC7280 based platforms with existing value. Also add few micro seconds sleep after enabling boot core start register. Signed-off-by: Srinivasa Rao Mandadapu --- drivers/remoteproc/qcom_q6v5_adsp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index ca45d2c..2b5b172 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -34,7 +34,7 @@ /* time out value */ #define ACK_TIMEOUT 1000 #define ACK_TIMEOUT_US 1000000 -#define BOOT_FSM_TIMEOUT 10000 +#define BOOT_FSM_TIMEOUT 1000000 /* mask values */ #define EVB_MASK GENMASK(27, 4) /*QDSP6SS register offsets*/ @@ -534,13 +534,14 @@ static int adsp_start(struct rproc *rproc) /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */ writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG); + usleep_range(100, 110); /* Trigger boot FSM to start QDSP6 */ writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG); /* Wait for core to come out of reset */ ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG, - val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); + val, (val & BIT(0)) != 0, 100, BOOT_FSM_TIMEOUT); if (ret) { dev_err(adsp->dev, "failed to bootup adsp\n"); goto disable_adsp_clks;