From patchwork Sat Aug 13 05:32:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12942681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD720C25B08 for ; Sat, 13 Aug 2022 05:32:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234156AbiHMFcu (ORCPT ); Sat, 13 Aug 2022 01:32:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230147AbiHMFcs (ORCPT ); Sat, 13 Aug 2022 01:32:48 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7921AEE0B; Fri, 12 Aug 2022 22:32:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660368767; x=1691904767; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=69VAjh6MSJVwDBvgpchlCi4/LZxKGIBKEymJkel47EQ=; b=DqqAPNNz076mvyXJZRUGsooLVOr/L/3QlU7eTTw+mzGQlN1xuMq01QG+ +DxpwE8l9QaSpdLRERbIrOUh36L1RfTWwHkRfNT0Ky0noVDroE7TCsUsA hjUZ4sJJ+cgxzAYxP6JjZdiIEAyA9pJYoD8UOrBcMVt6wxVVtkVMSIaGs xJqt5hgrL/wilgKBTiQDmmSkf4zqn3Q0jcN0gu4W3g+T2d+jRgX3pRXcD 98N3Cx3+MBsbx09Tloi1K2btJ+jzQ6dcKZsHretAycB33//VGTSYON7JS LgViP/1W3mITbMdxsFVFCYDav7xEuN4wwWqbpupMmwImdbQ2p2caYQroT w==; X-IronPort-AV: E=McAfee;i="6400,9594,10437"; a="289298886" X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="289298886" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:46 -0700 X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="933949170" Received: from jchen8-mobl.amr.corp.intel.com (HELO localhost) ([10.212.10.85]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:46 -0700 From: ira.weiny@intel.com To: Dan Williams Cc: Ira Weiny , Alison Schofield , Vishal Verma , Ben Widawsky , Steven Rostedt , Jonathan Cameron , Davidlohr Bueso , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [RFC PATCH 1/9] cxl/mem: Implement Get Event Records command Date: Fri, 12 Aug 2022 22:32:35 -0700 Message-Id: <20220813053243.757363-2-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220813053243.757363-1-ira.weiny@intel.com> References: <20220813053243.757363-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny Event records are defined for CXL devices. Each record is reported in one event log. Devices are required to support the storage of at least one event record in each event log type. Devices track event log overflow by incrementing a counter and tracking the time of the first and last overflow event seen. Software queries events via the Get Event Record mailbox command; CXL v3.0 section 8.2.9.2.2. Issue the Get Event Record mailbox command on driver load. Trace each record found, as well as any overflow conditions. Only 1 event is requested for each query. Optimization of multiple record queries is deferred. This patch traces a raw event record only and leaves the specific event record types to subsequent patches. NOTE: checkpatch is not completely happy with the tracing part of this patch but AFAICT it is correct. I'm open to suggestions if I've done something wrong. Signed-off-by: Ira Weiny --- MAINTAINERS | 1 + drivers/cxl/core/mbox.c | 60 ++++++++++++++ drivers/cxl/cxlmem.h | 66 ++++++++++++++++ include/trace/events/cxl-events.h | 127 ++++++++++++++++++++++++++++++ include/uapi/linux/cxl_mem.h | 1 + 5 files changed, 255 insertions(+) create mode 100644 include/trace/events/cxl-events.h diff --git a/MAINTAINERS b/MAINTAINERS index 54fa6e2059de..1cb9cec31009 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5014,6 +5014,7 @@ M: Dan Williams L: linux-cxl@vger.kernel.org S: Maintained F: drivers/cxl/ +F: include/trace/events/cxl*.h F: include/uapi/linux/cxl_mem.h CONEXANT ACCESSRUNNER USB DRIVER diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index 16176b9278b4..2cceed8608dc 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -7,6 +7,9 @@ #include #include +#define CREATE_TRACE_POINTS +#include + #include "core.h" static bool cxl_raw_allow_all; @@ -48,6 +51,7 @@ static struct cxl_mem_command cxl_mem_commands[CXL_MEM_COMMAND_ID_MAX] = { CXL_CMD(RAW, CXL_VARIABLE_PAYLOAD, CXL_VARIABLE_PAYLOAD, 0), #endif CXL_CMD(GET_SUPPORTED_LOGS, 0, CXL_VARIABLE_PAYLOAD, CXL_CMD_FLAG_FORCE_ENABLE), + CXL_CMD(GET_EVENT_RECORD, 1, CXL_VARIABLE_PAYLOAD, 0), CXL_CMD(GET_FW_INFO, 0, 0x50, 0), CXL_CMD(GET_PARTITION_INFO, 0, 0x20, 0), CXL_CMD(GET_LSA, 0x8, CXL_VARIABLE_PAYLOAD, 0), @@ -704,6 +708,62 @@ int cxl_enumerate_cmds(struct cxl_dev_state *cxlds) } EXPORT_SYMBOL_NS_GPL(cxl_enumerate_cmds, CXL); +static int cxl_mem_get_records_log(struct cxl_dev_state *cxlds, + enum cxl_event_log_type type) +{ + struct cxl_get_event_payload payload; + + do { + u8 log_type = type; + u16 record_count; + int rc; + + rc = cxl_mbox_send_cmd(cxlds, CXL_MBOX_OP_GET_EVENT_RECORD, + &log_type, sizeof(log_type), + &payload, sizeof(payload)); + if (rc) + return rc; + + record_count = le16_to_cpu(payload.record_count); + if (record_count > 0) + trace_cxl_event(dev_name(cxlds->dev), type, + &payload.record); + + if (payload.flags & CXL_GET_EVENT_FLAG_OVERFLOW) + trace_cxl_event_overflow(dev_name(cxlds->dev), type, + &payload); + + } while (payload.flags & CXL_GET_EVENT_FLAG_MORE_RECORDS); + + return 0; +} + +/** + * cxl_mem_get_event_records - Get Event Records from the device + * @cxlds: The device data for the operation + * + * Retrieve all event records available on the device and report them as trace + * events. + * + * See CXL v3.0 @8.2.9.2.2 Get Event Records + */ +void cxl_mem_get_event_records(struct cxl_dev_state *cxlds) +{ + struct device *dev = cxlds->dev; + enum cxl_event_log_type log_type; + + for (log_type = CXL_EVENT_TYPE_INFO; + log_type < CXL_EVENT_TYPE_MAX; log_type++) { + int rc; + + rc = cxl_mem_get_records_log(cxlds, log_type); + if (rc) + dev_err(dev, "Failed to query %s Event Logs : %d", + cxl_event_log_type_str(log_type), rc); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_mem_get_event_records, CXL); + /** * cxl_mem_get_partition_info - Get partition info * @cxlds: The device data for the operation diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 88e3a8e54b6a..f83634f3bc8d 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -4,6 +4,7 @@ #define __CXL_MEM_H__ #include #include +#include #include "cxl.h" /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ @@ -253,6 +254,7 @@ struct cxl_dev_state { enum cxl_opcode { CXL_MBOX_OP_INVALID = 0x0000, CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, + CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, CXL_MBOX_OP_GET_FW_INFO = 0x0200, CXL_MBOX_OP_ACTIVATE_FW = 0x0202, CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, @@ -322,6 +324,69 @@ struct cxl_mbox_identify { u8 qos_telemetry_caps; } __packed; +/* + * Common Event Record Format + * CXL v3.0 section 8.2.9.2.1; Table 8-42 + */ +struct cxl_event_record_hdr { + uuid_t id; + __le32 flags_length; + __le16 handle; + __le16 related_handle; + __le64 timestamp; + __le64 reserved1; + __le64 reserved2; +} __packed; + +#define EVENT_RECORD_DATA_LENGTH 0x50 +struct cxl_event_record_raw { + struct cxl_event_record_hdr hdr; + u8 data[EVENT_RECORD_DATA_LENGTH]; +} __packed; + +/* + * Get Event Records output payload + * CXL v3.0 section 8.2.9.2.2; Table 8-50 + * + * Space given for 1 record + */ +#define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) +#define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) +struct cxl_get_event_payload { + u8 flags; + u8 reserved1; + __le16 overflow_err_count; + __le64 first_overflow_timestamp; + __le64 last_overflow_timestamp; + __le16 record_count; + u8 reserved2[0xa]; + struct cxl_event_record_raw record; +} __packed; + +enum cxl_event_log_type { + CXL_EVENT_TYPE_INFO = 0x00, + CXL_EVENT_TYPE_WARN, + CXL_EVENT_TYPE_FAIL, + CXL_EVENT_TYPE_FATAL, + CXL_EVENT_TYPE_MAX +}; +static inline char *cxl_event_log_type_str(enum cxl_event_log_type type) +{ + switch (type) { + case CXL_EVENT_TYPE_INFO: + return "Informational"; + case CXL_EVENT_TYPE_WARN: + return "Warning"; + case CXL_EVENT_TYPE_FAIL: + return "Failure"; + case CXL_EVENT_TYPE_FATAL: + return "Fatal"; + default: + break; + } + return ""; +} + struct cxl_mbox_get_partition_info { __le64 active_volatile_cap; __le64 active_persistent_cap; @@ -381,6 +446,7 @@ int cxl_mem_create_range_info(struct cxl_dev_state *cxlds); struct cxl_dev_state *cxl_dev_state_create(struct device *dev); void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); +void cxl_mem_get_event_records(struct cxl_dev_state *cxlds); #ifdef CONFIG_CXL_SUSPEND void cxl_mem_active_inc(void); void cxl_mem_active_dec(void); diff --git a/include/trace/events/cxl-events.h b/include/trace/events/cxl-events.h new file mode 100644 index 000000000000..f4baeae66cf3 --- /dev/null +++ b/include/trace/events/cxl-events.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM cxl_events + +#if !defined(_CXL_TRACE_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ) +#define _CXL_TRACE_EVENTS_H + +#include + +#define EVENT_LOGS \ + EM(CXL_EVENT_TYPE_INFO, "Info") \ + EM(CXL_EVENT_TYPE_WARN, "Warning") \ + EM(CXL_EVENT_TYPE_FAIL, "Failure") \ + EM(CXL_EVENT_TYPE_FATAL, "Fatal") \ + EMe(CXL_EVENT_TYPE_MAX, "") + +/* + * First define the enums in the above macros to be exported to userspace via + * TRACE_DEFINE_ENUM(). + */ +#undef EM +#undef EMe +#define EM(a, b) TRACE_DEFINE_ENUM(a); +#define EMe(a, b) TRACE_DEFINE_ENUM(a); + +EVENT_LOGS +#define show_log_type(type) __print_symbolic(type, EVENT_LOGS) + +/* + * Now redefine the EM and EMe macros to map the enums to the strings that will + * be printed in the output + */ +#undef EM +#undef EMe +#define EM(a, b) {a, b}, +#define EMe(a, b) {a, b} + +TRACE_EVENT(cxl_event_overflow, + + TP_PROTO(const char *dev_name, enum cxl_event_log_type log, + struct cxl_get_event_payload *payload), + + TP_ARGS(dev_name, log, payload), + + TP_STRUCT__entry( + __string(dev_name, dev_name) + __field(int, log) + __field(u16, count) + __field(u64, first) + __field(u64, last) + ), + + TP_fast_assign( + __assign_str(dev_name, dev_name); + __entry->log = log; + __entry->count = le16_to_cpu(payload->overflow_err_count); + __entry->first = le64_to_cpu(payload->first_overflow_timestamp); + __entry->last = le64_to_cpu(payload->last_overflow_timestamp); + ), + + TP_printk("%s: EVENT LOG %s OVERFLOW %u records from %llu to %llu", + __get_str(dev_name), show_log_type(__entry->log), + __entry->count, __entry->first, __entry->last) + +); + +/* + * Common Event Record Format + * CXL v2.0 section 8.2.9.1.1; Table 153 + */ +#define CXL_EVENT_RECORD_FLAG_PERMANENT BIT(2) +#define CXL_EVENT_RECORD_FLAG_MAINT_NEEDED BIT(3) +#define CXL_EVENT_RECORD_FLAG_PERF_DEGRADED BIT(4) +#define CXL_EVENT_RECORD_FLAG_HW_REPLACE BIT(5) +#define show_hdr_flags(flags) __print_flags(flags, " | ", \ + { CXL_EVENT_RECORD_FLAG_PERMANENT, "Permanent Condition" }, \ + { CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, "Maintanance Needed" }, \ + { CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, "Performance Degraded" }, \ + { CXL_EVENT_RECORD_FLAG_HW_REPLACE, "Hardware Replacement Needed" } \ +) + +TRACE_EVENT(cxl_event, + + TP_PROTO(const char *dev_name, enum cxl_event_log_type log, + struct cxl_event_record_raw *rec), + + TP_ARGS(dev_name, log, rec), + + TP_STRUCT__entry( + __string(dev_name, dev_name) + __field(int, log) + __array(u8, id, UUID_SIZE) + __field(u32, flags) + __field(u16, handle) + __field(u16, related_handle) + __field(u64, timestamp) + __array(u8, data, EVENT_RECORD_DATA_LENGTH) + __field(u8, length) + ), + + TP_fast_assign( + __assign_str(dev_name, dev_name); + memcpy(__entry->id, &rec->hdr.id, UUID_SIZE); + __entry->log = log; + __entry->flags = le32_to_cpu(rec->hdr.flags_length) >> 8; + __entry->length = le32_to_cpu(rec->hdr.flags_length) & 0xFF; + __entry->handle = le16_to_cpu(rec->hdr.handle); + __entry->related_handle = le16_to_cpu(rec->hdr.related_handle); + __entry->timestamp = le64_to_cpu(rec->hdr.timestamp); + memcpy(__entry->data, &rec->data, EVENT_RECORD_DATA_LENGTH); + ), + + TP_printk("%s: %s time=%llu id=%pUl handle=%x related_handle=%x hdr_flags='%s' " \ + ": %s", + __get_str(dev_name), show_log_type(__entry->log), + __entry->timestamp, __entry->id, __entry->handle, + __entry->related_handle, show_hdr_flags(__entry->flags), + __print_hex(__entry->data, EVENT_RECORD_DATA_LENGTH) + ) +); + +#endif /* _CXL_TRACE_EVENTS_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE cxl-events +#include diff --git a/include/uapi/linux/cxl_mem.h b/include/uapi/linux/cxl_mem.h index c71021a2a9ed..70459be5bdd4 100644 --- a/include/uapi/linux/cxl_mem.h +++ b/include/uapi/linux/cxl_mem.h @@ -24,6 +24,7 @@ ___C(IDENTIFY, "Identify Command"), \ ___C(RAW, "Raw device command"), \ ___C(GET_SUPPORTED_LOGS, "Get Supported Logs"), \ + ___C(GET_EVENT_RECORD, "Get Event Record"), \ ___C(GET_FW_INFO, "Get FW Info"), \ ___C(GET_PARTITION_INFO, "Get Partition Information"), \ ___C(GET_LSA, "Get Label Storage Area"), \ From patchwork Sat Aug 13 05:32:36 2022 Content-Type: text/plain; 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12 Aug 2022 22:32:47 -0700 From: ira.weiny@intel.com To: Dan Williams Cc: Ira Weiny , Alison Schofield , Vishal Verma , Ben Widawsky , Steven Rostedt , Jonathan Cameron , Davidlohr Bueso , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [RFC PATCH 2/9] cxl/mem: Implement Clear Event Records command Date: Fri, 12 Aug 2022 22:32:36 -0700 Message-Id: <20220813053243.757363-3-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220813053243.757363-1-ira.weiny@intel.com> References: <20220813053243.757363-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny CXL v3.0 section 8.2.9.2.3 defines the Clear Event Records mailbox command. After an event record is read it needs to be cleared from the event log. Implement cxl_clear_event_record() and call it for each record retrieved from the device. Each record is cleared individually. A clear all bit is specified but events could arrive between a get and the final clear all operation. Therefore each event is cleared specifically. Signed-off-by: Ira Weiny Reviewed-by: Jonathan Cameron --- drivers/cxl/core/mbox.c | 31 ++++++++++++++++++++++++++++--- drivers/cxl/cxlmem.h | 15 +++++++++++++++ include/uapi/linux/cxl_mem.h | 1 + 3 files changed, 44 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index 2cceed8608dc..493f5ceb5d1c 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -52,6 +52,7 @@ static struct cxl_mem_command cxl_mem_commands[CXL_MEM_COMMAND_ID_MAX] = { #endif CXL_CMD(GET_SUPPORTED_LOGS, 0, CXL_VARIABLE_PAYLOAD, CXL_CMD_FLAG_FORCE_ENABLE), CXL_CMD(GET_EVENT_RECORD, 1, CXL_VARIABLE_PAYLOAD, 0), + CXL_CMD(CLEAR_EVENT_RECORD, CXL_VARIABLE_PAYLOAD, 0, 0), CXL_CMD(GET_FW_INFO, 0, 0x50, 0), CXL_CMD(GET_PARTITION_INFO, 0, 0x20, 0), CXL_CMD(GET_LSA, 0x8, CXL_VARIABLE_PAYLOAD, 0), @@ -708,6 +709,26 @@ int cxl_enumerate_cmds(struct cxl_dev_state *cxlds) } EXPORT_SYMBOL_NS_GPL(cxl_enumerate_cmds, CXL); +static int cxl_clear_event_record(struct cxl_dev_state *cxlds, + enum cxl_event_log_type log, + __le16 handle) +{ + struct cxl_mbox_clear_event_payload payload; + int rc; + + memset(&payload, 0, sizeof(payload)); + payload.event_log = log; + payload.nr_recs = 1; + payload.handle = handle; + + rc = cxl_mbox_send_cmd(cxlds, CXL_MBOX_OP_CLEAR_EVENT_RECORD, + &payload, sizeof(payload), NULL, 0); + if (rc) + return rc; + + return 0; +} + static int cxl_mem_get_records_log(struct cxl_dev_state *cxlds, enum cxl_event_log_type type) { @@ -725,9 +746,12 @@ static int cxl_mem_get_records_log(struct cxl_dev_state *cxlds, return rc; record_count = le16_to_cpu(payload.record_count); - if (record_count > 0) + if (record_count > 0) { trace_cxl_event(dev_name(cxlds->dev), type, &payload.record); + cxl_clear_event_record(cxlds, type, + payload.record.hdr.handle); + } if (payload.flags & CXL_GET_EVENT_FLAG_OVERFLOW) trace_cxl_event_overflow(dev_name(cxlds->dev), type, @@ -742,10 +766,11 @@ static int cxl_mem_get_records_log(struct cxl_dev_state *cxlds, * cxl_mem_get_event_records - Get Event Records from the device * @cxlds: The device data for the operation * - * Retrieve all event records available on the device and report them as trace - * events. + * Retrieve all event records available on the device, report them as trace + * events, and clear them. * * See CXL v3.0 @8.2.9.2.2 Get Event Records + * See CXL v3.0 @8.2.9.2.3 Clear Event Records */ void cxl_mem_get_event_records(struct cxl_dev_state *cxlds) { diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index f83634f3bc8d..5506e7210cf6 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -255,6 +255,7 @@ enum cxl_opcode { CXL_MBOX_OP_INVALID = 0x0000, CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, + CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, CXL_MBOX_OP_GET_FW_INFO = 0x0200, CXL_MBOX_OP_ACTIVATE_FW = 0x0202, CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, @@ -387,6 +388,20 @@ static inline char *cxl_event_log_type_str(enum cxl_event_log_type type) return ""; } +/* + * Clear Event Records input payload + * CXL v3.0 section 8.2.9.2.3; Table 8-51 + * + * Space given for 1 record + */ +struct cxl_mbox_clear_event_payload { + u8 event_log; /* enum cxl_event_log_type */ + u8 clear_flags; + u8 nr_recs; /* 1 for this struct */ + u8 reserved[3]; + __le16 handle; +}; + struct cxl_mbox_get_partition_info { __le64 active_volatile_cap; __le64 active_persistent_cap; diff --git a/include/uapi/linux/cxl_mem.h b/include/uapi/linux/cxl_mem.h index 70459be5bdd4..7c1ad8062792 100644 --- a/include/uapi/linux/cxl_mem.h +++ b/include/uapi/linux/cxl_mem.h @@ -25,6 +25,7 @@ ___C(RAW, "Raw device command"), \ ___C(GET_SUPPORTED_LOGS, "Get Supported Logs"), \ ___C(GET_EVENT_RECORD, "Get Event Record"), \ + ___C(CLEAR_EVENT_RECORD, "Clear Event Record"), \ ___C(GET_FW_INFO, "Get FW Info"), \ ___C(GET_PARTITION_INFO, "Get Partition Information"), \ ___C(GET_LSA, "Get Label Storage Area"), \ From patchwork Sat Aug 13 05:32:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12942683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2AB2C3F6B0 for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10437"; a="292999046" X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="292999046" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:49 -0700 X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="695472746" Received: from jchen8-mobl.amr.corp.intel.com (HELO localhost) ([10.212.10.85]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:48 -0700 From: ira.weiny@intel.com To: Dan Williams Cc: Ira Weiny , Alison Schofield , Vishal Verma , Ben Widawsky , Steven Rostedt , Jonathan Cameron , Davidlohr Bueso , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [RFC PATCH 3/9] cxl/mem: Clear events on driver load Date: Fri, 12 Aug 2022 22:32:37 -0700 Message-Id: <20220813053243.757363-4-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220813053243.757363-1-ira.weiny@intel.com> References: <20220813053243.757363-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny The information contained in the events prior to the driver loading can be queried at any time through other mailbox commands. Ensure a clean slate of events by reading and clearing the events. The events are sent to the trace buffer but it is not anticipated to have anyone listening to it at driver load time. Signed-off-by: Ira Weiny --- drivers/cxl/pci.c | 2 ++ tools/testing/cxl/test/mem.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index faeb5d9d7a7a..5f1b492bd388 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -498,6 +498,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); + cxl_mem_get_event_records(cxlds); + if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) rc = devm_cxl_add_nvdimm(&pdev->dev, cxlmd); diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index aa2df3a15051..e2f5445d24ff 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -285,6 +285,8 @@ static int cxl_mock_mem_probe(struct platform_device *pdev) if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); + cxl_mem_get_event_records(cxlds); + if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) rc = devm_cxl_add_nvdimm(dev, cxlmd); From patchwork Sat Aug 13 05:32:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12942684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D2B0C25B0F for ; Sat, 13 Aug 2022 05:32:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236835AbiHMFcx (ORCPT ); Sat, 13 Aug 2022 01:32:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234527AbiHMFcu (ORCPT ); Sat, 13 Aug 2022 01:32:50 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C286EDF9E; Fri, 12 Aug 2022 22:32:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660368769; x=1691904769; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t1CKHupjLSzcqL9IntpBMboL/6n3rDuduL1KykS+0jI=; b=jdkvSmV2lLvjPmOFfozgpEfmr0K9uWsdQwHecl0lkGHg7/LQMi0+KaA0 c/m24Rk/NnlAi+VSwPvhftaDV7uAQ8FYt69n6Jsh+PMBEIM3Ps+KBQ+1u 8W68luphinkOEVScxHPTIVkR9ds7pRQTvnJRe6vwNkZOaI+/GF1dYYdM0 nFPpdmSZr0w5FlkfRzoLdaaHH1qS2bVJLmltryLxewS7ZfWMP4ZAN8dhG 6R1bqV50AZZmdPGbgM48J7vMtkkY9O5lTbwe/SxMtf+ZTQ1xb7SeECkay oj548oqqYdHUTmGzJDSIJT+cobtI2DJwrASy8AR9Pz0IfvAEgIbvOwrZq g==; X-IronPort-AV: E=McAfee;i="6400,9594,10437"; a="317706338" X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="317706338" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:49 -0700 X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="609456059" Received: from jchen8-mobl.amr.corp.intel.com (HELO localhost) ([10.212.10.85]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:49 -0700 From: ira.weiny@intel.com To: Dan Williams Cc: Ira Weiny , Alison Schofield , Vishal Verma , Ben Widawsky , Steven Rostedt , Jonathan Cameron , Davidlohr Bueso , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [RFC PATCH 4/9] cxl/mem: Trace General Media Event Record Date: Fri, 12 Aug 2022 22:32:38 -0700 Message-Id: <20220813053243.757363-5-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220813053243.757363-1-ira.weiny@intel.com> References: <20220813053243.757363-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny CXL v3.0 section 8.2.9.2.1.1 defines the General Media Event Record. Determine if the event read is a general media record and if so trace the record. Signed-off-by: Ira Weiny --- A couple of specification questions I've had. 1) The component id is not specified as a UUID or any particular format. It is therefore reported as a byte array. Is this intentional? 2) This record has a very odd byte layout with a 16 bit field (validity_flags) landing on a 3 byte boundary and a 3 byte bit field (device) landing on a 7 byte boundary. I've made my best guess as to how the endianess of these fields should be resolved. But I'm happy to hear from other folks if what I have done is wrong. struct cxl_evt_gen_media { struct cxl_event_record_hdr hdr; __le64 phys_addr; u8 descriptor; u8 type; u8 transaction_type; u16 validity_flags; /* ??? */ u8 channel; u8 rank; u8 device[CXL_EVT_GEN_MED_DEV_SIZE]; /* ??? */ u8 component_id[CXL_EVT_GEN_MED_COMP_ID_SIZE]; } __packed; --- drivers/cxl/core/mbox.c | 30 ++++++- drivers/cxl/cxlmem.h | 19 +++++ include/trace/events/cxl-events.h | 125 ++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index 493f5ceb5d1c..0e433f072163 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -709,6 +709,32 @@ int cxl_enumerate_cmds(struct cxl_dev_state *cxlds) } EXPORT_SYMBOL_NS_GPL(cxl_enumerate_cmds, CXL); +/* + * General Media Event Record + * CXL v3.0 Section 8.2.9.2.1.1; Table 8-43 + */ +static const uuid_t gen_media_event_uuid = + UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, + 0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6); + +static void cxl_trace_event_record(const char *dev_name, + enum cxl_event_log_type type, + struct cxl_get_event_payload *payload) +{ + uuid_t *id = &payload->record.hdr.id; + + if (uuid_equal(id, &gen_media_event_uuid)) { + struct cxl_evt_gen_media *rec = + (struct cxl_evt_gen_media *)&payload->record; + + trace_cxl_gen_media_event(dev_name, type, rec); + return; + } + + /* For unknown record types print just the header */ + trace_cxl_event(dev_name, type, &payload->record); +} + static int cxl_clear_event_record(struct cxl_dev_state *cxlds, enum cxl_event_log_type log, __le16 handle) @@ -747,8 +773,8 @@ static int cxl_mem_get_records_log(struct cxl_dev_state *cxlds, record_count = le16_to_cpu(payload.record_count); if (record_count > 0) { - trace_cxl_event(dev_name(cxlds->dev), type, - &payload.record); + cxl_trace_event_record(dev_name(cxlds->dev), type, + &payload); cxl_clear_event_record(cxlds, type, payload.record.hdr.handle); } diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 5506e7210cf6..33669459ae4b 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -402,6 +402,25 @@ struct cxl_mbox_clear_event_payload { __le16 handle; }; +/* + * General Media Event Record + * CXL v3.0 Section 8.2.9.2.1.1; Table 8-43 + */ +#define CXL_EVT_GEN_MED_DEV_SIZE 3 +#define CXL_EVT_GEN_MED_COMP_ID_SIZE 0x10 +struct cxl_evt_gen_media { + struct cxl_event_record_hdr hdr; + __le64 phys_addr; + u8 descriptor; + u8 type; + u8 transaction_type; + u16 validity_flags; + u8 channel; + u8 rank; + u8 device[CXL_EVT_GEN_MED_DEV_SIZE]; + u8 component_id[CXL_EVT_GEN_MED_COMP_ID_SIZE]; +} __packed; + struct cxl_mbox_get_partition_info { __le64 active_volatile_cap; __le64 active_persistent_cap; diff --git a/include/trace/events/cxl-events.h b/include/trace/events/cxl-events.h index f4baeae66cf3..b51c51fd4e62 100644 --- a/include/trace/events/cxl-events.h +++ b/include/trace/events/cxl-events.h @@ -119,6 +119,131 @@ TRACE_EVENT(cxl_event, ) ); +/* + * General Media Event Record - GMER + * CXL v2.0 Section 8.2.9.1.1.1; Table 154 + */ +#define CXL_GMER_PHYS_ADDR_VOLATILE BIT(0) +#define CXL_GMER_PHYS_ADDR_MASK 0x3f + +#define CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT BIT(0) +#define CXL_GMER_EVT_DESC_THRESHOLD_EVENT BIT(1) +#define CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW BIT(2) +#define show_event_desc_flags(flags) __print_flags(flags, "|", \ + { CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT, "Uncorrectable Event" }, \ + { CXL_GMER_EVT_DESC_THRESHOLD_EVENT, "Threshold event" }, \ + { CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW, "Poison List Overflow" } \ +) + +#define CXL_GMER_MEM_EVT_TYPE_ECC_ERROR 0x00 +#define CXL_GMER_MEM_EVT_TYPE_INV_ADDR 0x01 +#define CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x02 +#define show_mem_event_type(type) __print_symbolic(type, \ + { CXL_GMER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \ + { CXL_GMER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \ + { CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" } \ +) + +#define CXL_GMER_TRANS_UNKNOWN 0x00 +#define CXL_GMER_TRANS_HOST_READ 0x01 +#define CXL_GMER_TRANS_HOST_WRITE 0x02 +#define CXL_GMER_TRANS_HOST_SCAN_MEDIA 0x03 +#define CXL_GMER_TRANS_HOST_INJECT_POISON 0x04 +#define CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB 0x05 +#define CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT 0x06 +#define show_trans_type(type) __print_symbolic(type, \ + { CXL_GMER_TRANS_UNKNOWN, "Unknown" }, \ + { CXL_GMER_TRANS_HOST_READ, "Host Read" }, \ + { CXL_GMER_TRANS_HOST_WRITE, "Host Write" }, \ + { CXL_GMER_TRANS_HOST_SCAN_MEDIA, "Host Scan Media" }, \ + { CXL_GMER_TRANS_HOST_INJECT_POISON, "Host Inject Poison" }, \ + { CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, "Internal Media Scrub" }, \ + { CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT, "Internal Media Management" } \ +) + +#define CXL_GMER_VALID_CHANNEL BIT(0) +#define CXL_GMER_VALID_RANK BIT(1) +#define CXL_GMER_VALID_DEVICE BIT(2) +#define CXL_GMER_VALID_COMPONENT BIT(3) +#define show_valid_flags(flags) __print_flags(flags, "|", \ + { CXL_GMER_VALID_CHANNEL, "CHANNEL" }, \ + { CXL_GMER_VALID_RANK, "RANK" }, \ + { CXL_GMER_VALID_DEVICE, "DEVICE" }, \ + { CXL_GMER_VALID_COMPONENT, "COMPONENT" } \ +) + +TRACE_EVENT(cxl_gen_media_event, + + TP_PROTO(const char *dev_name, enum cxl_event_log_type log, + struct cxl_evt_gen_media *rec), + + TP_ARGS(dev_name, log, rec), + + TP_STRUCT__entry( + /* Common */ + __string(dev_name, dev_name) + __field(int, log) + __array(u8, id, UUID_SIZE) + __field(u32, flags) + __field(u16, handle) + __field(u16, related_handle) + __field(u64, timestamp) + + /* General Media */ + __field(u64, phys_addr) + __field(u8, descriptor) + __field(u8, type) + __field(u8, transaction_type) + __field(u8, channel) + __field(u32, device) + __array(u8, comp_id, CXL_EVT_GEN_MED_COMP_ID_SIZE) + __field(u16, validity_flags) + __field(u8, rank) /* Out of order to pack trace record */ + ), + + TP_fast_assign( + /* Common */ + __assign_str(dev_name, dev_name); + memcpy(__entry->id, &rec->hdr.id, UUID_SIZE); + __entry->log = log; + __entry->flags = le32_to_cpu(rec->hdr.flags_length) >> 8; + __entry->handle = le16_to_cpu(rec->hdr.handle); + __entry->related_handle = le16_to_cpu(rec->hdr.related_handle); + __entry->timestamp = le64_to_cpu(rec->hdr.timestamp); + + /* General Media */ + __entry->phys_addr = le64_to_cpu(rec->phys_addr); + __entry->descriptor = rec->descriptor; + __entry->type = rec->type; + __entry->transaction_type = rec->transaction_type; + __entry->channel = rec->channel; + __entry->rank = rec->rank; + __entry->device = rec->device[0] << 24 | + rec->device[1] << 16 | + rec->device[2] << 8; /* 3 byte LE ? */ + __entry->device = le32_to_cpu(__entry->device); + memcpy(__entry->comp_id, &rec->component_id, + CXL_EVT_GEN_MED_COMP_ID_SIZE); + __entry->validity_flags = le16_to_cpu(rec->validity_flags); + ), + + TP_printk("%s: %s time=%llu id=%pUl handle=%x related_handle=%x hdr_flags='%s': " \ + "phys_addr=%llx volatile=%s desc='%s' type='%s' trans_type='%s' channel=%u " \ + "rank=%u device=%x comp_id=%s valid_flags='%s'", + __get_str(dev_name), show_log_type(__entry->log), + __entry->timestamp, __entry->id, __entry->handle, + __entry->related_handle, show_hdr_flags(__entry->flags), + __entry->phys_addr & ~CXL_GMER_PHYS_ADDR_MASK, + (__entry->phys_addr & CXL_GMER_PHYS_ADDR_VOLATILE) ? "TRUE" : "FALSE", + show_event_desc_flags(__entry->descriptor), + show_mem_event_type(__entry->type), + show_trans_type(__entry->transaction_type), + __entry->channel, __entry->rank, __entry->device, + __print_hex(__entry->comp_id, CXL_EVT_GEN_MED_COMP_ID_SIZE), + show_valid_flags(__entry->validity_flags) + ) +); + #endif /* _CXL_TRACE_EVENTS_H */ /* This part must be outside protection */ From patchwork Sat Aug 13 05:32:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12942687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C2D5C282E7 for ; Sat, 13 Aug 2022 05:32:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237447AbiHMFcz (ORCPT ); Sat, 13 Aug 2022 01:32:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236829AbiHMFcx (ORCPT ); Sat, 13 Aug 2022 01:32:53 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11AF0EE0B; Fri, 12 Aug 2022 22:32:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660368772; x=1691904772; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KS09Ureev+x8AiPXriOsrbPJglvnTPySNu4gk0iotoU=; b=VeR5SpTT2dwQTg7ZpsWuCYQIyVGw0GXXSbA1ehgOB8elOzf1SRueX1PK 1wDe8BIaQTBoGIL1+TzkFSOVyH5GyWJk9sYYfvQHcbL03mPB4Cay7wMNS QF5mSWsvXXDR1MaHIIG48aF0u/N/ckK38eIVc3SAmc2SqEBLD4wJHLX2r ypBFpUxPHlNdaXbayVRN6FTtNyANFJU8dlTgmpmPuu9PRmprgXL98U7le d9pYgpdpnwhxK7SOGIqiMjqcEe7sn0ViLyxKCSLSYoHN78Pwdrfhn8O7f ywHt0oAuwAl15BI1iPXVhk8UAGAbNnMKYWBhZFkMqZZvj9irHEHqXOcKH w==; X-IronPort-AV: E=McAfee;i="6400,9594,10437"; a="278684321" X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="278684321" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:51 -0700 X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="674310980" Received: from jchen8-mobl.amr.corp.intel.com (HELO localhost) ([10.212.10.85]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:49 -0700 From: ira.weiny@intel.com To: Dan Williams Cc: Ira Weiny , Alison Schofield , Vishal Verma , Ben Widawsky , Steven Rostedt , Jonathan Cameron , Davidlohr Bueso , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [RFC PATCH 5/9] cxl/mem: Trace DRAM Event Record Date: Fri, 12 Aug 2022 22:32:39 -0700 Message-Id: <20220813053243.757363-6-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220813053243.757363-1-ira.weiny@intel.com> References: <20220813053243.757363-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny CXL v3.0 section 8.2.9.2.1.2 defines the DRAM Event Record. Determine if the event read is a DRAM event record and if so trace the record. Signed-off-by: Ira Weiny --- This record has a very odd byte layout with 2 - 16 bit fields (validity_flags and column) aligned on an odd byte boundary. In addition nibble_mask and row are oddly aligned. I've made my best guess as to how the endianess of these fields should be resolved. But I'm happy to hear from other folks if what I have is wrong. struct cxl_evt_dram_rec { struct cxl_event_record_hdr hdr; __le64 phys_addr; u8 descriptor; u8 type; u8 transaction_type; u16 validity_flags; u8 channel; u8 rank; u8 nibble_mask[CXL_EVT_DER_NIBBLE_MASK_SIZE]; u8 bank_group; u8 bank; u8 row[CXL_EVT_DER_ROW_SIZE]; u16 column; u8 correction_mask[CXL_EVT_DER_CORRECTION_MASK_SIZE]; } __packed; --- drivers/cxl/core/mbox.c | 16 +++++ drivers/cxl/cxlmem.h | 24 +++++++ include/trace/events/cxl-events.h | 114 ++++++++++++++++++++++++++++++ 3 files changed, 154 insertions(+) diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index 0e433f072163..6414588a3c7b 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -717,6 +717,14 @@ static const uuid_t gen_media_event_uuid = UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6); +/* + * DRAM Event Record + * CXL v3.0 section 8.2.9.2.1.2; Table 8-44 + */ +static const uuid_t dram_event_uuid = + UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, + 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24); + static void cxl_trace_event_record(const char *dev_name, enum cxl_event_log_type type, struct cxl_get_event_payload *payload) @@ -731,6 +739,14 @@ static void cxl_trace_event_record(const char *dev_name, return; } + if (uuid_equal(id, &dram_event_uuid)) { + struct cxl_evt_dram_rec *rec = + (struct cxl_evt_dram_rec *)&payload->record; + + trace_cxl_dram_event(dev_name, type, rec); + return; + } + /* For unknown record types print just the header */ trace_cxl_event(dev_name, type, &payload->record); } diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 33669459ae4b..50536c0a7850 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -421,6 +421,30 @@ struct cxl_evt_gen_media { u8 component_id[CXL_EVT_GEN_MED_COMP_ID_SIZE]; } __packed; +/* + * DRAM Event Record - DER + * CXL v3.0 section 8.2.9.2.1.2; Table 3-44 + */ +#define CXL_EVT_DER_NIBBLE_MASK_SIZE 3 +#define CXL_EVT_DER_ROW_SIZE 3 +#define CXL_EVT_DER_CORRECTION_MASK_SIZE 0x20 +struct cxl_evt_dram_rec { + struct cxl_event_record_hdr hdr; + __le64 phys_addr; + u8 descriptor; + u8 type; + u8 transaction_type; + u16 validity_flags; + u8 channel; + u8 rank; + u8 nibble_mask[CXL_EVT_DER_NIBBLE_MASK_SIZE]; + u8 bank_group; + u8 bank; + u8 row[CXL_EVT_DER_ROW_SIZE]; + u16 column; + u8 correction_mask[CXL_EVT_DER_CORRECTION_MASK_SIZE]; +} __packed; + struct cxl_mbox_get_partition_info { __le64 active_volatile_cap; __le64 active_persistent_cap; diff --git a/include/trace/events/cxl-events.h b/include/trace/events/cxl-events.h index b51c51fd4e62..db9b34ddd240 100644 --- a/include/trace/events/cxl-events.h +++ b/include/trace/events/cxl-events.h @@ -244,6 +244,120 @@ TRACE_EVENT(cxl_gen_media_event, ) ); +/* + * DRAM Event Record - DER + * + * CXL v2.0 section 8.2.9.1.1.2; Table 155 + */ +/* + * DRAM Event Record defines many fields the same as the General Media Event + * Record. Reuse those definitions as appropriate. + */ +#define CXL_DER_VALID_CHANNEL BIT(0) +#define CXL_DER_VALID_RANK BIT(1) +#define CXL_DER_VALID_NIBBLE BIT(2) +#define CXL_DER_VALID_BANK_GROUP BIT(3) +#define CXL_DER_VALID_BANK BIT(4) +#define CXL_DER_VALID_ROW BIT(5) +#define CXL_DER_VALID_COLUMN BIT(6) +#define CXL_DER_VALID_CORRECTION_MASK BIT(7) +#define show_dram_valid_flags(flags) __print_flags(flags, "|", \ + { CXL_DER_VALID_CHANNEL, "CHANNEL" }, \ + { CXL_DER_VALID_RANK, "RANK" }, \ + { CXL_DER_VALID_NIBBLE, "NIBBLE" }, \ + { CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \ + { CXL_DER_VALID_BANK, "BANK" }, \ + { CXL_DER_VALID_ROW, "ROW" }, \ + { CXL_DER_VALID_COLUMN, "COLUMN" }, \ + { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" } \ +) + +TRACE_EVENT(cxl_dram_event, + + TP_PROTO(const char *dev_name, enum cxl_event_log_type log, + struct cxl_evt_dram_rec *rec), + + TP_ARGS(dev_name, log, rec), + + TP_STRUCT__entry( + /* Common */ + __string(dev_name, dev_name) + __field(int, log) + __array(u8, id, UUID_SIZE) + __field(u32, flags) + __field(u16, handle) + __field(u16, related_handle) + __field(u64, timestamp) + + /* DRAM */ + __field(u64, phys_addr) + __field(u8, descriptor) + __field(u8, type) + __field(u8, transaction_type) + __field(u8, channel) + __field(u16, validity_flags) + __field(u16, column) /* Out of order to pack trace record */ + __field(u32, nibble_mask) + __field(u32, row) + __array(u8, cor_mask, CXL_EVT_DER_CORRECTION_MASK_SIZE) + __field(u8, rank) /* Out of order to pack trace record */ + __field(u8, bank_group) /* Out of order to pack trace record */ + __field(u8, bank) /* Out of order to pack trace record */ + ), + + TP_fast_assign( + /* Common */ + __assign_str(dev_name, dev_name); + memcpy(__entry->id, &rec->hdr.id, UUID_SIZE); + __entry->log = log; + __entry->flags = le32_to_cpu(rec->hdr.flags_length) >> 8; + __entry->handle = le16_to_cpu(rec->hdr.handle); + __entry->related_handle = le16_to_cpu(rec->hdr.related_handle); + __entry->timestamp = le64_to_cpu(rec->hdr.timestamp); + + /* DRAM */ + __entry->phys_addr = le64_to_cpu(rec->phys_addr); + __entry->descriptor = rec->descriptor; + __entry->type = rec->type; + __entry->transaction_type = rec->transaction_type; + __entry->validity_flags = le16_to_cpu(rec->validity_flags); + __entry->channel = rec->channel; + __entry->rank = rec->rank; + __entry->nibble_mask = rec->nibble_mask[0] << 24 | + rec->nibble_mask[1] << 16 | + rec->nibble_mask[2] << 8; /* 3 byte LE ? */ + __entry->nibble_mask = le32_to_cpu(__entry->nibble_mask); + __entry->bank_group = rec->bank_group; + __entry->bank = rec->bank; + __entry->row = rec->row[0] << 24 | + rec->row[1] << 16 | + rec->row[2] << 8; /* 3 byte LE ? */ + __entry->row = le32_to_cpu(__entry->row); + __entry->column = le16_to_cpu(rec->column); + memcpy(__entry->cor_mask, &rec->correction_mask, + CXL_EVT_DER_CORRECTION_MASK_SIZE); + ), + + TP_printk("%s: %s time=%llu id=%pUl handle=%x related_handle=%x hdr_flags='%s': " \ + "phys_addr=%llx volatile=%s desc='%s' type='%s' trans_type='%s' channel=%u " \ + "rank=%u nibble_mask=%x bank_group=%u bank=%u row=%u column=%u " \ + "cor_mask=%s valid_flags='%s'", + __get_str(dev_name), show_log_type(__entry->log), + __entry->timestamp, __entry->id, __entry->handle, + __entry->related_handle, show_hdr_flags(__entry->flags), + __entry->phys_addr & ~CXL_GMER_PHYS_ADDR_MASK, + (__entry->phys_addr & CXL_GMER_PHYS_ADDR_VOLATILE) ? "TRUE" : "FALSE", + show_event_desc_flags(__entry->descriptor), + show_mem_event_type(__entry->type), + show_trans_type(__entry->transaction_type), + __entry->channel, __entry->rank, __entry->nibble_mask, + __entry->bank_group, __entry->bank, + __entry->row, __entry->column, + __print_hex(__entry->cor_mask, CXL_EVT_DER_CORRECTION_MASK_SIZE), + show_dram_valid_flags(__entry->validity_flags) + ) +); + #endif /* _CXL_TRACE_EVENTS_H */ /* This part must be outside protection */ From patchwork Sat Aug 13 05:32:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12942685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B3AFC3F6B0 for ; Sat, 13 Aug 2022 05:32:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237115AbiHMFcy (ORCPT ); Sat, 13 Aug 2022 01:32:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233151AbiHMFcv (ORCPT ); Sat, 13 Aug 2022 01:32:51 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1C27EE0B; Fri, 12 Aug 2022 22:32:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660368770; x=1691904770; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D6VnTO6wFUzvwPIr6RrrOgbRnQbphIg09pNi3QgmP+I=; b=Esjb4z22AJXUC2nR1tSch/mbd7lGB/yoW0etkEhwIAlNa2ZG9Q+JL2We OgBKKG9dizIisYXFFiZxb15xS4PxWvVgH/Go2MIRHCm3HeSWFiOE0L4xk SIeq5pZTbEnOQQT/lbM1Elqh+qXtOuhNK0PSIre7eKclPSBRTLBMSxhqV 3KyJCyye3nLKOUAaut/9Tax7TmtezCaLU7p6JLPyz/Rn4SL/xkwAQS4Tk M59LMZBNmMJLrVORNWOmNmN664j8kL6t6RE6hwojuJwXOYwmnyzrgV3VN 6relQe+GUk8y9nbT8ShdaLeCkTaz+JQlE5wgMRiNmiaQzEry/XpL8nCqe A==; X-IronPort-AV: E=McAfee;i="6400,9594,10437"; a="317706339" X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="317706339" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:50 -0700 X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="609456066" Received: from jchen8-mobl.amr.corp.intel.com (HELO localhost) ([10.212.10.85]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:50 -0700 From: ira.weiny@intel.com To: Dan Williams Cc: Ira Weiny , Alison Schofield , Vishal Verma , Ben Widawsky , Steven Rostedt , Jonathan Cameron , Davidlohr Bueso , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [RFC PATCH 6/9] cxl/mem: Trace Memory Module Event Record Date: Fri, 12 Aug 2022 22:32:40 -0700 Message-Id: <20220813053243.757363-7-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220813053243.757363-1-ira.weiny@intel.com> References: <20220813053243.757363-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny CXL v3.0 section 8.2.9.2.1.3 defines the Memory Module Event Record. Determine if the event read is memory module record and if so trace the record. Signed-off-by: Ira Weiny --- drivers/cxl/core/mbox.c | 16 +++ drivers/cxl/cxlmem.h | 25 +++++ include/trace/events/cxl-events.h | 155 ++++++++++++++++++++++++++++++ 3 files changed, 196 insertions(+) diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index 6414588a3c7b..99b09bfeaff5 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -725,6 +725,14 @@ static const uuid_t dram_event_uuid = UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24); +/* + * Memory Module Event Record + * CXL v3.0 section 8.2.9.2.1.3; Table 8-45 + */ +static const uuid_t mem_mod_event_uuid = + UUID_INIT(0xfe927475, 0xdd59, 0x4339, + 0xa5, 0x86, 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74); + static void cxl_trace_event_record(const char *dev_name, enum cxl_event_log_type type, struct cxl_get_event_payload *payload) @@ -747,6 +755,14 @@ static void cxl_trace_event_record(const char *dev_name, return; } + if (uuid_equal(id, &mem_mod_event_uuid)) { + struct cxl_evt_mem_mod_rec *rec = + (struct cxl_evt_mem_mod_rec *)&payload->record; + + trace_cxl_mem_mod_event(dev_name, type, rec); + return; + } + /* For unknown record types print just the header */ trace_cxl_event(dev_name, type, &payload->record); } diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 50536c0a7850..a02a41dfd988 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -445,6 +445,31 @@ struct cxl_evt_dram_rec { u8 correction_mask[CXL_EVT_DER_CORRECTION_MASK_SIZE]; } __packed; +/* + * Get Health Info Record + * CXL v3.0 section 8.2.9.8.3.1; Table 8-100 + */ +struct cxl_get_health_info { + u8 health_status; + u8 media_status; + u8 add_status; + u8 life_used; + u16 device_temp; + u32 dirty_shutdown_cnt; + u32 cor_vol_err_cnt; + u32 cor_per_err_cnt; +} __packed; + +/* + * Memory Module Event Record + * CXL v3.0 section 8.2.9.2.1.3; Table 8-45 + */ +struct cxl_evt_mem_mod_rec { + struct cxl_event_record_hdr hdr; + u8 event_type; + struct cxl_get_health_info info; +} __packed; + struct cxl_mbox_get_partition_info { __le64 active_volatile_cap; __le64 active_persistent_cap; diff --git a/include/trace/events/cxl-events.h b/include/trace/events/cxl-events.h index db9b34ddd240..dbbe25fee25c 100644 --- a/include/trace/events/cxl-events.h +++ b/include/trace/events/cxl-events.h @@ -358,6 +358,161 @@ TRACE_EVENT(cxl_dram_event, ) ); +/* + * Memory Module Event Record - MMER + * + * CXL v2.0 section 8.2.9.1.1.3; Table 156, Table 181 + * + * Device Health Information - DHI; Table 181 + */ +#define CXL_MMER_HEALTH_STATUS_CHANGE 0x00 +#define CXL_MMER_MEDIA_STATUS_CHANGE 0x01 +#define CXL_MMER_LIFE_USED_CHANGE 0x02 +#define CXL_MMER_TEMP_CHANGE 0x03 +#define CXL_MMER_DATA_PATH_ERROR 0x04 +#define CXL_MMER_LAS_ERROR 0x05 +#define show_dev_evt_type(type) __print_symbolic(type, \ + { CXL_MMER_HEALTH_STATUS_CHANGE, "Health Status Change" }, \ + { CXL_MMER_MEDIA_STATUS_CHANGE, "Media Status Change" }, \ + { CXL_MMER_LIFE_USED_CHANGE, "Life Used Change" }, \ + { CXL_MMER_TEMP_CHANGE, "Temperature Change" }, \ + { CXL_MMER_DATA_PATH_ERROR, "Data Path Error" }, \ + { CXL_MMER_LAS_ERROR, "LSA Error" } \ +) + +#define CXL_DHI_HS_MAINTENANCE_NEEDED BIT(0) +#define CXL_DHI_HS_PERFORMANCE_DEGRADED BIT(1) +#define CXL_DHI_HS_HW_REPLACEMENT_NEEDED BIT(2) +#define show_health_status_flags(flags) __print_flags(flags, "|", \ + { CXL_DHI_HS_MAINTENANCE_NEEDED, "Maintenance Needed" }, \ + { CXL_DHI_HS_PERFORMANCE_DEGRADED, "Performance Degraded" }, \ + { CXL_DHI_HS_HW_REPLACEMENT_NEEDED, "Replacement Needed" } \ +) + +#define CXL_DHI_MS_NORMAL 0x00 +#define CXL_DHI_MS_NOT_READY 0x01 +#define CXL_DHI_MS_WRITE_PERSISTENCY_LOST 0x02 +#define CXL_DHI_MS_ALL_DATA_LOST 0x03 +#define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS 0x04 +#define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN 0x05 +#define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT 0x06 +#define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS 0x07 +#define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN 0x08 +#define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT 0x09 +#define show_media_status(ms) __print_symbolic(ms, \ + { CXL_DHI_MS_NORMAL, \ + "Normal" }, \ + { CXL_DHI_MS_NOT_READY, \ + "Not Ready" }, \ + { CXL_DHI_MS_WRITE_PERSISTENCY_LOST, \ + "Write Persistency Lost" }, \ + { CXL_DHI_MS_ALL_DATA_LOST, \ + "All Data Lost" }, \ + { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS, \ + "Write Persistency Loss in the Event of Power Loss" }, \ + { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN, \ + "Write Persistency Loss in Event of Shutdown" }, \ + { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT, \ + "Write Persistency Loss Imminent" }, \ + { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS, \ + "All Data Loss in Event of Power Loss" }, \ + { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN, \ + "All Data loss in the Event of Shutdown" }, \ + { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT, \ + "All Data Loss Imminent" } \ +) + +#define CXL_DHI_AS_NORMAL 0x0 +#define CXL_DHI_AS_WARNING 0x1 +#define CXL_DHI_AS_CRITICAL 0x2 +#define show_add_status(as) __print_symbolic(as, \ + { CXL_DHI_AS_NORMAL, "Normal" }, \ + { CXL_DHI_AS_WARNING, "Warning" }, \ + { CXL_DHI_AS_CRITICAL, "Critical" } \ +) + +#define CXL_DHI_AS_LIFE_USED(as) (as & 0x3) +#define CXL_DHI_AS_DEV_TEMP(as) ((as & 0xC) >> 2) +#define CXL_DHI_AS_COR_VOL_ERR_CNT(as) ((as & 0x10) >> 4) +#define CXL_DHI_AS_COR_PER_ERR_CNT(as) ((as & 0x20) >> 5) + +TRACE_EVENT(cxl_mem_mod_event, + + TP_PROTO(const char *dev_name, enum cxl_event_log_type log, + struct cxl_evt_mem_mod_rec *rec), + + TP_ARGS(dev_name, log, rec), + + TP_STRUCT__entry( + /* Common */ + __string(dev_name, dev_name) + __field(int, log) + __array(u8, id, UUID_SIZE) + __field(u32, flags) + __field(u16, handle) + __field(u16, related_handle) + __field(u64, timestamp) + + /* Memory Module Event */ + __field(u8, event_type) + + /* Device Health Info */ + __field(u8, health_status) + __field(u8, media_status) + __field(u8, life_used) + __field(u32, dirty_shutdown_cnt) + __field(u32, cor_vol_err_cnt) + __field(u32, cor_per_err_cnt) + __field(s16, device_temp) + __field(u8, add_status) + ), + + TP_fast_assign( + /* Common */ + __assign_str(dev_name, dev_name); + memcpy(__entry->id, &rec->hdr.id, UUID_SIZE); + __entry->log = log; + __entry->flags = le32_to_cpu(rec->hdr.flags_length) >> 8; + __entry->handle = le16_to_cpu(rec->hdr.handle); + __entry->related_handle = le16_to_cpu(rec->hdr.related_handle); + __entry->timestamp = le64_to_cpu(rec->hdr.timestamp); + + /* Memory Module Event */ + __entry->event_type = rec->event_type; + + /* Device Health Info */ + __entry->health_status = rec->info.health_status; + __entry->media_status = rec->info.media_status; + __entry->life_used = rec->info.life_used; + __entry->dirty_shutdown_cnt = le32_to_cpu(rec->info.dirty_shutdown_cnt); + __entry->cor_vol_err_cnt = le32_to_cpu(rec->info.cor_vol_err_cnt); + __entry->cor_per_err_cnt = le32_to_cpu(rec->info.cor_per_err_cnt); + __entry->device_temp = le16_to_cpu(rec->info.device_temp); + __entry->add_status = rec->info.add_status; + ), + + TP_printk("%s: %s time=%llu id=%pUl handle=%x related_handle=%x hdr_flags='%s': " \ + "evt_type='%s' health_status='%s' media_status='%s' as_life_used=%s " \ + "as_dev_temp=%s as_cor_vol_err_cnt=%s as_cor_per_err_cnt=%s " \ + "life_used=%u dev_temp=%d dirty_shutdown_cnt=%u cor_vol_err_cnt=%u " \ + "cor_per_err_cnt=%u", + __get_str(dev_name), show_log_type(__entry->log), + __entry->timestamp, __entry->id, __entry->handle, + __entry->related_handle, show_hdr_flags(__entry->flags), + + show_dev_evt_type(__entry->event_type), + show_health_status_flags(__entry->health_status), + show_media_status(__entry->media_status), + show_add_status(CXL_DHI_AS_LIFE_USED(__entry->add_status)), + show_add_status(CXL_DHI_AS_DEV_TEMP(__entry->add_status)), + show_add_status(CXL_DHI_AS_COR_VOL_ERR_CNT(__entry->add_status)), + show_add_status(CXL_DHI_AS_COR_PER_ERR_CNT(__entry->add_status)), + __entry->life_used, __entry->device_temp, + __entry->dirty_shutdown_cnt, __entry->cor_vol_err_cnt, + __entry->cor_per_err_cnt) +); + + #endif /* _CXL_TRACE_EVENTS_H */ /* This part must be outside protection */ From patchwork Sat Aug 13 05:32:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12942686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BC7DC28B2B for ; Sat, 13 Aug 2022 05:32:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237375AbiHMFcy (ORCPT ); Sat, 13 Aug 2022 01:32:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236678AbiHMFcx (ORCPT ); Sat, 13 Aug 2022 01:32:53 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 015D615FE2; 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d="scan'208";a="709235717" Received: from jchen8-mobl.amr.corp.intel.com (HELO localhost) ([10.212.10.85]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:51 -0700 From: ira.weiny@intel.com To: Dan Williams Cc: Ira Weiny , Alison Schofield , Vishal Verma , Ben Widawsky , Steven Rostedt , Jonathan Cameron , Davidlohr Bueso , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [RFC PATCH 7/9] cxl/test: Add generic mock events Date: Fri, 12 Aug 2022 22:32:41 -0700 Message-Id: <20220813053243.757363-8-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220813053243.757363-1-ira.weiny@intel.com> References: <20220813053243.757363-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny Facilitate testing basic Get/Clear Event functionality by creating multiple logs and generic events with made up UUID's. Data is completely made up with data patterns which should be easy to spot in trace output. Test traces are easy to obtain with a small script such as this: #!/bin/bash -x devices=`find /sys/devices/platform -name cxl_mem*` # Generate fake events if reset is passed in if [ "$1" == "reset" ]; then for device in $devices; do echo 1 > $device/mem*/event_reset done fi # Turn on tracing echo "" > /sys/kernel/tracing/trace echo 1 > /sys/kernel/tracing/events/cxl_events/enable echo 1 > /sys/kernel/tracing/tracing_on # Generate fake interrupt for device in $devices; do echo 1 > $device/mem*/event_trigger # just trigger 1 break; done # Turn off tracing and report events echo 0 > /sys/kernel/tracing/tracing_on cat /sys/kernel/tracing/trace Signed-off-by: Ira Weiny --- tools/testing/cxl/test/mem.c | 291 +++++++++++++++++++++++++++++++++++ 1 file changed, 291 insertions(+) diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index e2f5445d24ff..87196d62acf5 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -9,6 +9,8 @@ #include #include +#include + #define LSA_SIZE SZ_128K #define DEV_SIZE SZ_2G #define EFFECT(x) (1U << x) @@ -137,6 +139,287 @@ static int mock_partition_info(struct cxl_dev_state *cxlds, return 0; } +/* + * Mock Events + */ +struct mock_event_log { + int cur_event; + int nr_events; + struct xarray events; +}; + +struct mock_event_store { + struct cxl_dev_state *cxlds; + struct mock_event_log *mock_logs[CXL_EVENT_TYPE_MAX]; +}; + +DEFINE_XARRAY(mock_cxlds_event_store); + +void delete_event_store(void *ds) +{ + xa_store(&mock_cxlds_event_store, (unsigned long)ds, NULL, GFP_KERNEL); +} + +void store_event_store(struct mock_event_store *es) +{ + struct cxl_dev_state *cxlds = es->cxlds; + + if (xa_insert(&mock_cxlds_event_store, (unsigned long)cxlds, es, + GFP_KERNEL)) { + dev_err(cxlds->dev, "Event store not available for %s\n", + dev_name(cxlds->dev)); + return; + } + + devm_add_action_or_reset(cxlds->dev, delete_event_store, cxlds); +} + +struct mock_event_log *find_event_log(struct cxl_dev_state *cxlds, int log_type) +{ + struct mock_event_store *es = xa_load(&mock_cxlds_event_store, + (unsigned long)cxlds); + + if (!es || log_type >= CXL_EVENT_TYPE_MAX) + return NULL; + return es->mock_logs[log_type]; +} + +struct cxl_event_record_raw *get_cur_event(struct mock_event_log *log) +{ + return xa_load(&log->events, log->cur_event); +} + +__le16 get_cur_event_handle(struct mock_event_log *log) +{ + return cpu_to_le16(log->cur_event); +} + +static bool log_empty(struct mock_event_log *log) +{ + return log->cur_event == log->nr_events; +} + +static int log_rec_left(struct mock_event_log *log) +{ + return log->nr_events - log->cur_event; +} + +static void xa_events_destroy(void *l) +{ + struct mock_event_log *log = l; + + xa_destroy(&log->events); +} + +static void event_store_add_event(struct mock_event_store *es, + enum cxl_event_log_type log_type, + struct cxl_event_record_raw *event) +{ + struct mock_event_log *log; + struct device *dev = es->cxlds->dev; + int rc; + + if (log_type >= CXL_EVENT_TYPE_MAX) + return; + + log = es->mock_logs[log_type]; + if (!log) { + log = devm_kzalloc(dev, sizeof(*log), GFP_KERNEL); + if (!log) { + dev_err(dev, "Failed to create %s log\n", + cxl_event_log_type_str(log_type)); + return; + } + xa_init(&log->events); + devm_add_action(dev, xa_events_destroy, log); + es->mock_logs[log_type] = log; + } + + rc = xa_insert(&log->events, log->nr_events, event, GFP_KERNEL); + if (rc) { + dev_err(dev, "Failed to store event %s log\n", + cxl_event_log_type_str(log_type)); + return; + } + log->nr_events++; +} + +/* + * Get and clear event only handle 1 record at a time as this is what is + * currently implemented in the main code. + */ +static int mock_get_event(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) +{ + struct cxl_get_event_payload *pl; + struct mock_event_log *log; + u8 log_type; + + /* Valid request? */ + if (cmd->size_in != 1) + return -EINVAL; + + log_type = *((u8 *)cmd->payload_in); + if (log_type >= CXL_EVENT_TYPE_MAX) + return -EINVAL; + + log = find_event_log(cxlds, log_type); + if (!log || log_empty(log)) + goto no_data; + + /* Don't handle more than 1 record at a time */ + if (cmd->size_out < sizeof(*pl)) + return -EINVAL; + + pl = cmd->payload_out; + memset(pl, 0, sizeof(*pl)); + + pl->record_count = cpu_to_le16(1); + + if (log_rec_left(log) > 1) + pl->flags |= CXL_GET_EVENT_FLAG_MORE_RECORDS; + + memcpy(&pl->record, get_cur_event(log), sizeof(pl->record)); + pl->record.hdr.handle = get_cur_event_handle(log); + return 0; + +no_data: + /* Room for header? */ + if (cmd->size_out < (sizeof(*pl) - sizeof(pl->record))) + return -EINVAL; + + memset(cmd->payload_out, 0, cmd->size_out); + return 0; +} + +/* + * Get and clear event only handle 1 record at a time as this is what is + * currently implemented in the main code. + */ +static int mock_clear_event(struct cxl_dev_state *cxlds, + struct cxl_mbox_cmd *cmd) +{ + struct cxl_mbox_clear_event_payload *pl = cmd->payload_in; + struct mock_event_log *log; + u8 log_type = pl->event_log; + + /* Don't handle more than 1 record at a time */ + if (pl->nr_recs != 1) + return -EINVAL; + + if (log_type >= CXL_EVENT_TYPE_MAX) + return -EINVAL; + + log = find_event_log(cxlds, log_type); + if (!log) + return 0; /* No mock data in this log */ + + /* + * The current code clears events as they are read + * Test that behavior; not clearning from the middle of the log + */ + if (log->cur_event != le16_to_cpu(pl->handle)) { + dev_err(cxlds->dev, "Clearing events out of order\n"); + return -EINVAL; + } + + log->cur_event++; + return 0; +} + +static ssize_t event_reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cxl_memdev *cxlmd = container_of(dev, struct cxl_memdev, dev); + int i; + + for (i = CXL_EVENT_TYPE_INFO; i < CXL_EVENT_TYPE_MAX; i++) { + struct mock_event_log *log; + + log = find_event_log(cxlmd->cxlds, i); + if (log) + log->cur_event = 0; + } + + return count; +} +static DEVICE_ATTR_WO(event_reset); + +static ssize_t event_trigger_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cxl_memdev *cxlmd = container_of(dev, struct cxl_memdev, dev); + + cxl_mem_get_event_records(cxlmd->cxlds); + + return count; +} +static DEVICE_ATTR_WO(event_trigger); + +static struct attribute *cxl_mock_event_attrs[] = { + &dev_attr_event_reset.attr, + &dev_attr_event_trigger.attr, + NULL +}; +ATTRIBUTE_GROUPS(cxl_mock_event); + +void remove_mock_event_groups(void *dev) +{ + device_remove_groups(dev, cxl_mock_event_groups); +} + +struct cxl_event_record_raw maint_needed = { + .hdr = { + .id = UUID_INIT(0xDEADBEEF, 0xCAFE, 0xBABE, 0xa5, 0x5a, 0xa5, 0x5a, 0xa5, 0xa5, 0x5a, 0xa5), + .flags_length = cpu_to_le32((CXL_EVENT_RECORD_FLAG_MAINT_NEEDED << 8) | + sizeof(struct cxl_event_record_raw)), + /* .handle = Set dynamically */ + .related_handle = cpu_to_le16(0xa5b6), + }, + .data = { 0xDE, 0xAD, 0xBE, 0xEF }, +}; + +struct cxl_event_record_raw hardware_replace = { + .hdr = { + .id = UUID_INIT(0xBABECAFE, 0xBEEF, 0xDEAD, 0xa5, 0x5a, 0xa5, 0x5a, 0xa5, 0xa5, 0x5a, 0xa5), + .flags_length = cpu_to_le32((CXL_EVENT_RECORD_FLAG_HW_REPLACE << 8) | + sizeof(struct cxl_event_record_raw)), + /* .handle = Set dynamically */ + .related_handle = cpu_to_le16(0xb6a5), + }, + .data = { 0xDE, 0xAD, 0xBE, 0xEF }, +}; + +static void devm_cxl_mock_event_logs(struct cxl_memdev *cxlmd) +{ + struct device *dev = &cxlmd->dev; + struct mock_event_store *es; + + /* + * The memory device gets the sysfs attributes such that the cxlmd + * pointer can be used to get to a cxlds pointer. + */ + if (device_add_groups(dev, cxl_mock_event_groups)) + return; + if (devm_add_action_or_reset(dev, remove_mock_event_groups, dev)) + return; + + /* + * All the mock event data hangs off the device itself. + */ + es = devm_kzalloc(cxlmd->cxlds->dev, sizeof(*es), GFP_KERNEL); + if (!es) + return; + es->cxlds = cxlmd->cxlds; + + event_store_add_event(es, CXL_EVENT_TYPE_INFO, &maint_needed); + + event_store_add_event(es, CXL_EVENT_TYPE_FATAL, &hardware_replace); + + store_event_store(es); +} + static int mock_get_lsa(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) { struct cxl_mbox_get_lsa *get_lsa = cmd->payload_in; @@ -224,6 +507,12 @@ static int cxl_mock_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd * case CXL_MBOX_OP_GET_PARTITION_INFO: rc = mock_partition_info(cxlds, cmd); break; + case CXL_MBOX_OP_GET_EVENT_RECORD: + rc = mock_get_event(cxlds, cmd); + break; + case CXL_MBOX_OP_CLEAR_EVENT_RECORD: + rc = mock_clear_event(cxlds, cmd); + break; case CXL_MBOX_OP_SET_LSA: rc = mock_set_lsa(cxlds, cmd); break; @@ -285,6 +574,8 @@ static int cxl_mock_mem_probe(struct platform_device *pdev) if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); + devm_cxl_mock_event_logs(cxlmd); + cxl_mem_get_event_records(cxlds); if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) From patchwork Sat Aug 13 05:32:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12942688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6C3EC25B0D for ; Sat, 13 Aug 2022 05:32:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233020AbiHMFcz (ORCPT ); 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X-IronPort-AV: E=McAfee;i="6400,9594,10437"; a="292525193" X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="292525193" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:51 -0700 X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="709235721" Received: from jchen8-mobl.amr.corp.intel.com (HELO localhost) ([10.212.10.85]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:51 -0700 From: ira.weiny@intel.com To: Dan Williams Cc: Ira Weiny , Alison Schofield , Vishal Verma , Ben Widawsky , Steven Rostedt , Jonathan Cameron , Davidlohr Bueso , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [RFC PATCH 8/9] cxl/test: Add specific events Date: Fri, 12 Aug 2022 22:32:42 -0700 Message-Id: <20220813053243.757363-9-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220813053243.757363-1-ira.weiny@intel.com> References: <20220813053243.757363-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny Each type of event has different trace point outputs. Add mock General Media Event, DRAM event, and Memory Module Event records to the mock list of events returned. Signed-off-by: Ira Weiny --- tools/testing/cxl/test/mem.c | 70 ++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index 87196d62acf5..c5d7857ae2e5 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -391,6 +391,70 @@ struct cxl_event_record_raw hardware_replace = { .data = { 0xDE, 0xAD, 0xBE, 0xEF }, }; +struct cxl_evt_gen_media gen_media = { + .hdr = { + .id = UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, + 0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6), + .flags_length = cpu_to_le32((CXL_EVENT_RECORD_FLAG_PERMANENT << 8) | + sizeof(struct cxl_evt_gen_media)), + /* .handle = Set dynamically */ + .related_handle = cpu_to_le16(0), + }, + .phys_addr = cpu_to_le64(0x2000), + .descriptor = CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT, + .type = CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, + .transaction_type = CXL_GMER_TRANS_HOST_WRITE, + .validity_flags = cpu_to_le16(CXL_GMER_VALID_CHANNEL | + CXL_GMER_VALID_RANK), + .channel = 1, + .rank = 30 +}; + +struct cxl_evt_dram_rec dram_rec = { + .hdr = { + .id = UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, + 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24), + .flags_length = cpu_to_le32((CXL_EVENT_RECORD_FLAG_PERF_DEGRADED << 8) | + sizeof(struct cxl_evt_dram_rec)), + /* .handle = Set dynamically */ + .related_handle = cpu_to_le16(0), + }, + .phys_addr = cpu_to_le64(0x8000), + .descriptor = CXL_GMER_EVT_DESC_THRESHOLD_EVENT, + .type = CXL_GMER_MEM_EVT_TYPE_INV_ADDR, + .transaction_type = CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, + .validity_flags = cpu_to_le16(CXL_DER_VALID_CHANNEL | + CXL_DER_VALID_BANK_GROUP | + CXL_DER_VALID_BANK | + CXL_DER_VALID_COLUMN), + .channel = 1, + .bank_group = 5, + .bank = 2, + .column = cpu_to_le16(1024) +}; + +struct cxl_evt_mem_mod_rec mem_mod_rec = { + .hdr = { + .id = UUID_INIT(0xfe927475, 0xdd59, 0x4339, + 0xa5, 0x86, 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74), + .flags_length = cpu_to_le32(sizeof(struct cxl_evt_mem_mod_rec)), + /* .handle = Set dynamically */ + .related_handle = cpu_to_le16(0), + }, + .event_type = CXL_MMER_TEMP_CHANGE, + .info = { + .health_status = CXL_DHI_HS_PERFORMANCE_DEGRADED, + .media_status = CXL_DHI_MS_ALL_DATA_LOST, + .add_status = (CXL_DHI_AS_CRITICAL << 2) | + (CXL_DHI_AS_WARNING << 4) | + (CXL_DHI_AS_WARNING << 5), + .device_temp = cpu_to_le16(1000), + .dirty_shutdown_cnt = cpu_to_le32(30000), + .cor_vol_err_cnt = cpu_to_le32(30100), + .cor_per_err_cnt = cpu_to_le32(40100), + } +}; + static void devm_cxl_mock_event_logs(struct cxl_memdev *cxlmd) { struct device *dev = &cxlmd->dev; @@ -414,8 +478,14 @@ static void devm_cxl_mock_event_logs(struct cxl_memdev *cxlmd) es->cxlds = cxlmd->cxlds; event_store_add_event(es, CXL_EVENT_TYPE_INFO, &maint_needed); + event_store_add_event(es, CXL_EVENT_TYPE_INFO, + (struct cxl_event_record_raw *)&gen_media); + event_store_add_event(es, CXL_EVENT_TYPE_INFO, + (struct cxl_event_record_raw *)&mem_mod_rec); event_store_add_event(es, CXL_EVENT_TYPE_FATAL, &hardware_replace); + event_store_add_event(es, CXL_EVENT_TYPE_FATAL, + (struct cxl_event_record_raw *)&dram_rec); store_event_store(es); } From patchwork Sat Aug 13 05:32:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12942689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13D02C2BB41 for ; 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X-IronPort-AV: E=McAfee;i="6400,9594,10437"; a="278684328" X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="278684328" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:52 -0700 X-IronPort-AV: E=Sophos;i="5.93,233,1654585200"; d="scan'208";a="582320729" Received: from jchen8-mobl.amr.corp.intel.com (HELO localhost) ([10.212.10.85]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2022 22:32:52 -0700 From: ira.weiny@intel.com To: Dan Williams Cc: Ira Weiny , Alison Schofield , Vishal Verma , Ben Widawsky , Steven Rostedt , Jonathan Cameron , Davidlohr Bueso , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [RFC PATCH 9/9] cxl/test: Simulate event log overflow Date: Fri, 12 Aug 2022 22:32:43 -0700 Message-Id: <20220813053243.757363-10-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220813053243.757363-1-ira.weiny@intel.com> References: <20220813053243.757363-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny Log overflow is marked by a separate trace message. Simulate a log with lots of messages and flag overflow until it is drained a bit. Signed-off-by: Ira Weiny --- tools/testing/cxl/test/mem.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index c5d7857ae2e5..87e6b10896c9 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -244,6 +244,15 @@ static void event_store_add_event(struct mock_event_store *es, log->nr_events++; } +static u16 log_overflow(struct mock_event_log *log) +{ + int cnt = log_rec_left(log) - 5; + + if (cnt < 0) + return 0; + return cnt; +} + /* * Get and clear event only handle 1 record at a time as this is what is * currently implemented in the main code. @@ -253,6 +262,7 @@ static int mock_get_event(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) struct cxl_get_event_payload *pl; struct mock_event_log *log; u8 log_type; + u16 nr_overflow; /* Valid request? */ if (cmd->size_in != 1) @@ -278,6 +288,20 @@ static int mock_get_event(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) if (log_rec_left(log) > 1) pl->flags |= CXL_GET_EVENT_FLAG_MORE_RECORDS; + nr_overflow = log_overflow(log); + if (nr_overflow) { + u64 ns; + + pl->flags |= CXL_GET_EVENT_FLAG_OVERFLOW; + pl->overflow_err_count = cpu_to_le16(nr_overflow); + ns = ktime_get_real_ns(); + ns -= 5000000000; /* 5s ago */ + pl->first_overflow_timestamp = cpu_to_le64(ns); + ns = ktime_get_real_ns(); + ns -= 1000000000; /* 1s ago */ + pl->last_overflow_timestamp = cpu_to_le64(ns); + } + memcpy(&pl->record, get_cur_event(log), sizeof(pl->record)); pl->record.hdr.handle = get_cur_event_handle(log); return 0; @@ -483,6 +507,18 @@ static void devm_cxl_mock_event_logs(struct cxl_memdev *cxlmd) event_store_add_event(es, CXL_EVENT_TYPE_INFO, (struct cxl_event_record_raw *)&mem_mod_rec); + event_store_add_event(es, CXL_EVENT_TYPE_FAIL, &maint_needed); + event_store_add_event(es, CXL_EVENT_TYPE_FAIL, &hardware_replace); + event_store_add_event(es, CXL_EVENT_TYPE_FAIL, + (struct cxl_event_record_raw *)&dram_rec); + event_store_add_event(es, CXL_EVENT_TYPE_FAIL, + (struct cxl_event_record_raw *)&gen_media); + event_store_add_event(es, CXL_EVENT_TYPE_FAIL, + (struct cxl_event_record_raw *)&mem_mod_rec); + event_store_add_event(es, CXL_EVENT_TYPE_FAIL, &hardware_replace); + event_store_add_event(es, CXL_EVENT_TYPE_FAIL, + (struct cxl_event_record_raw *)&dram_rec); + event_store_add_event(es, CXL_EVENT_TYPE_FATAL, &hardware_replace); event_store_add_event(es, CXL_EVENT_TYPE_FATAL, (struct cxl_event_record_raw *)&dram_rec);