From patchwork Mon Aug 15 06:34:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12943152 Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44ECB1102 for ; Mon, 15 Aug 2022 06:38:34 +0000 (UTC) Received: by mail-pj1-f41.google.com with SMTP id h21-20020a17090aa89500b001f31a61b91dso13615372pjq.4 for ; Sun, 14 Aug 2022 23:38:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=t0lzq9wXtDZalDc+MqW+q/Qr6dM8adTctzXUvTWqjXw=; b=mJZ4VkOcUookg2qKkoDfdsGdAK5ungyXoH75mzIMbXSlD1e3Fb2fu6nmK757mhROgs UNXG+dWaInBvgNqv+PAI8VUaledvrOzwjnAT1UxeYn1iOBTzM/2Htua1MwLDVf1QjVHu CHcv6VV+jVlxAhUX7PsYB7f7OWJCEJiuszq1E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=t0lzq9wXtDZalDc+MqW+q/Qr6dM8adTctzXUvTWqjXw=; b=V5spqppzU36fdFDwnT6AuTuV9SxALNpWBNQf8peoO9vwHydEUTat107JESUVkdNVMN mFYD3yC3X5AbZI92gpAyCOwQbjdLGPlMbeh3RKpbop8vPYHn+s2y1+v5Ff1qcnsb9Aml 9GzFuZhwGOr8O5tfwKmZxF7Iwqo3f7AnlElFi/nvE612K0TgwQUZ+MJIRWRMq3450rTB HVFcmgYSk1bDOqu1U7WcSgBKIJTGXqHHLioOi+m5LBhis6dfD5xx7cVXX2cUtnm69zOU 4+w9EPbSh+W6ayIj/qz3pEFblgff/CfSwGeqIWf/7cnE9yvYhS8FajibbBZeKh11h1DH QVOQ== X-Gm-Message-State: ACgBeo0wwAUcWG9YThs0daOzI24B7sPRdCcZpGBNGzlUU3/TK/haFRo9 Anpnjc9CKh6Tmd7omfUegPP3pPYG/6DE5Q== X-Google-Smtp-Source: AA6agR7lhgSd83SNVI3JVmj+q3jlu0eT7XHkY/HqQvsYT2lX6B8gSJ8NGEu++JfxXrv3C9yGkog63g== X-Received: by 2002:a17:90b:4a05:b0:1f5:62d5:4155 with SMTP id kk5-20020a17090b4a0500b001f562d54155mr17504326pjb.6.1660545513764; Sun, 14 Aug 2022 23:38:33 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.38.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:38:33 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 1/7] platform/chrome: Add Type-C mux set command definitions Date: Mon, 15 Aug 2022 06:34:17 +0000 Message-Id: <20220815063555.1384505-2-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Copy EC header definitions for the USB Type-C Mux control command from the EC code base. Also pull in "TBT_UFP_REPLY" definitions, since that is the prior entry in the enum. These headers are already present in the EC code base. [1] [1] https://chromium.googlesource.com/chromiumos/platform/ec/+/b80f85a94a423273c1638ef7b662c56931a138dd/include/ec_commands.h Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. include/linux/platform_data/cros_ec_commands.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h index 8b1b795867a1..5744a2d746aa 100644 --- a/include/linux/platform_data/cros_ec_commands.h +++ b/include/linux/platform_data/cros_ec_commands.h @@ -5724,8 +5724,21 @@ enum typec_control_command { TYPEC_CONTROL_COMMAND_EXIT_MODES, TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY, + TYPEC_CONTROL_COMMAND_USB_MUX_SET, }; +/* Replies the AP may specify to the TBT EnterMode command as a UFP */ +enum typec_tbt_ufp_reply { + TYPEC_TBT_UFP_REPLY_NAK, + TYPEC_TBT_UFP_REPLY_ACK, +}; + +struct typec_usb_mux_set { + uint8_t mux_index; /* Index of the mux to set in the chain */ + uint8_t mux_flags; /* USB_PD_MUX_*-encoded USB mux state to set */ +} __ec_align1; + struct ec_params_typec_control { uint8_t port; uint8_t command; /* enum typec_control_command */ @@ -5739,6 +5752,8 @@ struct ec_params_typec_control { union { uint32_t clear_events_mask; uint8_t mode_to_enter; /* enum typec_mode */ + uint8_t tbt_ufp_reply; /* enum typec_tbt_ufp_reply */ + struct typec_usb_mux_set mux_params; uint8_t placeholder[128]; }; } __ec_align1; @@ -5817,6 +5832,9 @@ enum tcpc_cc_polarity { #define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) #define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) #define PD_STATUS_EVENT_HARD_RESET BIT(2) +#define PD_STATUS_EVENT_DISCONNECTED BIT(3) +#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4) +#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5) struct ec_params_typec_status { uint8_t port; From patchwork Mon Aug 15 06:34:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12943153 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AAF91102 for ; Mon, 15 Aug 2022 06:40:00 +0000 (UTC) Received: by mail-pl1-f176.google.com with SMTP id y1so5663433plb.2 for ; Sun, 14 Aug 2022 23:40:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=3xUHf3HqS3mIbAzLpagrtMfBUff89AJ2SzxASGdwC3U=; b=NyMFVyLH/XSwsw8kvV+j7VDk1gXRk3KDssB9npb6dIfiQSh1g8j1sUNVXvmR6Z+NZx 5ME+fz5LIFMfLrr0vMXJd+hMTuH1NTqQKk5/C41bEJdtZRV3da27DKnf6bRILG4V3UBP UGKOKf/KFPKdVvmUdmhlxfQjSU2ZS7vQo35Y0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=3xUHf3HqS3mIbAzLpagrtMfBUff89AJ2SzxASGdwC3U=; b=nLss8VK9/y69eXXfJWXdtGE9kkDBDIH4HEwJcNbaa8pE+FQTf6liLYNQN/y+Dokjdq rNIRm2dTLj9hHj+saUN4txLlLDOE+o/+29LZJXe8v3N6U5p0CM1j+Q87Z4GSnEf2QVfK nUy6ByEjrifW+d5WhvRbYZjozcBhCdZuZoELI+O69f9lWG2fSv3aLqt01eUVB/Bh5ERn kaWZAZUJyrTztovdBt8JrACcqt1CyJIb3S2JRRzyTCOp+B0XwkwBiH2xUBVRNkd6hqGl nCRRZZQuH4FZJ//pMDz5BuV1UDIEkr2YP1olgg1OZBRBA9DpYXKuCUmjuZULdG+QpPPv Yndw== X-Gm-Message-State: ACgBeo0QBqv5TAbvL22zb3x3/Yb5gba6cicSCyakNR31OUCn85edthlp 6Uu4tUqOfiiKWSQeo9194jaMSg== X-Google-Smtp-Source: AA6agR7YLxLck7accSogjcD0azd/9aNq35LIa8JTqXEvJ/9TlpetoFWCVjY8v0YSb5Q9jLMYWU/YFg== X-Received: by 2002:a17:903:41c6:b0:16f:3d1:f63 with SMTP id u6-20020a17090341c600b0016f03d10f63mr15463762ple.50.1660545599581; Sun, 14 Aug 2022 23:39:59 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:39:59 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Lee Jones , Sebastian Reichel , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 2/7] platform/chrome: cros_typec_switch: Add switch driver Date: Mon, 15 Aug 2022 06:34:19 +0000 Message-Id: <20220815063555.1384505-3-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce a driver to configure USB Type-C mode switches and retimers which are controlled by the Chrome OS EC (Embedded Controller). This allows Type-C port drivers, as well as alternate mode drivers to configure their relevant mode switches and retimers according to the Type-C state they want to achieve. ACPI devices with ID GOOG001A will bind to this driver. Currently, we only register a retimer switch with a stub set function. Subsequent patches will implement the host command set functionality, and introduce mode switches. Signed-off-by: Prashant Malani --- Changes since v4: - Add ACPI dependency to Kconfig. Changes since v3: - No changes. Changes since v2: - Fixed missing "static" identifier. - Removed unnecessary new line for function signature. Changes since v1: - No changes. MAINTAINERS | 1 + drivers/platform/chrome/Kconfig | 11 ++ drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_typec_switch.c | 170 ++++++++++++++++++++ 4 files changed, 183 insertions(+) create mode 100644 drivers/platform/chrome/cros_typec_switch.c diff --git a/MAINTAINERS b/MAINTAINERS index b7221f4143cb..6fa4da411275 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4884,6 +4884,7 @@ M: Prashant Malani L: chrome-platform@lists.linux.dev S: Maintained F: drivers/platform/chrome/cros_ec_typec.c +F: drivers/platform/chrome/cros_typec_switch.c CHROMEOS EC USB PD NOTIFY DRIVER M: Prashant Malani diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig index c45fb376d653..55b68f247f02 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -265,6 +265,17 @@ config CHROMEOS_PRIVACY_SCREEN this should probably always be built into the kernel to avoid or minimize drm probe deferral. +config CROS_TYPEC_SWITCH + tristate "ChromeOS EC Type-C Switch Control" + depends on MFD_CROS_EC_DEV && TYPEC && ACPI + default MFD_CROS_EC_DEV + help + If you say Y here, you get support for configuring the Chrome OS EC Type C + muxes and retimers. + + To compile this driver as a module, choose M here: the module will be + called cros_typec_switch. + source "drivers/platform/chrome/wilco_ec/Kconfig" # Kunit test cases diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index f7e74a845afc..2950610101f1 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CHROMEOS_TBMC) += chromeos_tbmc.o obj-$(CONFIG_CROS_EC) += cros_ec.o obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_ISHTP) += cros_ec_ishtp.o +obj-$(CONFIG_CROS_TYPEC_SWITCH) += cros_typec_switch.o obj-$(CONFIG_CROS_EC_RPMSG) += cros_ec_rpmsg.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c new file mode 100644 index 000000000000..0d319e315d57 --- /dev/null +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2022 Google LLC + * + * This driver provides the ability to configure Type C muxes and retimers which are controlled by + * the Chrome OS EC. + */ + +#include +#include +#include +#include +#include + +#define DRV_NAME "cros-typec-switch" + +/* Handles and other relevant data required for each port's switches. */ +struct cros_typec_port { + int port_num; + struct typec_retimer *retimer; + struct cros_typec_switch_data *sdata; +}; + +/* Driver-specific data. */ +struct cros_typec_switch_data { + struct device *dev; + struct cros_ec_device *ec; + struct cros_typec_port *ports[EC_USB_PD_MAX_PORTS]; +}; + +static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_retimer_state *state) +{ + return 0; +} + +static void cros_typec_unregister_switches(struct cros_typec_switch_data *sdata) +{ + int i; + + for (i = 0; i < EC_USB_PD_MAX_PORTS; i++) { + if (!sdata->ports[i]) + continue; + typec_retimer_unregister(sdata->ports[i]->retimer); + } +} + +static int cros_typec_register_retimer(struct cros_typec_port *port, struct fwnode_handle *fwnode) +{ + struct typec_retimer_desc retimer_desc = { + .fwnode = fwnode, + .drvdata = port, + .name = fwnode_get_name(fwnode), + .set = cros_typec_retimer_set, + }; + + port->retimer = typec_retimer_register(port->sdata->dev, &retimer_desc); + if (IS_ERR(port->retimer)) + return PTR_ERR(port->retimer); + + return 0; +} + +static int cros_typec_register_switches(struct cros_typec_switch_data *sdata) +{ + struct cros_typec_port *port = NULL; + struct device *dev = sdata->dev; + struct fwnode_handle *fwnode; + struct acpi_device *adev; + unsigned long long index; + int ret = 0; + int nports; + + nports = device_get_child_node_count(dev); + if (nports == 0) { + dev_err(dev, "No switch devices found.\n"); + return -ENODEV; + } + + device_for_each_child_node(dev, fwnode) { + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) { + ret = -ENOMEM; + goto err_switch; + } + + adev = to_acpi_device_node(fwnode); + if (!adev) { + dev_err(fwnode->dev, "Couldn't get ACPI device handle\n"); + ret = -ENODEV; + goto err_switch; + } + + ret = acpi_evaluate_integer(adev->handle, "_ADR", NULL, &index); + if (ACPI_FAILURE(ret)) { + dev_err(fwnode->dev, "_ADR wasn't evaluated\n"); + ret = -ENODATA; + goto err_switch; + } + + if (index < 0 || index >= EC_USB_PD_MAX_PORTS) { + dev_err(fwnode->dev, "Invalid port index number: %llu", index); + ret = -EINVAL; + goto err_switch; + } + port->sdata = sdata; + port->port_num = index; + sdata->ports[index] = port; + + ret = cros_typec_register_retimer(port, fwnode); + if (ret) { + dev_err(dev, "Retimer switch register failed\n"); + goto err_switch; + } + + dev_dbg(dev, "Retimer switch registered for index %llu\n", index); + } + + return 0; +err_switch: + cros_typec_unregister_switches(sdata); + return ret; +} + +static int cros_typec_switch_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cros_typec_switch_data *sdata; + + sdata = devm_kzalloc(dev, sizeof(*sdata), GFP_KERNEL); + if (!sdata) + return -ENOMEM; + + sdata->dev = dev; + sdata->ec = dev_get_drvdata(pdev->dev.parent); + + platform_set_drvdata(pdev, sdata); + + return cros_typec_register_switches(sdata); +} + +static int cros_typec_switch_remove(struct platform_device *pdev) +{ + struct cros_typec_switch_data *sdata = platform_get_drvdata(pdev); + + cros_typec_unregister_switches(sdata); + return 0; +} + +#ifdef CONFIG_ACPI +static const struct acpi_device_id cros_typec_switch_acpi_id[] = { + { "GOOG001A", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, cros_typec_switch_acpi_id); +#endif + +static struct platform_driver cros_typec_switch_driver = { + .driver = { + .name = DRV_NAME, + .acpi_match_table = ACPI_PTR(cros_typec_switch_acpi_id), + }, + .probe = cros_typec_switch_probe, + .remove = cros_typec_switch_remove, +}; + +module_platform_driver(cros_typec_switch_driver); + +MODULE_AUTHOR("Prashant Malani "); +MODULE_DESCRIPTION("Chrome OS EC Type C Switch control"); +MODULE_LICENSE("GPL"); From patchwork Mon Aug 15 06:34:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12943157 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A8BA1102 for ; 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[34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.41.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:41:52 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 3/7] platform/chrome: cros_typec_switch: Set EC retimer Date: Mon, 15 Aug 2022 06:34:21 +0000 Message-Id: <20220815063555.1384505-4-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Invoke Chrome EC host commands to set EC-controlled retimer switches to the state the Type-C framework instructs. Signed-off-by: Prashant Malani --- Changes since v4: - Update cros_ec_command() to cros_ec_cmd(). Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. drivers/platform/chrome/cros_typec_switch.c | 56 ++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c index 0d319e315d57..befe35655a9a 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -9,7 +9,10 @@ #include #include #include +#include #include +#include +#include #include #define DRV_NAME "cros-typec-switch" @@ -28,9 +31,60 @@ struct cros_typec_switch_data { struct cros_typec_port *ports[EC_USB_PD_MAX_PORTS]; }; +static int cros_typec_cmd_mux_set(struct cros_typec_switch_data *sdata, int port_num, u8 index, + u8 state) +{ + struct typec_usb_mux_set params = { + .mux_index = index, + .mux_flags = state, + }; + + struct ec_params_typec_control req = { + .port = port_num, + .command = TYPEC_CONTROL_COMMAND_USB_MUX_SET, + .mux_params = params, + }; + + return cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_CONTROL, &req, + sizeof(req), NULL, 0); +} + +static int cros_typec_get_mux_state(unsigned long mode, struct typec_altmode *alt) +{ + int ret = -EOPNOTSUPP; + + if (mode == TYPEC_STATE_SAFE) + ret = USB_PD_MUX_SAFE_MODE; + else if (mode == TYPEC_STATE_USB) + ret = USB_PD_MUX_USB_ENABLED; + else if (alt && alt->svid == USB_TYPEC_DP_SID) + ret = USB_PD_MUX_DP_ENABLED; + + return ret; +} + +/* + * The Chrome EC treats both mode-switches and retimers as "muxes" for the purposes of the + * host command API. This common function configures and verifies the retimer/mode-switch + * according to the provided setting. + */ +static int cros_typec_configure_mux(struct cros_typec_switch_data *sdata, int port_num, int index, + unsigned long mode, struct typec_altmode *alt) +{ + int ret = cros_typec_get_mux_state(mode, alt); + + if (ret < 0) + return ret; + + return cros_typec_cmd_mux_set(sdata, port_num, index, (u8)ret); +} + static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_retimer_state *state) { - return 0; + struct cros_typec_port *port = typec_retimer_get_drvdata(retimer); + + /* Retimers have index 1. */ + return cros_typec_configure_mux(port->sdata, port->port_num, 1, state->mode, state->alt); } static void cros_typec_unregister_switches(struct cros_typec_switch_data *sdata) From patchwork Mon Aug 15 06:34:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12943158 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 608001102 for ; Mon, 15 Aug 2022 06:44:35 +0000 (UTC) Received: by mail-pg1-f182.google.com with SMTP id 24so5829194pgr.7 for ; Sun, 14 Aug 2022 23:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=RJziAcdwqSHxXgUj0onY2n8IS5JD3vb95lzQbzWkWLI=; b=XsJEoodtcCGJbDsuP0RLg51aYou66Ds+346IKLbcNX1VzKwLOBFeMf/YEsKX6AVUoR fWlxxUFBeE/4hBHmemMrlt6x9+e8yTABXmMhPZHbWS6LEKKfuHvCnuCsTBl70thUdU6n t7K5vQvej6G9KDjCE28HFd/n7+bZIMDze6fhs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=RJziAcdwqSHxXgUj0onY2n8IS5JD3vb95lzQbzWkWLI=; b=dmiq5KaqH9Aciwhfy/VR5GnS0V84jfz83ejQeEtbMLeOG2/xGUliR8etMVj2Gq7gB1 gv7K1IgGuVK2nuYBoKep2V6xrwLN1TXg8dWmE/WQbtR1tE2Z5Lo/Ci3J962GJMHohNkf E5u1uto5A5z87DAppNzkiFlxv+IA4VAddc3w+dgddWW1wbrqWFHdj9iWGEM6DkbjapXg TnkWyOyi24OfCUpWoJUsYsE+/BeBFONvVbebvblzSwXtKJo9e33XEzF39Ao4bKO5sjbg VgFR56/G0ZdfwAn8CTfc8W7MkRhnj8/d/aB4V3IYuI8xpH8YANGLQVE6DPK6MKrRblZL 6Jsg== X-Gm-Message-State: ACgBeo1aZL8huL9F713UgNai/dvgl/Rs88TS7ZUqxaRuHA7wlb86n11a EoPhtHW7oy9cidKrlWzcilAiWg== X-Google-Smtp-Source: AA6agR446wHPCYbLAa9lBoYkAl5m6yhRbR4u1jAAQ8WRws1gaRsilRU1+B7KO66gatZg4a0FpR9Gkg== X-Received: by 2002:a63:8548:0:b0:428:a204:c9f7 with SMTP id u69-20020a638548000000b00428a204c9f7mr3906037pgd.331.1660545874813; Sun, 14 Aug 2022 23:44:34 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:44:34 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Lee Jones , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 4/7] platform/chrome: cros_typec_switch: Add event check Date: Mon, 15 Aug 2022 06:34:24 +0000 Message-Id: <20220815063555.1384505-5-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Chrome EC updates Type-C status events when mux set requests from the Application Processor (AP) are completed. Add a check to the flow of configuring muxes to look for this status done bit, so that the driver is aware that the mux set completed successfully or not. Signed-off-by: Prashant Malani --- Changes since v4: - Update cros_ec_command() to cros_ec_cmd(). - Dropped unnecessary Reported-by tag (since this patch is not a bug fix). Changes since v3: - No changes. Changes since v2: - Fixed missing "static" identifier. Changes since v1: - No changes. drivers/platform/chrome/cros_typec_switch.c | 72 ++++++++++++++++++++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c index befe35655a9a..a9e114391321 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -7,6 +7,8 @@ */ #include +#include +#include #include #include #include @@ -63,6 +65,40 @@ static int cros_typec_get_mux_state(unsigned long mode, struct typec_altmode *al return ret; } +static int cros_typec_send_clear_event(struct cros_typec_switch_data *sdata, int port_num, + u32 events_mask) +{ + struct ec_params_typec_control req = { + .port = port_num, + .command = TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, + .clear_events_mask = events_mask, + }; + + return cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_CONTROL, &req, + sizeof(req), NULL, 0); +} + +static bool cros_typec_check_event(struct cros_typec_switch_data *sdata, int port_num, u32 mask) +{ + struct ec_response_typec_status resp; + struct ec_params_typec_status req = { + .port = port_num, + }; + int ret; + + ret = cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_STATUS, &req, sizeof(req), + &resp, sizeof(resp)); + if (ret < 0) { + dev_warn(sdata->dev, "EC_CMD_TYPEC_STATUS failed for port: %d\n", port_num); + return false; + } + + if (resp.events & mask) + return true; + + return false; +} + /* * The Chrome EC treats both mode-switches and retimers as "muxes" for the purposes of the * host command API. This common function configures and verifies the retimer/mode-switch @@ -71,12 +107,44 @@ static int cros_typec_get_mux_state(unsigned long mode, struct typec_altmode *al static int cros_typec_configure_mux(struct cros_typec_switch_data *sdata, int port_num, int index, unsigned long mode, struct typec_altmode *alt) { - int ret = cros_typec_get_mux_state(mode, alt); + unsigned long end; + u32 event_mask; + u8 mux_state; + int ret; + + ret = cros_typec_get_mux_state(mode, alt); + if (ret < 0) + return ret; + mux_state = (u8)ret; + /* Clear any old mux set done event. */ + if (index == 0) + event_mask = PD_STATUS_EVENT_MUX_0_SET_DONE; + else + event_mask = PD_STATUS_EVENT_MUX_1_SET_DONE; + + ret = cros_typec_send_clear_event(sdata, port_num, event_mask); + if (ret < 0) + return ret; + + /* Send the set command. */ + ret = cros_typec_cmd_mux_set(sdata, port_num, index, mux_state); if (ret < 0) return ret; - return cros_typec_cmd_mux_set(sdata, port_num, index, (u8)ret); + /* Check for the mux set done event. */ + end = jiffies + msecs_to_jiffies(1000); + do { + if (cros_typec_check_event(sdata, port_num, event_mask)) + return 0; + + usleep_range(500, 1000); + } while (time_before(jiffies, end)); + + dev_err(sdata->dev, "Timed out waiting for mux set done on index: %d, state: %d\n", + index, mux_state); + + return -ETIMEDOUT; } static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_retimer_state *state) From patchwork Mon Aug 15 06:34:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12943159 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D24171102 for ; Mon, 15 Aug 2022 06:45:55 +0000 (UTC) Received: by mail-pf1-f181.google.com with SMTP id h28so5968009pfq.11 for ; Sun, 14 Aug 2022 23:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=gDBcg0wiSt3vt58MkrYOdJVnzrhs/iuSr5KaWkfmmJs=; b=Rpg2cHfn9geuKVw2PWXcGPrGGPdoOcCuc2mzQtFYXHUc1NFqJoHD+Q65LeIDlTAkZh Ho+BCTnrV1FW7s+DXLxQ86XaSgG7uTc0Kbtduz27bdUQ1Z+6tQ/JEgkYxGBgyePQESfo VyQ4VUkp78/Jr5UqUfUJ2o7oIlrxzC6oSoZeY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=gDBcg0wiSt3vt58MkrYOdJVnzrhs/iuSr5KaWkfmmJs=; b=mW3oLd+EelFGXnA+2HvUb+gXQ7hl/WG3erZPU6xcTI3rmPg9tnqQaOKlnO+0QLVK3t JEMb3IXXsV96GTj+D2ArQaWm/lMQl6jufqeZqT/ziJvaYVy7e08RHPDd2/HYE0EmcHwZ n74RZGPpgr+FVqbjb7RIerOy7WpRiu1gJmCldp4rmc0BYgDIDwFXa5MTrD/c7oqxQ00e TvEZp2vUZshAx+W3j5MBxhgnQavQGEPZvLnG/7gfjXOOq+hxYSOV+W2BE1Urp/+A4WSR yykG6HqAWL4bMa3kvSBr4nSwbg+SjRhgy8Zlvz7r8IiDfRM1Zhvcu6ITzr96c00p9Htq R1Kg== X-Gm-Message-State: ACgBeo1FChSz3JUa/MQKAMMtIm1URtIIoLN5W/y6vCtwEQma+ToONXK4 b4QnIU45vVDaLkEi6TKmU1wXCA== X-Google-Smtp-Source: AA6agR6+QNzJvVOPc6SO6E5AvT3N2Uy4ByBUAkDC38sn+9xFIB7EdYtQAcgRJhYAz/madR1QwA0M7w== X-Received: by 2002:a65:57c8:0:b0:41c:fa29:ae1d with SMTP id q8-20020a6557c8000000b0041cfa29ae1dmr13125889pgr.136.1660545955347; Sun, 14 Aug 2022 23:45:55 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:45:54 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Kees Cook , Sebastian Reichel , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 5/7] platform/chrome: cros_typec_switch: Register mode switches Date: Mon, 15 Aug 2022 06:34:26 +0000 Message-Id: <20220815063555.1384505-6-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Register mode switch devices for Type C connectors, when they are specified by firmware. These control Type C configuration for any USB Type-C mode switches (sometimes known as "muxes") which are controlled by the Chrome EC. Signed-off-by: Prashant Malani --- Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - Fixed missing "static" identifier. Changes since v1: - No changes. drivers/platform/chrome/cros_typec_switch.c | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c index a9e114391321..9eb37b3b754f 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #define DRV_NAME "cros-typec-switch" @@ -22,6 +23,7 @@ /* Handles and other relevant data required for each port's switches. */ struct cros_typec_port { int port_num; + struct typec_mux_dev *mode_switch; struct typec_retimer *retimer; struct cros_typec_switch_data *sdata; }; @@ -147,6 +149,15 @@ static int cros_typec_configure_mux(struct cros_typec_switch_data *sdata, int po return -ETIMEDOUT; } +static int cros_typec_mode_switch_set(struct typec_mux_dev *mode_switch, + struct typec_mux_state *state) +{ + struct cros_typec_port *port = typec_mux_get_drvdata(mode_switch); + + /* Mode switches have index 0. */ + return cros_typec_configure_mux(port->sdata, port->port_num, 0, state->mode, state->alt); +} + static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_retimer_state *state) { struct cros_typec_port *port = typec_retimer_get_drvdata(retimer); @@ -163,9 +174,27 @@ static void cros_typec_unregister_switches(struct cros_typec_switch_data *sdata) if (!sdata->ports[i]) continue; typec_retimer_unregister(sdata->ports[i]->retimer); + typec_mux_unregister(sdata->ports[i]->mode_switch); } } +static int cros_typec_register_mode_switch(struct cros_typec_port *port, + struct fwnode_handle *fwnode) +{ + struct typec_mux_desc mode_switch_desc = { + .fwnode = fwnode, + .drvdata = port, + .name = fwnode_get_name(fwnode), + .set = cros_typec_mode_switch_set, + }; + + port->mode_switch = typec_mux_register(port->sdata->dev, &mode_switch_desc); + if (IS_ERR(port->mode_switch)) + return PTR_ERR(port->mode_switch); + + return 0; +} + static int cros_typec_register_retimer(struct cros_typec_port *port, struct fwnode_handle *fwnode) { struct typec_retimer_desc retimer_desc = { @@ -235,6 +264,17 @@ static int cros_typec_register_switches(struct cros_typec_switch_data *sdata) } dev_dbg(dev, "Retimer switch registered for index %llu\n", index); + + if (!fwnode_property_read_bool(fwnode, "mode-switch")) + continue; + + ret = cros_typec_register_mode_switch(port, fwnode); + if (ret) { + dev_err(dev, "Mode switch register failed\n"); + goto err_switch; + } + + dev_dbg(dev, "Mode switch registered for index %llu\n", index); } return 0; From patchwork Mon Aug 15 06:34:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12943162 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 297541102 for ; Mon, 15 Aug 2022 06:46:50 +0000 (UTC) Received: by mail-pf1-f172.google.com with SMTP id 130so5960770pfv.13 for ; Sun, 14 Aug 2022 23:46:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=1w/+dFs3qHXbDgwwcXAk7wk0nI9cjI/ETzQwM0WXM7M=; b=c+Ok3qnKqp9fTdGMCOumYQW8c7kdDIeshFpol5j9R1lh85E9ONXyN9Ks5tp5BKso1r IcapWSIm+VQmVbWWdGuvB7X358tWZR0/Ury571YiT43L1wQrv+nc6FZoT56hCNEDzK5u aXpwpLDf4f3WJL1E7tUbzy+wn6B0Mo1K1yabc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=1w/+dFs3qHXbDgwwcXAk7wk0nI9cjI/ETzQwM0WXM7M=; b=RvYMwDJKYoAyKcVg1nmk1dMcmAg+8j8lCeqfK+IgME1SmCoRRbbyKoIUXMFl9QamM/ Bcjs733zamW5vuUbC+OCMlRI9WhTFdpc2jtPbjQ0jpXTQnoeef4dxnKz/OXePo9QU/u5 mD99O9fmjXOXNI782MWVk/caNmRBCRUiOzQxiNeiJVf1DLrsFYTmpCDW6Up6MkUP9U/j Qft8d10E9DoYZX7RJU2H90kJnoIYREQNU3v2xp2+SOwPUWPF4DmHG54Wn4H6HBrl1bGm jWTX+9JMzHsdIIqkvK6aUv8i8LPB4rVKG5GB99NH8MsNE8wdeO6hNwXba1B5/cF9fmwg xt4g== X-Gm-Message-State: ACgBeo0JxN6yNDa2nQN6fgg4vSFneUoOPyP/yfFHrxt0Dy1C4YXVKYwE iH3gXBUuX8KvOYvWXifW646s2w== X-Google-Smtp-Source: AA6agR5II5bdhSqLWarYZ2IWhos4bAF5oIBs5Mk8jg7lxj85GCJRpLEucneEznC0TaAzBMuusm1rWw== X-Received: by 2002:a63:8a44:0:b0:41c:cd7b:eda0 with SMTP id y65-20020a638a44000000b0041ccd7beda0mr13088494pgd.117.1660546009677; Sun, 14 Aug 2022 23:46:49 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:46:49 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Kees Cook , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 6/7] platform/chrome: cros_ec_typec: Cleanup switch handle return paths Date: Mon, 15 Aug 2022 06:34:28 +0000 Message-Id: <20220815063555.1384505-7-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some of the return paths for the cros_typec_get_switch_handles() aren't necessary. Clean up the return paths to only undo the handle get's which succeeded. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. drivers/platform/chrome/cros_ec_typec.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index de6ee0f926a6..ee54add992db 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -158,12 +158,10 @@ static int cros_typec_get_switch_handles(struct cros_typec_port *port, return 0; role_sw_err: - usb_role_switch_put(port->role_sw); -ori_sw_err: typec_switch_put(port->ori_sw); -mux_err: +ori_sw_err: typec_mux_put(port->mux); - +mux_err: return -ENODEV; } From patchwork Mon Aug 15 06:34:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12943163 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 993F21102 for ; Mon, 15 Aug 2022 06:48:19 +0000 (UTC) Received: by mail-pj1-f50.google.com with SMTP id o3-20020a17090a0a0300b001f7649cd317so13684963pjo.0 for ; Sun, 14 Aug 2022 23:48:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=r7FHO3XSuRcskZp9JaJ6GVlL/Z/2G05O5vC3OEP7QDc=; b=Skn62wd5hBqRH3K5HWiW94KGZmlsT3eBTTRKk3eQNYRMDJJhQh+HkXW5WcHd2TWd5Y you7kkNVhWXzXmMj5OLpOIPadbrrf4+C2XabfCPLnyo/LNh/LlahIpWUZaXvIZdxkoDu lo5RwLnwtZ0ySIWZPxsDd89uehq21KSiaxj+w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=r7FHO3XSuRcskZp9JaJ6GVlL/Z/2G05O5vC3OEP7QDc=; b=y0HmTwPaJaxf/Dzr76ZCMb5vRdqITD/i4mfLvEnDr2Ps5zjy3c074HscGtPpSZP9w6 ejLAzyu5YrCc6BZtmCR9bruP0vMqUZMOewPac9CQfXxk7KoxIordOZYONEeOR6jU0J6y 6bF48mrEBGNrj6dgrSIC58WYlxkQFKgZAl/avfn03d7af3pP9ND5L6k8YDr0ncJDVbXI 8vKWw7v4A4Etv0xVhW02GsE9axKDs2TTw62/BIgEdbY0JR35QNQOfEFEtKAJTEsb2Te8 uXQHVrSKSyp+K2XSRgkOubIyVEAwd5q4LO1BZfeod8LJBbr+qWIYYpCNLbLmVFbADAFT 916Q== X-Gm-Message-State: ACgBeo1E5hZa+yNjsCpFVKmDQlvY2XpAoaY0Ox9QlCc059gfm/YvmQbm YMJjAAt1gOtmF2a/ELMtYY4BG2zBzqX7SA== X-Google-Smtp-Source: AA6agR5fy9u+V+Zan5Q6cd+Rp1a+74ywHxOVM8U2haZGSKhWMngCa/oPeFKR/lJ+uXJRZ0dAliu8Bw== X-Received: by 2002:a17:90b:4ccb:b0:1f5:20b4:fc9e with SMTP id nd11-20020a17090b4ccb00b001f520b4fc9emr17006992pjb.69.1660546099182; Sun, 14 Aug 2022 23:48:19 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id 200-20020a6214d1000000b0052db82ad8b2sm5988233pfu.123.2022.08.14.23.48.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Aug 2022 23:48:18 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Kees Cook , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v5 7/7] platform/chrome: cros_ec_typec: Get retimer handle Date: Mon, 15 Aug 2022 06:34:30 +0000 Message-Id: <20220815063555.1384505-8-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220815063555.1384505-1-pmalani@chromium.org> References: <20220815063555.1384505-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Where available, obtain the handle to retimer switch specified via firmware, and update the mux configuration callsites to add retimer support for supported modes. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. drivers/platform/chrome/cros_ec_typec.c | 44 +++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index ee54add992db..a1f804ba9dca 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -55,6 +56,7 @@ struct cros_typec_port { struct usb_pd_identity c_identity; struct typec_switch *ori_sw; struct typec_mux *mux; + struct typec_retimer *retimer; struct usb_role_switch *role_sw; /* Variables keeping track of switch state. */ @@ -143,6 +145,12 @@ static int cros_typec_get_switch_handles(struct cros_typec_port *port, goto mux_err; } + port->retimer = fwnode_typec_retimer_get(fwnode); + if (IS_ERR(port->retimer)) { + dev_dbg(dev, "Retimer handle not found.\n"); + goto retimer_sw_err; + } + port->ori_sw = fwnode_typec_switch_get(fwnode); if (IS_ERR(port->ori_sw)) { dev_dbg(dev, "Orientation switch handle not found.\n"); @@ -160,6 +168,8 @@ static int cros_typec_get_switch_handles(struct cros_typec_port *port, role_sw_err: typec_switch_put(port->ori_sw); ori_sw_err: + typec_retimer_put(port->retimer); +retimer_sw_err: typec_mux_put(port->mux); mux_err: return -ENODEV; @@ -204,6 +214,21 @@ static void cros_typec_unregister_altmodes(struct cros_typec_data *typec, int po } } +/* + * Map the Type-C Mux state to retimer state and call the retimer set function. We need this + * because we re-use the Type-C mux state for retimers. + */ +static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_mux_state state) +{ + struct typec_retimer_state rstate = { + .alt = state.alt, + .mode = state.mode, + .data = state.data, + }; + + return typec_retimer_set(retimer, &rstate); +} + static int cros_typec_usb_disconnect_state(struct cros_typec_port *port) { port->state.alt = NULL; @@ -212,6 +237,7 @@ static int cros_typec_usb_disconnect_state(struct cros_typec_port *port) usb_role_switch_set_role(port->role_sw, USB_ROLE_NONE); typec_switch_set(port->ori_sw, TYPEC_ORIENTATION_NONE); + cros_typec_retimer_set(port->retimer, port->state); return typec_mux_set(port->mux, &port->state); } @@ -409,9 +435,14 @@ static int cros_typec_init_ports(struct cros_typec_data *typec) static int cros_typec_usb_safe_state(struct cros_typec_port *port) { + int ret; port->state.mode = TYPEC_STATE_SAFE; - return typec_mux_set(port->mux, &port->state); + ret = cros_typec_retimer_set(port->retimer, port->state); + if (!ret) + ret = typec_mux_set(port->mux, &port->state); + + return ret; } /* @@ -508,7 +539,11 @@ static int cros_typec_enable_dp(struct cros_typec_data *typec, port->state.data = &dp_data; port->state.mode = TYPEC_MODAL_STATE(ffs(pd_ctrl->dp_mode)); - return typec_mux_set(port->mux, &port->state); + ret = cros_typec_retimer_set(port->retimer, port->state); + if (!ret) + ret = typec_mux_set(port->mux, &port->state); + + return ret; } static int cros_typec_enable_usb4(struct cros_typec_data *typec, @@ -597,7 +632,10 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num, } else if (port->mux_flags & USB_PD_MUX_USB_ENABLED) { port->state.alt = NULL; port->state.mode = TYPEC_STATE_USB; - ret = typec_mux_set(port->mux, &port->state); + + ret = cros_typec_retimer_set(port->retimer, port->state); + if (!ret) + ret = typec_mux_set(port->mux, &port->state); } else { dev_dbg(typec->dev, "Unrecognized mode requested, mux flags: %x\n",