From patchwork Mon Aug 15 10:13:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12943417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F086C00140 for ; Mon, 15 Aug 2022 10:14:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242414AbiHOKOa (ORCPT ); Mon, 15 Aug 2022 06:14:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242545AbiHOKNu (ORCPT ); Mon, 15 Aug 2022 06:13:50 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 474E623BF9 for ; Mon, 15 Aug 2022 03:13:40 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id d65-20020a17090a6f4700b001f303a97b14so6367624pjk.1 for ; Mon, 15 Aug 2022 03:13:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=oAq6o0jFtqV3Z32Di7VJjVh+El5W8i0/stoBlm7/lCs=; b=ph8Ui4daxtmuQgm/V3RnXn7BZv4Cc8CTiQos4otj2w0Mif4dR6pWK+LWiS1OLD/5bk 7hMTLGbb3qCzIch/9LFMeQDnSXFanG8YvBYp2j4iXLnfQE3itCAduaPJuaRmJxcJicSd NySKW/G4vysIABptWMbGnf6/Kd2R101mB//wobotl/zFN75RYxy6hxSxzSgzuuanVdfN sw0T9nz0neHVMkyZoImfy3Mxj2kk+oNYBb4cqwroAFecNSFaIt9JezmXpcz4mo4arPQ7 NDns8NwCVzPuxBYUn5gGFFYhP8JgX1wCMmuP6MuactLcJD12qs8HecopliyXmJAueefu vDiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=oAq6o0jFtqV3Z32Di7VJjVh+El5W8i0/stoBlm7/lCs=; b=nRvOFM8NdGuQ5asZpkGyR03uTIz3e7Fsy/U3ePVlysl4FiCO2NToxcaipa2RJD1Qa8 4QZXJqHZU369bohFQ6u7Q2Gt6OciwxLfhtopz6cy4YklVchCunsGEQZDHGjxs23OZdxo fL05zdPrEgYzdOuoQEnNwamD7VX/ogR+6uKUW781yRJtAifD1sgpwC7M9rxEq1gLkzda J/49WykQfbC7L01FUqe1BfaWKwvtiY0NkMwzO1itIWE0ifEQdnpdLr5PX2uZy0Dm+WlO PvzzmGQ+rM3UFpqESJJTg5vmuAVndSRcH/mhvOmA+wTLDqXNBIoe+k/w0Ugk8nFblksW KSQA== X-Gm-Message-State: ACgBeo1W/F3f2M4BoXhMOdhggD3FDnrLWmVx2cV0USnyW3ZikhpN9a98 cZl21u+QRWiagoRfRgXBw60CxA== X-Google-Smtp-Source: AA6agR6GUGkgeL6fjqK6d4JNckN6bf2vXB/2uri4aqb6qVtVU6k+rTl8k6aiOw2+s27xN+PZJkAxqw== X-Received: by 2002:a17:902:e742:b0:16f:2ef:77d8 with SMTP id p2-20020a170902e74200b0016f02ef77d8mr16138906plf.32.1660558419474; Mon, 15 Aug 2022 03:13:39 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.84.46]) by smtp.gmail.com with ESMTPSA id i190-20020a6254c7000000b0052d4f2e2f6asm6267437pfb.119.2022.08.15.03.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Aug 2022 03:13:38 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [PATCH kvmtool 1/5] Update UAPI headers based on Linux-6.0-rc1 Date: Mon, 15 Aug 2022 15:43:21 +0530 Message-Id: <20220815101325.477694-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220815101325.477694-1-apatel@ventanamicro.com> References: <20220815101325.477694-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We update all UAPI headers based on Linux-6.0-rc1 so that we can use latest features. Signed-off-by: Anup Patel --- arm/aarch64/include/asm/kvm.h | 36 +++++++ include/linux/kvm.h | 181 ++++++++++++++++++++++++++++++++-- include/linux/virtio_9p.h | 2 +- include/linux/virtio_config.h | 7 +- include/linux/virtio_ids.h | 14 +-- include/linux/virtio_net.h | 34 ++++++- include/linux/virtio_pci.h | 2 + riscv/include/asm/kvm.h | 22 +++++ x86/include/asm/kvm.h | 33 ++++--- 9 files changed, 301 insertions(+), 30 deletions(-) diff --git a/arm/aarch64/include/asm/kvm.h b/arm/aarch64/include/asm/kvm.h index c1b6ddc..3bb1343 100644 --- a/arm/aarch64/include/asm/kvm.h +++ b/arm/aarch64/include/asm/kvm.h @@ -139,8 +139,10 @@ struct kvm_guest_debug_arch { __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; }; +#define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0) struct kvm_debug_exit_arch { __u32 hsr; + __u32 hsr_high; /* ESR_EL2[61:32] */ __u64 far; /* used for watchpoints */ }; @@ -332,6 +334,40 @@ struct kvm_arm_copy_mte_tags { #define KVM_ARM64_SVE_VLS_WORDS \ ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) +/* Bitmap feature firmware registers */ +#define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) +#define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ + KVM_REG_ARM_FW_FEAT_BMAP | \ + ((r) & 0xffff)) + +#define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0) + +enum { + KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0, +#ifdef __KERNEL__ + KVM_REG_ARM_STD_BMAP_BIT_COUNT, +#endif +}; + +#define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1) + +enum { + KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0, +#ifdef __KERNEL__ + KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT, +#endif +}; + +#define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2) + +enum { + KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, + KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, +#ifdef __KERNEL__ + KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT, +#endif +}; + /* Device Control API: ARM VGIC */ #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 diff --git a/include/linux/kvm.h b/include/linux/kvm.h index 91a6fe4..eed0315 100644 --- a/include/linux/kvm.h +++ b/include/linux/kvm.h @@ -270,6 +270,8 @@ struct kvm_xen_exit { #define KVM_EXIT_X86_BUS_LOCK 33 #define KVM_EXIT_XEN 34 #define KVM_EXIT_RISCV_SBI 35 +#define KVM_EXIT_RISCV_CSR 36 +#define KVM_EXIT_NOTIFY 37 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -444,8 +446,17 @@ struct kvm_run { #define KVM_SYSTEM_EVENT_SHUTDOWN 1 #define KVM_SYSTEM_EVENT_RESET 2 #define KVM_SYSTEM_EVENT_CRASH 3 +#define KVM_SYSTEM_EVENT_WAKEUP 4 +#define KVM_SYSTEM_EVENT_SUSPEND 5 +#define KVM_SYSTEM_EVENT_SEV_TERM 6 __u32 type; - __u64 flags; + __u32 ndata; + union { +#ifndef __KERNEL__ + __u64 flags; +#endif + __u64 data[16]; + }; } system_event; /* KVM_EXIT_S390_STSI */ struct { @@ -487,6 +498,18 @@ struct kvm_run { unsigned long args[6]; unsigned long ret[2]; } riscv_sbi; + /* KVM_EXIT_RISCV_CSR */ + struct { + unsigned long csr_num; + unsigned long new_value; + unsigned long write_mask; + unsigned long ret_value; + } riscv_csr; + /* KVM_EXIT_NOTIFY */ + struct { +#define KVM_NOTIFY_CONTEXT_INVALID (1 << 0) + __u32 flags; + } notify; /* Fix the size of the union. */ char padding[256]; }; @@ -533,7 +556,7 @@ struct kvm_coalesced_mmio { struct kvm_coalesced_mmio_ring { __u32 first, last; - struct kvm_coalesced_mmio coalesced_mmio[0]; + struct kvm_coalesced_mmio coalesced_mmio[]; }; #define KVM_COALESCED_MMIO_MAX \ @@ -612,7 +635,7 @@ struct kvm_clear_dirty_log { /* for KVM_SET_SIGNAL_MASK */ struct kvm_signal_mask { __u32 len; - __u8 sigset[0]; + __u8 sigset[]; }; /* for KVM_TPR_ACCESS_REPORTING */ @@ -640,6 +663,7 @@ struct kvm_vapic_addr { #define KVM_MP_STATE_OPERATING 7 #define KVM_MP_STATE_LOAD 8 #define KVM_MP_STATE_AP_RESET_HOLD 9 +#define KVM_MP_STATE_SUSPENDED 10 struct kvm_mp_state { __u32 mp_state; @@ -1144,6 +1168,15 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_S390_MEM_OP_EXTENSION 211 #define KVM_CAP_PMU_CAPABILITY 212 #define KVM_CAP_DISABLE_QUIRKS2 213 +#define KVM_CAP_VM_TSC_CONTROL 214 +#define KVM_CAP_SYSTEM_EVENT_DATA 215 +#define KVM_CAP_ARM_SYSTEM_SUSPEND 216 +#define KVM_CAP_S390_PROTECTED_DUMP 217 +#define KVM_CAP_X86_TRIPLE_FAULT_EVENT 218 +#define KVM_CAP_X86_NOTIFY_VMEXIT 219 +#define KVM_CAP_VM_DISABLE_NX_HUGE_PAGES 220 +#define KVM_CAP_S390_ZPCI_OP 221 +#define KVM_CAP_S390_CPU_TOPOLOGY 222 #ifdef KVM_CAP_IRQ_ROUTING @@ -1208,7 +1241,7 @@ struct kvm_irq_routing_entry { struct kvm_irq_routing { __u32 nr; __u32 flags; - struct kvm_irq_routing_entry entries[0]; + struct kvm_irq_routing_entry entries[]; }; #endif @@ -1232,6 +1265,7 @@ struct kvm_x86_mce { #define KVM_XEN_HVM_CONFIG_SHARED_INFO (1 << 2) #define KVM_XEN_HVM_CONFIG_RUNSTATE (1 << 3) #define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL (1 << 4) +#define KVM_XEN_HVM_CONFIG_EVTCHN_SEND (1 << 5) struct kvm_xen_hvm_config { __u32 flags; @@ -1327,7 +1361,7 @@ struct kvm_dirty_tlb { struct kvm_reg_list { __u64 n; /* number of regs */ - __u64 reg[0]; + __u64 reg[]; }; struct kvm_one_reg { @@ -1470,7 +1504,8 @@ struct kvm_s390_ucas_mapping { #define KVM_SET_PIT2 _IOW(KVMIO, 0xa0, struct kvm_pit_state2) /* Available with KVM_CAP_PPC_GET_PVINFO */ #define KVM_PPC_GET_PVINFO _IOW(KVMIO, 0xa1, struct kvm_ppc_pvinfo) -/* Available with KVM_CAP_TSC_CONTROL */ +/* Available with KVM_CAP_TSC_CONTROL for a vCPU, or with +* KVM_CAP_VM_TSC_CONTROL to set defaults for a VM */ #define KVM_SET_TSC_KHZ _IO(KVMIO, 0xa2) #define KVM_GET_TSC_KHZ _IO(KVMIO, 0xa3) /* Available with KVM_CAP_PCI_2_3 */ @@ -1645,6 +1680,55 @@ struct kvm_s390_pv_unp { __u64 tweak; }; +enum pv_cmd_dmp_id { + KVM_PV_DUMP_INIT, + KVM_PV_DUMP_CONFIG_STOR_STATE, + KVM_PV_DUMP_COMPLETE, + KVM_PV_DUMP_CPU, +}; + +struct kvm_s390_pv_dmp { + __u64 subcmd; + __u64 buff_addr; + __u64 buff_len; + __u64 gaddr; /* For dump storage state */ + __u64 reserved[4]; +}; + +enum pv_cmd_info_id { + KVM_PV_INFO_VM, + KVM_PV_INFO_DUMP, +}; + +struct kvm_s390_pv_info_dump { + __u64 dump_cpu_buffer_len; + __u64 dump_config_mem_buffer_per_1m; + __u64 dump_config_finalize_len; +}; + +struct kvm_s390_pv_info_vm { + __u64 inst_calls_list[4]; + __u64 max_cpus; + __u64 max_guests; + __u64 max_guest_addr; + __u64 feature_indication; +}; + +struct kvm_s390_pv_info_header { + __u32 id; + __u32 len_max; + __u32 len_written; + __u32 reserved; +}; + +struct kvm_s390_pv_info { + struct kvm_s390_pv_info_header header; + union { + struct kvm_s390_pv_info_dump dump; + struct kvm_s390_pv_info_vm vm; + }; +}; + enum pv_cmd_id { KVM_PV_ENABLE, KVM_PV_DISABLE, @@ -1653,6 +1737,8 @@ enum pv_cmd_id { KVM_PV_VERIFY, KVM_PV_PREP_RESET, KVM_PV_UNSHARE_ALL, + KVM_PV_INFO, + KVM_PV_DUMP, }; struct kvm_pv_cmd { @@ -1686,6 +1772,32 @@ struct kvm_xen_hvm_attr { struct { __u64 gfn; } shared_info; + struct { + __u32 send_port; + __u32 type; /* EVTCHNSTAT_ipi / EVTCHNSTAT_interdomain */ + __u32 flags; +#define KVM_XEN_EVTCHN_DEASSIGN (1 << 0) +#define KVM_XEN_EVTCHN_UPDATE (1 << 1) +#define KVM_XEN_EVTCHN_RESET (1 << 2) + /* + * Events sent by the guest are either looped back to + * the guest itself (potentially on a different port#) + * or signalled via an eventfd. + */ + union { + struct { + __u32 port; + __u32 vcpu; + __u32 priority; + } port; + struct { + __u32 port; /* Zero for eventfd */ + __s32 fd; + } eventfd; + __u32 padding[4]; + } deliver; + } evtchn; + __u32 xen_version; __u64 pad[8]; } u; }; @@ -1694,11 +1806,17 @@ struct kvm_xen_hvm_attr { #define KVM_XEN_ATTR_TYPE_LONG_MODE 0x0 #define KVM_XEN_ATTR_TYPE_SHARED_INFO 0x1 #define KVM_XEN_ATTR_TYPE_UPCALL_VECTOR 0x2 +/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */ +#define KVM_XEN_ATTR_TYPE_EVTCHN 0x3 +#define KVM_XEN_ATTR_TYPE_XEN_VERSION 0x4 /* Per-vCPU Xen attributes */ #define KVM_XEN_VCPU_GET_ATTR _IOWR(KVMIO, 0xca, struct kvm_xen_vcpu_attr) #define KVM_XEN_VCPU_SET_ATTR _IOW(KVMIO, 0xcb, struct kvm_xen_vcpu_attr) +/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */ +#define KVM_XEN_HVM_EVTCHN_SEND _IOW(KVMIO, 0xd0, struct kvm_irq_routing_xen_evtchn) + #define KVM_GET_SREGS2 _IOR(KVMIO, 0xcc, struct kvm_sregs2) #define KVM_SET_SREGS2 _IOW(KVMIO, 0xcd, struct kvm_sregs2) @@ -1716,6 +1834,13 @@ struct kvm_xen_vcpu_attr { __u64 time_blocked; __u64 time_offline; } runstate; + __u32 vcpu_id; + struct { + __u32 port; + __u32 priority; + __u64 expires_ns; + } timer; + __u8 vector; } u; }; @@ -1726,6 +1851,10 @@ struct kvm_xen_vcpu_attr { #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_CURRENT 0x3 #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_DATA 0x4 #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADJUST 0x5 +/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */ +#define KVM_XEN_VCPU_ATTR_TYPE_VCPU_ID 0x6 +#define KVM_XEN_VCPU_ATTR_TYPE_TIMER 0x7 +#define KVM_XEN_VCPU_ATTR_TYPE_UPCALL_VECTOR 0x8 /* Secure Encrypted Virtualization command */ enum sev_cmd_id { @@ -2025,7 +2154,8 @@ struct kvm_stats_header { #define KVM_STATS_UNIT_BYTES (0x1 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_SECONDS (0x2 << KVM_STATS_UNIT_SHIFT) #define KVM_STATS_UNIT_CYCLES (0x3 << KVM_STATS_UNIT_SHIFT) -#define KVM_STATS_UNIT_MAX KVM_STATS_UNIT_CYCLES +#define KVM_STATS_UNIT_BOOLEAN (0x4 << KVM_STATS_UNIT_SHIFT) +#define KVM_STATS_UNIT_MAX KVM_STATS_UNIT_BOOLEAN #define KVM_STATS_BASE_SHIFT 8 #define KVM_STATS_BASE_MASK (0xF << KVM_STATS_BASE_SHIFT) @@ -2060,4 +2190,41 @@ struct kvm_stats_desc { /* Available with KVM_CAP_XSAVE2 */ #define KVM_GET_XSAVE2 _IOR(KVMIO, 0xcf, struct kvm_xsave) +/* Available with KVM_CAP_S390_PROTECTED_DUMP */ +#define KVM_S390_PV_CPU_COMMAND _IOWR(KVMIO, 0xd0, struct kvm_pv_cmd) + +/* Available with KVM_CAP_X86_NOTIFY_VMEXIT */ +#define KVM_X86_NOTIFY_VMEXIT_ENABLED (1ULL << 0) +#define KVM_X86_NOTIFY_VMEXIT_USER (1ULL << 1) + +/* Available with KVM_CAP_S390_ZPCI_OP */ +#define KVM_S390_ZPCI_OP _IOW(KVMIO, 0xd1, struct kvm_s390_zpci_op) + +struct kvm_s390_zpci_op { + /* in */ + __u32 fh; /* target device */ + __u8 op; /* operation to perform */ + __u8 pad[3]; + union { + /* for KVM_S390_ZPCIOP_REG_AEN */ + struct { + __u64 ibv; /* Guest addr of interrupt bit vector */ + __u64 sb; /* Guest addr of summary bit */ + __u32 flags; + __u32 noi; /* Number of interrupts */ + __u8 isc; /* Guest interrupt subclass */ + __u8 sbo; /* Offset of guest summary bit vector */ + __u16 pad; + } reg_aen; + __u64 reserved[8]; + } u; +}; + +/* types for kvm_s390_zpci_op->op */ +#define KVM_S390_ZPCIOP_REG_AEN 0 +#define KVM_S390_ZPCIOP_DEREG_AEN 1 + +/* flags for kvm_s390_zpci_op->u.reg_aen.flags */ +#define KVM_S390_ZPCIOP_REGAEN_HOST (1 << 0) + #endif /* __LINUX_KVM_H */ diff --git a/include/linux/virtio_9p.h b/include/linux/virtio_9p.h index 4410474..374b68f 100644 --- a/include/linux/virtio_9p.h +++ b/include/linux/virtio_9p.h @@ -38,7 +38,7 @@ struct virtio_9p_config { /* length of the tag name */ __virtio16 tag_len; /* non-NULL terminated tag name */ - __u8 tag[0]; + __u8 tag[]; } __attribute__((packed)); #endif /* _LINUX_VIRTIO_9P_H */ diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index f0fb0ae..3c05162 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -52,7 +52,7 @@ * rest are per-device feature bits. */ #define VIRTIO_TRANSPORT_F_START 28 -#define VIRTIO_TRANSPORT_F_END 38 +#define VIRTIO_TRANSPORT_F_END 41 #ifndef VIRTIO_CONFIG_NO_LEGACY /* Do we get callbacks when the ring is completely used, even if we've @@ -98,4 +98,9 @@ * Does the device support Single Root I/O Virtualization? */ #define VIRTIO_F_SR_IOV 37 + +/* + * This feature indicates that the driver can reset a queue individually. + */ +#define VIRTIO_F_RING_RESET 40 #endif /* _UAPI_LINUX_VIRTIO_CONFIG_H */ diff --git a/include/linux/virtio_ids.h b/include/linux/virtio_ids.h index 80d76b7..7aa2eb7 100644 --- a/include/linux/virtio_ids.h +++ b/include/linux/virtio_ids.h @@ -73,12 +73,12 @@ * Virtio Transitional IDs */ -#define VIRTIO_TRANS_ID_NET 1000 /* transitional virtio net */ -#define VIRTIO_TRANS_ID_BLOCK 1001 /* transitional virtio block */ -#define VIRTIO_TRANS_ID_BALLOON 1002 /* transitional virtio balloon */ -#define VIRTIO_TRANS_ID_CONSOLE 1003 /* transitional virtio console */ -#define VIRTIO_TRANS_ID_SCSI 1004 /* transitional virtio SCSI */ -#define VIRTIO_TRANS_ID_RNG 1005 /* transitional virtio rng */ -#define VIRTIO_TRANS_ID_9P 1009 /* transitional virtio 9p console */ +#define VIRTIO_TRANS_ID_NET 0x1000 /* transitional virtio net */ +#define VIRTIO_TRANS_ID_BLOCK 0x1001 /* transitional virtio block */ +#define VIRTIO_TRANS_ID_BALLOON 0x1002 /* transitional virtio balloon */ +#define VIRTIO_TRANS_ID_CONSOLE 0x1003 /* transitional virtio console */ +#define VIRTIO_TRANS_ID_SCSI 0x1004 /* transitional virtio SCSI */ +#define VIRTIO_TRANS_ID_RNG 0x1005 /* transitional virtio rng */ +#define VIRTIO_TRANS_ID_9P 0x1009 /* transitional virtio 9p console */ #endif /* _LINUX_VIRTIO_IDS_H */ diff --git a/include/linux/virtio_net.h b/include/linux/virtio_net.h index 3f55a42..29ced55 100644 --- a/include/linux/virtio_net.h +++ b/include/linux/virtio_net.h @@ -56,7 +56,7 @@ #define VIRTIO_NET_F_MQ 22 /* Device supports Receive Flow * Steering */ #define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */ - +#define VIRTIO_NET_F_NOTF_COAL 53 /* Guest can handle notifications coalescing */ #define VIRTIO_NET_F_HASH_REPORT 57 /* Supports hash report */ #define VIRTIO_NET_F_RSS 60 /* Supports RSS RX steering */ #define VIRTIO_NET_F_RSC_EXT 61 /* extended coalescing info */ @@ -355,4 +355,36 @@ struct virtio_net_hash_config { #define VIRTIO_NET_CTRL_GUEST_OFFLOADS 5 #define VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET 0 +/* + * Control notifications coalescing. + * + * Request the device to change the notifications coalescing parameters. + * + * Available with the VIRTIO_NET_F_NOTF_COAL feature bit. + */ +#define VIRTIO_NET_CTRL_NOTF_COAL 6 +/* + * Set the tx-usecs/tx-max-packets patameters. + * tx-usecs - Maximum number of usecs to delay a TX notification. + * tx-max-packets - Maximum number of packets to send before a TX notification. + */ +struct virtio_net_ctrl_coal_tx { + __le32 tx_max_packets; + __le32 tx_usecs; +}; + +#define VIRTIO_NET_CTRL_NOTF_COAL_TX_SET 0 + +/* + * Set the rx-usecs/rx-max-packets patameters. + * rx-usecs - Maximum number of usecs to delay a RX notification. + * rx-max-frames - Maximum number of packets to receive before a RX notification. + */ +struct virtio_net_ctrl_coal_rx { + __le32 rx_max_packets; + __le32 rx_usecs; +}; + +#define VIRTIO_NET_CTRL_NOTF_COAL_RX_SET 1 + #endif /* _UAPI_LINUX_VIRTIO_NET_H */ diff --git a/include/linux/virtio_pci.h b/include/linux/virtio_pci.h index 3a86f36..f703afc 100644 --- a/include/linux/virtio_pci.h +++ b/include/linux/virtio_pci.h @@ -202,6 +202,8 @@ struct virtio_pci_cfg_cap { #define VIRTIO_PCI_COMMON_Q_AVAILHI 44 #define VIRTIO_PCI_COMMON_Q_USEDLO 48 #define VIRTIO_PCI_COMMON_Q_USEDHI 52 +#define VIRTIO_PCI_COMMON_Q_NDATA 56 +#define VIRTIO_PCI_COMMON_Q_RESET 58 #endif /* VIRTIO_PCI_NO_MODERN */ diff --git a/riscv/include/asm/kvm.h b/riscv/include/asm/kvm.h index f808ad1..7351417 100644 --- a/riscv/include/asm/kvm.h +++ b/riscv/include/asm/kvm.h @@ -82,6 +82,25 @@ struct kvm_riscv_timer { __u64 state; }; +/* + * ISA extension IDs specific to KVM. This is not the same as the host ISA + * extension IDs as that is internal to the host and should not be exposed + * to the guest. This should always be contiguous to keep the mapping simple + * in KVM implementation. + */ +enum KVM_RISCV_ISA_EXT_ID { + KVM_RISCV_ISA_EXT_A = 0, + KVM_RISCV_ISA_EXT_C, + KVM_RISCV_ISA_EXT_D, + KVM_RISCV_ISA_EXT_F, + KVM_RISCV_ISA_EXT_H, + KVM_RISCV_ISA_EXT_I, + KVM_RISCV_ISA_EXT_M, + KVM_RISCV_ISA_EXT_SVPBMT, + KVM_RISCV_ISA_EXT_SSTC, + KVM_RISCV_ISA_EXT_MAX, +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -123,6 +142,9 @@ struct kvm_riscv_timer { #define KVM_REG_RISCV_FP_D_REG(name) \ (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) +/* ISA Extension registers are mapped as type 7 */ +#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) + #endif #endif /* __LINUX_KVM_RISCV_H */ diff --git a/x86/include/asm/kvm.h b/x86/include/asm/kvm.h index bf6e960..46de10a 100644 --- a/x86/include/asm/kvm.h +++ b/x86/include/asm/kvm.h @@ -198,13 +198,13 @@ struct kvm_msrs { __u32 nmsrs; /* number of msrs in entries */ __u32 pad; - struct kvm_msr_entry entries[0]; + struct kvm_msr_entry entries[]; }; /* for KVM_GET_MSR_INDEX_LIST */ struct kvm_msr_list { __u32 nmsrs; /* number of msrs in entries */ - __u32 indices[0]; + __u32 indices[]; }; /* Maximum size of any access bitmap in bytes */ @@ -241,7 +241,7 @@ struct kvm_cpuid_entry { struct kvm_cpuid { __u32 nent; __u32 padding; - struct kvm_cpuid_entry entries[0]; + struct kvm_cpuid_entry entries[]; }; struct kvm_cpuid_entry2 { @@ -263,7 +263,7 @@ struct kvm_cpuid_entry2 { struct kvm_cpuid2 { __u32 nent; __u32 padding; - struct kvm_cpuid_entry2 entries[0]; + struct kvm_cpuid_entry2 entries[]; }; /* for KVM_GET_PIT and KVM_SET_PIT */ @@ -306,7 +306,8 @@ struct kvm_pit_state { struct kvm_pit_channel_state channels[3]; }; -#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 +#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 +#define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002 struct kvm_pit_state2 { struct kvm_pit_channel_state channels[3]; @@ -325,6 +326,7 @@ struct kvm_reinject_control { #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 #define KVM_VCPUEVENT_VALID_SMM 0x00000008 #define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010 +#define KVM_VCPUEVENT_VALID_TRIPLE_FAULT 0x00000020 /* Interrupt shadow states */ #define KVM_X86_SHADOW_INT_MOV_SS 0x01 @@ -359,7 +361,10 @@ struct kvm_vcpu_events { __u8 smm_inside_nmi; __u8 latched_init; } smi; - __u8 reserved[27]; + struct { + __u8 pending; + } triple_fault; + __u8 reserved[26]; __u8 exception_has_payload; __u64 exception_payload; }; @@ -389,7 +394,7 @@ struct kvm_xsave { * the contents of CPUID leaf 0xD on the host. */ __u32 region[1024]; - __u32 extra[0]; + __u32 extra[]; }; #define KVM_MAX_XCRS 16 @@ -428,11 +433,13 @@ struct kvm_sync_regs { struct kvm_vcpu_events events; }; -#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) -#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) -#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) -#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) -#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) +#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) +#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) +#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) +#define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) +#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) +#define KVM_X86_QUIRK_FIX_HYPERCALL_INSN (1 << 5) +#define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS (1 << 6) #define KVM_STATE_NESTED_FORMAT_VMX 0 #define KVM_STATE_NESTED_FORMAT_SVM 1 @@ -515,7 +522,7 @@ struct kvm_pmu_event_filter { __u32 fixed_counter_bitmap; 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([171.76.84.46]) by smtp.gmail.com with ESMTPSA id i190-20020a6254c7000000b0052d4f2e2f6asm6267437pfb.119.2022.08.15.03.13.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Aug 2022 03:13:42 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra , Anup Patel Subject: [PATCH kvmtool 2/5] riscv: Append ISA extensions to the device tree Date: Mon, 15 Aug 2022 15:43:22 +0530 Message-Id: <20220815101325.477694-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220815101325.477694-1-apatel@ventanamicro.com> References: <20220815101325.477694-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Atish Patra The riscv,isa DT property only contains single letter base extensions until now. However, there are also multi-letter extensions which were ratified recently. Add a mechanism to append those extension details to the device tree so that guest can leverage those. Signed-off-by: Atish Patra Signed-off-by: Anup Patel --- riscv/fdt.c | 30 ++++++++++++++++++++++++++++++ riscv/include/kvm/kvm-cpu-arch.h | 11 +++++++++++ riscv/kvm-cpu.c | 11 ----------- 3 files changed, 41 insertions(+), 11 deletions(-) diff --git a/riscv/fdt.c b/riscv/fdt.c index de15bfe..1818cf7 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -9,6 +9,16 @@ #include #include +#define RISCV_ISA_EXT_REG(id) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \ + id, KVM_REG_SIZE_ULONG) +struct isa_ext_info { + const char *name; + unsigned long ext_id; +}; + +struct isa_ext_info isa_info_arr[] = { +}; + static void dump_fdt(const char *dtb_file, void *fdt) { int count, fd; @@ -31,6 +41,7 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) { int cpu, pos, i, index, valid_isa_len; const char *valid_isa_order = "IEMAFDQCLBJTPVNSUHKORWXYZG"; + int arr_sz = ARRAY_SIZE(isa_info_arr); _FDT(fdt_begin_node(fdt, "cpus")); _FDT(fdt_property_cell(fdt, "#address-cells", 0x1)); @@ -42,6 +53,8 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) char cpu_name[CPU_NAME_MAX_LEN]; char cpu_isa[CPU_ISA_MAX_LEN]; struct kvm_cpu *vcpu = kvm->cpus[cpu]; + struct kvm_one_reg reg; + unsigned long isa_ext_out = 0; snprintf(cpu_name, CPU_NAME_MAX_LEN, "cpu@%x", cpu); @@ -53,6 +66,23 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) if (vcpu->riscv_isa & (1 << (index))) cpu_isa[pos++] = 'a' + index; } + + for (i = 0; i < arr_sz; i++) { + reg.id = RISCV_ISA_EXT_REG(isa_info_arr[i].ext_id); + reg.addr = (unsigned long)&isa_ext_out; + if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) + continue; + if (!isa_ext_out) + /* This extension is not available in hardware */ + continue; + + if ((strlen(isa_info_arr[i].name) + pos + 1) >= CPU_ISA_MAX_LEN) { + pr_warning("Insufficient space to append ISA exension\n"); + break; + } + pos += snprintf(cpu_isa + pos, CPU_ISA_MAX_LEN, "_%s", + isa_info_arr[i].name); + } cpu_isa[pos] = '\0'; _FDT(fdt_begin_node(fdt, cpu_name)); diff --git a/riscv/include/kvm/kvm-cpu-arch.h b/riscv/include/kvm/kvm-cpu-arch.h index 78fcd01..4b3e602 100644 --- a/riscv/include/kvm/kvm-cpu-arch.h +++ b/riscv/include/kvm/kvm-cpu-arch.h @@ -7,6 +7,17 @@ #include "kvm/kvm.h" +static inline __u64 __kvm_reg_id(__u64 type, __u64 idx, __u64 size) +{ + return KVM_REG_RISCV | type | idx | size; +} + +#if __riscv_xlen == 64 +#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64 +#else +#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32 +#endif + struct kvm_cpu { pthread_t thread; diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c index df90c7b..a17b957 100644 --- a/riscv/kvm-cpu.c +++ b/riscv/kvm-cpu.c @@ -18,17 +18,6 @@ int kvm_cpu__get_debug_fd(void) return debug_fd; } -static __u64 __kvm_reg_id(__u64 type, __u64 idx, __u64 size) -{ - return KVM_REG_RISCV | type | idx | size; -} - -#if __riscv_xlen == 64 -#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64 -#else -#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32 -#endif - #define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \ KVM_REG_RISCV_CONFIG_REG(name), \ KVM_REG_SIZE_ULONG) From patchwork Mon Aug 15 10:13:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12943419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72D3CC00140 for ; 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([171.76.84.46]) by smtp.gmail.com with ESMTPSA id i190-20020a6254c7000000b0052d4f2e2f6asm6267437pfb.119.2022.08.15.03.13.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Aug 2022 03:13:46 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [PATCH kvmtool 3/5] riscv: Add Svpbmt extension support Date: Mon, 15 Aug 2022 15:43:23 +0530 Message-Id: <20220815101325.477694-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220815101325.477694-1-apatel@ventanamicro.com> References: <20220815101325.477694-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The Svpbmt extension allows PTE based memory attributes in page tables. This extension also allows Guest/VM to use PTE based memory attributes in VS-stage page tables so let us add it Guest/VM ISA string when KVM RISC-V supports it. Signed-off-by: Anup Patel --- riscv/fdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index 1818cf7..eb7851e 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -17,6 +17,7 @@ struct isa_ext_info { }; struct isa_ext_info isa_info_arr[] = { + {"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT}, }; static void dump_fdt(const char *dtb_file, void *fdt) From patchwork Mon Aug 15 10:13:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12943420 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E65BAC282E7 for ; Mon, 15 Aug 2022 10:15:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242545AbiHOKOm (ORCPT ); Mon, 15 Aug 2022 06:14:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242490AbiHOKOV (ORCPT ); Mon, 15 Aug 2022 06:14:21 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 796351929A for ; Mon, 15 Aug 2022 03:13:52 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id f30so6294928pfq.4 for ; Mon, 15 Aug 2022 03:13:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=dFKzWK8a4yXz4IM3nrzPfNkwPwctqNlzhtFsMB1wqCk=; b=mQEAZpYQ0EVvDahiUTuG7qmuHXN7H9wD4VlttXtK7HD43Z25oqTz4sFNhcb1MBdQV+ WqEAMvem+Z7ttYaPMozJ2GtZaYTPt79cUZgAmFDdJ03twbf1NPPB/5SWJDxovSpntkZ1 l3RPrkuRWOhTX1ihLufr+OnUrf1+Rm6OxwJPXZdAZIRkm2+bS8of0+bDF1EHp0G2vgz9 kGdL1x489bwuMXunyEUkS5yAftbeCRbiPCAe5Si50XS2eSNeFr+4ghZ2SrTzP7FCNboY bHlBG69v153LAexHsmQ5TZmzYQlT+nAj3u/w9c2dkkCQ6U6tvSOYa2X78Cob/bgAt0k9 GicA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=dFKzWK8a4yXz4IM3nrzPfNkwPwctqNlzhtFsMB1wqCk=; b=mPNFzz7JGs7QY9O1BW1cPWB8pB/6+1IBUipPrUfnBrChVTgA86WpO757bt7y88SHLz cXOYPRwQsrsRLYD098DFqf0BRSs9bVZBnvfSXAMNPBnF1JT1Eemu+vUQBdlXuXBzeYRv 6EVJD2VluhC9rQG1II0c5IPH3t9bh+Qt0nFLAMuM6pRjg5Rkr05cOPQiakZ/la9GWj8L +cCEyBIlYY5pFGth9CPySnXcPQXu29keGSyK34k24fEFS/EfFT1h0ZOewnpvuW7yq0mL FbQopmhG0kv0ORZagNF3PwybHHgGIgaCAQqQjwqA5nQ/hE9rQmRHVKBKLGqTy4Ma+MpI mLdA== X-Gm-Message-State: ACgBeo0R/DOORUSXOR8FOFXCNyWDXd+cq+72vldQOA7tjJIUuJpXPQd6 raXrHFlbOAAS5XkVc0ewEZiCVBIwFxuR+A== X-Google-Smtp-Source: AA6agR4YrU02hkB6ryQizenDJpvTjG1tvszIQSB8Cn/CJIYXgttujnGGifI9OkjGT9OMCGuwML5KSw== X-Received: by 2002:a62:e114:0:b0:52d:24b6:a89 with SMTP id q20-20020a62e114000000b0052d24b60a89mr15843272pfh.65.1660558431589; Mon, 15 Aug 2022 03:13:51 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.84.46]) by smtp.gmail.com with ESMTPSA id i190-20020a6254c7000000b0052d4f2e2f6asm6267437pfb.119.2022.08.15.03.13.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Aug 2022 03:13:50 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra , Anup Patel Subject: [PATCH kvmtool 4/5] riscv: Add Sstc extension support Date: Mon, 15 Aug 2022 15:43:24 +0530 Message-Id: <20220815101325.477694-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220815101325.477694-1-apatel@ventanamicro.com> References: <20220815101325.477694-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Atish Patra Sstc extension allows the guest OS to program the timer directly without relying on the SBI call. The kernel detects the presence of Sstc extnesion from the riscv,isa DT property. Add the Sstc extension to the device tree if it is supported by the host. Signed-off-by: Atish Patra Signed-off-by: Anup Patel --- riscv/fdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index eb7851e..aeba042 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -18,6 +18,7 @@ struct isa_ext_info { struct isa_ext_info isa_info_arr[] = { {"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT}, + {"sstc", KVM_RISCV_ISA_EXT_SSTC}, }; static void dump_fdt(const char *dtb_file, void *fdt) From patchwork Mon Aug 15 10:13:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12943421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 979A1C00140 for ; Mon, 15 Aug 2022 10:15:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242359AbiHOKPE (ORCPT ); Mon, 15 Aug 2022 06:15:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242525AbiHOKO0 (ORCPT ); Mon, 15 Aug 2022 06:14:26 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FBEC237E0 for ; Mon, 15 Aug 2022 03:13:57 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id o3so5982784ple.5 for ; Mon, 15 Aug 2022 03:13:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=IWTUh3iHbEb9pKm4ekruP42bdO6T5Kf1OPdg5bKcFFY=; b=hs8JZ2qN2qrEX3eOADSLayJdksTSs20yujb94oPfHNp/Kv/0nWiquIFXCE7fgNIIPz xBzsS24ShG5QvwDFoFjVVyoxfZDKQ5N3Vy0jzzY8WEofn5IksBwqSnGC5jNSCOPhSxn+ oFgx0IV5AydJ1t+97pSkFoLMuxtpX3suJ0zh5xTW7POWU/lbsINpCodwK4PgCzSGhV8m rPDsrxdR9ZAdDcwtZ+ZZZD0OLrtzQm/RYQwcucH3fg+L8Q97lwjdvTpNBBO2oRaBmOqi QoHI4OSJNUyKCY3+WGhqq8n8AOUQrC40yymajR26ktI2n2ij7U5qtmlloyBIqHFKkuMC G0YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=IWTUh3iHbEb9pKm4ekruP42bdO6T5Kf1OPdg5bKcFFY=; b=POfmRQyOvvAXjCBKz3U6D7pwzGWl/cFeLTbN9n0++dAc6WEvfxGVJEnL6FZfnn4HB8 3F3BaXwAipQ75IzZzmvEEapMG8yXeZo6B6IYBGxLinIaPXLjocmc1baC1g2d7mgQz9KK 3Ovsm5R43/wMZWViGWok8fGTOzNNq0iWjsSsMnu9oqHxOGZABmm5jayWL81/stNg9ExS Am2jg4MRvg6eNpM7wNSxuAM06+4eSdJuBwEIpn0x8fC39nlQz4o+7dQj4M0Csy13iqUF IACkJ89l0bz2qHWKLmKrwSWL/79vbNaQ3cywn5F9YK0XjlKX+WeHUNFWNsuIO4Wc5PQ1 a5cg== X-Gm-Message-State: ACgBeo2ZcOi3UzOfWDo4cjWSyPxrp+GrM42LuBwZPLAOyztJ2EGwcEtC YM9XLHZYpmUmYMGuIsgXUaiGeZfWDGlNwg== X-Google-Smtp-Source: AA6agR7e4z4yL9cHsHmNZBsmwSBeF40lbm/phYGDuKLJVl2x6I+ye3+yQV+ERxuYj6vtGLmf4dcdlw== X-Received: by 2002:a17:90a:7407:b0:1f4:fe7e:bd51 with SMTP id a7-20020a17090a740700b001f4fe7ebd51mr27412621pjg.218.1660558435881; Mon, 15 Aug 2022 03:13:55 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.84.46]) by smtp.gmail.com with ESMTPSA id i190-20020a6254c7000000b0052d4f2e2f6asm6267437pfb.119.2022.08.15.03.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Aug 2022 03:13:55 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [PATCH kvmtool 5/5] riscv: Fix serial0 alias path Date: Mon, 15 Aug 2022 15:43:25 +0530 Message-Id: <20220815101325.477694-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220815101325.477694-1-apatel@ventanamicro.com> References: <20220815101325.477694-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We have all MMIO devices under "/smb" DT node so the serial0 alias path should have "/smb" prefix. Fixes: 7c9aac003925 ("riscv: Generate FDT at runtime for Guest/VM") Signed-off-by: Anup Patel --- riscv/fdt.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/riscv/fdt.c b/riscv/fdt.c index aeba042..e3d7717 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -122,6 +122,7 @@ static int setup_fdt(struct kvm *kvm) cpu_to_fdt64(kvm->arch.memory_guest_start), cpu_to_fdt64(kvm->ram_size), }; + char *str; void *fdt = staging_fdt; void *fdt_dest = guest_flat_to_host(kvm, kvm->arch.dtb_guest_start); @@ -205,12 +206,15 @@ static int setup_fdt(struct kvm *kvm) _FDT(fdt_end_node(fdt)); if (fdt_stdout_path) { - _FDT(fdt_begin_node(fdt, "aliases")); - _FDT(fdt_property_string(fdt, "serial0", fdt_stdout_path)); - _FDT(fdt_end_node(fdt)); - + str = malloc(strlen(fdt_stdout_path) + strlen("/smb") + 1); + sprintf(str, "/smb%s", fdt_stdout_path); free(fdt_stdout_path); fdt_stdout_path = NULL; + + _FDT(fdt_begin_node(fdt, "aliases")); + _FDT(fdt_property_string(fdt, "serial0", str)); + _FDT(fdt_end_node(fdt)); + free(str); } /* Finalise. */