From patchwork Tue Aug 16 21:48:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12945324 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B02F76AA9 for ; Tue, 16 Aug 2022 21:49:32 +0000 (UTC) Received: by mail-pl1-f169.google.com with SMTP id jm11so8163380plb.13 for ; Tue, 16 Aug 2022 14:49:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Dpx0PwACWbQFxixTVFk/61UCM3kuZHHFS7n8j4zijMQ=; b=FRgbWwyP7EWE0icWc2RFJVeZqv8kIQ0lB0mhEn/eyAI/mpax2GzRstd2pefdvVa8Zf gxkDlWiw3KbxMal0E/z1DZyUnGQ0WglhfDOcD1ksrq2mnzOrGbYktsaIy7HmklrycNew 5x9yabw9ILeGKD/r52jqw0eoGHIQPp5626BeI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Dpx0PwACWbQFxixTVFk/61UCM3kuZHHFS7n8j4zijMQ=; b=LGgkvIojdkFAScF3WYunjvE1ds+P0lPgR8sB5CkRmIWZJ2SNa/MN1KzpIwQ5iohdm5 L1btvlbtE95OUZT+1m/+oMvszwNizZ+ov7g159mbanfOIrPSKfw8D2wtrawsB7aSh43O KxenNzYH+c4TiqZG+5wVv34uQqKUzHwiAQCrAKPfgQapzYilqws6lYqcXAlpTmU1+9ze oOvU7ptijvfaFs/WByB7nXLomxYJ+acx1IQucHVdAiwp5hB6mzcPZmEs4bTIjMOFvtJ0 eHjs5KcOye7i6k0tWN838kKaKtKuLVEvjngxUzoIonSCS8kjmMqb3lj3Ow+0BpPTKFWl TTCA== X-Gm-Message-State: ACgBeo3NHGzelxmSYHBbBtPJXw61Hc3lfOTJQFZuPCakDFVrIn6uOcDE ku6qQqqOrHIZTqTN9iVnfsqwGA== X-Google-Smtp-Source: AA6agR7TNB5zQ63ecTmqMx8UI/o9MDKSbE814YlS5wFCIQHu/6qamsTObsVT65zOn9TQ///HUVDcVA== X-Received: by 2002:a17:90a:bb96:b0:1f4:414a:d89e with SMTP id v22-20020a17090abb9600b001f4414ad89emr606470pjr.240.1660686572172; Tue, 16 Aug 2022 14:49:32 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id z5-20020a623305000000b005323a1a9fecsm8916650pfz.101.2022.08.16.14.49.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:49:31 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Tzung-Bi Shih , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Sebastian Reichel , Tinghan Shen , Xiang wangx Subject: [PATCH v6 1/7] platform/chrome: Add Type-C mux set command definitions Date: Tue, 16 Aug 2022 21:48:29 +0000 Message-Id: <20220816214857.2088914-2-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220816214857.2088914-1-pmalani@chromium.org> References: <20220816214857.2088914-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Copy EC header definitions for the USB Type-C Mux control command from the EC code base. Also pull in "TBT_UFP_REPLY" definitions, since that is the prior entry in the enum. These headers are already present in the EC code base. [1] [1] https://chromium.googlesource.com/chromiumos/platform/ec/+/b80f85a94a423273c1638ef7b662c56931a138dd/include/ec_commands.h Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v5: - Picked by Reviewed-by tag. - No functional changes. Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. include/linux/platform_data/cros_ec_commands.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h index 8b1b795867a1..5744a2d746aa 100644 --- a/include/linux/platform_data/cros_ec_commands.h +++ b/include/linux/platform_data/cros_ec_commands.h @@ -5724,8 +5724,21 @@ enum typec_control_command { TYPEC_CONTROL_COMMAND_EXIT_MODES, TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY, + TYPEC_CONTROL_COMMAND_USB_MUX_SET, }; +/* Replies the AP may specify to the TBT EnterMode command as a UFP */ +enum typec_tbt_ufp_reply { + TYPEC_TBT_UFP_REPLY_NAK, + TYPEC_TBT_UFP_REPLY_ACK, +}; + +struct typec_usb_mux_set { + uint8_t mux_index; /* Index of the mux to set in the chain */ + uint8_t mux_flags; /* USB_PD_MUX_*-encoded USB mux state to set */ +} __ec_align1; + struct ec_params_typec_control { uint8_t port; uint8_t command; /* enum typec_control_command */ @@ -5739,6 +5752,8 @@ struct ec_params_typec_control { union { uint32_t clear_events_mask; uint8_t mode_to_enter; /* enum typec_mode */ + uint8_t tbt_ufp_reply; /* enum typec_tbt_ufp_reply */ + struct typec_usb_mux_set mux_params; uint8_t placeholder[128]; }; } __ec_align1; @@ -5817,6 +5832,9 @@ enum tcpc_cc_polarity { #define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) #define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) #define PD_STATUS_EVENT_HARD_RESET BIT(2) +#define PD_STATUS_EVENT_DISCONNECTED BIT(3) +#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4) +#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5) struct ec_params_typec_status { uint8_t port; From patchwork Tue Aug 16 21:48:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12945325 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00FB46AA9 for ; Tue, 16 Aug 2022 21:49:55 +0000 (UTC) Received: by mail-pl1-f169.google.com with SMTP id jm11so8164094plb.13 for ; Tue, 16 Aug 2022 14:49:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Q4zoMhmVpBlLqmtSRNrbVa7gTMbKl6eNBoUi0qpgn3E=; b=fCPsDw/r5fnExQMIkEHHsstPyHzT5sJhS0E8Qa217xg+unHhETgPfWdqTePf9TKlLm OIV0gDs2sWTN9L+gNlxsELPYR2onBQmgagXLzKsD+aykTvuNHWt4LQqRnYjB1mDhpeFN T9nGQdvC8VYfgd8PWjFoo5fthfVPwYlHENHTo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Q4zoMhmVpBlLqmtSRNrbVa7gTMbKl6eNBoUi0qpgn3E=; b=d1rE+wPJPyt01SV562EiEM123cSDCJPjs8uXHYUjHogfNwvM+J77l5mM7+TnnqnPtP VbDcHLk/H41wVnbyM8i5z37lMMB6otfYGUCDDKVCSNMoufOs6eqcPLZEVF5unRemyTAe bN05keSN+1FsAdNcoA+w0EXhtqV8RMeBd0jjhqQDtl88+2jjqD3QUslhM1iHOkGiVp9h RyPavxzcVMk8OJjDKVVn+sejlWo57y2ktcve1D7FnnV9/uWMroOyF8VWfmk25DSrxpKp N6Dijtc6dgXEjU5MCdwqy3xE9DWhRRwn4ZHwXSbb4at8dxfYlWcSbGe/P7ktCKGZ9TFD M5gw== X-Gm-Message-State: ACgBeo1wFaYzyoLAFFL2lR6mb2U4R1cZ37RSN1N7huQ9oS7MvDTZQOyr g/sNZZWvo598jcpKwUxJUzbq+w== X-Google-Smtp-Source: AA6agR5AdidDLEA9mMTsAH8df/6yVyuy7N/c/eFNbzd/K+0cy/zrKKtVDvh4sCNr7iD53su7FYqoaw== X-Received: by 2002:a17:902:f64a:b0:172:7576:2124 with SMTP id m10-20020a170902f64a00b0017275762124mr8101036plg.155.1660686595664; Tue, 16 Aug 2022 14:49:55 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id z5-20020a623305000000b005323a1a9fecsm8916650pfz.101.2022.08.16.14.49.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:49:55 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Lee Jones , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v6 2/7] platform/chrome: cros_typec_switch: Add switch driver Date: Tue, 16 Aug 2022 21:48:30 +0000 Message-Id: <20220816214857.2088914-3-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220816214857.2088914-1-pmalani@chromium.org> References: <20220816214857.2088914-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce a driver to configure USB Type-C mode switches and retimers which are controlled by the ChromeOS EC (Embedded Controller). This allows Type-C port drivers, as well as alternate mode drivers to configure their relevant mode switches and retimers according to the Type-C state they want to achieve. ACPI devices with ID GOOG001A will bind to this driver. Currently, we only register a retimer switch with a stub set function. Subsequent patches will implement the host command set functionality, and introduce mode switches. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v5: - Change "Chrome OS -> "ChromeOS". - Change "Type C" -> "Type-C". - Remove unnecessary variable init in cros_typec_register_switches(). Changes since v4: - Add ACPI dependency to Kconfig. Changes since v3: - No changes. Changes since v2: - Fixed missing "static" identifier. - Removed unnecessary new line for function signature. Changes since v1: - No changes. MAINTAINERS | 1 + drivers/platform/chrome/Kconfig | 11 ++ drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_typec_switch.c | 169 ++++++++++++++++++++ 4 files changed, 182 insertions(+) create mode 100644 drivers/platform/chrome/cros_typec_switch.c diff --git a/MAINTAINERS b/MAINTAINERS index 8a5012ba6ff9..c1e4977cb1c3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4894,6 +4894,7 @@ M: Prashant Malani L: chrome-platform@lists.linux.dev S: Maintained F: drivers/platform/chrome/cros_ec_typec.c +F: drivers/platform/chrome/cros_typec_switch.c CHROMEOS EC USB PD NOTIFY DRIVER M: Prashant Malani diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig index c45fb376d653..6b954c5acadb 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -265,6 +265,17 @@ config CHROMEOS_PRIVACY_SCREEN this should probably always be built into the kernel to avoid or minimize drm probe deferral. +config CROS_TYPEC_SWITCH + tristate "ChromeOS EC Type-C Switch Control" + depends on MFD_CROS_EC_DEV && TYPEC && ACPI + default MFD_CROS_EC_DEV + help + If you say Y here, you get support for configuring the ChromeOS EC Type-C + muxes and retimers. + + To compile this driver as a module, choose M here: the module will be + called cros_typec_switch. + source "drivers/platform/chrome/wilco_ec/Kconfig" # Kunit test cases diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index f7e74a845afc..2950610101f1 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CHROMEOS_TBMC) += chromeos_tbmc.o obj-$(CONFIG_CROS_EC) += cros_ec.o obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_ISHTP) += cros_ec_ishtp.o +obj-$(CONFIG_CROS_TYPEC_SWITCH) += cros_typec_switch.o obj-$(CONFIG_CROS_EC_RPMSG) += cros_ec_rpmsg.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c new file mode 100644 index 000000000000..db773bf57899 --- /dev/null +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2022 Google LLC + * + * This driver provides the ability to configure Type-C muxes and retimers which are controlled by + * the ChromeOS EC. + */ + +#include +#include +#include +#include +#include + +#define DRV_NAME "cros-typec-switch" + +/* Handles and other relevant data required for each port's switches. */ +struct cros_typec_port { + int port_num; + struct typec_retimer *retimer; + struct cros_typec_switch_data *sdata; +}; + +/* Driver-specific data. */ +struct cros_typec_switch_data { + struct device *dev; + struct cros_ec_device *ec; + struct cros_typec_port *ports[EC_USB_PD_MAX_PORTS]; +}; + +static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_retimer_state *state) +{ + return 0; +} + +static void cros_typec_unregister_switches(struct cros_typec_switch_data *sdata) +{ + int i; + + for (i = 0; i < EC_USB_PD_MAX_PORTS; i++) { + if (!sdata->ports[i]) + continue; + typec_retimer_unregister(sdata->ports[i]->retimer); + } +} + +static int cros_typec_register_retimer(struct cros_typec_port *port, struct fwnode_handle *fwnode) +{ + struct typec_retimer_desc retimer_desc = { + .fwnode = fwnode, + .drvdata = port, + .name = fwnode_get_name(fwnode), + .set = cros_typec_retimer_set, + }; + + port->retimer = typec_retimer_register(port->sdata->dev, &retimer_desc); + if (IS_ERR(port->retimer)) + return PTR_ERR(port->retimer); + + return 0; +} + +static int cros_typec_register_switches(struct cros_typec_switch_data *sdata) +{ + struct cros_typec_port *port; + struct device *dev = sdata->dev; + struct fwnode_handle *fwnode; + struct acpi_device *adev; + unsigned long long index; + int nports, ret; + + nports = device_get_child_node_count(dev); + if (nports == 0) { + dev_err(dev, "No switch devices found.\n"); + return -ENODEV; + } + + device_for_each_child_node(dev, fwnode) { + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) { + ret = -ENOMEM; + goto err_switch; + } + + adev = to_acpi_device_node(fwnode); + if (!adev) { + dev_err(fwnode->dev, "Couldn't get ACPI device handle\n"); + ret = -ENODEV; + goto err_switch; + } + + ret = acpi_evaluate_integer(adev->handle, "_ADR", NULL, &index); + if (ACPI_FAILURE(ret)) { + dev_err(fwnode->dev, "_ADR wasn't evaluated\n"); + ret = -ENODATA; + goto err_switch; + } + + if (index < 0 || index >= EC_USB_PD_MAX_PORTS) { + dev_err(fwnode->dev, "Invalid port index number: %llu", index); + ret = -EINVAL; + goto err_switch; + } + port->sdata = sdata; + port->port_num = index; + sdata->ports[index] = port; + + ret = cros_typec_register_retimer(port, fwnode); + if (ret) { + dev_err(dev, "Retimer switch register failed\n"); + goto err_switch; + } + + dev_dbg(dev, "Retimer switch registered for index %llu\n", index); + } + + return 0; +err_switch: + cros_typec_unregister_switches(sdata); + return ret; +} + +static int cros_typec_switch_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cros_typec_switch_data *sdata; + + sdata = devm_kzalloc(dev, sizeof(*sdata), GFP_KERNEL); + if (!sdata) + return -ENOMEM; + + sdata->dev = dev; + sdata->ec = dev_get_drvdata(pdev->dev.parent); + + platform_set_drvdata(pdev, sdata); + + return cros_typec_register_switches(sdata); +} + +static int cros_typec_switch_remove(struct platform_device *pdev) +{ + struct cros_typec_switch_data *sdata = platform_get_drvdata(pdev); + + cros_typec_unregister_switches(sdata); + return 0; +} + +#ifdef CONFIG_ACPI +static const struct acpi_device_id cros_typec_switch_acpi_id[] = { + { "GOOG001A", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, cros_typec_switch_acpi_id); +#endif + +static struct platform_driver cros_typec_switch_driver = { + .driver = { + .name = DRV_NAME, + .acpi_match_table = ACPI_PTR(cros_typec_switch_acpi_id), + }, + .probe = cros_typec_switch_probe, + .remove = cros_typec_switch_remove, +}; + +module_platform_driver(cros_typec_switch_driver); + +MODULE_AUTHOR("Prashant Malani "); +MODULE_DESCRIPTION("ChromeOS EC Type-C Switch control"); +MODULE_LICENSE("GPL"); From patchwork Tue Aug 16 21:48:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12945326 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 386776AA9 for ; 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[34.168.22.137]) by smtp.gmail.com with ESMTPSA id z5-20020a623305000000b005323a1a9fecsm8916650pfz.101.2022.08.16.14.50.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:50:26 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Kees Cook , Sebastian Reichel , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v6 3/7] platform/chrome: cros_typec_switch: Set EC retimer Date: Tue, 16 Aug 2022 21:48:31 +0000 Message-Id: <20220816214857.2088914-4-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220816214857.2088914-1-pmalani@chromium.org> References: <20220816214857.2088914-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Invoke ChromeOS EC host commands to set EC-controlled retimer switches to the state the Type-C framework instructs. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v5: - Change "Chrome OS" -> "ChromeOS". - Change "Type C" -> "Type-C". - Inline mux_params struct initialization. - Make cros_ec_cmd() invocation fit on 1 line. Changes since v4: - Update cros_ec_command() to cros_ec_cmd(). Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. drivers/platform/chrome/cros_typec_switch.c | 53 ++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c index db773bf57899..eae7d26416aa 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -9,7 +9,10 @@ #include #include #include +#include #include +#include +#include #include #define DRV_NAME "cros-typec-switch" @@ -28,9 +31,57 @@ struct cros_typec_switch_data { struct cros_typec_port *ports[EC_USB_PD_MAX_PORTS]; }; +static int cros_typec_cmd_mux_set(struct cros_typec_switch_data *sdata, int port_num, u8 index, + u8 state) +{ + struct ec_params_typec_control req = { + .port = port_num, + .command = TYPEC_CONTROL_COMMAND_USB_MUX_SET, + .mux_params = { + .mux_index = index, + .mux_flags = state, + }, + }; + + return cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_CONTROL, &req, sizeof(req), NULL, 0); +} + +static int cros_typec_get_mux_state(unsigned long mode, struct typec_altmode *alt) +{ + int ret = -EOPNOTSUPP; + + if (mode == TYPEC_STATE_SAFE) + ret = USB_PD_MUX_SAFE_MODE; + else if (mode == TYPEC_STATE_USB) + ret = USB_PD_MUX_USB_ENABLED; + else if (alt && alt->svid == USB_TYPEC_DP_SID) + ret = USB_PD_MUX_DP_ENABLED; + + return ret; +} + +/* + * The ChromeOS EC treats both mode-switches and retimers as "muxes" for the purposes of the + * host command API. This common function configures and verifies the retimer/mode-switch + * according to the provided setting. + */ +static int cros_typec_configure_mux(struct cros_typec_switch_data *sdata, int port_num, int index, + unsigned long mode, struct typec_altmode *alt) +{ + int ret = cros_typec_get_mux_state(mode, alt); + + if (ret < 0) + return ret; + + return cros_typec_cmd_mux_set(sdata, port_num, index, (u8)ret); +} + static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_retimer_state *state) { - return 0; + struct cros_typec_port *port = typec_retimer_get_drvdata(retimer); + + /* Retimers have index 1. */ + return cros_typec_configure_mux(port->sdata, port->port_num, 1, state->mode, state->alt); } static void cros_typec_unregister_switches(struct cros_typec_switch_data *sdata) From patchwork Tue Aug 16 21:48:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12945327 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 618A36AA9 for ; Tue, 16 Aug 2022 21:51:01 +0000 (UTC) Received: by mail-pj1-f43.google.com with SMTP id ch17-20020a17090af41100b001fa74771f61so2292460pjb.0 for ; Tue, 16 Aug 2022 14:51:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=tjMBMSeLf47Dl9twMgr77h09YFRDoxykrXGPZHBAccY=; b=MbZdnqhDu3qlh1Cy6jJRu1PFT0mgvRF/UzbWWvdiCnSbqwBAcPduwys9Yt977aNLAR t8FY7+27CjCn906Nnnt+DEXHYIYioH9+Wq0L54MGDpk95ih6PHETpfmhZ5dSi40pxART 3QauOv9pmCCfcr6Gv1gtFLfjKqgKt46BW9VkY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=tjMBMSeLf47Dl9twMgr77h09YFRDoxykrXGPZHBAccY=; b=Moh/WKpW4PSJX7fAdzR5jTE3Q888sUyXZ8Rrcpsu+NDpPHxY8ybPYBFo/gq4eORivV sF02rU7AeKZYJfpwN96SXKhRo6K24zObvOt6tRxyRiwnV5NJA/CVHWHozXlYcHSwkbjg L6ayE/yPca5epQDE/i6begQsc5wpXG1J6z2igjymACfAO+e66jr2ZLZY5DiEeeiMwuRG 7XWJnhK3X+Yr2yEbIhohpX0DP2uEYskBihXmBnmYWLVwAk53a7dihXJxAo0eoqxmXdcP 3n4aZf6vO9H/OhpMuYrCh/BYaITXpiszm/OC3HwXVrzga8iVfENbxlrXHh/YIegPZkQ7 CLDw== X-Gm-Message-State: ACgBeo2p2LiScFbG1gzKEFYGDWpplxGM4SN7ySZ1GF+7G9i4RAYi0+3r mwfRrfg1rSojTHDQK/CM9fayAjri/Wdxvw== X-Google-Smtp-Source: AA6agR4vBYgz2zHsn0+x4VIXE126q6rD9Mi4i/Y2ISPSXNn4+YYi9wPEDAkrdZ0LoEcwyduFjRNWgQ== X-Received: by 2002:a17:90b:1bd0:b0:1f3:396f:9942 with SMTP id oa16-20020a17090b1bd000b001f3396f9942mr573956pjb.220.1660686660978; Tue, 16 Aug 2022 14:51:00 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id z5-20020a623305000000b005323a1a9fecsm8916650pfz.101.2022.08.16.14.51.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:51:00 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Kees Cook , Lee Jones , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v6 4/7] platform/chrome: cros_typec_switch: Add event check Date: Tue, 16 Aug 2022 21:48:32 +0000 Message-Id: <20220816214857.2088914-5-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220816214857.2088914-1-pmalani@chromium.org> References: <20220816214857.2088914-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ChromeOS EC updates Type-C status events when mux set requests from the Application Processor (AP) are completed. Add a check to the flow of configuring muxes to look for this status done bit, so that the driver is aware that the mux set completed successfully or not. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v5: - Change "Chrome OS" -> "ChromeOS". - Make cros_ec_cmd() invocation fit on 1 line. Changes since v4: - Update cros_ec_command() to cros_ec_cmd(). - Dropped unnecessary Reported-by tag (since this patch is not a bug fix). Changes since v3: - No changes. Changes since v2: - Fixed missing "static" identifier. Changes since v1: - No changes. drivers/platform/chrome/cros_typec_switch.c | 71 ++++++++++++++++++++- 1 file changed, 69 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c index eae7d26416aa..dc84cdec8f7f 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -7,6 +7,8 @@ */ #include +#include +#include #include #include #include @@ -60,6 +62,39 @@ static int cros_typec_get_mux_state(unsigned long mode, struct typec_altmode *al return ret; } +static int cros_typec_send_clear_event(struct cros_typec_switch_data *sdata, int port_num, + u32 events_mask) +{ + struct ec_params_typec_control req = { + .port = port_num, + .command = TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, + .clear_events_mask = events_mask, + }; + + return cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_CONTROL, &req, sizeof(req), NULL, 0); +} + +static bool cros_typec_check_event(struct cros_typec_switch_data *sdata, int port_num, u32 mask) +{ + struct ec_response_typec_status resp; + struct ec_params_typec_status req = { + .port = port_num, + }; + int ret; + + ret = cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_STATUS, &req, sizeof(req), + &resp, sizeof(resp)); + if (ret < 0) { + dev_warn(sdata->dev, "EC_CMD_TYPEC_STATUS failed for port: %d\n", port_num); + return false; + } + + if (resp.events & mask) + return true; + + return false; +} + /* * The ChromeOS EC treats both mode-switches and retimers as "muxes" for the purposes of the * host command API. This common function configures and verifies the retimer/mode-switch @@ -68,12 +103,44 @@ static int cros_typec_get_mux_state(unsigned long mode, struct typec_altmode *al static int cros_typec_configure_mux(struct cros_typec_switch_data *sdata, int port_num, int index, unsigned long mode, struct typec_altmode *alt) { - int ret = cros_typec_get_mux_state(mode, alt); + unsigned long end; + u32 event_mask; + u8 mux_state; + int ret; + + ret = cros_typec_get_mux_state(mode, alt); + if (ret < 0) + return ret; + mux_state = (u8)ret; + + /* Clear any old mux set done event. */ + if (index == 0) + event_mask = PD_STATUS_EVENT_MUX_0_SET_DONE; + else + event_mask = PD_STATUS_EVENT_MUX_1_SET_DONE; + ret = cros_typec_send_clear_event(sdata, port_num, event_mask); if (ret < 0) return ret; - return cros_typec_cmd_mux_set(sdata, port_num, index, (u8)ret); + /* Send the set command. */ + ret = cros_typec_cmd_mux_set(sdata, port_num, index, mux_state); + if (ret < 0) + return ret; + + /* Check for the mux set done event. */ + end = jiffies + msecs_to_jiffies(1000); + do { + if (cros_typec_check_event(sdata, port_num, event_mask)) + return 0; + + usleep_range(500, 1000); + } while (time_before(jiffies, end)); + + dev_err(sdata->dev, "Timed out waiting for mux set done on index: %d, state: %d\n", + index, mux_state); + + return -ETIMEDOUT; } static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_retimer_state *state) From patchwork Tue Aug 16 21:48:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12945328 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87F646AA9 for ; Tue, 16 Aug 2022 21:51:28 +0000 (UTC) Received: by mail-pl1-f179.google.com with SMTP id c2so2025690plo.3 for ; Tue, 16 Aug 2022 14:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=V/HBLUGtbrafHDulaBOAprTvFvaFzo8t7Aw95pdiRo4=; b=FR1I6kqyyzfgEPe7rWRaKSh18xY/1LGfk3cjVcbvWKfPteUhAaHpUJbC008d/iCqZx Nb8O+c25QOEO989XAH3yS7KXALbBav/48cXQZATiHgypiOh36KlcpgQPtO8m6bIcFSaX dVdAzk8Qku5a5AZ+6K2eneVmQqTpi8evjyquI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=V/HBLUGtbrafHDulaBOAprTvFvaFzo8t7Aw95pdiRo4=; b=WQUqr54ScNtvJKwBw3oVfmIu5RcO8rCDsAOdKPUbxE7UmB1sxfcWPz19F8178y5rn5 HglwT5++Div1qvDHpB6EWI71+9icCtATZUatGThxanoYludwX3H3F9KD/rqWONMWM8HK myqq9bETkhCUvZkPnrJzKB5exEho/muRcdlsWGB6ZdlJ7W6Q/z5k3u2/a1MgSWjwiLLw YVyCdynrrAlUp0pCgcCvweI7nsaIaWd0MdUD7G5kXxcxs8P6C2c7k//gfGCbQKCGi2+Y Sl9EkZVJeWmUNYAOLtG5PZm287VMQFNf1Pp/7Q7rixi+EDlFQm/5zGHIXYy5xyxospkc UDrw== X-Gm-Message-State: ACgBeo3+Jb3kpm0j25xs47/sa7XV56oSuYsfHRIrIbJGJbDULdMcgc9c +iuHx+IZrD2MMvuH728+hpcwgw== X-Google-Smtp-Source: AA6agR7zQmHstsMNN6y95CEPVGXA2copp9QkGVlEg4zN3irJ5gdVFcpG71l1MNHoPClicMycG1svag== X-Received: by 2002:a17:902:aa87:b0:172:689f:106b with SMTP id d7-20020a170902aa8700b00172689f106bmr14026659plr.127.1660686688000; Tue, 16 Aug 2022 14:51:28 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id z5-20020a623305000000b005323a1a9fecsm8916650pfz.101.2022.08.16.14.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:51:27 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Tinghan Shen , Tzung-Bi Shih , Xiang wangx Subject: [PATCH v6 5/7] platform/chrome: cros_typec_switch: Register mode switches Date: Tue, 16 Aug 2022 21:48:33 +0000 Message-Id: <20220816214857.2088914-6-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220816214857.2088914-1-pmalani@chromium.org> References: <20220816214857.2088914-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Register mode switch devices for Type-C connectors, when they are specified by firmware. These control Type-C configuration for any USB Type-C mode switches (sometimes known as "muxes") which are controlled by the ChromeOS EC. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v5: - Change "Chrome OS" -> "ChromeOS". - Change "Type C" -> "Type-C". - Use device_property_present instead of fwnode_property_read_bool. Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - Fixed missing "static" identifier. Changes since v1: - No changes. drivers/platform/chrome/cros_typec_switch.c | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c index dc84cdec8f7f..f85687adb594 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #define DRV_NAME "cros-typec-switch" @@ -22,6 +23,7 @@ /* Handles and other relevant data required for each port's switches. */ struct cros_typec_port { int port_num; + struct typec_mux_dev *mode_switch; struct typec_retimer *retimer; struct cros_typec_switch_data *sdata; }; @@ -143,6 +145,15 @@ static int cros_typec_configure_mux(struct cros_typec_switch_data *sdata, int po return -ETIMEDOUT; } +static int cros_typec_mode_switch_set(struct typec_mux_dev *mode_switch, + struct typec_mux_state *state) +{ + struct cros_typec_port *port = typec_mux_get_drvdata(mode_switch); + + /* Mode switches have index 0. */ + return cros_typec_configure_mux(port->sdata, port->port_num, 0, state->mode, state->alt); +} + static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_retimer_state *state) { struct cros_typec_port *port = typec_retimer_get_drvdata(retimer); @@ -159,9 +170,27 @@ static void cros_typec_unregister_switches(struct cros_typec_switch_data *sdata) if (!sdata->ports[i]) continue; typec_retimer_unregister(sdata->ports[i]->retimer); + typec_mux_unregister(sdata->ports[i]->mode_switch); } } +static int cros_typec_register_mode_switch(struct cros_typec_port *port, + struct fwnode_handle *fwnode) +{ + struct typec_mux_desc mode_switch_desc = { + .fwnode = fwnode, + .drvdata = port, + .name = fwnode_get_name(fwnode), + .set = cros_typec_mode_switch_set, + }; + + port->mode_switch = typec_mux_register(port->sdata->dev, &mode_switch_desc); + if (IS_ERR(port->mode_switch)) + return PTR_ERR(port->mode_switch); + + return 0; +} + static int cros_typec_register_retimer(struct cros_typec_port *port, struct fwnode_handle *fwnode) { struct typec_retimer_desc retimer_desc = { @@ -230,6 +259,17 @@ static int cros_typec_register_switches(struct cros_typec_switch_data *sdata) } dev_dbg(dev, "Retimer switch registered for index %llu\n", index); + + if (!device_property_present(fwnode->dev, "mode-switch")) + continue; + + ret = cros_typec_register_mode_switch(port, fwnode); + if (ret) { + dev_err(dev, "Mode switch register failed\n"); + goto err_switch; + } + + dev_dbg(dev, "Mode switch registered for index %llu\n", index); } return 0; From patchwork Tue Aug 16 21:48:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12945330 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 255856AA9 for ; Tue, 16 Aug 2022 21:51:56 +0000 (UTC) Received: by mail-pl1-f177.google.com with SMTP id d16so10379017pll.11 for ; Tue, 16 Aug 2022 14:51:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=ZUDKiJcy/NR4RiCY5xiO+505IhInHi372I8JGaQYasY=; b=huvYyD9DsHp8RsAMq8umXLvqy3zdfey2HAeowr1WoEseaI+1cHIhtxaBWSPSrjiexw y6MQpFZJIoz2Oj2y1p+nbkxgrOfIJpttGB/lBK3ExogrNhH6b6S0jKD9jxLfp6Vwmuq7 1T0idtLboE4jZ4dpu+YtT6Lcd8R2EGilEXfY4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=ZUDKiJcy/NR4RiCY5xiO+505IhInHi372I8JGaQYasY=; b=fLPhFaPl5lKzn/thS5nzVCz2z4ii+rexnbdDXqL7V7WRVFwqHCdntye/PO8tYXHbgF EvaVTIsyYTj3/WLdaUJDyyPXPfF3GCKhEdAcTSBQ6gbWcHJZFUfevFTH8AZQCxgt8Vqb 7AVUEQSmfHg1bUYBcUtR60HyXIJHQpIpW3z6K6tJVPoiFrLM0S3GI4WxK/MotBR+WRnX 26C/DOn96LeIBUmgY0VPbwcvyrwhTy5Uu7XVOzUTC5lXPE86TJBihw5TJqeY8z6DYBC8 rRKVIfiZGrf1ceU4X+EZ6e6aUJ8/PkZByK1X2EWCwT6BWkYlpDqgVwxzLJHGV3HHEwRp rUyw== X-Gm-Message-State: ACgBeo0InJhVO7UIk5Bnk5kVUdHX3WnNHtMQ+BPBdjs8qd5z9KBZEnIw VJKkPmAOTYhEhft8FbIZ/gbQhA== X-Google-Smtp-Source: AA6agR4aSEdxsFuYhrYD+dK3r6Qv8LSY+0sTjAp4rl7A3rC6pwExZBKSQEAsNcsMXVpOct3lVsJ57g== X-Received: by 2002:a17:90b:3b8a:b0:1f5:1df2:1fff with SMTP id pc10-20020a17090b3b8a00b001f51df21fffmr578753pjb.169.1660686715695; Tue, 16 Aug 2022 14:51:55 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id z5-20020a623305000000b005323a1a9fecsm8916650pfz.101.2022.08.16.14.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:51:55 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Tzung-Bi Shih , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , "Gustavo A. R. Silva" , Lee Jones , Sebastian Reichel , Tinghan Shen Subject: [PATCH v6 6/7] platform/chrome: cros_ec_typec: Cleanup switch handle return paths Date: Tue, 16 Aug 2022 21:48:34 +0000 Message-Id: <20220816214857.2088914-7-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220816214857.2088914-1-pmalani@chromium.org> References: <20220816214857.2088914-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some of the return paths for the cros_typec_get_switch_handles() aren't necessary. Clean up the return paths to only undo the handle get's which succeeded. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v5: - Picked up Reviewed-by tags. Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. drivers/platform/chrome/cros_ec_typec.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index de6ee0f926a6..ee54add992db 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -158,12 +158,10 @@ static int cros_typec_get_switch_handles(struct cros_typec_port *port, return 0; role_sw_err: - usb_role_switch_put(port->role_sw); -ori_sw_err: typec_switch_put(port->ori_sw); -mux_err: +ori_sw_err: typec_mux_put(port->mux); - +mux_err: return -ENODEV; } From patchwork Tue Aug 16 21:48:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashant Malani X-Patchwork-Id: 12945331 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D57966AA9 for ; Tue, 16 Aug 2022 21:52:20 +0000 (UTC) Received: by mail-pl1-f171.google.com with SMTP id jm11so8168435plb.13 for ; Tue, 16 Aug 2022 14:52:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=ABHvUphZ0aIs8EGZBbtNv5cxZuZ8nYm2ItFqz4z9eZo=; b=gC2+U4BX0e8V7cnJCyV8KNzKXV3FB+nHx8CR5zFGwOvSMXsOtAVLamDDZcoCtSzmjn lbj3cM6R0gpLFvS3JZhnXXHjxEkMK0NFq1M5VoPxuKm7zFMF0Gk3RaoE2pHF+IRov5E4 HNSMfJr9DeNc5m+81ILqMI5pyIUVYw1XRTwh8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=ABHvUphZ0aIs8EGZBbtNv5cxZuZ8nYm2ItFqz4z9eZo=; b=R43ER54jG5cbTontCW2r9JdQIj3OO6/uNhMKg5qWjHa/XNjJi5Y8PG4hCS7NnB0LCd 62rLbWqXAh+iCiatFw9im1t7+RPpxW2LFxahy15ZILKcCO0MxE5euoDNVix9y66uQiTO jGsFaUw5uRhdpU2ZmfszgMErWsEquBrpI7WzJcXrQ9R/BZ6fg2sX3u3SO0thZD9rVPLy Kv/NXZzEmmGh7WRhKIVtNvVT8mmafbxvVmZh1OEvhY2XjcxZv9reK1PeSMgdETGKFrEW K2O0H9C/XE/lJuKp8HNZ6JcnX6kGBkSV0DgA7vDTU41bMnWQrzvGIFPQPAUTqDSqZYmT vUlg== X-Gm-Message-State: ACgBeo1XNAo3+LplyrT3CmQebQZXJG9RrgmfMvzrcznByw0y1CBx/06s tE8Rq8hcKiAsmL3GakEg4hB8hQ== X-Google-Smtp-Source: AA6agR4bdAQZGh1YJ8rZ+knDDc9jY0Kt1RJx/SZ5KJ/BVrfvCgeiDoA2MoCSv8CIy8EeoyOpj7fTtw== X-Received: by 2002:a17:902:9882:b0:172:793b:ccc3 with SMTP id s2-20020a170902988200b00172793bccc3mr6252689plp.27.1660686740371; Tue, 16 Aug 2022 14:52:20 -0700 (PDT) Received: from pmalani.c.googlers.com.com (137.22.168.34.bc.googleusercontent.com. [34.168.22.137]) by smtp.gmail.com with ESMTPSA id z5-20020a623305000000b005323a1a9fecsm8916650pfz.101.2022.08.16.14.52.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 14:52:20 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, Prashant Malani , Tzung-Bi Shih , Daisuke Nojiri , "Dustin L. Howett" , Greg Kroah-Hartman , Guenter Roeck , Kees Cook , Lee Jones , Sebastian Reichel , Tinghan Shen , Xiang wangx Subject: [PATCH v6 7/7] platform/chrome: cros_ec_typec: Get retimer handle Date: Tue, 16 Aug 2022 21:48:35 +0000 Message-Id: <20220816214857.2088914-8-pmalani@chromium.org> X-Mailer: git-send-email 2.37.1.595.g718a3a8f04-goog In-Reply-To: <20220816214857.2088914-1-pmalani@chromium.org> References: <20220816214857.2088914-1-pmalani@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Where available, obtain the handle to retimer switch specified via firmware, and update the mux configuration callsites to add retimer support for supported modes. Signed-off-by: Prashant Malani Reviewed-by: Tzung-Bi Shih --- Changes since v5: - Picked up Reviewed-by tag. - Removed double space. Changes since v4: - No changes. Changes since v3: - No changes. Changes since v2: - No changes. Changes since v1: - No changes. drivers/platform/chrome/cros_ec_typec.c | 44 +++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index ee54add992db..3ffe3c082ea2 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -55,6 +56,7 @@ struct cros_typec_port { struct usb_pd_identity c_identity; struct typec_switch *ori_sw; struct typec_mux *mux; + struct typec_retimer *retimer; struct usb_role_switch *role_sw; /* Variables keeping track of switch state. */ @@ -143,6 +145,12 @@ static int cros_typec_get_switch_handles(struct cros_typec_port *port, goto mux_err; } + port->retimer = fwnode_typec_retimer_get(fwnode); + if (IS_ERR(port->retimer)) { + dev_dbg(dev, "Retimer handle not found.\n"); + goto retimer_sw_err; + } + port->ori_sw = fwnode_typec_switch_get(fwnode); if (IS_ERR(port->ori_sw)) { dev_dbg(dev, "Orientation switch handle not found.\n"); @@ -160,6 +168,8 @@ static int cros_typec_get_switch_handles(struct cros_typec_port *port, role_sw_err: typec_switch_put(port->ori_sw); ori_sw_err: + typec_retimer_put(port->retimer); +retimer_sw_err: typec_mux_put(port->mux); mux_err: return -ENODEV; @@ -204,6 +214,21 @@ static void cros_typec_unregister_altmodes(struct cros_typec_data *typec, int po } } +/* + * Map the Type-C Mux state to retimer state and call the retimer set function. We need this + * because we re-use the Type-C mux state for retimers. + */ +static int cros_typec_retimer_set(struct typec_retimer *retimer, struct typec_mux_state state) +{ + struct typec_retimer_state rstate = { + .alt = state.alt, + .mode = state.mode, + .data = state.data, + }; + + return typec_retimer_set(retimer, &rstate); +} + static int cros_typec_usb_disconnect_state(struct cros_typec_port *port) { port->state.alt = NULL; @@ -212,6 +237,7 @@ static int cros_typec_usb_disconnect_state(struct cros_typec_port *port) usb_role_switch_set_role(port->role_sw, USB_ROLE_NONE); typec_switch_set(port->ori_sw, TYPEC_ORIENTATION_NONE); + cros_typec_retimer_set(port->retimer, port->state); return typec_mux_set(port->mux, &port->state); } @@ -409,9 +435,14 @@ static int cros_typec_init_ports(struct cros_typec_data *typec) static int cros_typec_usb_safe_state(struct cros_typec_port *port) { + int ret; port->state.mode = TYPEC_STATE_SAFE; - return typec_mux_set(port->mux, &port->state); + ret = cros_typec_retimer_set(port->retimer, port->state); + if (!ret) + ret = typec_mux_set(port->mux, &port->state); + + return ret; } /* @@ -508,7 +539,11 @@ static int cros_typec_enable_dp(struct cros_typec_data *typec, port->state.data = &dp_data; port->state.mode = TYPEC_MODAL_STATE(ffs(pd_ctrl->dp_mode)); - return typec_mux_set(port->mux, &port->state); + ret = cros_typec_retimer_set(port->retimer, port->state); + if (!ret) + ret = typec_mux_set(port->mux, &port->state); + + return ret; } static int cros_typec_enable_usb4(struct cros_typec_data *typec, @@ -597,7 +632,10 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num, } else if (port->mux_flags & USB_PD_MUX_USB_ENABLED) { port->state.alt = NULL; port->state.mode = TYPEC_STATE_USB; - ret = typec_mux_set(port->mux, &port->state); + + ret = cros_typec_retimer_set(port->retimer, port->state); + if (!ret) + ret = typec_mux_set(port->mux, &port->state); } else { dev_dbg(typec->dev, "Unrecognized mode requested, mux flags: %x\n",