From patchwork Wed Aug 17 12:32:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 12945800 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 989CFC32771 for ; Wed, 17 Aug 2022 12:33:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238909AbiHQMdJ (ORCPT ); Wed, 17 Aug 2022 08:33:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231828AbiHQMdF (ORCPT ); Wed, 17 Aug 2022 08:33:05 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B33AC861F5; Wed, 17 Aug 2022 05:33:03 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 094851C0004; Wed, 17 Aug 2022 12:33:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1660739582; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xVWN5PxBhZIwLb93ut/eDZPEDDFTMNIGRTSGWGj2JKU=; b=OKQl5XXmtgSgmp7EcRPFIDbk3sBDvMr6ueYAMEMHHix7CiRyBtcPkESvU6HHwaj9zo6E+g dUdKCevbyBWrW5ZXFUuWu0rWA75rLzOuUVJlcyofGTX2aAOc9YJ4JlSP6ffeoedLvlbqD/ CyXmkzPmKvvdK73066S7aIdBSPFsvRdC9IhKBMdebdg34jDgxptRWWGMM5ltXueMiodGcS HAoaaoMuGbwmW9+WOjbeBLiLuMaeB08e4Rzn8Nh1E2QJNjbhN0jH8aJqLsTj7WN96l4xxT nxFsbB++HPNCT1ZSMgOD5c7TSpHfm30twHfmJ/o6OAZ0ppnR6x4AqR+dmoT1Cw== From: Maxime Chevallier To: davem@davemloft.net, Rob Herring Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Richard Cochran , Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com Subject: [PATCH net-next RESEND v4 1/4] net: phy: Introduce QUSGMII PHY mode Date: Wed, 17 Aug 2022 14:32:52 +0200 Message-Id: <20220817123255.111130-2-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817123255.111130-1-maxime.chevallier@bootlin.com> References: <20220817123255.111130-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The QUSGMII mode is a derivative of Cisco's USXGMII standard. This standard is pretty similar to SGMII, but allows for faster speeds, and has the build-in bits for Quad and Octa variants (like QSGMII). The main difference with SGMII/QSGMII is that USXGMII/QUSGMII re-uses the preamble to carry various information, named 'Extensions'. As of today, the USXGMII standard only mentions the "PCH" extension, which is used to convey timestamps, allowing in-band signaling of PTP timestamps without having to modify the frame itself. This commit adds support for that mode. When no extension is in use, it behaves exactly like QSGMII, although it's not compatible with QSGMII. Signed-off-by: Maxime Chevallier Reviewed-by: Andrew Lunn --- V1->V2 : No changes V2->v3 : Added missing documentation on the new enum value V3->V4 : Added Andrew's R'd-by Documentation/networking/phy.rst | 9 +++++++++ drivers/net/phy/phylink.c | 3 +++ include/linux/phy.h | 4 ++++ 3 files changed, 16 insertions(+) diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index 704f31da5167..712e44caebd0 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -308,6 +308,15 @@ Some of the interface modes are described below: rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying data rate of 100Mpbs. +``PHY_INTERFACE_MODE_QUSGMII`` + This defines the Cisco the Quad USGMII mode, which is the Quad variant of + the USGMII (Universal SGMII) link. It's very similar to QSGMII, but uses + a Packet Control Header (PCH) instead of the 7 bytes preamble to carry not + only the port id, but also so-called "extensions". The only documented + extension so-far in the specification is the inclusion of timestamps, for + PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the + same capabilities in terms of link speed and negociation. + Pause frames / flow control =========================== diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 9bd69328dc4d..d2455df1d8d2 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -321,6 +321,7 @@ void phylink_get_linkmodes(unsigned long *linkmodes, phy_interface_t interface, case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_GMII: caps |= MAC_1000HD | MAC_1000FD; @@ -632,6 +633,7 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode) switch (pl->link_config.interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: phylink_set(pl->supported, 10baseT_Half); phylink_set(pl->supported, 10baseT_Full); phylink_set(pl->supported, 100baseT_Half); @@ -2929,6 +2931,7 @@ void phylink_mii_c22_pcs_decode_state(struct phylink_link_state *state, case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: phylink_decode_sgmii_word(state, lpa); break; diff --git a/include/linux/phy.h b/include/linux/phy.h index 87638c55d844..9eeab9b9a74c 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -115,6 +115,7 @@ extern const int phy_10gbit_features_array[1]; * @PHY_INTERFACE_MODE_25GBASER: 25G BaseR * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN + * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII * @PHY_INTERFACE_MODE_MAX: Book keeping * * Describes the interface between the MAC and PHY. @@ -152,6 +153,7 @@ typedef enum { PHY_INTERFACE_MODE_USXGMII, /* 10GBASE-KR - with Clause 73 AN */ PHY_INTERFACE_MODE_10GKR, + PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -267,6 +269,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "10gbase-kr"; case PHY_INTERFACE_MODE_100BASEX: return "100base-x"; + case PHY_INTERFACE_MODE_QUSGMII: + return "qusgmii"; default: return "unknown"; } From patchwork Wed Aug 17 12:32:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 12945801 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC72BC28B2B for ; Wed, 17 Aug 2022 12:33:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239433AbiHQMdQ (ORCPT ); Wed, 17 Aug 2022 08:33:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236605AbiHQMdH (ORCPT ); Wed, 17 Aug 2022 08:33:07 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5261D1EA; Wed, 17 Aug 2022 05:33:05 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 7637F1C0009; Wed, 17 Aug 2022 12:33:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1660739584; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gMXi6tOgQ+Hza2wQKmYRJpoHYy7nWj7ZNMRDGHNfuhs=; b=Hrj3b4duKFd2X8gyFGwbdzXCDDLkREjlA0tvQjyvzpint+7hzfOJjJHNUf5AwNYdEaN9Ax MkJu1D4+PcbOB7oFPpPzACypPLWhRT3OZWjwz0JZYBpm56CNNn4h2SGBX3ZhQX9vs3gDyA HcVu3mw8YU9UA1bYI2xvFdD7ykkXHZiJWoGFtqdon4iprp7nv3FcxPqf7DC+xG0yoZsf9n rJIckEdfZJOz+lqSKt3Uk7t7kG8kDC2V0aEX7gpLYaDeOiIN5KzuiKSWRQ6DrOHgo3JRbo BPyEp2yPQ6IngUscoPr7KVt5SkLIlkfsxEuBLr8IkWuK0y9mvImSl9EJRmxEFA== From: Maxime Chevallier To: davem@davemloft.net, Rob Herring Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Richard Cochran , Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com, Rob Herring Subject: [PATCH net-next RESEND v4 2/4] dt-bindings: net: ethernet-controller: add QUSGMII mode Date: Wed, 17 Aug 2022 14:32:53 +0200 Message-Id: <20220817123255.111130-3-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817123255.111130-1-maxime.chevallier@bootlin.com> References: <20220817123255.111130-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add a new QUSGMII mode, standing for "Quad Universal Serial Gigabit Media Independent Interface", a derivative of USGMII which, similarly to QSGMII, allows to multiplex 4 1Gbps links to a Quad-PHY. The main difference with QSGMII is that QUSGMII can include an extension instead of the standard 7bytes ethernet preamble, allowing to convey arbitrary data such as Timestamps. Signed-off-by: Maxime Chevallier Acked-by: Rob Herring Reviewed-by: Andrew Lunn --- V1->V2 : Added Rob's acked-by V2->V3 : No changes V3->V4 : Added Andrew's R'd-by Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index c138a1022879..4b3c590fcebf 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -67,6 +67,7 @@ properties: - gmii - sgmii - qsgmii + - qusgmii - tbi - rev-mii - rmii From patchwork Wed Aug 17 12:32:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 12945802 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A330C25B08 for ; Wed, 17 Aug 2022 12:33:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239462AbiHQMdT (ORCPT ); Wed, 17 Aug 2022 08:33:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238854AbiHQMdJ (ORCPT ); Wed, 17 Aug 2022 08:33:09 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 043A0D54; Wed, 17 Aug 2022 05:33:06 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 1F11A1C0008; Wed, 17 Aug 2022 12:33:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1660739585; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=R3uwO/NLqiqs5GMimReLDw1QptwLULET5iPOIJMtdzQ=; b=XBLAAZdHdwZ2Gc2wWHfLLcWI6Z1cfEShR3sgmYiwpRft08s3YxbQynSx4gLAPRThBvk9oZ Mv3fLkZoVbzeNf+kKclkrWgasVxTwEMQjqrtEMX+69tDm8hX0cqUp/9HX/HCflLnSkYmZb Jpp24UVxD8aTzvSrs6S7+a5hzmhb9LnTGVaWfcvuyDDlYl91DS0e7LDpoccCA0FX4qRObB t3RTQEqUfLe1/O8ie3Io3dRv3bM+o7PH1PlYe7qmb1EWGQz+AieP1fw1RKLAP8QmAJ3VgR M//2EfGiM9lpTw4LKjtUuJohgACwB8YZ7rvqugpvO9XE739vkf/5CsEqz2/ASQ== From: Maxime Chevallier To: davem@davemloft.net, Rob Herring Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Richard Cochran , Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com Subject: [PATCH net-next RESEND v4 3/4] net: phy: Add helper to derive the number of ports from a phy mode Date: Wed, 17 Aug 2022 14:32:54 +0200 Message-Id: <20220817123255.111130-4-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817123255.111130-1-maxime.chevallier@bootlin.com> References: <20220817123255.111130-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Some phy modes such as QSGMII multiplex several MAC<->PHY links on one single physical interface. QSGMII used to be the only one supported, but other modes such as QUSGMII also carry multiple links. This helper allows getting the number of links that are multiplexed on a given interface. Signed-off-by: Maxime Chevallier Reviewed-by: Andrew Lunn --- V1->V2 : New patch V2->V3 : Made PHY_INTERFACE_MODE_INTERNAL 1 port, and added the MAX case. V3->V4 : No change drivers/net/phy/phy-core.c | 52 ++++++++++++++++++++++++++++++++++++++ include/linux/phy.h | 2 ++ 2 files changed, 54 insertions(+) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 1f2531a1a876..f8ec12d3d6ae 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -74,6 +74,58 @@ const char *phy_duplex_to_str(unsigned int duplex) } EXPORT_SYMBOL_GPL(phy_duplex_to_str); +/** + * phy_interface_num_ports - Return the number of links that can be carried by + * a given MAC-PHY physical link. Returns 0 if this is + * unknown, the number of links else. + * + * @interface: The interface mode we want to get the number of ports + */ +int phy_interface_num_ports(phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_NA: + return 0; + case PHY_INTERFACE_MODE_INTERNAL: + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_TBI: + case PHY_INTERFACE_MODE_REVMII: + case PHY_INTERFACE_MODE_RMII: + case PHY_INTERFACE_MODE_REVRMII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RTBI: + case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_XLGMII: + case PHY_INTERFACE_MODE_MOCA: + case PHY_INTERFACE_MODE_TRGMII: + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_5GBASER: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_25GBASER: + case PHY_INTERFACE_MODE_10GKR: + case PHY_INTERFACE_MODE_100BASEX: + case PHY_INTERFACE_MODE_RXAUI: + case PHY_INTERFACE_MODE_XAUI: + return 1; + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: + return 4; + case PHY_INTERFACE_MODE_MAX: + WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode"); + return 0; + } + return 0; +} +EXPORT_SYMBOL_GPL(phy_interface_num_ports); + /* A mapping of all SUPPORTED settings to speed/duplex. This table * must be grouped by speed and sorted in descending match priority * - iow, descending speed. diff --git a/include/linux/phy.h b/include/linux/phy.h index 9eeab9b9a74c..7c49ab95441b 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -968,6 +968,8 @@ struct phy_fixup { const char *phy_speed_to_str(int speed); const char *phy_duplex_to_str(unsigned int duplex); +int phy_interface_num_ports(phy_interface_t interface); + /* A structure for mapping a particular speed and duplex * combination to a particular SUPPORTED and ADVERTISED value */ From patchwork Wed Aug 17 12:32:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 12945803 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72A46C32771 for ; Wed, 17 Aug 2022 12:33:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239486AbiHQMd2 (ORCPT ); Wed, 17 Aug 2022 08:33:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239354AbiHQMdO (ORCPT ); Wed, 17 Aug 2022 08:33:14 -0400 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E049F1A3A3; Wed, 17 Aug 2022 05:33:11 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id E99041C000C; Wed, 17 Aug 2022 12:33:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1660739587; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QeuyLgP/uLqTmp79qxlI42HvqT4YfSlW6cpz6A3J+iI=; b=VCjU4qBUf2YTBpExlJw4JRDC3jXYvs+FL/l+J5eDKuA64r6lcSUTUbzxZ+Dy5a0N4aMwjw /1NxLNjxnhhsmYmEGibSH9n8Mcy+KRyCTbEnitCk+/wZaRwfsHWbAyg5YgozgHmnxGhgCm mZKn2feMRijOnh+6RpR1fqpKYTOnOq62nhO/hMatskkKmcIkOuiPdj1hK4p9aMtKpEtUUN 9M1mpcKURWeO7v5X6ezbdfWzIWHo+DrPyJ598le3pafVCDcHo5xIkzotrFBEoDnL5GtM1k xvv8OCkMv9I9hkAd1gZsJ3zA3SsC48G4hTb2X+ykZ5PIka2C9UfLcpq/JVjL3Q== From: Maxime Chevallier To: davem@davemloft.net, Rob Herring Cc: Maxime Chevallier , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.petazzoni@bootlin.com, Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-kernel@lists.infradead.org, Richard Cochran , Horatiu.Vultur@microchip.com, Allan.Nielsen@microchip.com, UNGLinuxDriver@microchip.com Subject: [PATCH net-next RESEND v4 4/4] net: lan966x: Add QUSGMII support for lan966x Date: Wed, 17 Aug 2022 14:32:55 +0200 Message-Id: <20220817123255.111130-5-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817123255.111130-1-maxime.chevallier@bootlin.com> References: <20220817123255.111130-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The Lan996x controller supports the QUSGMII mode, which is very similar to QSGMII in the way it's configured and the autonegociation capababilities it provides. This commit adds support for that mode, treating it most of the time like QSGMII, making sure that we do configure the PCS how we should. Signed-off-by: Maxime Chevallier Reviewed-by: Andrew Lunn --- V1->V2 : Pass the QUSGMII mode as-is to the generic PHY driver, and use phy_interface_num_ports, as per Russell's review V2->V3 : No changes V3->V4 : No changes .../ethernet/microchip/lan966x/lan966x_main.c | 2 ++ .../microchip/lan966x/lan966x_phylink.c | 3 ++- .../ethernet/microchip/lan966x/lan966x_port.c | 22 ++++++++++++++----- .../ethernet/microchip/lan966x/lan966x_regs.h | 6 +++++ 4 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c index 1d6e3b641b2e..1e604e8db20c 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.c @@ -778,6 +778,8 @@ static int lan966x_probe_port(struct lan966x *lan966x, u32 p, port->phylink_config.supported_interfaces); __set_bit(PHY_INTERFACE_MODE_QSGMII, port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_QUSGMII, + port->phylink_config.supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, port->phylink_config.supported_interfaces); __set_bit(PHY_INTERFACE_MODE_2500BASEX, diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c b/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c index 38a7e95d69b4..87f3d3a57aed 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c @@ -28,11 +28,12 @@ static int lan966x_phylink_mac_prepare(struct phylink_config *config, phy_interface_t iface) { struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); + phy_interface_t serdes_mode = iface; int err; if (port->serdes) { err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, - iface); + serdes_mode); if (err) { netdev_err(to_net_dev(config->dev), "Could not set mode of SerDes\n"); diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_port.c b/drivers/net/ethernet/microchip/lan966x/lan966x_port.c index f141644e4372..bbf42fc8c8d5 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_port.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_port.c @@ -168,7 +168,7 @@ static void lan966x_port_link_up(struct lan966x_port *port) /* Also the GIGA_MODE_ENA(1) needs to be set regardless of the * port speed for QSGMII ports. */ - if (config->portmode == PHY_INTERFACE_MODE_QSGMII) + if (phy_interface_num_ports(config->portmode) == 4) mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1); lan_wr(config->duplex | mode, @@ -331,10 +331,14 @@ int lan966x_port_pcs_set(struct lan966x_port *port, struct lan966x *lan966x = port->lan966x; bool inband_aneg = false; bool outband; + bool full_preamble = false; + + if (config->portmode == PHY_INTERFACE_MODE_QUSGMII) + full_preamble = true; if (config->inband) { if (config->portmode == PHY_INTERFACE_MODE_SGMII || - config->portmode == PHY_INTERFACE_MODE_QSGMII) + phy_interface_num_ports(config->portmode) == 4) inband_aneg = true; /* Cisco-SGMII in-band-aneg */ else if (config->portmode == PHY_INTERFACE_MODE_1000BASEX && config->autoneg) @@ -345,9 +349,15 @@ int lan966x_port_pcs_set(struct lan966x_port *port, outband = true; } - /* Disable or enable inband */ - lan_rmw(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(outband), - DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, + /* Disable or enable inband. + * For QUSGMII, we rely on the preamble to transmit data such as + * timestamps, therefore force full preamble transmission, and prevent + * premable shortening + */ + lan_rmw(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(outband) | + DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(full_preamble), + DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA | + DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, lan966x, DEV_PCS1G_MODE_CFG(port->chip_port)); /* Enable PCS */ @@ -396,7 +406,7 @@ void lan966x_port_init(struct lan966x_port *port) if (lan966x->fdma) lan966x_fdma_netdev_init(lan966x, port->dev); - if (config->portmode != PHY_INTERFACE_MODE_QSGMII) + if (phy_interface_num_ports(config->portmode) != 4) return; lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(0) | diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h index 8265ad89f0bc..c53bae5d8dbd 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h @@ -504,6 +504,12 @@ enum lan966x_target { #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) +#define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) +#define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ + FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) +#define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ + FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) + /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4)