From patchwork Wed Aug 17 21:21:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12946490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71BF5C25B08 for ; Wed, 17 Aug 2022 21:21:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241321AbiHQVVy (ORCPT ); Wed, 17 Aug 2022 17:21:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233446AbiHQVVx (ORCPT ); Wed, 17 Aug 2022 17:21:53 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5C6CA5992 for ; Wed, 17 Aug 2022 14:21:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660771312; x=1692307312; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hHnadg+FQz/bxwMasnEh5F8RFZep1jQ+3pDdoqRodEM=; b=nLvNnoBSOzCWDGhBmRIV8LgQfOo0vvTM+M6o+yi2JmIfSisq7D5gW7H9 yptpeFG1klXaXzCiRkMT+4F31VxnE6Uehjkpz0cBdjjEL6MeAMEmO2yI2 xEVbkiI8pQFjS7oxcP/he+Ua5TGceP3Gkwd7DSd1Gz5DC4BnSGM551yAI 8/Nip9azgGbB0Hr+bc4hiT/z0s7BKtRz/CJc2/SMzxJHnXVLr1d8HBkfq zDWcmsQ+6leNnROMQcMHp0SRYX+TCBEcOF63+JOqW92iAP4cFfFmEZWAm 1s26Iq/eVmjKpZ+0VhUeuaYb3q3JcVqz2dPSvefkL4zLrWXHExfwlYOyJ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10442"; a="293397811" X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="293397811" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:21:43 -0700 X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="696929574" Received: from djiang5-desk4.jf.intel.com ([10.165.157.96]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:21:43 -0700 Subject: [PATCH v4 1/6] cxl: Add check for result of interleave ways plus granularity combo From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Wed, 17 Aug 2022 14:21:42 -0700 Message-ID: <166077130292.1743055.11442563469460270244.stgit@djiang5-desk4.jf.intel.com> In-Reply-To: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> References: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Add a helper function to check the combination of interleave ways and interleave granularity together is sane against the interleave mask from the HDM decoder. Add the check to cxl_region_attach() to make sure the region config is sane. Add the check to cxl_port_setup_targets() to make sure the port setup config is also sane. Calculation refers to CXL spec v3 8.2.4.19.13 implementation note #3. Reviewed-by: Dan Williams Signed-off-by: Dave Jiang --- drivers/cxl/core/region.c | 47 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 401148016978..28272b0196e6 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -940,6 +940,42 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled, return 0; } +static int cxl_interleave_capable(struct cxl_port *port, struct device *dev, + int ways, int granularity) +{ + struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev); + unsigned int addr_mask; + u16 eig; + u8 eiw; + int rc; + + rc = granularity_to_cxl(granularity, &eig); + if (rc) + return rc; + + rc = ways_to_cxl(ways, &eiw); + if (rc) + return rc; + + if (eiw == 0) + return 0; + + if (is_power_of_2(eiw)) + addr_mask = GENMASK(eig + 8 + eiw - 1, eig + 8); + else + addr_mask = GENMASK((eig + eiw) / 3 - 1, eig + 8); + + if (~cxlhdm->interleave_mask & addr_mask) { + dev_dbg(dev, + "%s:%s interleave (eig: %d eiw: %d mask: %#x) exceed cap (mask: %#x)\n", + dev_name(port->uport), dev_name(&port->dev), eig, eiw, + cxlhdm->interleave_mask, addr_mask); + return -EINVAL; + } + + return 0; +} + static int cxl_port_setup_targets(struct cxl_port *port, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled) @@ -1047,6 +1083,10 @@ static int cxl_port_setup_targets(struct cxl_port *port, return rc; } + rc = cxl_interleave_capable(port, &cxlr->dev, iw, ig); + if (rc) + return rc; + cxld->interleave_ways = iw; cxld->interleave_granularity = ig; cxld->hpa_range = (struct range) { @@ -1196,6 +1236,12 @@ static int cxl_region_attach(struct cxl_region *cxlr, return -EBUSY; } + ep_port = cxled_to_port(cxled); + rc = cxl_interleave_capable(ep_port, &cxlr->dev, p->interleave_ways, + p->interleave_granularity); + if (rc) + return rc; + for (i = 0; i < p->interleave_ways; i++) { struct cxl_endpoint_decoder *cxled_target; struct cxl_memdev *cxlmd_target; @@ -1214,7 +1260,6 @@ static int cxl_region_attach(struct cxl_region *cxlr, } } - ep_port = cxled_to_port(cxled); root_port = cxlrd_to_port(cxlrd); dport = cxl_find_dport_by_dev(root_port, ep_port->host_bridge); if (!dport) { From patchwork Wed Aug 17 21:21:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12946489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD76BC25B08 for ; Wed, 17 Aug 2022 21:21:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238882AbiHQVVu (ORCPT ); Wed, 17 Aug 2022 17:21:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233446AbiHQVVt (ORCPT ); Wed, 17 Aug 2022 17:21:49 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00AB5A598F for ; Wed, 17 Aug 2022 14:21:48 -0700 (PDT) DKIM-Signature: v=1; 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17 Aug 2022 14:21:48 -0700 Subject: [PATCH v4 2/6] cxl: Add CXL spec v3.0 interleave support From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Wed, 17 Aug 2022 14:21:48 -0700 Message-ID: <166077130837.1743055.16772443540776610507.stgit@djiang5-desk4.jf.intel.com> In-Reply-To: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> References: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org CXL spec v3.0 added 2 CAP bits to the CXL HDM Decoder Capability Register. CXL spec v3.0 8.2.4.19.1. Bit 11 indicates that 3, 6, and 12 way interleave is capable. Bit 12 indicates that 16 way interleave is capable. Add code to parse_hdm_decoder_caps() to cache those new bits. Add check in cxl_interleave_verify() call to make sure those CAP bits matches the passed in interleave value. Reviewed-by: Dan Williams Signed-off-by: Dave Jiang Reviewed-by: Jonathan Cameron --- drivers/cxl/core/hdm.c | 6 ++++++ drivers/cxl/core/region.c | 3 +++ drivers/cxl/cxl.h | 2 ++ drivers/cxl/cxlmem.h | 5 +++++ 4 files changed, 16 insertions(+) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index d1d2caea5c62..2f91ff9b0227 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -80,6 +80,12 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm) cxlhdm->interleave_mask |= GENMASK(11, 8); if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap)) cxlhdm->interleave_mask |= GENMASK(14, 12); + + cxlhdm->interleave_cap = CXL_HDM_INTERLEAVE_CAP_DEFAULT; + if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap)) + cxlhdm->interleave_cap |= CXL_HDM_INTERLEAVE_CAP_3_6_12; + if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap)) + cxlhdm->interleave_cap |= CXL_HDM_INTERLEAVE_CAP_16; } static void __iomem *map_hdm_decoder_regs(struct cxl_port *port, diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 28272b0196e6..9851ab2782f2 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -960,6 +960,9 @@ static int cxl_interleave_capable(struct cxl_port *port, struct device *dev, if (eiw == 0) return 0; + if (!test_bit(ways, &cxlhdm->interleave_cap)) + return -EINVAL; + if (is_power_of_2(eiw)) addr_mask = GENMASK(eig + 8 + eiw - 1, eig + 8); else diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index f680450f0b16..11f2a14f42eb 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -42,6 +42,8 @@ #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) +#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) +#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 #define CXL_HDM_DECODER_ENABLE BIT(1) #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 88e3a8e54b6a..4e65c9cc1d30 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -393,11 +393,16 @@ static inline void cxl_mem_active_dec(void) } #endif +#define CXL_HDM_INTERLEAVE_CAP_DEFAULT BIT(1) | BIT(2) | BIT(4) | BIT(8) +#define CXL_HDM_INTERLEAVE_CAP_3_6_12 BIT(3) | BIT(6) | BIT(12) +#define CXL_HDM_INTERLEAVE_CAP_16 BIT(16) + struct cxl_hdm { struct cxl_component_regs regs; unsigned int decoder_count; unsigned int target_count; unsigned int interleave_mask; + unsigned long interleave_cap; struct cxl_port *port; }; From patchwork Wed Aug 17 21:21:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12946492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A7C0C32772 for ; Wed, 17 Aug 2022 21:22:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241223AbiHQVWB (ORCPT ); Wed, 17 Aug 2022 17:22:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233446AbiHQVWA (ORCPT ); Wed, 17 Aug 2022 17:22:00 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12663A61F8 for ; Wed, 17 Aug 2022 14:22:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660771320; x=1692307320; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6EaW6u8QngBuh6zk7ZxPWQ4L5alvQ/apItGwG+3+9+E=; b=BYXdq08ERRVaGG8NpnhKDoMW9MF4c5FvLUlC/wSR0kEu7uuAorH9kYfS lGXhGVSMxkDXQ+lYaQOMWAkCD7akrbINqZnbJzrf06OVc6wMqvMftPTeW Cfo5OyxqxxOJ1MYVk6ythHBGuEsGkyxp+vJT+oProR6RH2hiWCXyLnX0L bNry8nxu+2r32evy/W9rt943f/lpoEiY+6YM9c0pa4YvQIQ5fZZbY2EZl b9+zC3OU8o/tXxtHS1MIoGBHiumm+RxOxV8uYqefBzWkqnj/UoTy+MFG2 d4hlFnxiFV4xdWuv7yidoxrRauiRt1skUnktj9x3A13/zMMCBxf6vLWMy w==; X-IronPort-AV: E=McAfee;i="6500,9779,10442"; a="291358766" X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="291358766" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:21:54 -0700 X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="558279063" Received: from djiang5-desk4.jf.intel.com ([10.165.157.96]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:21:53 -0700 Subject: [PATCH v4 3/6] tools/testing/cxl: Add interleave check support to mock cxl port device From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Wed, 17 Aug 2022 14:21:53 -0700 Message-ID: <166077131383.1743055.4589788759198107631.stgit@djiang5-desk4.jf.intel.com> In-Reply-To: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> References: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Attach the cxl mock hdm to the port device to allow cxl_interleave_verify() to check the interleave configuration. Set the interleave_mask as well to support the new verification code. Reviewed-by: Dan Williams Signed-off-by: Dave Jiang --- tools/testing/cxl/test/cxl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index a072b2d3e726..3ce353a20b80 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -398,6 +398,9 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port) return ERR_PTR(-ENOMEM); cxlhdm->port = port; + cxlhdm->interleave_mask = GENMASK(14, 8); + cxlhdm->interleave_cap = CXL_HDM_INTERLEAVE_CAP_DEFAULT; + dev_set_drvdata(&port->dev, cxlhdm); return cxlhdm; } From patchwork Wed Aug 17 21:21:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12946491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06020C25B08 for ; Wed, 17 Aug 2022 21:22:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241550AbiHQVWA (ORCPT ); Wed, 17 Aug 2022 17:22:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241519AbiHQVV7 (ORCPT ); Wed, 17 Aug 2022 17:21:59 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5399BA598F for ; Wed, 17 Aug 2022 14:21:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660771319; x=1692307319; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T/pSJqcSTEdpoMuCFrcd+/my6mKmMgTWveifoWDRxhw=; b=H2K7n78c4v7Jr3k3G4CihWtHdTRRGojsXBxvc4tP6/5FQEVy37EGYI5C ocnNqcWuwDJwgdwZ2K3KYfhz0jG+TxL1O51uVem7hqFexGp34YwBkb3Kl NLX5mFdULsFYR2DTrgMXocnkkT/jgd1ssD7cgQvhWvDLhE8JUAnzGqCSq +5PsMqPJMOMbkwNQ5i/wozRLpkxnG0Cf0YVtex/qQFUrDKIMfYgbS+F0j BKjue29fYBRKwsCVa2BsbiyCpwFrKkqwRYLdruw4fBrpt/nJSweSHeWMB SJHN0FMZjc0UQEcNetOm5OnlGR7fumhmOY5STpkDSv+/taSsucsTnu3ht A==; X-IronPort-AV: E=McAfee;i="6500,9779,10442"; a="279571156" X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="279571156" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:21:58 -0700 X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="640615849" Received: from djiang5-desk4.jf.intel.com ([10.165.157.96]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:21:58 -0700 Subject: [PATCH v4 4/6] cxl: change cxl_port_attribute_groups naming to avoid confusion From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Wed, 17 Aug 2022 14:21:58 -0700 Message-ID: <166077131892.1743055.1029132844466334751.stgit@djiang5-desk4.jf.intel.com> In-Reply-To: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> References: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Both cxl/port.c and cxl/core/port.c have cxl_port_attribute_groups. Change cxl_port_attribute_groups in cxl/port.c to cxl_port_dynamic_attr_groups in order to avoid confusion. Suggested-by: Dan Williams Signed-off-by: Dave Jiang Reviewed-by: Jonathan Cameron --- drivers/cxl/port.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 5453771bf330..c4aa073b7e31 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -123,7 +123,7 @@ static struct attribute_group cxl_cdat_attribute_group = { .is_bin_visible = cxl_port_bin_attr_is_visible, }; -static const struct attribute_group *cxl_port_attribute_groups[] = { +static const struct attribute_group *cxl_port_dynamic_attr_groups[] = { &cxl_cdat_attribute_group, NULL, }; @@ -133,7 +133,7 @@ static struct cxl_driver cxl_port_driver = { .probe = cxl_port_probe, .id = CXL_DEVICE_PORT, .drv = { - .dev_groups = cxl_port_attribute_groups, + .dev_groups = cxl_port_dynamic_attr_groups, }, }; From patchwork Wed Aug 17 21:22:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12946493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AA37C25B08 for ; Wed, 17 Aug 2022 21:22:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233446AbiHQVWF (ORCPT ); Wed, 17 Aug 2022 17:22:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241519AbiHQVWE (ORCPT ); Wed, 17 Aug 2022 17:22:04 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 407ACA5992 for ; Wed, 17 Aug 2022 14:22:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660771324; x=1692307324; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DuV2w/E/x5CRj5hRlf24x5UhznIR6oKB5UmE6BcvlHI=; b=M8K3EQ17Op1AHEvPr03/YCdcsGEq806ZPpYuVF1BzTCtXmByKiP0c7zF DzNgOzE6RzcJEokduVewd6GgCOxoA5PuQxvFsiNDLEDHriHwzelhX55LD 4774reuH6DpMtezjuEO2TZhJr5i+HFfRQ242vqaNtIPBnhtoUoCY2+joR FjqsSVxlVQsBsTThnKhzODnIGfaAHzFcjDf+7RROyYlV3GZ6rfr4WOU// QZIiqnHlhrldjPyJdTAqVLbdrk5KRWuI2UQGjaoKeZBYQivMd+i/pzHls TzVbGwiRVwe+1wrCGWEf2P9XS2HjkXVVDPRWzSKg8lVTBHJp2IdK4XTFQ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10442"; a="279571168" X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="279571168" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:22:04 -0700 X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="607589365" Received: from djiang5-desk4.jf.intel.com ([10.165.157.96]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:22:04 -0700 Subject: [PATCH v4 5/6] cxl: export interleave address mask as port sysfs attribute From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Wed, 17 Aug 2022 14:22:04 -0700 Message-ID: <166077132400.1743055.3807533324287792337.stgit@djiang5-desk4.jf.intel.com> In-Reply-To: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> References: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Export the interleave address mask as a sysfs attribute for a port. The interleave address mask is created based off the CXL HDM Decoder Capability Register (CXL spec v3 8.2.4.19.1) and sets the bits indicated by th "A11to8 Interleave Capable" bit and the "A14to12 Interleave Capable" bit. It indicates the decoder supports interleaveing based on those address bits. The exported sysfs attribute will help user region creation to do more valid configuration checking. Suggested-by: Dan Williams Signed-off-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-cxl | 11 +++++++++++ drivers/cxl/port.c | 19 +++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 8494ef27e8d2..c6f533f47e50 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -191,6 +191,17 @@ Description: the data is 0 reading the CDAT data failed. Otherwise the CDAT data is reported. +What: /sys/bus/cxl/devices/endpointX/interleave_mask + /sys/bus/cxl/devices/portX/interleave_mask +Date: Aug, 2020 +KernelVersion: v6.1 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) Interleve address mask from the HDM decoder attached to the + port. The address bits are set depending on the CXL HDM Decoder + Capability Register (CXL spec v3 8.2.4.19.1) where the "A11to8 + Interleave Capable" bit and the "AA14to12 Interleave Capable" bits + are set. What: /sys/bus/cxl/devices/decoderX.Y/mode Date: May, 2022 diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index c4aa073b7e31..567f62fd4ded 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -123,8 +123,27 @@ static struct attribute_group cxl_cdat_attribute_group = { .is_bin_visible = cxl_port_bin_attr_is_visible, }; +static ssize_t interleave_mask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_hdm *cxlhdm = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%#x\n", cxlhdm->interleave_mask); +} +static DEVICE_ATTR_RO(interleave_mask); + +static struct attribute *cxl_port_info_attributes[] = { + &dev_attr_interleave_mask.attr, + NULL, +}; + +static struct attribute_group cxl_port_info_attribute_group = { + .attrs = cxl_port_info_attributes, +}; + static const struct attribute_group *cxl_port_dynamic_attr_groups[] = { &cxl_cdat_attribute_group, + &cxl_port_info_attribute_group, NULL, }; From patchwork Wed Aug 17 21:22:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12946494 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04669C25B08 for ; Wed, 17 Aug 2022 21:22:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241533AbiHQVWM (ORCPT ); Wed, 17 Aug 2022 17:22:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233026AbiHQVWK (ORCPT ); Wed, 17 Aug 2022 17:22:10 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB7CDA5992 for ; Wed, 17 Aug 2022 14:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660771329; x=1692307329; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/Qs+Fndfo4GMPthFtjTpWI6qxU2HSfduBs/vgpdS1SM=; b=gz79qU4fYDeTTeIl1rm9qFEFNGx/hceR79n68qMsW0Z1Tghk+mgxE+w+ 11HSFKbHgGvp4UBERLjy2cR7QHuQhwstVN5aGhrHutrXdGJr2j6rzJfWs 0y/r7p1Bbsv1bHLhxa+3shZyu/tNn7vaFKVnN60mEOu1ZOgB/rDbH/AGo HY4p3NBc75al55e3MIlyI2C7kgmfCmLjBsnB94+Q/fIRDCmYLJEB5xp00 wLWiGjbg8cvF676U+/F3svORLxRZuA6Q6WZuU+7bttg7aaWit15ysrJTK 5u4A2Beg0sy5Ho+zXM3Q/oJ8hVI1kB3SszydUdvkSrzCkYLcjz0CKSeDw A==; X-IronPort-AV: E=McAfee;i="6500,9779,10442"; a="275657571" X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="275657571" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:22:09 -0700 X-IronPort-AV: E=Sophos;i="5.93,244,1654585200"; d="scan'208";a="733825843" Received: from djiang5-desk4.jf.intel.com ([10.165.157.96]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 14:22:09 -0700 Subject: [PATCH v4 6/6] cxl: export intereleave capability as port sysfs attribute From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com Date: Wed, 17 Aug 2022 14:22:09 -0700 Message-ID: <166077132912.1743055.6028619361637977647.stgit@djiang5-desk4.jf.intel.com> In-Reply-To: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> References: <166077102447.1743055.17158560277276060113.stgit@djiang5-desk4.jf.intel.com> User-Agent: StGit/1.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Export the interleave capability as a sysfs attribute for a port. The exported mask is interpreted from the CXL HDM Decoder Capability Register (CXL spec v 8.2.4.19.1). Each bit in the mask represents the number of interleave ways the decoder supports. For example, CXL devices designed from CXL spec v2.0 supports 1, 2, 4, and 8 interleave ways. The exported mask would show 0x116. The exported sysfs attribute will help user region creation to do more valid configuration checking. Suggested-by: Dan Williams Signed-off-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-cxl | 13 +++++++++++++ drivers/cxl/port.c | 10 ++++++++++ 2 files changed, 23 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index c6f533f47e50..5a13806a77ab 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -203,6 +203,19 @@ Description: Interleave Capable" bit and the "AA14to12 Interleave Capable" bits are set. +What: /sys/bus/cxl/devices/endpointX/interleave_cap + /sys/bus/cxl/devices/portX/interleave_cap +Date: Aug, 2020 +KernelVersion: v6.1 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) Interleave capability mask from the HDM decoder attached to the + port. Each bit in the mask represents the number of interleave ways + the decoder supports. For CXL devices designed from CXL spec v2.0 or + earlier, 1, 2, 4, and 8 interleave ways are supported. With CXL spec + v3.0 or later, the capability register (CXL spec v3 8.2.4.19.1) + indicates 3, 6, and 12 ways supported or 16 ways supported. + What: /sys/bus/cxl/devices/decoderX.Y/mode Date: May, 2022 KernelVersion: v5.20 diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 567f62fd4ded..f856a31bec65 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -132,8 +132,18 @@ static ssize_t interleave_mask_show(struct device *dev, } static DEVICE_ATTR_RO(interleave_mask); +static ssize_t interleave_cap_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct cxl_hdm *cxlhdm = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%#lx\n", cxlhdm->interleave_cap); +} +static DEVICE_ATTR_RO(interleave_cap); + static struct attribute *cxl_port_info_attributes[] = { &dev_attr_interleave_mask.attr, + &dev_attr_interleave_cap.attr, NULL, };