From patchwork Thu Aug 18 13:51:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947121 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D9CEC00140 for ; Thu, 18 Aug 2022 13:51:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244570AbiHRNvv (ORCPT ); Thu, 18 Aug 2022 09:51:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244720AbiHRNvv (ORCPT ); Thu, 18 Aug 2022 09:51:51 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC7006110B for ; Thu, 18 Aug 2022 06:51:49 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5AE4CB82195 for ; Thu, 18 Aug 2022 13:51:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8A39BC4347C; Thu, 18 Aug 2022 13:51:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830707; bh=G+gw4VfrgeslPZXeo4NP+QRBVZNGHXSb8Gk3ybhCeNI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PCe6mgF8NVsLo4WYzxxNSY0CYnqJa4nUXwrnntOyCfVtluPUbEjhmpGnjX2IBuYa5 lDRXerOBflsgFVaPAFLZ0XFIPTB/W5AKNOAKaanT5131FSp4YDOOQG0K7sWzq2SYnr 04a8tWUDUvTRHldJNk0UgtVTs0+s6hiejZUL+nYGJNFKV5+BS4S8eX+Vlnm8LzpqQX c73prcmgPcPMozScCGRpMiRVjynpsZRCfuj1QsMuGBDSC25M3v/aLNy7dV3fzDoHQq xZu4T4oMV+KPcm09/qxup5cPFnI72SnrRLzX9IZoOBH4d2iwGYM9C3E2lplSCzYoI2 39+dJnulE7a3w== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas , Lukas Wunner Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 01/11] PCI: pciehp: Enable DLLSC interrupt only if supported Date: Thu, 18 Aug 2022 15:51:30 +0200 Message-Id: <20220818135140.5996-2-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Don't enable Data Link Layer State Changed interrupt if it isn't supported. Data Link Layer Link Active Reporting Capable bit in Link Capabilities register indicates if Data Link Layer State Changed Enable is supported. Although Lukas Wunner says [1] According to PCIe r6.0, sec. 7.5.3.6, "For a hot-plug capable Downstream Port [...], this bit must be hardwired to 1b." the reason we want this is because of the pci-bridge-emul driver, which emulates a bridge, but does not support asynchronous operations (since implementing them is unneeded and would require massive changes to the whole driver). Therefore enabling DLLSC unconditionally makes the corresponding bit set only in the emulated configuration space of the pci-bridge-emul driver, which - results in confusing information when dumping the config space (it says that the interrupt is not supported but enabled), which may confuse developers when debugging PCIe issues, - may cause bugs in the future if someone adds code that checks whether DLLSC is enabled and then waits for the interrupt. [1] https://www.spinics.net/lists/linux-pci/msg124727.html Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- Changes since batch 5: - changed commit message, previously we wrote that the change is needed to fix a bug where kernel was waiting for an event which did not come. This turns out to be false. See https://lore.kernel.org/linux-pci/20220818142243.4c046c59@dellmb/T/#u --- drivers/pci/hotplug/pciehp_hpc.c | 30 +++++++++++++++++++++++------- drivers/pci/hotplug/pnv_php.c | 13 +++++++++---- 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 040ae076ec0e..373bb396fe22 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -788,6 +788,7 @@ static int pciehp_poll(void *data) static void pcie_enable_notification(struct controller *ctrl) { u16 cmd, mask; + u32 link_cap; /* * TBD: Power fault detected software notification support. @@ -800,12 +801,17 @@ static void pcie_enable_notification(struct controller *ctrl) * next power fault detected interrupt was notified again. */ + pcie_capability_read_dword(ctrl_dev(ctrl), PCI_EXP_LNKCAP, &link_cap); + /* - * Always enable link events: thus link-up and link-down shall - * always be treated as hotplug and unplug respectively. Enable - * presence detect only if Attention Button is not present. + * Enable link events if their support is indicated in Link Capability + * register: thus link-up and link-down shall always be treated as + * hotplug and unplug respectively. Enable presence detect only if + * Attention Button is not present. */ - cmd = PCI_EXP_SLTCTL_DLLSCE; + cmd = 0; + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) + cmd |= PCI_EXP_SLTCTL_DLLSCE; if (ATTN_BUTTN(ctrl)) cmd |= PCI_EXP_SLTCTL_ABPE; else @@ -844,9 +850,14 @@ void pcie_clear_hotplug_events(struct controller *ctrl) void pcie_enable_interrupt(struct controller *ctrl) { + u32 link_cap; u16 mask; - mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + pcie_capability_read_dword(ctrl_dev(ctrl), PCI_EXP_LNKCAP, &link_cap); + + mask = PCI_EXP_SLTCTL_HPIE; + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) + mask |= PCI_EXP_SLTCTL_DLLSCE; pcie_write_cmd(ctrl, mask, mask); } @@ -904,19 +915,24 @@ int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe) struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 stat_mask = 0, ctrl_mask = 0; + u32 link_cap; int rc; if (probe) return 0; + pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); + down_write_nested(&ctrl->reset_lock, ctrl->depth); if (!ATTN_BUTTN(ctrl)) { ctrl_mask |= PCI_EXP_SLTCTL_PDCE; stat_mask |= PCI_EXP_SLTSTA_PDC; } - ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; - stat_mask |= PCI_EXP_SLTSTA_DLLSC; + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { + ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; + stat_mask |= PCI_EXP_SLTSTA_DLLSC; + } pcie_write_cmd(ctrl, 0, ctrl_mask); ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c index 881d420637bf..118b514f66b9 100644 --- a/drivers/pci/hotplug/pnv_php.c +++ b/drivers/pci/hotplug/pnv_php.c @@ -841,6 +841,7 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq) struct pci_dev *pdev = php_slot->pdev; u32 broken_pdc = 0; u16 sts, ctrl; + u32 link_cap; int ret; /* Allocate workqueue */ @@ -874,17 +875,21 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq) return; } + pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); + /* Enable the interrupts */ pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &ctrl); if (php_slot->flags & PNV_PHP_FLAG_BROKEN_PDC) { ctrl &= ~PCI_EXP_SLTCTL_PDCE; - ctrl |= (PCI_EXP_SLTCTL_HPIE | - PCI_EXP_SLTCTL_DLLSCE); + ctrl |= PCI_EXP_SLTCTL_HPIE; } else { ctrl |= (PCI_EXP_SLTCTL_HPIE | - PCI_EXP_SLTCTL_PDCE | - PCI_EXP_SLTCTL_DLLSCE); + PCI_EXP_SLTCTL_PDCE); } + if (link_cap & PCI_EXP_LNKCAP_DLLLARC) + ctrl |= PCI_EXP_SLTCTL_DLLSCE; + else + ctrl &= ~PCI_EXP_SLTCTL_DLLSCE; pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, ctrl); /* The interrupt is initialized successfully when @irq is valid */ From patchwork Thu Aug 18 13:51:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947122 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61B59C28B2B for ; Thu, 18 Aug 2022 13:51:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244720AbiHRNvx (ORCPT ); Thu, 18 Aug 2022 09:51:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245059AbiHRNvw (ORCPT ); Thu, 18 Aug 2022 09:51:52 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7ED2606BF for ; Thu, 18 Aug 2022 06:51:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 64A37B8218F for ; Thu, 18 Aug 2022 13:51:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8D13AC43470; Thu, 18 Aug 2022 13:51:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830709; bh=C2D3Jj4PCvtjMZxe3v8o6HA9+SpgibNASF4uxV6GlWc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I+w0ABLf/nmw/TzhnhwhryYvr9P7ecUwG2oa/2kO2pw8fYBClPt27lOIgtra1q2Bj 64lmFqYVUkOrnr6XujLONoa0XHuTUU7lTTaZM5SJ+CPmkQYlmtW5juiUJ9peXQ5x+C RcIT+NWTY1Yz5grVTzC3Ades2TS/THY985cTq/W0GDt54qEmJYsWH79t1RL8Y/t8Lv 6RX2fWsaiV56joBzLX52jxZKXbuarRMxXAzpleF2Xtf6vuV0G8T/oc+r/ODuBdaL6a Xf32Fls9Md9pg1eZOLoTuaEbxunie8a/HforQU8c/EGye/l7M5b3Z+E1aj/lsT+BDG NxezwjkdqUggQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas , Lukas Wunner Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 02/11] PCI: pciehp: Enable Command Completed Interrupt only if supported Date: Thu, 18 Aug 2022 15:51:31 +0200 Message-Id: <20220818135140.5996-3-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár The No Command Completed Support bit in the Slot Capabilities register indicates whether Command Completed Interrupt Enable is unsupported. We already check whether No Command Completed Support bit is set in pcie_wait_cmd(), and do not wait in this case. Let's not enable this Command Completed Interrupt at all if NCCS is set, so that when users dump configuration space from userspace, the dump does not confuse them by saying that Command Completed Interrupt is not supported, but it is enabled. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Reviewed-by: Lukas Wunner --- Changes since batch 5: - changed commit message, previously we wrote that the change is needed to fix a bug where kernel was waiting for an event which did not come. This turns out to be false. See https://lore.kernel.org/linux-pci/20220818142243.4c046c59@dellmb/T/#u --- drivers/pci/hotplug/pciehp_hpc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 373bb396fe22..838eb6cc3ec7 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -817,7 +817,9 @@ static void pcie_enable_notification(struct controller *ctrl) else cmd |= PCI_EXP_SLTCTL_PDCE; if (!pciehp_poll_mode) - cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; + cmd |= PCI_EXP_SLTCTL_HPIE; + if (!pciehp_poll_mode && !NO_CMD_CMPL(ctrl)) + cmd |= PCI_EXP_SLTCTL_CCIE; mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | PCI_EXP_SLTCTL_PFDE | From patchwork Thu Aug 18 13:51:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947123 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4F54C32772 for ; Thu, 18 Aug 2022 13:51:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245059AbiHRNvy (ORCPT ); Thu, 18 Aug 2022 09:51:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245273AbiHRNvx (ORCPT ); Thu, 18 Aug 2022 09:51:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05BB26110B for ; Thu, 18 Aug 2022 06:51:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 960A3615FB for ; Thu, 18 Aug 2022 13:51:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8EDF3C433D6; Thu, 18 Aug 2022 13:51:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830711; bh=cWiFKrjn8B1g5TW9Qk+4fkbMr0616y3TR9z10rI81Hs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mcOkz4dHwq1e3ouY2wgh+BAZgSl/GMiYwvVnaS2TANd7fGKkewcq15vmtJobjfofh PvDmGiCHFo1HXBs2G6fHyXfGEK4du4FfAwCJIPwdyJI4TT1t17xZ88GFsws8qWlFeS r8CeuFUJF/vd7zxhVxKyM/E4F+V76cBnNWgGK1mtNiodCy5OUpYSakQmhXcGhCQNN9 oRuy61xCJ/53HmuGIXFOrkE+d8+BkpfhnE2wSy/BgxWlMoNnxF+pciRJEoHU1VLD7/ chuwyNWRn4kFcpB/t1ku6gTnab3bK7ZeBzXNWTMb3Hz/iJm5FMDVnAUXAnPKwh2oZX yAxunVg8Hnq3g== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 03/11] PCI: aardvark: Add support for DLLSC and hotplug interrupt Date: Thu, 18 Aug 2022 15:51:32 +0200 Message-Id: <20220818135140.5996-4-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Add support for Data Link Layer State Change in the emulated slot registers and hotplug interrupt via the emulated root bridge. This is mainly useful for when an error causes link down event. With this change, drivers can try recovery. Link down state change can be implemented because Aardvark supports Link Down event interrupt. Use it for signaling that Data Link Layer Link is not active anymore via Hot-Plug Interrupt on emulated root bridge. Link up interrupt is not available on Aardvark, but we check for whether link is up in the advk_pcie_link_up() function. By triggering Hot-Plug Interrupt from this function we achieve Link up event, so long as the function is called (which it is after probe and when rescanning). Although it is not ideal, it is better than nothing. Since advk_pcie_link_up() is not called from interrupt handler, we cannot call generic_handle_domain_irq() from it directly. Instead create a TIMER_IRQSAFE timer and trigger it from advk_pcie_link_up(). (We haven't been able to find any documentation for a Link Up interrupt on Aardvark, but it is possible there is one, in some undocumented register. If we manage to find this information, this can be rewritten.) Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- Change since batch 5: - changed commit message (add paragraph about why the change is needed) - select hotplug and pcieportbus in Kconfig --- drivers/pci/controller/Kconfig | 3 + drivers/pci/controller/pci-aardvark.c | 101 ++++++++++++++++++++++++-- 2 files changed, 99 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index d1c5fcf00a8a..5e8a84f5c654 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -21,6 +21,9 @@ config PCI_AARDVARK depends on OF depends on PCI_MSI_IRQ_DOMAIN select PCI_BRIDGE_EMUL + select PCIEPORTBUS + select HOTPLUG_PCI + select HOTPLUG_PCI_PCIE help Add support for Aardvark 64bit PCIe Host Controller. This controller is part of the South Bridge of the Marvel Armada diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 966c8b48bd96..31da28ebc5d1 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "../pci.h" #include "../pci-bridge-emul.h" @@ -100,6 +101,7 @@ #define PCIE_MSG_PM_PME_MASK BIT(7) #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) #define PCIE_ISR0_MSI_INT_PENDING BIT(24) +#define PCIE_ISR0_LINK_DOWN BIT(1) #define PCIE_ISR0_CORR_ERR BIT(11) #define PCIE_ISR0_NFAT_ERR BIT(12) #define PCIE_ISR0_FAT_ERR BIT(13) @@ -284,6 +286,8 @@ struct advk_pcie { DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; int link_gen; + bool link_was_up; + struct timer_list link_irq_timer; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; struct phy *phy; @@ -313,7 +317,24 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) { /* check if LTSSM is in normal operation - some L* state */ u8 ltssm_state = advk_pcie_ltssm_state(pcie); - return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; + bool link_is_up; + u16 slotsta; + + link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; + + if (link_is_up && !pcie->link_was_up) { + dev_info(&pcie->pdev->dev, "link up\n"); + + pcie->link_was_up = true; + + slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); + slotsta |= PCI_EXP_SLTSTA_DLLSC; + pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); + + mod_timer(&pcie->link_irq_timer, jiffies + 1); + } + + return link_is_up; } static inline bool advk_pcie_link_active(struct advk_pcie *pcie) @@ -442,8 +463,6 @@ static void advk_pcie_train_link(struct advk_pcie *pcie) ret = advk_pcie_wait_for_link(pcie); if (ret < 0) dev_err(dev, "link never came up\n"); - else - dev_info(dev, "link up\n"); } /* @@ -592,6 +611,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg &= ~PCIE_ISR0_MSI_INT_PENDING; advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + /* Unmask Link Down interrupt */ + reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); + reg &= ~PCIE_ISR0_LINK_DOWN; + advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); + /* Unmask PME interrupt for processing of PME requester */ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); reg &= ~PCIE_MSG_PM_PME_MASK; @@ -918,6 +942,14 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, advk_pcie_wait_for_retrain(pcie); break; + case PCI_EXP_SLTCTL: { + u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); + /* Only emulation of HPIE and DLLSCE bits is provided */ + slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); + break; + } + case PCI_EXP_RTCTL: { u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); /* Only emulation of PMEIE and CRSSVE bits is provided */ @@ -1035,6 +1067,7 @@ static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) { struct pci_bridge_emul *bridge = &pcie->bridge; + u32 slotcap; bridge->conf.vendor = cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); @@ -1061,6 +1094,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); /* + * Mark bridge as Hot Plug Capable since this is the way how to enable + * delivering of Data Link Layer State Change interrupts. + * + * Set No Command Completed Support because bridge does not support + * Command Completed Interrupt. Every command is executed immediately + * without any delay. + * * Set Presence Detect State bit permanently since there is no support * for unplugging the card nor detecting whether it is plugged. (If a * platform exists in the future that supports it, via a GPIO for @@ -1070,8 +1110,9 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) * value is reserved for ports within the same silicon as Root Port * which is not our case. */ - bridge->pcie_conf.slotcap = cpu_to_le32(FIELD_PREP(PCI_EXP_SLTCAP_PSN, - 1)); + slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | + FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1); + bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); /* Indicates supports for Completion Retry Status */ @@ -1568,6 +1609,24 @@ static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) irq_domain_remove(pcie->rp_irq_domain); } +static void advk_pcie_link_irq_handler(struct timer_list *timer) +{ + struct advk_pcie *pcie = from_timer(pcie, timer, link_irq_timer); + u16 slotctl; + + slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); + if (!(slotctl & PCI_EXP_SLTCTL_DLLSCE) || + !(slotctl & PCI_EXP_SLTCTL_HPIE)) + return; + + /* + * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe + * interrupt 0 + */ + if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) + dev_err_ratelimited(&pcie->pdev->dev, "unhandled HP IRQ\n"); +} + static void advk_pcie_handle_pme(struct advk_pcie *pcie) { u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; @@ -1619,6 +1678,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) { u32 isr0_val, isr0_mask, isr0_status; u32 isr1_val, isr1_mask, isr1_status; + u16 slotsta; int i; isr0_val = advk_readl(pcie, PCIE_ISR0_REG); @@ -1645,6 +1705,26 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); } + /* Process Link Down interrupt as HP IRQ */ + if (isr0_status & PCIE_ISR0_LINK_DOWN) { + advk_writel(pcie, PCIE_ISR0_LINK_DOWN, PCIE_ISR0_REG); + + dev_info(&pcie->pdev->dev, "link down\n"); + + pcie->link_was_up = false; + + slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); + slotsta |= PCI_EXP_SLTSTA_DLLSC; + pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); + + /* + * Deactivate timer and call advk_pcie_link_irq_handler() + * function directly as we are in the interrupt context. + */ + del_timer_sync(&pcie->link_irq_timer); + advk_pcie_link_irq_handler(&pcie->link_irq_timer); + } + /* Process MSI interrupts */ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) advk_pcie_handle_msi(pcie); @@ -1881,6 +1961,14 @@ static int advk_pcie_probe(struct platform_device *pdev) if (ret) return ret; + /* + * generic_handle_domain_irq() expects local IRQs to be disabled since + * normally it is called from interrupt context, so use TIMER_IRQSAFE + * flag for this link_irq_timer. + */ + timer_setup(&pcie->link_irq_timer, advk_pcie_link_irq_handler, + TIMER_IRQSAFE); + advk_pcie_setup_hw(pcie); ret = advk_sw_pci_bridge_init(pcie); @@ -1969,6 +2057,9 @@ static int advk_pcie_remove(struct platform_device *pdev) advk_pcie_remove_msi_irq_domain(pcie); advk_pcie_remove_irq_domain(pcie); + /* Deactivate link event timer */ + del_timer_sync(&pcie->link_irq_timer); + /* Free config space for emulated root bridge */ pci_bridge_emul_cleanup(&pcie->bridge); From patchwork Thu Aug 18 13:51:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947124 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DAC2C00140 for ; Thu, 18 Aug 2022 13:51:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245273AbiHRNvz (ORCPT ); Thu, 18 Aug 2022 09:51:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245276AbiHRNvy (ORCPT ); Thu, 18 Aug 2022 09:51:54 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D25D8606BF for ; Thu, 18 Aug 2022 06:51:53 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7053A615FB for ; Thu, 18 Aug 2022 13:51:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6825EC433C1; Thu, 18 Aug 2022 13:51:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830712; bh=PUps/ldFkt1/yI6ZmwNvDNq7YAuTSGdZNC88IA2kSQk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GtUW0z+ql1r8xqOWnS7UxzbPJmU0XOPOOg/UAVuDZbXSCOe9I6BvIuL+8xmcAc+jO 0/g5MidIAYmqNioWQVM+SKYWDq0movNgZkY+kG3F4Wqj1gp2H+vGRF+Jn/0k+cBHYA +MYMPFbEUhGjBYwMrgSPESQGxer63TRhhKqW7iLLJ753hfrKkjT0pC6YCa+AS0ffFC Y+xK3pDVkAKOJd2VeLGIV5dqNaBlYp/wlAvfqKhiFip+ls/N+g/h2eFd7vPJs38Eve X2gWV6Yh5P1R/phxXtppj8FHDszGsLwFWSPq0/SXNRAigf0GnLIRHmuoiryR6pAP2o iJechtaLVRWVA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 04/11] PCI: aardvark: Send Set_Slot_Power_Limit message Date: Thu, 18 Aug 2022 15:51:33 +0200 Message-Id: <20220818135140.5996-5-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Emulate Slot PowerLimit Scale and Value bits in the Slot Capabilities register of the emulated bridge and if slot power limit value is defined, send that Set_Slot_Power_Limit message via Message Generation Control Register in Link Up handler on link up event. Slot power limit value is read from device-tree property 'slot-power-limit-milliwatt'. If this property is not specified, we treat it as "Slot Capabilities register has not yet been initialized". According to PCIe Base specification 3.0, when transitioning from a non-DL_Up Status to a DL_Up Status, the Port must initiate the transmission of a Set_Slot_Power_Limit Message to the other component on the Link to convey the value programmed in the Slot Power Limit Scale and Value fields of the Slot Capabilities register. This transmission is optional if the Slot Capabilities register has not yet been initialized. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 51 ++++++++++++++++++++++++--- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 31da28ebc5d1..03e318bc171f 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -213,6 +213,11 @@ enum { }; #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) +#define PME_MSG_GEN_CTRL (LMI_BASE_ADDR + 0x220) +#define SEND_SET_SLOT_POWER_LIMIT BIT(13) +#define SEND_PME_TURN_OFF BIT(14) +#define SLOT_POWER_LIMIT_DATA_SHIFT 16 +#define SLOT_POWER_LIMIT_DATA_MASK GENMASK(25, 16) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -285,6 +290,8 @@ struct advk_pcie { raw_spinlock_t msi_irq_lock; DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); struct mutex msi_used_lock; + u8 slot_power_limit_value; + u8 slot_power_limit_scale; int link_gen; bool link_was_up; struct timer_list link_irq_timer; @@ -317,8 +324,9 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) { /* check if LTSSM is in normal operation - some L* state */ u8 ltssm_state = advk_pcie_ltssm_state(pcie); + u16 slotsta, slotctl; + u32 slotpwr, val; bool link_is_up; - u16 slotsta; link_is_up = ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; @@ -332,6 +340,27 @@ static inline bool advk_pcie_link_up(struct advk_pcie *pcie) pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta); mod_timer(&pcie->link_irq_timer, jiffies + 1); + + /* + * According to PCIe Base specification 3.0, when transitioning + * from a non-DL_Up Status to a DL_Up Status, the Port must + * initiate the transmission of a Set_Slot_Power_Limit Message + * to the other component on the Link to convey the value + * programmed in the Slot Power Limit Scale and Value fields of + * the Slot Capabilities register. This transmission is optional + * if the Slot Capabilities register has not yet been + * initialized. + */ + slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); + slotpwr = FIELD_GET(PCI_EXP_SLTCAP_SPLV | PCI_EXP_SLTCAP_SPLS, + le32_to_cpu(pcie->bridge.pcie_conf.slotcap)); + if (!(slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE) && slotpwr) { + val = advk_readl(pcie, PME_MSG_GEN_CTRL); + val &= ~SLOT_POWER_LIMIT_DATA_MASK; + val |= slotpwr << SLOT_POWER_LIMIT_DATA_SHIFT; + val |= SEND_SET_SLOT_POWER_LIMIT; + advk_writel(pcie, val, PME_MSG_GEN_CTRL); + } } return link_is_up; @@ -944,8 +973,9 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, case PCI_EXP_SLTCTL: { u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); - /* Only emulation of HPIE and DLLSCE bits is provided */ - slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; + /* Only emulation of HPIE, DLLSCE and ASPLD bits is provided */ + slotctl &= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE | + PCI_EXP_SLTCTL_ASPL_DISABLE; bridge->pcie_conf.slotctl = cpu_to_le16(slotctl); break; } @@ -1109,9 +1139,13 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) * Set physical slot number to 1 since there is only one port and zero * value is reserved for ports within the same silicon as Root Port * which is not our case. + * + * Set slot power limit. */ slotcap = PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC | - FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1); + FIELD_PREP(PCI_EXP_SLTCAP_PSN, 1) | + FIELD_PREP(PCI_EXP_SLTCAP_SPLV, pcie->slot_power_limit_value) | + FIELD_PREP(PCI_EXP_SLTCAP_SPLS, pcie->slot_power_limit_scale); bridge->pcie_conf.slotcap = cpu_to_le32(slotcap); bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); @@ -1837,6 +1871,7 @@ static int advk_pcie_probe(struct platform_device *pdev) struct advk_pcie *pcie; struct pci_host_bridge *bridge; struct resource_entry *entry; + u32 slot_power_limit; int ret, irq; bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); @@ -1957,6 +1992,14 @@ static int advk_pcie_probe(struct platform_device *pdev) else pcie->link_gen = ret; + slot_power_limit = of_pci_get_slot_power_limit(dev->of_node, + &pcie->slot_power_limit_value, + &pcie->slot_power_limit_scale); + if (slot_power_limit) + dev_info(dev, "Slot Power Limit: %u.%uW\n", + slot_power_limit / 1000, + (slot_power_limit / 100) % 10); + ret = advk_pcie_setup_phy(pcie); if (ret) return ret; From patchwork Thu Aug 18 13:51:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947126 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42619C28B2B for ; Thu, 18 Aug 2022 13:52:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245291AbiHRNv6 (ORCPT ); Thu, 18 Aug 2022 09:51:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245274AbiHRNv6 (ORCPT ); Thu, 18 Aug 2022 09:51:58 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58C54606BF for ; Thu, 18 Aug 2022 06:51:57 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 11B11B82198 for ; Thu, 18 Aug 2022 13:51:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 43BC5C433D6; Thu, 18 Aug 2022 13:51:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830714; bh=KM7YvgpO+UoAIHJk/hRytiOdqT/ZECH6OH4Q6FHzez0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tZYOgk/2eC8DMU6IN0yc6+lHxjMeIvk+BLHG7Q1BDUQDKLW4NCL7mPn5FZhmlXK1D PTh5yNW50rHSyHGV5vJl4ZKRStnpYSBHrkyQbZ5vY3d0qAK5QB4uhnyK1lGNsZh7YD eSFlvU16kMvUJi0/k7Vx7IKzs0STpAtH2nNlkVwUmOmL0sVtM3byI2Ht8L4Kv/MGtc BMqZJFkRiAe2fkXwaQQkVViNZmBiCnvUa2MIB6jORC+0ygQy5o5pBtvTGK/u4uBlYD xWKE1BArJeqBWcvuhG2QunVA/0YBQPw3ohfOHRt2okpYICgT+39gMAbclG/HVqT1tG xQempnf6EseYg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas , Gregory CLEMENT Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 05/11] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Date: Thu, 18 Aug 2022 15:51:34 +0200 Message-Id: <20220818135140.5996-6-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár PCIe Slot Power Limit on Turris Mox is 10W. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index ada164d423f3..5d2b221dbd96 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -136,6 +136,7 @@ &pcie0 { pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; status = "okay"; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; + slot-power-limit-milliwatt = <10000>; /* * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and From patchwork Thu Aug 18 13:51:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947125 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60A94C3F6B0 for ; Thu, 18 Aug 2022 13:52:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245305AbiHRNv7 (ORCPT ); Thu, 18 Aug 2022 09:51:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245294AbiHRNv6 (ORCPT ); Thu, 18 Aug 2022 09:51:58 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFD2E61128 for ; Thu, 18 Aug 2022 06:51:57 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 73E10615FB for ; Thu, 18 Aug 2022 13:51:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4456DC433D7; Thu, 18 Aug 2022 13:51:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830716; bh=YOHpPreByGGoyZO9gaJvQCWGWwT25levFv1BixvDFn4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FljnI6DlzFT8ISKS5JMRv1+4awZwKejh4pnHTboWu6jaznWiXI91rnAOU9LAvCaPz 9bmQ6tKn7oSOTt/r9wqutoVYaUlU2kdPYaZOOxZGuZpHgPzr7eXBEXTFiUW0cnD9Ts OeGztvl37+8/lDNsUg/ikmsc9462O4Xpq8GKwddUYgAJxVuf+y0793criBIGZwWKw6 OtQGurMWybu9LVNYXFDHege+j5WrwOXMLlOWZSdiwInSxq6rbuy45a7UE8xkkMhdvU WPoLX94fpq87zPCm/URbaTC0oewdqmi7bdFRDKBwpA4HYAFeRrm12a6+dCdw1P7YOc A/Ex9YrRnU50w== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Miquel Raynal , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 06/11] PCI: aardvark: Add clock support Date: Thu, 18 Aug 2022 15:51:35 +0200 Message-Id: <20220818135140.5996-7-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Miquel Raynal The IP relies on a gated clock. When we will add S2RAM support, this clock will need to be resumed before any PCIe registers are accessed. Add support for this clock. Signed-off-by: Miquel Raynal Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 03e318bc171f..3beafc893969 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -297,6 +298,7 @@ struct advk_pcie { struct timer_list link_irq_timer; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; + struct clk *clk; struct phy *phy; }; @@ -1809,6 +1811,29 @@ static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return of_irq_parse_and_map_pci(dev, slot, pin); } +static int advk_pcie_setup_clk(struct advk_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + int ret; + + pcie->clk = devm_clk_get(dev, NULL); + if (IS_ERR(pcie->clk) && (PTR_ERR(pcie->clk) == -EPROBE_DEFER)) + return PTR_ERR(pcie->clk); + + /* Old bindings miss the clock handle */ + if (IS_ERR(pcie->clk)) { + dev_warn(dev, "Clock unavailable (%ld)\n", PTR_ERR(pcie->clk)); + pcie->clk = NULL; + return 0; + } + + ret = clk_prepare_enable(pcie->clk); + if (ret) + dev_err(dev, "Clock initialization failed (%d)\n", ret); + + return ret; +} + static void advk_pcie_disable_phy(struct advk_pcie *pcie) { phy_power_off(pcie->phy); @@ -2000,6 +2025,10 @@ static int advk_pcie_probe(struct platform_device *pdev) slot_power_limit / 1000, (slot_power_limit / 100) % 10); + ret = advk_pcie_setup_clk(pcie); + if (ret) + return ret; + ret = advk_pcie_setup_phy(pcie); if (ret) return ret; @@ -2122,6 +2151,9 @@ static int advk_pcie_remove(struct platform_device *pdev) /* Disable phy */ advk_pcie_disable_phy(pcie); + /* Disable clock */ + clk_disable_unprepare(pcie->clk); + return 0; } From patchwork Thu Aug 18 13:51:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947128 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DDD3C32772 for ; Thu, 18 Aug 2022 13:52:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245312AbiHRNwG (ORCPT ); Thu, 18 Aug 2022 09:52:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245314AbiHRNwD (ORCPT ); Thu, 18 Aug 2022 09:52:03 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14BC061B28 for ; Thu, 18 Aug 2022 06:52:02 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 7D2A9CE205A for ; Thu, 18 Aug 2022 13:52:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 459DFC433C1; Thu, 18 Aug 2022 13:51:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830718; bh=snynf6vI9g6lx4We//tC0xZE+ub4KkCEIjZQ8UQE3RI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L/7pdxeGNMAk4J8yYcb0RTyZGxVMXMzjs0sxRBwb4aRaQfFqEqtv1UrnIpwVSeaMg LywldMtf6NTx9JHk7GIWJgZTnvz6SvkpPNRvfOrVc6P50OU2Ff3Ph6NZeW775Q1CkO exaWocxgWtcsSm+5yAJdj2Ctq+Ghh3le1dzaPkeYVcSUgaGhWBqIaFFZuaAydhH8bX T/Oqtt1CTsYpyzGRU7PrJk5SeyQWdxRgknh14G0L/U0IcvS1t1wiZf6VPFlSg6nrnl D5VG6ALHVVa/Io8nw9pyTQK8Ivfy46WAAaloqg5JjGELPNRQBX6lKLYtSMHdxtRNQq g59mm+Lwt1Y4Q== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Miquel Raynal , =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 07/11] PCI: aardvark: Add suspend to RAM support Date: Thu, 18 Aug 2022 15:51:36 +0200 Message-Id: <20220818135140.5996-8-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Miquel Raynal Add suspend and resume callbacks. We need to use the NOIRQ variants to ensure the controller's IRQ handlers are not run during suspend() / resume(), which could cause races. Signed-off-by: Miquel Raynal Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- Changes since batch 5: - clarified commit message - changed to new macro NOIRQ_SYSTEM_SLEEP_PM_OPS, as was done for many PCI controller drivers with commit 19b7858c3357 ("PCI: Convert to new *_PM_OPS macros") --- drivers/pci/controller/pci-aardvark.c | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 3beafc893969..e30a33a4ecc6 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1890,6 +1890,39 @@ static int advk_pcie_setup_phy(struct advk_pcie *pcie) return ret; } +static int advk_pcie_suspend(struct device *dev) +{ + struct advk_pcie *pcie = dev_get_drvdata(dev); + + advk_pcie_disable_phy(pcie); + + clk_disable_unprepare(pcie->clk); + + return 0; +} + +static int advk_pcie_resume(struct device *dev) +{ + struct advk_pcie *pcie = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(pcie->clk); + if (ret) + return ret; + + ret = advk_pcie_enable_phy(pcie); + if (ret) + return ret; + + advk_pcie_setup_hw(pcie); + + return 0; +} + +static const struct dev_pm_ops advk_pcie_dev_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(advk_pcie_suspend, advk_pcie_resume) +}; + static int advk_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -2167,6 +2200,7 @@ static struct platform_driver advk_pcie_driver = { .driver = { .name = "advk-pcie", .of_match_table = advk_pcie_of_match_table, + .pm = &advk_pcie_dev_pm_ops, }, .probe = advk_pcie_probe, .remove = advk_pcie_remove, From patchwork Thu Aug 18 13:51:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947127 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93274C00140 for ; Thu, 18 Aug 2022 13:52:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245311AbiHRNwF (ORCPT ); Thu, 18 Aug 2022 09:52:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245313AbiHRNwC (ORCPT ); Thu, 18 Aug 2022 09:52:02 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD8916172B for ; Thu, 18 Aug 2022 06:52:01 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 47C24616DC for ; Thu, 18 Aug 2022 13:52:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 475CEC433D7; Thu, 18 Aug 2022 13:51:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830720; bh=ftDwjJuJM+DkNC+0FTyMWCZEExUs1HVzpUV1moRdYIY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h5qRu244x3gmBpOTSglilkSDjxheuXCv6Hf2GUBjZWje/wjR5fPZK4u07TR/W9xzi sBOcsRuXe9JErxzLW0KTlLrS9AmrxaP4tFKF8MLrLEgwsClDpeZ7CU6flRJ8ZG6kNh DQW8Vc08a6/kqM7QjhV1tXdTw5Y7UZwWZGOAAIquFGyClT/vSJyjU2DL6Ue6h7Knuv GUrIY+2Q6asuQ37OtLYH1q6dVAvEVOhb++BXRf4LH3QsjBVbx+egUtIT6VWoLdBs/p f3VSvkPVHElMYborDtZ7c10pzXEid0yuCFt3ehz4OwdPhcJRPbZuJMt6jBdfheTSYt Q3ecT9Ql6ok0g== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 08/11] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros Date: Thu, 18 Aug 2022 15:51:37 +0200 Message-Id: <20220818135140.5996-9-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Kernel already has these macros defined under different names. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index e30a33a4ecc6..4855ac733484 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -37,11 +37,7 @@ #define PCIE_CORE_DEV_REV_REG 0x8 #define PCIE_CORE_PCIEXP_CAP 0xc0 #define PCIE_CORE_PCIERR_CAP 0x100 -#define PCIE_CORE_ERR_CAPCTL_REG 0x118 -#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) -#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) -#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) -#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) + /* PIO registers base address and register offsets */ #define PIO_BASE_ADDR 0x4000 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) @@ -589,11 +585,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); /* Set Advanced Error Capabilities and Control PF0 register */ - reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | - PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | - PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | - PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; - advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); + reg = PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_GENE | + PCI_ERR_CAP_ECRC_CHKC | PCI_ERR_CAP_ECRC_CHKE; + advk_writel(pcie, reg, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP); /* Set PCIe Device Control register */ reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); From patchwork Thu Aug 18 13:51:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947129 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE316C28B2B for ; Thu, 18 Aug 2022 13:52:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245314AbiHRNwG (ORCPT ); Thu, 18 Aug 2022 09:52:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245274AbiHRNwF (ORCPT ); Thu, 18 Aug 2022 09:52:05 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D5F06170F for ; Thu, 18 Aug 2022 06:52:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C1508B82179 for ; Thu, 18 Aug 2022 13:52:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 207B4C433C1; Thu, 18 Aug 2022 13:52:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830722; bh=HbKz24Nfhn6/cZiuUPLYNM9zdj4uhadCwjvhLdFM3nA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vIj9yTawYe15eFIn/SasT5q9CtieZbV3xFGVfraiKRr3ohpvteKHYHl2RCpla0N3Q evprTZZW/rOqaFTkz1/BUl4ydzNeMZcECjvQJWOtd6TTEshExtzpPOim2/rltHX4bj E0+kxqlyFEkj2j1ut/1wFvvsd/AIXNtC1sNC0PXbdDco/K7mNdmutgZ+4YjnxSty2q +ZtrLRZDXajllxWjGbHqVyKbLdFyxyAR/35bxxP1JGmNIxmT6pSeQT7IREIXunvo/O EPXBuKeugFWXxnqJKaRZX5NVDKIk0tcgfbDiFlXk56x4p59x/vX2sNxEW9tgAsKXXO zV2xV9b7/fiAg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 09/11] PCI: aardvark: Don't write read-only bits explicitly in PCI_ERR_CAP register Date: Thu, 18 Aug 2022 15:51:38 +0200 Message-Id: <20220818135140.5996-10-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The bits PCI_ERR_CAP_ECRC_GENC and PCI_ERR_CAP_ECRC_CHKC are read only, reporting the capability of ECRC. Don't write them explicitly, instead read the register (where they are set), and add the bits that enable these features. Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 4855ac733484..e816ab726f66 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -584,9 +584,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); - /* Set Advanced Error Capabilities and Control PF0 register */ - reg = PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_GENE | - PCI_ERR_CAP_ECRC_CHKC | PCI_ERR_CAP_ECRC_CHKE; + /* Enable generation and checking of ECRC on Root Bridge */ + reg = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP); + reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE; advk_writel(pcie, reg, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP); /* Set PCIe Device Control register */ From patchwork Thu Aug 18 13:51:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947130 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8987C00140 for ; Thu, 18 Aug 2022 13:52:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245274AbiHRNwH (ORCPT ); Thu, 18 Aug 2022 09:52:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245313AbiHRNwG (ORCPT ); Thu, 18 Aug 2022 09:52:06 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AEE761B28 for ; Thu, 18 Aug 2022 06:52:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 05E6661615 for ; Thu, 18 Aug 2022 13:52:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 003EFC433B5; Thu, 18 Aug 2022 13:52:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830724; bh=tSjcRHzwdwDzj8PfrZEsmRIyZScrpL96WWWx0UfyT9o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=csGn5pEa56RauNN1l07VvOwdgMijpg+cXax+BegtJH73GQ+fK/IX046x+/f4V3jyf 14zwznu5vwWZ7TZFqnw0xbRfcpSsy7BxAiKvYOvlDb0/de1ErksgPZnEODLvcf47SK uGkTIk5gzxZgmKaISdYmRPo6LLyveR82/Z2IZLdLx54P35bt1o/HVLDayzFflK2ivG Fjc4ix7bSAFM41XyL8NUWHRmEeGgynj1f1A4QiT1ROGoiLga0QbfVvhkSy3+cuzT/c pnSmSEjPGqq3IK64ml653K6Un3Trh4DO3IGQ+324pSSs1ciDfr/Rg+BAkt5WseWzqu xecQbZYHZAqoA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 10/11] PCI: aardvark: Explicitly disable Marvell strict ordering Date: Thu, 18 Aug 2022 15:51:39 +0200 Message-Id: <20220818135140.5996-11-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of implicitly disabling BIT(5) (STRICT_ORDER_ENABLE bit) of the CORE_CTRL2 by writing PCIE_CORE_CTRL2_RESERVED | PCIE_CORE_CTRL2_TD_ENABLE to it, disable it explicitly, with read-modify-write. Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index e816ab726f66..73a604f70f06 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -600,8 +600,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); /* Program PCIe Control 2 to disable strict ordering */ - reg = PCIE_CORE_CTRL2_RESERVED | - PCIE_CORE_CTRL2_TD_ENABLE; + reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); + reg &= ~PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE; advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); /* Set lane X1 */ From patchwork Thu Aug 18 13:51:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 12947131 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03723C3F6B0 for ; Thu, 18 Aug 2022 13:52:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245321AbiHRNwJ (ORCPT ); Thu, 18 Aug 2022 09:52:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245316AbiHRNwI (ORCPT ); Thu, 18 Aug 2022 09:52:08 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52F5461B0B for ; Thu, 18 Aug 2022 06:52:07 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D589F616DC for ; Thu, 18 Aug 2022 13:52:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D04CFC43140; Thu, 18 Aug 2022 13:52:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660830726; bh=VWlDeVNSF8K5y9LwrhrOTt+8IGNO/UVbQ6FhhVMO6zE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tBLMCZCFSkhd3MF0YvDPuFdVEjDlCld1zLYdjqruPfyCxCFCJPsG5Iagf4C4rSTSx L5TQgiEzOXRAfqTTQqVjLWvthloBRjFRYFTTxWPvXJ8OoMHYXbNPDFOEQgaRCLkSWA 9xVvm0Xt0Z741HFXbOGrUQ+u3VMrT7EqpG8Tb8lBfuMCiqzrGqpFCLmylp+W0E1Pdf 0f9s6SGKAhEBdUP9er653kAAiptyyJo5Px+5SVSTdn73c5FwnaDgWIMmnysUCSTlFS k5gWGr21A1dsDxpdT8i8hd0PO2YmAMYvdIaITen+IBq5ja7OniJw7os0fxSlWxTiPK 5cgous8+RQDYg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Lorenzo Pieralisi , Bjorn Helgaas Cc: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , pali@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 11/11] PCI: aardvark: Cleanup some register macros Date: Thu, 18 Aug 2022 15:51:40 +0200 Message-Id: <20220818135140.5996-12-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220818135140.5996-1-kabel@kernel.org> References: <20220818135140.5996-1-kabel@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Pali Rohár Define SPEED_GEN_* macros with correct PCIE_GEN_SEL_SHIFT. Simplify macro for setting root complex mode (use BIT instead of MSK + SHIFT). Rename PCIE_MSG_PM_PME_MASK to PCIE_ISR0_MSG_PM_PME to match existing naming convention, rename PCIE_ISR0_MSI_INT_PENDING to PCIE_ISR0_MSI_INT as it is used for both interrupt mask and pending bit. Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- drivers/pci/controller/pci-aardvark.c | 28 +++++++++++++-------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 73a604f70f06..11afafe71e3d 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -66,11 +66,10 @@ #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) #define PCIE_GEN_SEL_MSK 0x3 #define PCIE_GEN_SEL_SHIFT 0x0 -#define SPEED_GEN_1 0 -#define SPEED_GEN_2 1 -#define SPEED_GEN_3 2 -#define IS_RC_MSK 1 -#define IS_RC_SHIFT 2 +#define SPEED_GEN_1 (0 << PCIE_GEN_SEL_SHIFT) +#define SPEED_GEN_2 (1 << PCIE_GEN_SEL_SHIFT) +#define SPEED_GEN_3 (2 << PCIE_GEN_SEL_SHIFT) +#define IS_RC BIT(2) #define LANE_CNT_MSK 0x18 #define LANE_CNT_SHIFT 0x3 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) @@ -95,16 +94,16 @@ #define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2) #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) -#define PCIE_MSG_PM_PME_MASK BIT(7) #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) -#define PCIE_ISR0_MSI_INT_PENDING BIT(24) #define PCIE_ISR0_LINK_DOWN BIT(1) +#define PCIE_ISR0_MSG_PM_PME BIT(7) #define PCIE_ISR0_CORR_ERR BIT(11) #define PCIE_ISR0_NFAT_ERR BIT(12) #define PCIE_ISR0_FAT_ERR BIT(13) #define PCIE_ISR0_ERR_MASK GENMASK(13, 11) #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) +#define PCIE_ISR0_MSI_INT BIT(24) #define PCIE_ISR0_ALL_MASK GENMASK(31, 0) #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) @@ -546,7 +545,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) /* Set PCI global control register to RC mode */ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); - reg |= (IS_RC_MSK << IS_RC_SHIFT); + reg |= IS_RC; advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); /* @@ -633,7 +632,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) /* Unmask summary MSI interrupt */ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); - reg &= ~PCIE_ISR0_MSI_INT_PENDING; + reg &= ~PCIE_ISR0_MSI_INT; advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); /* Unmask Link Down interrupt */ @@ -643,7 +642,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) /* Unmask PME interrupt for processing of PME requester */ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); - reg &= ~PCIE_MSG_PM_PME_MASK; + reg &= ~PCIE_ISR0_MSG_PM_PME; advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); /* Enable summary interrupt for GIC SPI source */ @@ -1661,7 +1660,7 @@ static void advk_pcie_handle_pme(struct advk_pcie *pcie) { u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; - advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG); + advk_writel(pcie, PCIE_ISR0_MSG_PM_PME, PCIE_ISR0_REG); /* * PCIE_MSG_LOG_REG contains the last inbound message, so store @@ -1700,8 +1699,7 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie) dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); } - advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, - PCIE_ISR0_REG); + advk_writel(pcie, PCIE_ISR0_MSI_INT, PCIE_ISR0_REG); } static void advk_pcie_handle_int(struct advk_pcie *pcie) @@ -1720,7 +1718,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); /* Process PME interrupt as the first one to do not miss PME requester id */ - if (isr0_status & PCIE_MSG_PM_PME_MASK) + if (isr0_status & PCIE_ISR0_MSG_PM_PME) advk_pcie_handle_pme(pcie); /* Process ERR interrupt */ @@ -1756,7 +1754,7 @@ static void advk_pcie_handle_int(struct advk_pcie *pcie) } /* Process MSI interrupts */ - if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) + if (isr0_status & PCIE_ISR0_MSI_INT) advk_pcie_handle_msi(pcie); /* Process legacy interrupts */